ICS673M-01

DATASHEET ICS673-01 PLL BUILDING BLOCK Description Features The ICS673-01 is a low cost, high-performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (the ICS674-01), the user can customize the clock to lock to a wide variety of input frequencies. • • • • • Packaged in 16-pin SOIC • • • • • • • Output Enable tri-states outputs The ICS673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power-down feature which turns off the entire device. For applications that require low jitter or jitter attenuation, see the MK2069. Available in RoHS compliant package Access to VCO input and feedback paths of PLL Output operating range up to 120 MHz (5 V) Able to lock MHz range outputs to kHz range inputs through the use of external dividers Low skew output clocks Power-down turns off chip VCO predivide to feedback divider of 1 or 4 25 mA output drive capability at TTL levels Advanced, low power, sub-micron CMOS process Single supply +3.3 V (±5%) or +5 V (±10%) operating voltage • Industrial and commercial temperature ranges • Forms a complete PLL, using the ICS674-01 • For better jitter performance, use the MK1575 Block Diagram CHCP VCOIN VDD 2 VDD Icp Clock Input REFIN FBIN CLK1 UP Phase/ Frequency Detector VCO DOWN 1 2 4 0 MUX 2 CLK2 Icp PD (entire chip) CAP 3 GND SEL OE (both outputs) External Feedback Divider (such as the ICS674-01) IDT™ / ICS™ PLL BUILDING BLOCK 1 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK Pin Assignment VCO Predivide Select Table SEL VCO Predivide F B IN 1 16 R E F IN 0 4 VDD 2 15 NC 1 1 VDD 3 14 C LK1 GND 4 13 C LK2 GND 5 12 PD GND 6 11 SEL CHGP 7 10 OE V C O IN 8 9 0 = connect pin directly to ground 1 = connect pin directly to VDD CAP 1 6 p in n a rro w (1 5 0 m il) S O IC Pin Descriptions Pin Number Pin Name Pin Type 1 FBIN Input Feedback clock input. Connect the feedback clock to this pin. Triggered on falling edge. 2 VDD Power Connect to +3.3 V or +5 V and to VDD on pin 3. 3 VDD Power Connect to VDD on pin 2. 4 GND Power Connect to ground. 5 GND Power Connect to ground. 6 GND Power Connect to ground. 7 CHGP Output Charge pump output. Connect to VCOIN under normal operation. 8 VCOIN Input Input to internal VCO. 9 CAP Input Loop filter return. 10 OE Input Output enable. Active when high. Tri-states both outputs when low. Internal weak pull-up resistor. 11 SEL Input Select pin for VCO predivide to feedback divider per table above. Internal weak pull-up resistor. 12 PD Input Power down. Turns off entire chip when pin is low. Outputs stop low. Internal weak pull-up resistor. 13 CLK2 Output Clock output 2. Low skew divide by two version of CLK1. 14 CLK1 Output Clock output 1. 15 NC - 16 REFIN Input IDT™ / ICS™ PLL BUILDING BLOCK Pin Description No connect. Nothing is connected internally to this pin. Reference input. Connect reference clock to this pin. Triggered on falling edge. 2 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS673-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70° C Industrial Temperature -40 to +85° C Storage Temperature -65 to +150° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 °C -40 +85 °C +3.13 +5.50 V Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics VDD=3.3 V ±5% or 5.0 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise. Parameter Operating Voltage Symbol Conditions VDD Typ. 3.13 Logic Input High Voltage VIH REFIN, FBIN, SEL Logic Input Low Voltage VIL REFIN, FBIN, SEL LF Input Voltage Range VI VOH IOH = -25 mA Output Low Voltage VOL IOL = 25 mA Output High Voltage, CMOS level VOH IOH = -8 mA Operating Supply Current IDD VDD = 5.0 V, No load, 40 MHz Short Circuit Current IOS Input Capacitance CIN Max. Units 5.50 V 2 V 0 Output High Voltage IDT™ / ICS™ PLL BUILDING BLOCK Min. 0.8 V VDD V 2.4 V 0.4 V VDD-0.4 15 mA CLK ±100 mA SEL 5 pF 3 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C, CLOAD at CLK = 15 pF, unless stated otherwise. Parameter Symbol Conditions Output Clock Frequency (from pin CLK) fCLK Input Clock Frequency (into pins REFIN or FBIN) fREF Output Rise Time tOR 0.8 to 2.0 V Output Fall Time tOF 2.0 to 0.8 V Output Clock Duty Cycle tDC At VDD/2 Min. Typ. Max. Units SEL = 1 1 100 MHz SEL = 0 0.25 25 MHz Note 1 8 MHz 1.2 2 ns 0.75 1.5 ns 50 60 % 40 Jitter, Absolute peak-to-peak tJ 250 ps VCO Gain KO 190 MHz/V Charge Pump Current Icp 2.5 µA VDD = 5.0 V ±10%, Ambient Temperature -40 to +85° C, CLOAD at CLK = 15 pF, unless stated otherwise. Parameter Symbol Conditions Output Clock Frequency (from pin CLK) fCLK Input Clock Frequency (into pins REFIN or FBIN) fREF Output Rise Time tOR 0.8 to 2.0 V Output Fall Time tOF 2.0 to 0.8 V Output Clock Duty Cycle tDC At VDD/2 Min. Typ. Max. Units SEL = 1 1 120 MHz SEL = 0 0.25 30 MHz Note 1 8 MHz 0.5 1 ns 0.5 1 ns 50 55 % 45 Jitter, Absolute peak-to-peak tJ 150 ps VCO Gain KO 190 MHz/V Charge Pump Current Icp 2.4 µA Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit. External Components Avoiding PLL Lockup The ICS673-01 requires a minimum number of external components for proper operation. A decoupling capacitor of 0.01µF should be connected between VDD and GND as close to the ICS673-01 as possible. A series termination resistor of 33Ω may be used at the clock output. In some applications, the ICS673-01 can “lock up” at the maximum VCO frequency. This is usually caused by power supply glitches or a very slow power supply ramp. This situation also occurs if the external divider starts to fail at high input frequencies. The usual failure mode of a divider circuit is that the output of the divider begins to miss clock edges. The phase detector interprets this as a too low output frequency and increases the VCO frequency. The Special considerations must be made in choosing loop components CS and CP. These can be found online at http://www.icst.com/products/telecom/loopfiltercap.htm IDT™ / ICS™ PLL BUILDING BLOCK 4 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK feedback divider begins to miss even more clock edges and the VCO frequency is continually increased until it is running at its maximum frequency. Whether caused by power supply issues or by the external divider, the loop can only recover by powering down the circuit or asserting PD. VDD R1 I CS673- 01 The simplest way to avoid this problem is to use an external divider that always operates correctly regardless of the VCO speed. Figures 2 and 3 show that the VCO is capable of high speeds. By using the internal divide-by-four and/or the CLK2 output, the maximum VCO frequency can be divided by 2, 4, or 8 and a slower counter can be used. Using the ICS673 internal dividers in this manner does reduce the number of frequencies that can be exactly synthesized by forcing the total VCO divide to change in increments of 2, 4, or 8. PD C3 A. Basi c Ci r cui t VDD If this lockup problem occurs, there are several solutions; three of which are described below. I CS673-01 1. If the system has a reset or power good signal, this should be applied to the PD pin, forcing the chip to stay powered down until the power supply voltage has stabilized. If the dividers are implemented in an FPGA or other circuit configured on power-up, it is critical keep the ICS673 powered down until the dividers are working properly. R1 D1 PD C3 B. Fast er Di scharge Fi g 1 . Po we r o n Re s e t Ci r c u i t s 2. If no power good signal is available, a simple power-on reset circuit can be attached to the PD pin, as shown in Figure 1. When the power supply ramps up, this circuit holds PD asserted (device powered down) until the capacitor charges. The circuit of Figure 1A is adequate in most cases, but the discharge rate of capacitor C3 when VDD goes low is limited by R1. As this discharge rate determines the minimum reset time, the circuit of Figure 1B may be used when a faster reset time is desired. The values of R1 and C3 should be selected to ensure that PD stays below 1.0 V until the power supply is stable. 3. A comparator circuit may be used to monitor the loop filter voltage as shown in Figure 2. This circuit will dump the charge off the loop filter by asserting PD if the VCO begins to run too fast and the PLL can recover. A good choice for the comparator is the National Semiconductor LMC7211BIM5X. It is low power, version of the small (SOT-23), low cost, and has high input impedance. The trigger voltage of the comparator is set by the voltage divider formed by R2 and R3. The voltage should be set to a value higher than the VCO input is expected to run during normal operation. Typically, this might be 0.5 V below VDD. Hysteresis should be added to the circuit by connecting R4. IDT™ / ICS™ PLL BUILDING BLOCK 5 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK Explanation of Operation CHGP VCOIN CAP The ICS673-01 is a PLL building block circuit that includes an integrated VCO with a wide operating range. The device uses external PLL loop filter components which through proper configuration allow for low input clock reference frequencies, such as a 15.7 kHz Hsync input. PD CP R2 RS CS + The phase/frequency detector compares the falling edges of the clocks inputted to FBIN and REFIN. It then generates an error signal to the charge pump, which produces a charge proportional to this error. The external loop filter integrates this charge, producing a voltage that then controls the frequency of the VCO. This process continues until the edges of FBIN are aligned with the edges of the REFIN clock, at which point the output frequency will be locked to the input frequency. R3 R4 Figure 2. Using an External Comparator to Reset the VCO The CLK output frequency may be up to 2x the maximum Output Clock Frequency listed in the AC Electrical Characteristics above when the device is in an unlocked condition. Make sure that the external divider can operate up to this frequency. Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference. +3.3 or 5 V CP 0.01 F RS SEL OE PD 200 kHz REFIN VDD CHGP VCOIN CS CAP ICS673-01 CLK1 40 MHz CLK2 20 MHz FBIN GND 200 kHz 100 Digital Divider such as ICS674-01 IDT™ / ICS™ PLL BUILDING BLOCK 6 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK Determining the Loop Filter Values and CS = 1.32 nF (1.2 nF is the nearest standard value). The loop filter components consist of CS, CP, and RS. Calculating these values is best illustrated by an example. Using the example in Figure 1, we can synthesize 20 MHz from a 200 kHz input. The capacitor CP is used to damp transients from the charge pump and should be approximately 1/20th the size of CS, i.e., The phase locked loop may be approximately described by the following equations: C P ≅ C S ⁄ 20 Therefore, CP = 60 pF (56 pF nearest standard value). BandwidthNBW R ⋅ K ⋅ I To summarize, the loop filter components are: CS = 1.2 nf CP = 56 pf RS = 26 kΩ S O CP = ------------------------------2 πN Damping factor,ζ = R S K O ⋅ I CP ⋅ C S ------ ----------------------------------2 N Output Clock Alignment to REFIN When choosing either CLK1 or CLK2 to drive the feedback divider, ICS recommends that CLK2 be used so that the falling edges of CLK2 and REFIN, and the rising edge of CLK1, are all synchronized. If CLK1 is used for feedback, CLK2 may be either a rising or falling edge when compared to REFIN. See diagrams below. where: KO = VCO gain (Hz/V) Icp = Charge pump current (A) N = Total feedback divide from VCO, including the internal VCO post divider CS = Loop filter capacitor (Farads) RS = Loop filter resistor (Ohms) CLK1 As a general rule, the bandwidth should be at least 20 times less than the reference frequency, i.e., BW ≤( REFIN ) ⁄ 20 CLK2 REFIN In this example, using the above equation, bandwidth should be less than or equal to 10 kHz. By setting the bandwith to 10kHz and using the first equation, RS can be determined since all other variables are known. In the example of Figure 1, N = 200, comprising the divide by 2 on the chip (VCO post divider) and the external divide by 100. Therefore, the bandwidth equation becomes: 6 CLK2 Feedback CLK1 – ⋅ 190 ⋅ 10 ⋅ 2.5 ⋅ 10 0,000 = -----------------------------------------------------------------2π ⋅ 200 RS CLK2 REFIN and RS = 26 kΩ CLK1 Feedback Choosing a damping factor of 0.7 (a minimal damping factor than can be used to ensure fast lock time), damping factor equation becomes: 6 0.7 = –6 25, 000 190 ⋅ 10 ⋅ 2.5 ⋅ 10 ⋅ C S --------------- --------------------------------------------------------------------2 200 IDT™ / ICS™ PLL BUILDING BLOCK 7 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D Inches* Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° *For reference only. Controlling dimensions in mm. A h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 673M-01I 673M-01IT 673M-01ILF 673M-01ILFT 673M-01 673M-01T 673M-01LF 673M-01LFT ICS673M-01I ICS673M-01I 673M-01ILF 673M-01ILF ICS673M-01 ICS673M-01 673M-01LF 673M-01LF Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT™ / ICS™ PLL BUILDING BLOCK 8 ICS673-01 REV Q 071906 ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA