ICS843023AGI

FemtoClock® Crystal-to-3.3V, 2.5V LVPECL Clock Generator 843023I DATASHEET GENERAL DESCRIPTION FEATURES • One differential 3.3V or 2.5V LVPECL output The 843023I is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM family of high performance devices from IDT. The 843023I uses a 25MHz crystal to synthesize 250MHz. The 843023I has excellent phase jitter performance, over the 1.875MHz – 20MHz integration range. The 843023I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal • Output frequency range: 240MHz - 320MHz • VCO range: 480MHz - 640MHz • RMS phase jitter @ 250MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.39ps (typical) Phase noise: Offset Noise Power 100Hz ..................-86.3 dBc/Hz 1kHz ................-114.6 dBc/Hz 10kHz ................-125.6 dBc/Hz 100kHz ................-126.0 dBc/Hz • Full 3.3V and 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT OE Pullup XTAL_IN 25MHz OSC XTAL_OUT Phase Detector VCO Q nQ ÷2 (fixed) VCC XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 Q nQ VCC OE 843023I ÷20 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View (fixed) 843023I REVISION B JANUARY 9, 2015 1 ©2015 Integrated Device Technology, Inc. 843023I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 6 VCC Power Core supply pin. 2, 3 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4 VEE Power Negative supply pin. 5 OE Input 7, 8 nQ, Q Output Pullup Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and the device is in power down mode. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR Test Conditions Minimum 2 Typical Maximum Units REVISION B 1/9/15 843023I DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC VCCA Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 75 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 70 mA Maximum Units TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE VCC = VIN = 3.465V or 2.625V IIL Input Low Current OE VCC = 3.465V or 2.625V, VIN = 0V Minimum Typical VCC = 3.3V 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V 5 µA -150 µA TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCC - 1.4 Typical VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. REVISION B 1/9/15 3 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 843023I DATA SHEET TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Maximum Units 32 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Typical Fundamental Frequency 24 TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 240 250MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% Maximum Units 320 MHz 0.39 ps 300 600 ps 47 53 % Maximum Units 320 MHz NOTE 1: Please refer to the Phase Noise Plot after this section. TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter (Random); NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 240 250MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% 0.39 ps 300 600 ps 47 53 % NOTE 1: Please refer to the Phase Noise Plot after this section. FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 4 REVISION B 1/9/15 843023I DATA SHEET 0 TYPICAL PHASE NOISE AT 250MHZ (3.3V) ➤ -10 -20 Gigabit Ethernet Filter -30 -40 250MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -50 -120 -130 -140 -150 ➤ -160 -170 -180 -190 100 1k 10k Phase Noise Result by adding Gigabit Ethernet Filter to raw data 100k 1M 10M 100M 500M OFFSET FREQUENCY (HZ) 0 TYPICAL PHASE NOISE AT 250MHZ (2.5V) ➤ -10 -20 Gigabit Ethernet Filter -30 -50 250MHz -60 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) -70 -80 -90 Raw Phase Noise Data -100 ➤ NOISE POWER dBc Hz -40 -110 -120 -130 -140 -150 -160 ➤ -170 -180 -190 100 1k 10k Phase Noise Result by adding Gigabit Ethernet Filter to raw data 100k 1M 10M 100M 500M OFFSET FREQUENCY (HZ) REVISION B 1/9/15 5 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 843023I DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 6 REVISION B 1/9/15 843023I DATA SHEET APPLICATION INFORMATION CRYSTAL INPUT INTERFACE The 843023I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. FIGURE 1. CRYSTAL INPUt INTERFACE LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by remov-ing R1 and making R2 50Ω. VDD VDD R1 Ro Rs .1uf Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 2. General Diagram for LVCMOS Driver to XTAL Input Interface REVISION B 1/9/15 7 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 843023I DATA SHEET TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are FIGURE 3A. LVPECL OUTPUT TERMINATION FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR FIGURE 3B. LVPECL OUTPUT TERMINATION 8 REVISION B 1/9/15 843023I DATA SHEET TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground Zo = 50 Ohm R1 250 2.5V VCC=2.5V 2.5V VCC=2.5V level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V Zo = 50 Ohm R3 250 + + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R2 50 R4 62.5 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE REVISION B 1/9/15 9 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 843023I DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 843023I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843023I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA = 259.87mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 259.87mW + 30mW = 389.87mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.290W * 90.5°C/W = 111.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 10 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W REVISION B 1/9/15 843023I DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC- 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW REVISION B 1/9/15 11 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 843023I DATA SHEET RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for 843023I is: 2360 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 12 REVISION B 1/9/15 843023I DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 13 REVISION B 1/9/15 843023I DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 843023AGILF 23AIL 8 lead “Lead Free” TSSOP Tube -40°C to +85°C 843023AGILFT 23AIL 8 lead “Lead Free” TSSOP Tape and Reel -40°C to +85°C NOTE: Parts that are ordered with an “LF suffix to the part number are Pb-Free and RoHS compliant. REVISION B 1/9/15 14 FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 843023I DATA SHEET REVISION HISTORY SHEET Rev Table Page 1 B B T4 4 T5A & T5B 4 7 T9 14 Description of Change Date Features Section - changed minimum output frequency range from 245MHz to 240MHz. Changed minumum VCO range from 490MHz to 480MHz. Crystal Characteristics Table - changed minumum frequency from 24.5MHz to 24MHz. AC Characteristics Tables - changed minumum output frequency from 245MHz to 240MHz. Added LVCMOS to XTAL Interface section. Ordering Information - removed leaded devices and added Marking for the Lead Free devices. Updated datasheet format. FEMTOCLOCKS® CRYSTAL-TO3.3V, 2.5V LVPECL CLOCK GENERATOR 15 1/9/07 1/9/15 REVISION B 1/9/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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