ICS951416AGLFT

ICS951416 System Clock Chip for ATI RS480 Output Features: • 3 - 14.318 MHz REF clocks • 1 - USB_48MHz USB clock • 1 - HyperTransport 66 MHz clock seed • 1 - PCI 33 MHz clock seed • 2 - Pairs of AMD K8 clocks • 6 - Pairs of SRC/PCI Express* clocks • 2 - Pairs of ATIG (SRC/PCI Express) clocks Features: • 2 - Programmable Clock Request pins for SRC clocks • ATIGCLKS are programmable for frequency • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal lead capacitors for maximum frequency accuracy Pin Configuration X1 X2 VDD48 USB_48MHz GND NC SCLK SDATA **FS2 **CLKREQA# **CLKREQB# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ICS951416 Recommended Application: ATI RS480 systems using AMD K8 processors VDDREF GND **FS0/REF0 **FS1/REF1 REF2 VDDPCI PCICLK0 GNDPCI VDDHTT HTTCLK0 GNDHTT CPUCLK8T0 CPUCLK8C0 VDDCPU GNDCPU CPUCLK8T1 CPUCLK8C1 VDDA GNDA IREF GNDSRC VDDSRC SRCCLKT0 SRCCLKC0 VDDATI GNDATI ATIGCLKT0 ATIGCLKC0 Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor 56 Pin SSOP/TSSOP Power Groups Pin Number VDD GND 56 55 51 49 Functionality FS1 FS0 CPU MHz Hi-Z HTT MHz Hi-Z PCI MHz Hi-Z Description FS2 Xtal, REF 0 0 0 PCICLK output 0 0 1 X X/3 X/6 0 1 0 180.00 60.00 30.00 0 1 1 220.00 73.12 36.56 1 0 0 100.00 66.66 33.33 48 46 HTTCLK output 43 14, 21, 32,35 39 42 15, 20, 26,31,36 38 CPU Outputs SRC outputs 1 0 1 133.33 66.66 33.33 Analog, CPU PLL 1 1 1 200.00 66.66 33.33 3 5 USB_48MHz output 0937H—05/26/05 *Other names and brands may be claimed as the property of others. ICS951416 Pin Descriptions PIN # PIN NAME PIN TYPE 1 2 3 4 5 6 7 8 9 X1 X2 VDD48 USB_48MHz GND NC SCLK SDATA **FS2 IN OUT PWR OUT PWR N/A IN I/O IN 10 **CLKREQA# IN 11 **CLKREQB# IN 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1 OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR OUT OUT DESCRIPTION Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48.00MHz USB clock Ground pin. No Connection. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Frequency select pin. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs True clock of differential SRC clock pair. Complementary clock of differential SRC clock pair. 0937H—05/26/05 2 ICS951416 Pin Descriptions (Continued) PIN # 29 30 31 32 33 34 35 36 ATIGCLKC0 ATIGCLKT0 GNDATI VDDATI SRCCLKC0 SRCCLKT0 VDDSRC GNDSRC OUT OUT PWR PWR OUT OUT PWR PWR 37 IREF This pin establishes the reference current for the differential current-mode OUT output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 GNDA VDDA CPUCLK8C1 CPUCLK8T1 GNDCPU VDDCPU CPUCLK8C0 CPUCLK8T0 GNDHTT HTTCLK0 VDDHTT GNDPCI PCICLK0 VDDPCI REF2 **FS1/REF1 **FS0/REF0 GND VDDREF PWR PWR OUT OUT PWR PWR OUT OUT PWR OUT PWR PWR OUT PWR OUT I/O I/O PWR PWR PIN NAME TYPE DESCRIPTION Complementary clock of differential SRC clock pair. True clock of differential SRC clock pair. Ground for ATI Gclocks, nominal 3.3V Power supply ATI Gclocks, nominal 3.3V Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs Ground pin for the PLL core. 3.3V power for the PLL core. Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the HTT outputs 3.3V Hyper Transport output Supply for HTT clocks, nominal 3.3V. Ground pin for the PCI outputs PCI clock output. Power supply for PCI clocks, nominal 3.3V 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin. Ref, XTAL power supply, nominal 3.3V 0937H—05/26/05 3 ICS951416 General Description The ICS951416 is a main clock synthesizer chip that provides all clocks required for ATI RS480-based systems. An SMBus interface allows full control of the device. Block Diagram REF(2:0) X1 X2 XTAL OSC. USB_48MHz FIXED PLL CPU PLL FS(2:0) CLKREQA# CLKREQB# PCI33 DIV PCICLK0 HTT66 DIV HTTCLK0 CPU DIV CPUCLK8(1:0) SRC DIV2 /8/7/6/5 ATIGCLK(1:0) SRC DIV1 SRCCLK(7:3,0) CONTROL LOGIC SDATA SCLK SRC PLL 0937H—05/26/05 4 ICS951416 General SMBus serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0937H—05/26/05 5 Not acknowledge stoP bit ICS951416 Table1: CPU Frequency Selection Table CPU CPU Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 (MHz) (B0:b4) (B0:b3) 0 0 0 0 0 Hi-Z 0 0 0 0 1 X/6 0 0 0 1 0 180.00 0 0 0 1 1 220.00 0 0 1 0 0 100.00 0 0 1 0 1 133.33 0 0 1 1 0 166.67 0 0 1 1 1 200.00 0 1 0 0 0 186.00 0 1 0 0 1 214.00 0 1 0 1 0 190.00 0 1 0 1 1 210.00 0 1 1 0 0 102.00 0 1 1 0 1 136.00 0 1 1 1 0 170.00 0 1 1 1 1 204.00 1 0 0 0 0 169.58 1 0 0 0 1 229.43 1 0 0 1 0 179.55 1 0 0 1 1 219.45 1 0 1 0 0 99.75 1 0 1 0 1 133.00 1 0 1 1 0 166.25 1 0 1 1 1 199.50 1 1 0 0 0 185.54 1 1 0 0 1 106.73 1 1 0 1 0 189.53 1 1 0 1 1 209.48 1 1 1 0 0 101.75 1 1 1 0 1 135.66 1 1 1 1 0 169.58 1 1 1 1 1 203.49 HTT66 PCI33 (MHz) (MHz) Hi-Z X/12 60.00 73.33 66.67 66.67 66.67 66.67 62.00 71.33 63.33 70.00 68.00 68.00 68.00 68.00 56.53 76.48 59.85 73.15 66.50 66.50 66.50 66.50 61.85 71.16 63.18 69.83 67.83 67.83 67.83 67.83 0937H—05/26/05 6 Hi-Z X/24 30.00 36.67 33.33 33.33 33.33 33.33 31.00 35.67 31.67 35.00 34.00 34.00 34.00 34.00 28.26 38.24 29.93 36.58 33.25 33.25 33.25 33.25 30.92 35.58 31.59 34.91 33.92 33.91 33.92 33.92 Spread % None None None None None None None None None None None None None None None None -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% ICS951416 Table2: SRC & ATIG Frequency Selection Table Byte 5 Bit4 Bit3 Bit2 Bit1 Bit0 SRC(7:3,0), Spread SRC ATIG(1:0) % FS4 SRC SRC SRC SRC (MHz) Spread FS3 FS2 FS1 FS0 Enable 0 0 0 0 0 0 100.00 0 0 0 0 0 1 100.00 0 0 0 0 1 0 100.00 0 0 0 0 1 1 100.00 0 0 0 1 0 0 101.00 0 0 0 1 0 1 101.00 0 0 0 1 1 0 101.00 0 0 0 1 1 1 101.00 0 0 1 0 0 0 102.00 0 0 1 0 0 1 102.00 0 0 1 0 1 0 102.00 0 0 1 0 1 1 102.00 0 0 1 1 0 0 104.00 0 0 1 1 0 1 104.00 0 0 1 1 1 0 104.00 0 0 1 1 1 1 104.00 -0.5% 1 0 0 0 0 99.75 -0.5% 1 0 0 0 1 99.75 -0.5% 1 0 0 1 0 99.75 -0.5% 1 0 0 1 1 99.75 -0.5% 1 0 1 0 0 100.74 -0.5% 1 0 1 0 1 100.74 -0.5% 1 0 1 1 0 100.74 -0.5% 1 0 1 1 1 100.74 -0.5% 1 1 0 0 0 101.74 -0.5% 1 1 0 0 1 101.74 -0.5% 1 1 0 1 0 101.74 -0.5% 1 1 0 1 1 101.74 -0.5% 1 1 1 0 0 103.74 -0.5% 1 1 1 0 1 103.74 -0.5% 1 1 1 1 0 103.74 -0.5% 1 1 1 1 1 103.74 0937H—05/26/05 7 SRC OverClock 1.00 1.00 1.00 1.00 1.01 1.01 1.01 1.01 1.02 1.02 1.02 1.02 1.04 1.04 1.04 1.04 1.00 1.00 1.00 1.00 1.01 1.01 1.01 1.01 1.02 1.02 1.02 1.02 1.04 1.04 1.04 1.04 ICS951416 Table 3: CPU Divider Ratios Divider (1:0) Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 2 3 5 15 Div 01 0100 0101 0110 0111 Address 4 3 5 15 Div 01 0100 0101 0110 0111 Address 2 3 5 7 Div 01 0100 0101 0110 0111 Address 4 6 10 30 Div 10 1000 1001 1010 1011 Address 8 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 120 Div 10 1000 1001 1010 1011 Address 16 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 32 24 40 120 Div 10 1000 1001 1010 1011 Address 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 56 Div Table 4: HTT Divider Ratios Divider (1:0) Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 8 6 10 30 Div Table 5: SRC, ATIG Divider Ratios Divider (1:0) Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 4 6 10 14 Div Table 6: Group Skews Parameter Description Test Conditions m e Tsk_CPU_CPU I n d e p e n e T i m e V a r i a n t Measured at crossing CPU to CPU Skew points of CPUCLKT rising edges Meastured at crossing Tsk_CPU_PCI CPU to PCI skew point for CPUCLKT and 1.5V for PCI clock Measured between rising Tsk_PCI33-HT66 PCI33 to HT66 skew edges at 1.5V Meastured at crossing Tsk_CPU_HT66 CPU to HT66 skew point for CPUCLKT and 1.5V for HT66 clock Measured at crossing Tsk_CPU_CPU CPU to CPU Skew points of CPUCLKT rising edges Meastured at crossing Tsk_CPU_PCI CPU to PCI skew point for CPUCLKT and 1.5V for PCI clock Measured between rising Tsk_PCI33-HT66 PCI33 to HT66 skew edges at 1.5V Meastured at crossing Tsk_CPU_HT66 CPU to HT66 skew point for CPUCLKT and 1.5V for HT66 clock Meastured at crossing Tsk_SRC_SRC SRC to SRC skew point for SRCCLKT 0937H—05/26/05 8 Skew Unit Window 250 ps 2000 ps 500 ps 2000 ps 200 ps 200 ps 200 ps 200 ps N/A ps ICS951416 SMBus Table: Frequency Select Register Byte 0 Pin # Name Control Function Type Latched Input or SMBus RW Frequency Select Bit 7 - FS Source Bit 6 Bit 5 Bit 4 Bit 3 - SS_EN Reserved FS4 FS3 PLL Spread Enable Reserved Freq Select Bit 4 Freq Select Bit 3 RW RW RW RW Bit 2 - FS2 Freq Select Bit 2 RW Bit 1 - FS1 Freq Select Bit 1 RW Bit 0 - FS0 Freq Select Bit 0 RW 0 1 PWD Latched Inputs SMBus 0 OFF Reserved ON Reserved 0 0 0 0 See Table 1: CPU Frequency Selection Latched Latched Latched Note: Byte 0 Bit 6, Byte 0 Bit 4 and Byte 5 Bit 4 must be set to '1' to fully enable spread. SMBus Table: Output Control Register Byte 1 Pin # Name Control Function PCICLK0 Output Enable 50 Bit 7 47 HTTCLK0 Output Enable Bit 6 4 USB_48MHz Output Enable Bit 5 54 REF0 Output Enable Bit 4 53 REF1 Output Enable Bit 3 52 REF2 Output Enable Bit 2 45,44 CPUCLK8(0) Output Enable Bit 1 41,40 CPUCLK8(1) Output Enable Bit 0 SMBus Table: CLKREQB# Output Control Register Pin # Name Control Function Byte 2 CLKREQB# Controls 12,13 REQBSRC7 Bit 7 SRC7 CLKREQB# Controls 16,17 REQBSRC6 Bit 6 SRC6 CLKREQB# Controls 18,19 REQBSRC5 Bit 5 SRC5 CLKREQB# Controls REQBSRC4 22,23 Bit 4 SRC4 CLKREQB# Controls REQBSRC3 24,25 Bit 3 SRC3 Reserved Reserved Bit 2 Reserved Reserved Bit 1 CLKREQB# Controls 34,33 REQBSRC0 Bit 0 SRC0 0937H—05/26/05 9 Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Type 0 Does not control Does not control Does not control Does not control Does not control Reserved Reserved Does not control 1 PWD Controls 0 Controls 0 Controls 0 Controls 0 Controls 0 Reserved Reserved X X Controls 0 RW RW RW RW RW RW RW RW ICS951416 SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register Byte 3 0 Pin # Name Control Function Type 12,13 SRCCLK7 RW Disable Bit 7 Master Output control. RW 16,17 SRCCLK6 Disable Bit 6 Enables or disables SRCCLK5 RW Disable 18,19 Bit 5 output, regardless of SRCCLK4 RW Disable 22,23 Bit 4 CLKREQ# inputs. SRCCLK3 RW Disable 24,25 Bit 3 SRCCLK0 RW Disable 34,33 Bit 2 CLKREQA# Controls Does not 24,25 REQASRC3 RW Bit 1 SRC3 control CLKREQA# Controls Does not 34,33 REQASRC0 RW Bit 0 SRC0 control SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register Byte 4 Pin # Name Control Function Type 0 CLKREQA# Controls Does not 12,13 REQASRC7 RW Bit 7 SRC7 control CLKREQA# Controls Does not 16,17 REQASRC6 RW Bit 6 SRC6 control CLKREQA# Controls Does not 18,19 REQASRC5 RW Bit 5 SRC5 control CLKREQA# Controls Does not 22,23 REQASRC4 RW Bit 4 SRC4 control Output Enable 27,28 ATIGCLK1 RW Disabled Bit 3 These outputs cannot be controlled by CLKREQ# 30,29 ATIGCLK0 RW Disabled Bit 2 pins. Reserved Reserved RW Reserved Bit 1 4 USB_48Str 48MHz Strength Control RW 1X Bit 0 1 Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 Controls 0 Controls 0 1 PWD Controls 0 Controls 0 Controls 0 Controls 0 Enabled 1 Enabled 1 Reserved 2X 0 0 Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output. Behavior of the device is undefined under these conditions. SMBus Table: Output Drive and ATIG Frequency Control Register 0 Byte 5 Pin # Name Control Function Type 52 Control RW 1X REF2Str REF2 Strength Bit 7 Reserved Reserved RW Reserved Bit 6 Reserved Reserved RW Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - SRCFS4 SSEN SRCFS3 SRCFS2 SRCFS1 SRCFS0 Freq Select Bit 4 Spread Enable RW Freq Select Freq Select Freq Select Freq Select RW RW RW RW Bit Bit Bit Bit 0937H—05/26/05 10 3 2 1 0 1 2X Reserved Reserved PWD 0 0 0 0 See Table 2: SRC Frequency Selection 0 0 0 0 ICS951416 SMBus Table: Device ID Register Byte 6 Pin # Name DevID 7 Bit 7 DevID 6 Bit 6 DevID 5 Bit 5 DevID 4 Bit 4 DevID 3 Bit 3 DevID 2 Bit 2 DevID 1 Bit 1 DevID 0 Bit 0 SMBus Table: Vendor ID Register Pin # Name Byte 7 RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBus Table: Byte Count Register Byte 8 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device ID MSB Device ID 6 Device ID 5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID LSB Type R R R R R R R R 0 - 1 - PWD 0 0 0 1 0 1 1 0 Control Function Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 Revision ID VENDOR ID (0001 = ICS) Control Function Byte Count Programming b(7:0) Type 0 1 RW RW RW Writing to this register RW will configure how many RW bytes will be read back, default is 9 bytes. RW RW RW SMBus Table: WD TimeR Control Register 0 1 Pin # Name Control Function Type Byte 9 Watchdog Hard Alarm WDH_EN RW Disable Enable Bit 7 Enable Watchdog Soft Alarm WDS_EN RW Disable Enable Bit 6 Enable WD Hard Status WD Hard Alarm Status R Normal Alarm Bit 5 WD Soft Status WD Soft Alarm Status R Normal Alarm Bit 4 Watch Dog Time base 290ms 1160ms WDTCtrl RW Bit 3 Control Base Base These bits represent WD2 WD Timer Bit 2 RW Bit 2 WD1 WD Timer Bit 1 RW X*290ms (or 1.16S) the Bit 1 watchdog timer waits WD0 WD Timer Bit 0 RW Bit 0 0937H—05/26/05 11 PWD 0 0 0 0 1 0 0 1 PWD 0 0 X X 0 1 1 1 ICS951416 SMBus Table: M/N Programming & WD Safe Frequency Control Register 0 1 Pin # Name Control Function Type Byte 10 CPU/SRC M/N M/N_EN RW Disable Enable Bit 7 Programming Enable Reserved Reserved RW Bit 6 WD Safe Freq Latch WD Safe Freq Source RW B10b(4:0) Bit 5 Source Inputs WD SF4 RW Bit 4 Writing to these bit will WD SF3 RW Bit 3 configure the safe Watch Dog Safe Freq WD SF2 RW Bit 2 frequency as Byte0 bit Programming bits WD SF1 RW Bit 1 (4:0). WD SF0 RW Bit 0 PWD 0 0 0 0 0 0 0 0 SMBus Table: CPU Frequency Control Register Byte 11 Pin # Name Control Function Type 0 1 The decimal RW N Div8 N Divider Prog bit 8 Bit 7 N Div9 N Divider Prog bit 9 RW representation of M and Bit 6 M Div5 RW N Divier in Byte 11 and Bit 5 12 will configure the M Div4 RW Bit 4 M Divider Programming CPU VCO frequency. M Div3 RW Bit 3 bit (5:0) Default at power up = M Div2 RW Bit 2 M Div1 RW latch-in or Byte 0 Rom Bit 1 M Div0 RW table. VCO Frequency = Bit 0 PWD X X X X X X X X SMBus Table: CPU Frequency Control Register Pin # Name Control Function Type 0 1 Byte 12 The decimal N Div7 RW Bit 7 N Div6 RW representation of M and Bit 6 N Div5 RW N Divier in Byte 11 and Bit 5 N Divider Programming 12 will configure the N Div4 RW Bit 4 Byte12 bit(7:0) and CPU VCO frequency. N Div3 RW Bit 3 Byte11 bit(7:6) Default at power up = N Div2 RW Bit 2 N Div1 RW latch-in or Byte 0 Rom Bit 1 N Div0 RW table. VCO Frequency = Bit 0 PWD X X X X X X X X SMBus Table: CPU Spread Spectrum Control Register Pin # Name Control Function Byte 13 SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum SSP4 Bit 4 Programming bit(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 PWD X X X X X X X X 0937H—05/26/05 12 Type 0 1 RW RW RW These Spread Spectrum RW bits in Byte 13 and 14 RW will program the spread pecentage of CPU RW RW RW ICS951416 SMBus Table: CPU Spread Spectrum Control Register Pin # Name Control Function Byte 14 Reserved Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum SSP11 Bit 3 Programming bit(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 0 1 Type R RW RW These Spread Spectrum RW bits in Byte 13 and 14 RW will program the spread RW pecentage of CPU RW RW PWD 0 X X X X X X X SMBus Table: SRC Frequency Control Register Pin # Name Control Function Type Byte 15 0 1 RW N Div8 N Divider Prog bit 8 The decimal Bit 7 N Div9 N Divider Prog bit 9 RW representation of M and Bit 6 M Div5 RW N Divier in Byte 15 and Bit 5 16 will configure the M Div4 RW Bit 4 M Divider Programming RW SRC VCO frequency. M Div3 Bit 3 bits Default at power up = M Div2 RW Bit 2 M Div1 RW latch-in or Byte 0 Rom Bit 1 M Div0 RW table. VCO Frequency Bit 0 PWD X X X X X X X X SMBus Table: SRC Frequency Control Register Byte 16 0 1 Pin # Name Control Function Type The decimal N Div7 RW Bit 7 N Div6 RW representation of M and Bit 6 N Div5 RW N Divier in Byte 15 and Bit 5 N Divider Programming 16 will configure the N Div4 RW Bit 4 b(7:0) SRC VCO frequency. N Div3 RW Bit 3 Default at power up = N Div2 RW Bit 2 N Div1 RW latch-in or Byte 0 Rom Bit 1 N Div0 RW table. VCO Frequency = Bit 0 PWD X X X X X X X X SMBus Table: SRC Spread Spectrum Control Register Byte 17 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum SSP4 Bit 4 Programming b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 PWD X X X X X X X X 0937H—05/26/05 13 Type 0 1 RW RW RW These Spread Spectrum RW bits in Byte 17 and 18 RW will program the spread pecentage of SRC RW RW RW ICS951416 SMBus Table: SRC Spread Spectrum Control Register Pin # Name Control Function Byte 18 Reserved Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum SSP11 Bit 3 Programming b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 Type 0 1 R RW RW These Spread Spectrum RW bits in Byte 17 and 18 RW will program the spread RW pecentage of SRC RW RW PWD 0 X X X X X X X SMBus Table: Programmable Output Divider Register Byte 19 Pin # Name Control Function CPUDiv3 Bit 7 CPU Divider Ratio CPUDiv2 Bit 6 Programming Bits CPUDiv1 Bit 5 CPUDiv0 Bit 4 HTT Divider Ratio HTTDiv3 Bit 3 Programming Bits (PCI HTTDiv2 Bit 2 divider is always 2x the HTTDiv1 Bit 1 HTT divider or 1/2 freq.) HTTDiv0 Bit 0 Type RW RW RW RW RW RW RW RW PWD X X X X X X X X SMBus Table: Programmable Output Divider Register Pin # Name Control Function Byte 20 SRC_Div3 Bit 7 SRC_ Divider Ratio SRC_Div2 Bit 6 Programming Bits SRC_Div1 Bit 5 SRC_Div0 Bit 4 ATIG_Div3 Bit 3 ATIG_ Divider Ratio ATIG_Div2 Bit 2 Programming Bits ATIG_Div1 Bit 1 ATIG_Div0 Bit 0 Type 0 1 RW RW RW RW See Table 5: SRC and ATIG Divider Ratios RW RW RW RW 0937H—05/26/05 14 0 1 See Table 3: CPU Divider Ratios See Table 4: HTT Divider Ratios PWD X X X X X X X X ICS951416 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5% 2 Input Low Voltage Input High Current VIL IIH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors all outputs driven VDD = 3.3 V VSS - 0.3 -5 I IL1 Input Low Current I IL2 Operating Current Input Frequency 3 Pin Inductance1 1 Input Capacitance Clk Stabilization1,2 Modulation Frequency SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time3 SCLK/SDATA Clock/Data Fall Time3 IDD3.3OP Fi Lpin CIN COUT CINX TSTAB VDD VOL Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD# to 1st clock Triangular Modulation TYP VDD + 0.3 0.8 5 UNITS NOTES V 1 V uA 1 1 -5 uA 1 -200 uA 1 7 5 6 5 mA MHz nH pF pF pF 3 1 1 1 1 3 ms 1,2 33 5.5 0.4 kHz V V mA 1 1 1 1 300 14.31818 30 2.7 @ I PULLUP IPULLUP MAX 4 TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1 Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2 0937H—05/26/05 15 ICS951416 Electrical Characteristics - K8 Push Pull Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load PARAMETER SYMBOL CONDITIONS Rising Edge Rate δV/δt Falling Edge Rate δV/δt Measured at the AMD64 processor's test load. 0 V +/- 400 mV (differential measurement) Differential Voltage Change in VDIFF_DC Magnitude VDIFF VCM Change in Common Mode Voltage ∆VCM Jitter, Cycle to cycle tjcyc-cyc 2 10 V/ns 1 2 10 V/ns 1 V 1 mV 1 V 1 200 mV 1 100 200 ps 1 0.4 ∆VDIFF Common Mode Voltage MIN TYP MAX UNITS NOTES -150 Measured at the AMD64 processor's test load. (single-ended measurement) 150 1.05 1.25 1.45 -200 Measurement from differential wavefrom. Maximum difference of cycle time between 2 adjacent cycles. 1.25 2.3 0 Measured using the JIT2 software package with a Tek 7404 scope. TIE (Time Interval Error) measurement tja -1000 1000 Jitter, Accumulated technique: Sample resolution = 50 ps, Sample Duration = 10 µs Measurement from differential dt3 Duty Cycle 45 53 wavefrom Average value during switching RON 35 55 Output Impedance transition. Used for determining series 15 termination value. Measurement from differential tsrc-skew Group Skew 250 wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz 3 Spread Spectrum is off 0937H—05/26/05 16 1,2,3 % 1 Ω 1 ps 1 ICS951416 Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Vovs Vuds Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf MAX UNITS NOTES Ω 1 850 1,3 mV -150 150 1150 -300 250 Variation of crossing over all edges see Tperiod min-max values 75.00 MHz nominal 75.00 MHz spread 100.00 MHz nominal 100.00 MHz spread 116.67 MHz nominal 116.67 MHz spread 133.33 MHz nominal 133.33 MHz spread @100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP -300 8.5684 8.5684 9.9970 9.9970 13.3303 13.3303 7.4972 7.4972 9.8720 175 175 1,3 mV 1 1 350 550 mV 1 12 140 mV 1 ppm ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 1,2 1 1 1 1 300 8.5744 8.6244 10.0000 10.0030 10.0530 13.3333 13.3363 13.3863 7.5002 7.5032 7.5532 8.5714 30 30 700 700 125 125 Measurement from differential 45 55 % 1 wavefrom Measurement from differential tsrc-skew Group Skew 250 ps wavefrom Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 100 ps 1 wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. Duty Cycle dt3 0937H—05/26/05 17 ICS951416 Electrical Characteristics - PCI33, HTT66 Clocks TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm PCI33 Clock period Tperiod HTT66 Clock period Tperiod Output High Voltage Output Low Voltage VOH VOL see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 66.67MHz output nominal 66.67MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V -300 29.9910 29.9910 14.9955 14.9955 2.4 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter, Cycle to cycle δV/δt δV/δt tr1 tf1 dt1 tsk1 tjcyc-cyc Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 1 -33 -50 47 58 1 1 0.5 0.5 45 TYP MAX 300 30.0090 30.1598 15.0045 15.0799 0.55 -46 -80 64 91 4 4 2 2 55 500 180 UNITS Notes ppm ns ns ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz 2 0937H—05/26/05 18 1,2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 ICS951416 Electrical Characteristics - 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Clock period Output High Voltage Output Low Voltage ppm Tperiod VOH VOL -200 20.8257 2.4 Output High Current IOH Output Low Current IOL Edge Rate Edge Rate δV/δt δV/δt tr1 tf1 dt1 tjcyc-cyc see Tperiod min-max values 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH@ MAX = 3.135 V VOL @MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle 1 TYP 200 20.8340 -33 -50 47 58 1 1 1 1 45 MAX 1.43 1.33 48 UNITS Notes 0.55 -46 -80 64 91 2 2 ppm ns V V mA mA mA mA V/ns V/ns 1,2 2 1 1 1 1 1 1 1 1 2 2 55 180 ns ns % ps 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz 2 0937H—05/26/05 19 ICS951416 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy see Tperiod min-max values -300 300 ppm 69.8270 69.8550 ns 2 V 1 0.4 V 1 mA 1 mA 1 Clock period ppm Tperiod Output High Voltage VOH 14.318MHz output nominal IOH = -1 mA Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL Edge Rate Edge Rate TYP MAX 2.4 UNITS Notes 1 V OH @MIN = 1.0 V -29 -41 V OH@MAX = 3.135 V VOL @MIN = 1.95 V -45 -71 39 54 VOL @MAX = 0.4 V 49 77 δV/δt Rising edge rate 1 4 V/ns 1 δV/δt tr1 Falling edge rate VOL = 0.4 V, VOH = 2.4 V 1 4 V/ns 1 1 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Skew tsk1 VT = 1.5 V 500 ps 1 Duty Cycle dt1 VT = 1.5 V 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 700 ps 1 Rise Time 1 45 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz 2 0937H—05/26/05 20 ICS951416 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non -coupled 50 ohm trace. 0.5 max L2 length, Route as non -coupled 50 ohm trace. 0.2 max L3 length, Route as non -coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coup led stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Rout e as coupled stripline 100 ohm differential trace. L1 Unit inch inch inch ohm ohm Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Dimension or Value 2 min to 16 max Unit inch 2 1.8 min to 14.4 max inch 2 Dimension or Value 0.25 to 14 max Unit inch 3 0.225 min to 12.6 max inch 3 Figure L2 L4 Rs L1’ L4’ L2’ Rs Fig.1 Figure Rt HSCL Output Buffer Rt L3’ L1 PCI Ex REF_CLK Test Load L3 L2 L4 Rs L1’ Fig.2 L4’ L2’ Rs Rt HSCL Output Buffer L3’ L1 Rt PCI Ex Board Down Device REF_CLK Input L3 L2 L4 Rs L4’ L1’ L2’ Rs Fig.3 Rt HSCL Output Buffer L3’ 0937H—05/26/05 21 Rt L3 PCI Ex Add In Board REF_CLK Input ICS951416 Shared Pin Operation Input/Output Pins The I/O pins designated by (input/output) on the ICS951416 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 0937H—05/26/05 22 ICS951416 56-Lead, 300 mil Body, 25 mil, SSOP c N SYMBOL L E1 INDEX AREA E 1 2 α h x 45° D In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS A N A1 -Ce A A1 b c D E E1 e h L N a In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE b .10 (.004) C 56 D mm. MIN 18.31 D (inch) MAX 18.55 MIN .720 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS951416yFLFT Example: ICS XXXX y F - LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device 0937H—05/26/05 23 MAX .730 ICS951416 c N L E1 INDEX AREA E 1 2 a D A A2 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS A1 -Ce b SEATING PLANE aaa C N 56 D mm. MIN 13.90 D (inch) MAX 14.10 MIN .547 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information ICS951416yGLFT Example: ICS XXXX y G - LF T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device 0937H—05/26/05 24 MAX .555 ICS951416 Revision History Rev. D E F G H Issue Date Description 11/11/2004 Changes Pull Down Symbol from ~ to ** 12/8/2004 Update CPU and SRC frequency selection table. Page # 1,2,3 6,7 1. Updated the Electrical Characteristics for HTT. 4/22/2005 2. Updated Ordering Information from "Lead Free" to "Annealed Lead Free". 18,23-24 4/29/2005 Updated the Electrical Characteristics for REF and USB. 19, 20 1. Changed Byte 10 bit 7 to "CPU/SRC M/N Programming Bit. 5/26/2005 2. Updated LF Ordering Information to "RoHS Compliant" 12, 23-24 0937H—05/26/05 25 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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