ICS954204BGLF

954204 Datasheet Programmable Timing Control Hub™ for Mobile P4™ Systems Recommended Application: CK410M Compliant Main Clock with Integrated LCD Spread Spectrum Clock. • PCI outputs cycle-cycle jitter < 500ps • +/- 300ppm frequency accuracy on CPU & SRC clocks • +/- 100ppm frequency accuracy on USB clocks Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and SRC • Supports programmable spread percentage and frequency Output Features: • 2 - 0.7V current-mode differential CPU pairs • 5 - 0.7V current-mode differential SRC pair for SATA and PCI-E • 1 - 0.7V current-mode differential CPU/SRC selectable pair • 4 - PCI (33MHz) • 2 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz • 1 - 0.7V current-mode differential LCD/SRC selectable pair. • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. • CLKREQ pins to support SRC power management. Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC outputs cycle-cycle jitter < 125ps Functionality VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 *SELSRC_LCDCLK#/PCICLK_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE LCDCLK_SST/SRCCLKT0 LCDCLK_SSC/SRCCLKC0 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS954204 Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCICLK2 PCI/SRC_STOP# CPU_STOP# FSLC/TEST_SEL REFOUT GND X1 X2 VDDREF SDATA SCLK GND 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU MHz 266.67 133.33 200.00 166.67 333.33 100.00 400.00 200.00 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the CPUCLKT0 Input/Supply/Common Output Parameters Table for correct values. Also refer CPUCLKC0 VDDCPU to the Test Clarification Table. CPUCLKT1 FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS 2. CPUCLKC1 specifications in the Input/Supply/Common Output Parameters Table for IREF correct values. GNDA VDDA CPUCLKT2_ITP/SRCCLKT7 CPUCLKC2_ITP/SRCCLKC7 VDDSRC CLKREQA#* CLKREQB#* SRCCLKT5 SRCCLKC5 GND 56-pin TSSOP *100Kohm Pull-Up Resistor 0933E—11/21/17 FS_C FS_B FS_A 954204 Datasheet Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 2 3 4 5 6 7 VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PWR PWR OUT OUT OUT PWR PWR 8 ITP_EN/PCICLK_F0 I/O 9 *SELSRC_LCDCLK#/PCICLK_F1 I/O 10 Vtt_PwrGd#/PD IN 11 VDD48 12 FSLA/USB_48MHz 13 14 15 GND DOTT_96MHz DOTC_96MHz 16 FSLB/TEST_MODE 17 LCDCLK_SST/SRCCLKT0 OUT 18 LCDCLK_SSC/SRCCLKC0 OUT 19 20 21 22 23 24 25 26 27 28 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR PWR I/O PWR OUT OUT IN Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair Latched input select for LCD_ss/ SRCCLK output frequency: 0 = LCD, 1 = SRCCLK/ 3.3V free-running PCI clock output. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK_SS output / True clock of SRCCLK differential pair. Selected by SEL_LCDCLK# Complementary clock of LCDCLK_SS output / Complementary clock of SRCCLK differential pair. Selected by SEL_LCDCLK# True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC/SATA pair. Complement clock of differential SRC/SATA pair. Supply for SRC clocks, 3.3V nominal 0933E—11/21/17 2 954204 Datasheet Pin Description (Continued) PIN # PIN NAME Type Pin Description 29 30 31 GND SRCCLKC5 SRCCLKT5 PWR OUT OUT 32 CLKREQB#* IN 33 CLKREQA#* IN 34 VDDSRC PWR 35 CPUCLKC2_ITP/SRCCLKC7 OUT 36 CPUCLKT2_ITP/SRCCLKT7 OUT 37 38 VDDA GNDA PWR PWR Ground pin. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Supply for SRC clocks, 3.3V nominal Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. 3.3V power for the PLL core. Ground pin for the PLL core. 39 IREF 40 IN This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. CPUCLKC1 OUT Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. 41 CPUCLKT1 OUT 42 VDDCPU PWR 43 CPUCLKC0 OUT 44 CPUCLKT0 OUT 45 46 47 48 49 50 51 52 GND SCLK SDATA VDDREF X2 X1 GND REFOUT PWR IN I/O PWR OUT IN PWR OUT True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. Reference Clock output 53 FSLC/TEST_SEL IN 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 54 CPU_STOP# IN Stops all CPUCLK, except those set to be free running clocks 55 PCI/SRC_STOP# IN Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0 level, when input low 56 PCICLK2 *Pins 32 and 33 have pull-ups. OUT PCI clock output. 0933E—11/21/17 3 954204 Datasheet General Description 954204 is a CK410M Compliant clock synthesizer. 954204 provides a single-chip solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. 954204 is driven with a 14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express. Block Diagram REFOUT USB_48MHz X1 X2 XTAL OSC. FIXED PLL DIVIDER DOT_96MHz PCICLK(5:2) PCICLK_F(1:0) PROG. SPREAD MAIN PLL SRCCLK(5:1) PROG. DIVIDERS CPUCLK2_ITP/SRCCLK7 CPUCLK(1:0) PCI/SRC_STOP# CPU_STOP# FSL(C:A) ITP_EN TEST_MODE VTT_PWRGD#/PD CLKREQ#A/B SDATA SCLK SelSRC/LCDCLK# LCDCLKSS/SRCCLK0 CONTROL LOGIC IREF 0933E—11/21/17 4 954204 Datasheet General SMBus serial interface information for the 954204 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0933E—11/21/17 5 Not acknowledge stoP bit 954204 Datasheet Absolute Max Symbol Parameter Min VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 Ts Storage Temperature -65 0 Tambient Ambient Operating Temp Tcase Case Temperature Input ESD protection ESD prot 2000 human body model Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V ° C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage SYMBOL VIH CONDITIONS 3.3 V +/-5% Input Low Voltage Input High Current VIL IIH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors IIL1 Input Low Current IIL2 Low Threshold Input High Voltage VIH_FS Low Threshold Input Low Voltage Operating Supply Current IDD3.3OP Powerdown Current IDD3.3PD Input Frequency3 Pin Inductance1 Fi Lpin CIN COUT CINX Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Tdrive_SRC Tdrive_PD Tfall_PD Trise_PD Tdrive_CPU_STOP TSTAB MIN 2 VSS - 0.3 -5 TYP MAX VDD + 0.3 UNITS V NOTES 1 0.8 5 V uA 1 1 -5 uA 1 -200 uA 1 3.3 V +/-5% 0.7 VDD + 0.3 V 1 3.3 V +/-5% VSS - 0.3 0.35 V 1 400 70 12 7 5 6 5 mA mA mA MHz nH pF pF pF 3 1 1 1 1 1.8 ms 1,2 33 kHz 1 10 ns 1 300 us 1 5 5 ns ns 1 2 10 ns 1 5 5 5.5 0.4 1000 ns ns V V mA ns 1 2 1 1 1 1,3 300 ns 1,3 Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation SRC output enable after PCI_STOP de-assertion Differential output enable after PD# de-assertion PD# fall time of PD# rise time of CPU output enable after CPU_STOP de-assertion CPU_STOP fall time of CPU_STOP rise time of 275 64 5 14.31818 1.3 30 Tfall_CPU_STOP Trise_CPU_STOP# VDD SMBus Voltage 2.7 VOL SDATA, SCLK @ IPULLUP Low-level Output Voltage IPULLUP VOL = 0.4 V Current sinking 4 TRI2C (Max VIL - 0.15) to SCLK/SDATA SCLK/SDATA (Min VIH + 0.15) to TFI2C Clock/Data Fall Time (Max VIL - 0.15) 1 Guaranteed by design, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet 0933E—11/21/17 6 954204 Datasheet Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min/max period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabs tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 400MHz non-spread 400MHz spread 333.33MHz non-spread 333.33MHz spread 266.66MHz non-spread 266.66MHz spread 200MHz non-spread 200MHz spread 166.66MHz non-spread 166.66MHz spread 133.33MHz non-spread 133.33MHz spread 100.00MHz non-spread 100.00MHz spread 400MHz non-spread 400MHz spread 333.33MHz non-spread 333.33MHz spread 266.66MHz non-spread 266.66MHz spread 200MHz non-spread 200MHz spread 166.66MHz non-spread 166.66MHz spread 133.33MHz non-spread 133.33MHz spread 100.00MHz non-spread 100.00MHz spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP 750 MAX dt3 0933E—11/21/17 7 NOTES  1 850 1,3 mV -150 0 150 790 0 390 1150 -300 250 550 mV 1 1 1 50 140 mV 1 310 305 20 15 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 2.5750 2.5983 3.0859 3.1010 3.8361 3.8550 5.0865 5.1116 6.0868 6.1170 7.5873 7.6250 10.0880 10.1383 700 700 125 125 ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.9120 175 175 Measurement from differential 45 50 55 wavefrom CPU(1:0), VT = 50% 20 100 tsk3 Skew CPU2_ITP, VT = 50% 90 150 Differential waveform tjcyc-cyc Jitter, Cycle to cycle 35 85 measurement, CPU(1:0) Differential waveform tjcyc-cyc 45 125 Jitter, Cycle to cycle measurement, CPU2_ITP 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. Duty Cycle UNITS 1,3 mV % 1 ps ps 1 1 ps 1 ps 1 954204 Datasheet Electrical Characteristics - SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF PARAMETER SYMBOL CONDITIONS MIN TYP MAX Current Source Output 1 V = V 3000 Zo O x Impedance Statistical measurement on single VHigh 660 750 850 Voltage High ended signal using oscilloscope VLow -150 0 150 Voltage Low Measurement on single ended Vovs 790 1150 Max Voltage signal using absolute value. Vuds -300 0 Min Voltage Vcross(abs) 250 350 550 Crossing Voltage (abs) Variation of crossing over all 12 140 Crossing Voltage (var) d-Vcross edges see Tperiod min-max values Long Accuracy ppm -300 300 10.0030 100.00MHz non-spread Tperiod Average period 9.9970 10.0533 100.00MHz spread 10.1280 100.00MHz non-spread Tabs 9.8720 Absolute min/max period 10.1783 100.00MHz spread tr VOL = 0.175V, VOH = 0.525V Rise Time 175 308 700 VOH = 0.525V, VOL = 0.175V tf 175 310 700 Fall Time d-tr 30 125 Rise Time Variation d-tf 30 125 Fall Time Variation Measurement from differential dt3 Duty Cycle 45 50 55 wavefrom VT = 50% tsk3 100 250 Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 40 125 wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. UNITS  Notes 1 mV 1,3 1,3 1 1 1 mV 1 ppm ns ns ns ns ps ps ps ps 1,2 2 2 1,2 1,2 1 1 1 1 % 1 ps 1 ps 1 UNITS Notes mV mV Electrical Characteristics - LCD_SS 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF PARAMETER SYMBOL CONDITIONS MIN TYP Current Source Output 1 VO = Vx 3000 Zo Impedance Statistical measurement on single Voltage High VHigh 660 750 ended signal using oscilloscope Voltage Low VLow -150 0 Measurement on single ended Max Voltage Vovs 790 signal using absolute value. Min Voltage Vuds -300 0 Crossing Voltage (abs) Vcross(abs) 250 350 Variation of crossing over all 12 Crossing Voltage (var) d-Vcross edges tr VOL = 0.175V, VOH = 0.525V Rise Time 175 308 VOH = 0.525V, VOL = 0.175V tf 175 310 Fall Time d-tr 30 Rise Time Variation d-tf 30 Fall Time Variation Measurement from differential dt3 45 50 Duty Cycle wavefrom tsk3 VT = 50% Skew 100 Measurement from differential t 40 Jitter, Cycle to cycle jcyc-cyc wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 0933E—11/21/17 8 MAX  850 150 1150 1 550 mV 1,2 1,2 1 1 1 140 mV 1 700 700 125 125 ps ps ps ps 1 1 1 1 55 % 1 250 ps 1 125 ps 1 mV mV 954204 Datasheet Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 33.33MHz output non-spread Tperiod Clock period 33.33MHz output spread 33.33MHz output non-spread Tabs Absolute min/max period 33.33MHz output spread VOH IOH = -1 mA Output High Voltage VOL IOL = 1 mA Output Low Voltage V OH = 1.0 V IOH Output High Current VOH = 3.135 V VOL = 1.95 V IOL Output Low Current VOL = 0.4 V Rising edge rate Edge Rate Falling edge rate Edge Rate tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time dt1 VT = 1.5 V Duty Cycle tsk1 VT = 1.5 V Skew VT = 1.5 V tjcyc-cyc Jitter MIN -300 TYP 29.9910 29.4910 MAX 300 30.0090 30.1598 30.5090 30.6598 2.4 0.55 -33 -33 30 1 1 0.5 0.5 45 1.37 1.6 50 50 95 38 4 4 2 2 55 500 500 UNITS ppm ns ns ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps Notes 1,2 2 2 1,2 1,2 1 1 1 1 1 1 1 1 1 1 1 1 1 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps Notes 1,2 2 1,2 1 1 1 1 1 1 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 2 Electrical Characteristics - 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy Tperiod Clock period 48.00000 MHz output Tabs Absolute min/max period 48.00000 MHz output VOH IOH = -1 mA Output High Voltage VOL IOL = 1 mA Output Low Voltage VOH = 1.0 V IOH Output High Current VOH = 3.135 V VOL = 1.95 V IOL Output Low Current VOL = 0.4 V Rising edge rate Edge Rate Edge Rate Falling edge rate tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time dt1 VT = 1.5 V Duty Cycle VT = 1.5 V tjcyc-cyc Jitter, Cycle to cycle 1 MIN -100 20.83125 20.4813 2.4 TYP MAX 100 20.83542 21.1854 0.55 -29 -23 29 1 1 1 1 45 1.8 1.6 1.43 1.33 48 150 27 2 2 2 2 55 350 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 2 0933E—11/21/17 9 954204 Datasheet Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF PARAMETER SYMBOL CONDITIONS MIN TYP MAX Current Source Output 1 V = V 3000 Zo O x Impedance Statistical measurement on single VHigh 660 790 850 Voltage High ended signal using oscilloscope VLow -150 0 150 Voltage Low Measurement on single ended Vovs 810 1150 Max Voltage signal using absolute value. Vuds -300 0 Min Voltage Crossing Voltage (abs) Vcross(abs) 250 400 550 Variation of crossing over all 10 140 Crossing Voltage (var) d-Vcross edges see Tperiod min-max values Long Accuracy ppm -100 100 Tperiod Average period 96.00MHz 10.4135 10.4198 Tabs Absolute min/max period 96.00MHz 10.1635 10.6698 VOL = 0.175V, VOH = 0.525V tr 175 250 700 Rise Time tf VOH = 0.525V, VOL = 0.175V Fall Time 175 240 700 d-tr 15 125 Rise Time Variation d-tf Fall Time Variation 30 125 Measurement from differential dt3 Duty Cycle 45 50 55 wavefrom Measurement from differential tjcyc-cyc 90 250 Jitter, Cycle to cycle wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. UNITS Notes  1 mV mV mV 1,3 1,3 1 1 1 mV 1 ppm ns ns ps ps ps ps 1,2 2 1,2 1 1 1 1 % 1 ps 1 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy Tperiod 14.318MHz output nominal Clock period VOH IOH = -1 mA Output High Voltage IOL = 1 mA VOL Output Low Voltage VOH = 1.0 V IOH Output High Current VOH = 3.135 V Output Low Current IOL Rise Time Fall Time Duty Cycle Jitter tr1 tf1 dt1 tjcyc-cyc VOL = 1.95 V VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 1 MIN -300 69.8270 2.4 TYP MAX 300 69.8550 0.4 10 Notes 1 1 1 1 -33 -33 mA 1 38 2 2 55 1000 mA mA ns ns % ps 1 1 1 1,2 1,2 1 30 0.5 0.5 45 1 1 53 750 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0933E—11/21/17 UNITS ppm ns V V 954204 Datasheet SMBus Table: Output Enable Control Register Byte 0 Pin # Name Bit 7 35, 36 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 30, 31 26, 27 24, 25 22, 23 19, 20 17, 18 CPUCLK2_ITP/SRCCLK7 Enable SRCCLK5 Enable SRCCLK4/SATA Enable SRCCLK3 Enable SRCCLK2 Enable SRCCLK1 Enable SRCCLK0 Enable Control Function Type 0 1 PWD Output Enable RW Disable (HiZ) Enable 1 Reserved Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable RW RW RW RW RW RW Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 Type RW RW RW RW 0 Disable Disable (HiZ) Disable Disable 1 Enable Enable Enable Enable RW RW Disable (HiZ) Disable (HiZ) Enable Enable PWD 1 1 1 1 1 1 RW SPREAD OFF SPREAD ON 0 Control Function Output Enable Output Enable Output Enable Output Enable Reserved Reserved Reserved Output Enable Type RW RW RW RW 0 Disable Disable Disable Disable 1 Enable Enable Enable Enable RW Disable Enable PWD 1 1 1 1 1 1 1 1 Control Function Free-Running Control Reserved Type RW 0 Free-Running 1 Stoppable RW RW Free-Running Free-Running Stoppable Stoppable PWD 0 0 0 0 RW Free-Running Stoppable 0 RW Free-Running Stoppable 0 SMBus Table: PLL1 Spread and Output Enable Control Register Byte 1 Pin # Name Control Function 8 PCI_F0 Enable Output Enable Bit 7 14,15 Bit 6 DOT_96MHz Enable Output Enable 12 USB_48MHz Enable Output Enable Bit 5 52 Bit 4 REFOUT Enable Output Enable Reserved Bit 3 41, 40 Bit 2 CPU_1 Enable Output Enable 44, 43 Bit 1 CPU_0 Enable Output Enable Spread Spectrum Mode Bit 0 Spread Control for PLL1 (CPU, SRC, PCIF, PCI) SMBus Table: Output Enable Control Register Byte 2 Pin # Name 5 Bit 7 PCICLK5 4 PCICLK4 Bit 6 3 Bit 5 PCICLK3 56 PCICLK2 Bit 4 Bit 3 Bit 2 Bit 1 9 Bit 0 PCI_F1 Enable SMBus Table: SRC Free-Running Control Register Byte 3 Pin # Name 35, 36 SRCCLK7 Bit 7 Bit 6 30, 31 SRCCLK5 Bit 5 26, 27 Bit 4 SRCCLK4/SATA Bit 3 24, 25 SRCCLK3 Bit 2 22, 23 SRCCLK2 Bit 1 19, 20 SRCCLK1 RW Free-Running Stoppable 0 Bit 0 17, 18 SRCCLK0 RW Free-Running Stoppable 0 Free-Running Control, not affected by PCI/SRC_STOP# 0933E—11/21/17 11 954204 Datasheet SMBus Table: DO T PD Mode and O utput Free-Running Control Register Pin # Nam e Control Function Byte 4 Reserv ed Bit 7 Type 0 1 PWD 0 0 14, 15 DO T_96MHz Power Down Mode Driv en in PD RW Driven Hi-Z 9 PCICLK_F1 RW Free-Running Stoppable Bit 3 8 PCICLK_F0 Reserv ed Free-Running Control, not affec ted by PCI/SRC_STO P# Bit 2 35, 36 CPUCLK_2 Bit 1 40, 41 CPUCLK_1 Bit 0 43, 44 CPUCLK_0 Bit 6 Bit 5 Bit 4 SMBus Table: O utput Mode Control Register Pin # Nam e Byte 5 SRC(7:0) 17-20, 22-27, PCI/SRC_STO P# Driv e Bit 7 30, 31, 35, 36 Mode 0 0 RW Free-Running Stoppable 0 RW Free-Running Stoppable 1 RW Free-Running Stoppable 1 RW Free-Running Stoppable 1 Control Function Type 0 1 PWD Driv en in PCI/SRC_STO P# RW Driven Hi-Z 0 Free-Running Control, not affec ted by CPU_STO P# Bit 6 35, 36 CPUCLK2_ITP CPU_STO P# Driv e Mode Driven in CPU_STO P# RW Driven Hi-Z 0 Bit 5 40, 41 CPUCLK_1 CPU_STO P# Driv e Mode Driven in CPU_STO P# RW Driven Hi-Z 0 Bit 4 43, 44 CPUCLK_0 CPU_STO P# Driv e Mode Driven in CPU_STO P# RW Driven Hi-Z 0 Bit 3 17-20, 22-27, 30, 31, 35, 36 SRC(7:0), 96MHz _SS PD Drive Mode Driv en in PD RW Driven Hi-Z 0 Bit 2 35, 36 CPUCLK2_ITP PD Drive Mode Driv en in PD RW Driven Hi-Z 0 Bit 1 40, 41 CPUCLK_1 PD Driv e Mode Driv en in PD RW Driven Hi-Z 0 Bit 0 43, 44 CPUCLK_0 PD Driv e Mode Driv en in PD RW Driven Hi-Z 0 Type 0 1 PWD RW Hi-Z REF/N 0 RW Normal O peration Tes t Mode per B6b7 0 Reserv ed Strength Prog RW 1X 2X SMBus Table: Test Mode, FS Readback, and PCI Stop# Control Register Pin # Nam e Control Function Byte 6 Tes t Mode Selection (Ac tive only when B6b6 = Test Mode Selec tion Bit 7 1) Bit 6 - Test Cloc k Mode Entry Tes t Mode 1 Bit 5 Bit 4 52 REFO UT STRENG TH Bit 3 - PCI/SRC_STO P# Stop all PCI and SRC cloc k s RW O utputs Stopped O utputs Activ e 1 Bit 2 Bit 1 Bit 0 53 16 12 FS_C FS_B FS_A Readbac k Readbac k Readbac k RW RW RW - - LATCHED LATCHED LATCHED 0933E—11/21/17 12 954204 Datasheet SMBus Table: Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Vendor & Revision ID Register Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISIO N ID VENDO R ID SMBus Table: Clock Request Control Register Pin # Name Byte 8 Bit 7 Control Reserved Type R R R R R R R R 0 - 1 - PWD x x x x 0 0 0 1 Type 0 1 PWD - Bit 6 32 CLKREQ B# Control SRCCLK5 is controlled RW Not Controlled Controlled 1 Bit 5 Bit 4 Bit 3 32 32 - CLKREQ B# Control CLKREQ B# Control SRCCLK3 is controlled SRCCLK1 is controlled Reserved RW RW Not Controlled Not Controlled Controlled Controlled 0 0 - Bit 2 33 CLKREQ A# Control SRCCLK4 is controlled RW Not Controlled Controlled 1 Bit 1 33 CLKREQ A# Control SRCCLK2 is controlled RW Not Controlled Controlled 0 Bit 0 33 CLKREQ A# Control SRCCLK0 is controlled RW Not Controlled Controlled 0 Control Bit S3 Bit S2 Bit S1 Bit S0 Type RW RW RW RW 0 1 PWD 0 1 1 1 SMBus Table: LCDCLK_SS Pin # Byte 9 Bit 7 Bit 6 17,18 Bit 5 Bit 4 Control Register Name LCDCLK_SS3 LCDCLK_SS2 LCDCLK_SS1 LCDCLK_SS0 See LCDCLK_SS Frequency Select Table 2 Bit 3 9 *SEL SRC_LCDCLK# Select LCDCLK_SS/SRCCLK0 R LCDCLK SRCCLK0 - Bit 2 17, 18 LCDCLK_SS/SRCCLK0 Enable O utput Enable RW Disable (HiZ) Enable 1 Bit 1 17, 18 LCDCLK_SS Spread Enable Enable SS RW O FF ON 1 Bit 0 - Reserved Table 2: LCDCLK_SS Frequency Select Byte9/ bit1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S3 S2 S1 S0 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin 17/18 Spread % Spread Type MHz 100.00 100.00 0.8 Down 100.00 1 Down 100.00 1.25 Down 100.00 1.5 Down 100.00 1.75 Down 100.00 2 Down 100.00 2.5 Down 100.00 3 Down 100.00 +/-0.3 Center 100.00 +/-0.4 Center 100.00 +/-0.5 Center 100.00 +/-0.6 Center 100.00 +/-0.8 Center 100.00 +/-1.0 Center 100.00 +/-1.25 Center 100.00 +/-1.5 Center 0933E—11/21/17 13 0 954204 Datasheet 1 Table 3. Power-Up CLKREQ# Timing Symbol Parameter Power Valid to CLKREQ# Output Active TPVCRL (Fig. 1) SRC Clock Stablilzation Time from assertion TSRCSTBL of CLKREQ# (Fig. 1) 1 This timing is valid only after system clocks are stable. Min Max Units 100 s 800 s Max Units Power Stable to Device V PCIEXDEV TPVCRL TSRCSTBL CLKREQ# SRCCLK Figure 1. Power-Up CLKREQ# Timing Table 4. CLKREQ# Control Timing Symbol TCRHoff TCRHon Parameter CLKREQ# De-asserted High to SRCCLK Parked (Fig. 2) CLKREQ# Asserted LOW to SRCCLK Active (Fig. 2) Min s 0 0.4 s CLKREQ# SRCCLK Figure 2. CLKREQ# Control Timing CLKREQ# - Assertion (transition from logic “1” to logic “0”) The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active. CLKREQ# - De-Assertion (transition from logic “0” to logic “1”) The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate condition per the timing found in Table 4. The clock will become inactive in a glitch free manner. 0933E—11/21/17 14 954204 Datasheet Table 5: PCI_STOP# Functionality PCI_STOP# 0 1 CPU Normal Normal CPU# Normal Normal SRC Normal Iref*6 or Float SRC# Normal Low PCIF/PCI 33MHz Low DOT Normal Normal DOT# Normal Normal USB 48MHz 48MHz REF 14.318MHz 14.318MHz SRC# Normal Float PCIF/PCI 33MHz Low DOT Normal DOT# Low Float USB 48MHz Low REF 14.318MHz Low Table 6: PD Functionality PD 0 1 CPU Normal CPU# Normal Float Iref*2 or Float SRC Normal Iref*2 or Float Iref*2 or Float Table 7: Tristate CPU Clock Control Truth Table Signal CPU[2:0] CPU[2:0] CPU[2:0] PD CPU_STOP# CPU_STOP Tristate BIT PD Tristate BIT 10 0 0 0 54 1 0 0 B5b[6, 5, 4] X 0 1 B5b[2,1,0] X X X NON-STOP OUTPUTS STOPPABLE OUTPUTS Running Running Running Running Driven @ IREF X6 Driven @ IREF X2 Tristate CPU[2:0] 1 X X 1 Driven @ IREF X2 CPU[2:0] 1 X X 0 Tristate Tristate NON-STOP OUTPUTS STOPPABLE OUTPUTS Running Running Running Running Driven @ IREF X6 Tristate Table 8: Tristate SRC Clock Control Truth Table PD PCI/SRC_STOP# PCI/SRC_STOP Tristate BIT PD Tristate BIT SRC SRC SRC 10 0 0 0 55 1 0 0 B5b7 X 0 1 B5b3 X X X SRC 1 X X 1 Driven @ IREF X2 Driven @ IREF X2 SRC 1 X X 0 Tristate Tristate Signal Table 9: Tristate DOT Clock Control Truth Table Signal DOT_96 DOT_96 DOT_96 PD 10 0 1 1 PD Tristate BIT B4b6 X 1 0 STOPPABLE OUTPUTS Running Driven @ IREF X2 Tristate Table10: CLKREQ# Clock Control Truth Table Signal SRC SRC SRC SRC SRC PD PCI/SRC_STOP# CLKREQA# CLKREQB# SELECTED OUTPUTS 10 0 0 0 0 1 55 1 1 0 0 X 33, 32 0 1 0 1 X Running Tristate Tristate Stopped per B5b7 Stopped per B5b3 0933E—11/21/17 15 954204 Datasheet c N L E1 INDEX AREA E 1 2 a D A A2 A1 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 -Ce b SEATING PLANE VARIATIONS N aaa C 56 D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 Reference Doc.: JEDEC Publication 95, M O-153 10-0039 Ordering Information 954204CGLFT Example: XXXX C G Lx T Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) 0933E—11/21/17 16 MAX .555 954204 Datasheet Revision History 11/21/2017 Rebranded datasheet with "IDT" logo, added company information and legal disclaimer. 17 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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