Dual Channel Type-1/Type-2 M-LVDS to
LVTTL/LVPECL/LVDS Transceiver
IDT5V5218
Version May 18, 2006
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2006 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................................... 3
LIST OF TABLES .................................................................................................................................................................... 4
LIST OF FIGURES ................................................................................................................................................................... 5
FEATURES .............................................................................................................................................................................. 6
APPLICATIONS....................................................................................................................................................................... 6
DESCRIPTION......................................................................................................................................................................... 6
FUNCTIONAL BLOCK DIAGRAM .......................................................................................................................................... 7
1
PIN ASSIGNMENT .......................................................................................................................................................... 8
2
PIN DESCRIPTION ......................................................................................................................................................... 9
3
ELECTRICAL SPECIFICATION ................................................................................................................................... 11
3.1
ABSOLUTE MAXIMUM RATING AND RECOMMENDED OPERATION CONDITIONS ................................. 11
3.2
LVTTL/LVDS/LVPECL DRIVER/RECEIVER CHARACTERISTICS ................................................................ 12
3.2.1 M-LVDS to LVTTL................................................................................................................................ 12
3.2.2 M-LVDS to LVDS ................................................................................................................................. 13
3.2.3 M-LVDS to LVPECL............................................................................................................................. 16
3.3
M-LVDS DRIVER TYPE-1/TYPE-2 RECEIVER CHARACTERISTICS ............................................................ 17
ORDERING INFORMATION.................................................................................................................................................. 24
Table of Contents
3
May 18, 2006
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
List of Tables
Pin Description............................................................................................................................................... 9
Absolute Maximum Rating ........................................................................................................................... 11
Recommended Operation Conditions.......................................................................................................... 11
LVTTL DC Parameters ................................................................................................................................ 12
LVTTL AC Parameters................................................................................................................................. 12
LVDS DC Parameters.................................................................................................................................. 13
LVDS AC Parameters .................................................................................................................................. 15
Differential LVPECL DC Parameters ........................................................................................................... 16
Differential LVPECL AC Parameters ........................................................................................................... 16
M-LVDS Type-1 Receiver Input Threshold Test Voltages ........................................................................... 17
M-LVDS Type-2 Receiver Input Threshold Test Voltages ........................................................................... 17
M-LVDS DC Parameters.............................................................................................................................. 18
M-LVDS Input Current Parameters.............................................................................................................. 20
M-LVDS AC Parameters.............................................................................................................................. 21
M-LVDS Type-1/Type-2 Receiver AC Parameters ...................................................................................... 22
M-LVDS Receiver output DC Parameters ................................................................................................... 23
M-LVDS Driver AC Parameter ..................................................................................................................... 23
4
May 18, 2006
List of Figures
Figure-1
Figure-2
Figure-3
Figure-4
Figure-5
Figure-6
Figure-7
Figure-8
Figure-9
Figure-10
Figure-11
Figure-12
Figure-13
Figure-14
Figure-15
Figure-16
List of Figures
Functional Block Diagram .............................................................................................................................. 7
IDT5V5218 TSSOP24 Package Pin Assignment ........................................................................................... 8
LVTTL Output Test Circuit and Waveforms ................................................................................................. 12
LVDS Receiver Input Common-mode Range Test Circuit ........................................................................... 13
LVDS Driver Output Voltage Test Circuit ..................................................................................................... 14
LVDS Driver Shorted to Ground .................................................................................................................. 14
LVDS Driver Shorted Together .................................................................................................................... 14
LVDS Output Test Circuit ............................................................................................................................. 15
LVPECL Driver Output Test Circuit and Waveforms ................................................................................... 16
M-LVDS Driver Output Voltage Test Circuit ................................................................................................. 18
M-LVDS Driver Short-Circuit Test Circuit ..................................................................................................... 18
M-LVDS Type-1/Type-2 Receiver Input Common-mode Range Test Circuit .............................................. 19
Various Input Currents Test Circuit .............................................................................................................. 20
Differential Skew .......................................................................................................................................... 21
M-LVDS Output Voltage Test Circuit ........................................................................................................... 21
Timing and Voltage Definitions for the Output Signal .................................................................................. 23
5
May 18, 2006
Dual Channel Type-1/Type-2 MLVDS to LVTTL/LVPECL/LVDS
FEATURES
Main Features
– Two independent channels
– Type-2 M-LVDS receiver supports 100 mV offset threshold
– Up to 166 MHz selectable input/output signals: LVTTL/
LVPECL/LVDS
– M-LVDS interface allows common-mode voltage: -1 V to 3.4 V
– Power up and power down glitch free
– M-LVDS interface pins in high impedance state when the
device is powered down or VDD < 1.5 V
– Capable of driving bus load from 30 Ω to 55 Ω
IDT5V5218
Other Features
– Low power consumption < 220 mW
– Hot swappable
– 24-pin TSSOP package
APPLICATIONS
–
–
–
–
Backplane transmission
Telecommunication system
Data communications
ATCA clock distribution
DESCRIPTION
The IDT5V5218 is a dual-channel transceiver which can interchange
data across multipoint data bus structures.
In the device, the two channels operate independently. Each channel
has selectable LVTTL/LVPECL/LVDS drivers and receivers, a selectable
Type-1/Type-2 M-LVDS receiver and M-LVDS driver. It translates
between LVTTL/LVPECL/LVDS signals and M-LVDS signals. The
drivers and the receivers can be enabled or disabled by external pins.
The M-LVDS driver is capable of driving bus load from 30 Ω to 55 Ω.
The M-LVDS interface allows common-mode voltage range of -1 V to
3.4 V.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
6
2006 Integrated Device Technology, Inc.
May 18, 2006
DSC-6966/-
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
FUNCTIONAL BLOCK DIAGRAM
RE1_EN
OUT1_A
OUT1_B
LVTTL/LVPECL/
LVDS Interface 1
IN1_A
M1_A
M-LVDS Interface 1
M1_B
IN1_B
DR1_EN
RE2_EN
OUT2_A
OUT2_B
LVTTL/LVPECL/
LVDS Interface 2
M2_A
IN2_A
M-LVDS Interface 2
IN2_B
M2_B
DR2_EN
I/O Config
DIFF_SEL
TYPE_SEL
Figure-1 Functional Block Diagram
Functional Block Diagram
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May 18, 2006
IDT5V5218
1
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
PIN ASSIGNMENT
DR2_EN
1
24
RE2_EN
IN2_A
2
23
OUT2_B
IN2_B
3
22
OUT2_A
OUT1_A
4
21
DIFF_SEL
OUT1_B
5
20
TYPE_SEL
RE1_EN
6
19
VDD1
DR1_EN
7
18
M1_B
IN1_A
8
17
M1_A
IN1_B
9
16
GND1
NC
10
15
VDD2
NC
11
14
M2_B
GND2
12
13
M2_A
IDT5V5218
Figure-2 IDT5V5218 TSSOP24 Package Pin Assignment
Pin Assignment
8
May 18, 2006
IDT5V5218
2
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
PIN DESCRIPTION
Table-1 Pin Description
Name
Pin No.
I/O
Type
Description
Global Signal
7
I
Pull-down
LVTTL
DR1_EN: M-LVDS Driver 1 Enable
This pin controls the M-LVDS driver for channel 1: high for enable and low for disable.
6
I
Pull-up
LVTTL
RE1_EN: Type-1/Type-2 M-LVDS Receiver 1 and LVTTL/LVPECL/LVDS Drivers 1 Enable
This pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/LVDS drivers for
channel 1: high for disable and low for enable. Note that the LVTTL driver is in high impedance
state when disabled.
RE1_EN
DR2_EN
1
I
Pull-down
LVTTL
DR2_EN: M-LVDS Driver 2 Enable
This pin controls the M-LVDS driver for channel 2: high for enable and low for disable.
RE2_EN
24
I
Pull-up
LVTTL
RE2_EN: Type-1/Type-2 M-LVDS Receiver 2 and LVTTL/LVPECL/LVDS Drivers 2 Enable
This pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/LVDS drivers for
channel 2: high for disable and low for enable. Note that the LVTTL driver is in high impedance
state when disabled.
TYPE_SEL
20
I
Pull-down
LVTTL
TYPE_SEL: Type-1/Type-2 M-LVDS Receiver Selection
This pin globally controls the Type-1/Type-2 M-LVDS receiver selection: high for Type-2 and
low for Type-1.
DIFF_SEL
21
I
Pull to VDD/2
LVTTL
DIFF_SEL: Type Selection for LVTTL/LVPECL/LVDS Interface Input/Output 1 and 2
This pin globally determines the type of input/output 1 and 2 of the LVTTL/LVPECL/LVDS
interface: high for LVDS, floating for LVTTL and low for LVPECL.
DR1_EN
LVTTL/LVPECL/LVDS Interface
IN1_A
IN1_B
IN2_A
IN2_B
OUT1_A
OUT1_B
8
9
2
3
4
5
Pin Description
I
I
O
LVTTL/LVPECL/LVDS
LVPECL/LVDS
LVTTL/LVPECL/LVDS
LVPECL/LVDS
LVTTL/LVPECL/LVDS
LVPECL/LVDS
IN1_A/IN1_B: Positive/Negative LVPECL/LVDS Input 1
An up to 166 MHz differential signal is input on this pair of pins. The input signal can be
LVPECL or LVDS, as selected by the DIFF_SEL pin.
IN1_A: LVTTL Input 1
An up to 166 MHz LVTTL signal is input on this pin, as selected by the DIFF_SEL pin. In this
case, the IN1_B pin will be in high impedance state.
IN2_A/IN2_B: Positive/Negative LVPECL/LVDS Input 2
An up to 166 MHz differential signal is input on this pair of pins. The input signal can be
LVPECL or LVDS, as selected by the DIFF_SEL pin.
IN2_A: LVTTL Input 2
An up to 166 MHz LVTTL signal is input on this pin, as selected by the DIFF_SEL pin. In this
case, the IN2_B pin will be in high impedance state.
OUT1_A/OUT1_B: Positive/Negative LVPECL/LVDS Output 1
This pair of pins output an up to 166 MHz differential signal. The output signal can be LVPECL
or LVDS, as selected by the DIFF_SEL pin.
OUT1_A: LVTTL Output 1
This pin outputs an up to 166 MHz LVTTL signal, as selected by the DIFF_SEL pin. In this
case, the OUT1_B pin will be in high impedance state.
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May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-1 Pin Description (Continued)
Name
OUT2_A
OUT2_B
Pin No.
22
23
I/O
O
Type
LVTTL/LVPECL/LVDS
LVPECL/LVDS
Description
OUT2_A/OUT2_B: Positive/Negative LVPECL/LVDS Output 2
This pair of pins output an up to 166 MHz differential signal. The output signal can be LVPECL
or LVDS, as selected by the DIFF_SEL pin.
OUT2_A: LVTTL Output 2
This pin outputs an up to 166 MHz LVTTL signal, as selected by the DIFF_SEL pin. In this
case, the OUT2_B pin will be in high impedance state.
M-LVDS Interface
M1_A
M1_B
17
18
I/O
M-LVDS
M1_A/M1_B: Positive/Negative M-LVDS Data Bus Interface 1
This pair of pins are connected to the M-LVDS data bus.
M2_A
M2_B
13
14
I/O
M-LVDS
M2_A/M2_B: Positive/Negative M-LVDS Data Bus Interface 2
This pair of pins are connected to the M-LVDS data bus.
Power Supply and Ground
VDD1
19
Power
-
3.3 V Power Supply for Channel 1
VDD2
15
Power
-
3.3 V Power Supply for Channel 2
GND1
16
Ground
-
Ground for Channel 1
GND2
12
Ground
-
Ground for Channel 2
Others
NC
10, 11
Pin Description
-
-
NC: No Connection
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May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
3
ELECTRICAL SPECIFICATION
3.1
ABSOLUTE MAXIMUM RATING AND RECOMMENDED OPERATION CONDITIONS
Table-2 Absolute Maximum Rating
Symbol
Parameter
Range
VDD
Supply Voltage
-0.5 V to 4.1 V
VIN
VOUT
Input Voltage
Output Voltage
Electrostatic Discharge
REn_EN(1), DRn_EN, INn_A, INn_B
-0.5 V to 4.1 V
Mn_A, Mn_B
-1.8 V to 4 V
OUTn_A, OUTn_B
-0.3 V to 4 V
Mn_A, Mn_B
-1.8 V to 4 V
Human Body Model Mn_A, Mn_B
±8 kV
All pins
±2 kV
TJ
Junction Temperature
150°C
TS
Storage Temperature
-65°C to 165°C
1. n = 1, 2
Table-3 Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Power Supply
3.0
3.3
3.6
V
VIH
High Level Input Voltage
2
3.0
V
VIL
Low Level Input Voltage
0
0.8
V
Voltage at any Bus Terminal
-1.4
3.8
V
Magnitude of Differential Input Voltage
0.05
3.0
V
Ambient Operating Temperature
-40
85
°C
TA
Electrical Specification
11
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
3.2
LVTTL/LVDS/LVPECL DRIVER/RECEIVER CHARACTERISTICS
3.2.1
M-LVDS TO LVTTL
Table-4 LVTTL DC Parameters
Symbol
Parameter
Test Conditions
VIHL
Input High Level
VILL
Min
Typ
Max
Unit
2.0
VDD + 0.3
V
Input Low Level
-0.3
0.8
V
IILL
Input Leakage Current
-1.0
1.0
µA
VOHL
Output High Voltage
Output Current = 17 mA, VDD = 3 V
VOLL
Output Low Voltage
Output Current = 12 mA, VDD = 3 V
2.4
V
0.4
V
Table-5 LVTTL AC Parameters
Symbol
Parameter
Test Conditions
tr
Rise Time
tf
Fall Time
fML
Frequency
Min
Max
Unit
Cload = 15 pF, 10% - 90%
1.2
ns
Cload = 15 pF, 10% - 90%
1.2
ns
166
MHz
OUTn
Typ
VOUT
15 pF
VA
1.2 V
VB
1.0 V
VID
0.2 V
0V
-0.2 V
tpHL
VO
tpLH
VOH
90%
10%
tf
tr
VOL
Figure-3 LVTTL Output Test Circuit and Waveforms
Electrical Specification
12
May 18, 2006
IDT5V5218
3.2.2
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
M-LVDS TO LVDS
Table-6 LVDS DC Parameters
Symbol
Parameter
VCM
Min
Typ
Max
Unit
Input Common-mode Voltage Range
0
1200
2400
mV
VDIFF
Input Peak Differential Voltage
100
900
mV
VIDTH
Input Differential Threshold
-100
100
mV
IIN
Input Leakage Current
20
µA
VOH
Output Voltage High
Rload = 100 Ω ± 1%
1350
1475
mV
VOL
Output Voltage Low
Rload = 100 Ω ± 1%
925
1100
mV
VOD
Differential Output Voltage
Rload = 100 Ω ± 1%
250
450
mV
VOS
Output Offset Voltage
Rload = 100 Ω ± 1%
1100
1300
mV
R0
Differential Output Impedance
VCM = 1.0 V or 1.4 V
80
120
Ohm
∆VOD
Change in VOD between Logic 0 and Logic 1
Rload = 100 Ω ± 1%
25
mV
∆VOS
Change in VOS between Logic 0 and Logic 1
Rload = 100 Ω ± 1%
25
mV
ISAISB
Output Current
Driver shorted to GND
24
mA
ISAB
Output Current
Driver shorted together
12
mA
10 kΩ
Test Conditions
INn_A
Mn_A
LVTTL/LVPECL/
LVDS Interface
+
VTEST
-
0 V to 2.4 V
VOUT
INn_B
10 kΩ
1 µF
100
M-LVDS Interface
Mn_B
1 µF
0~166 MHz
Figure-4 LVDS Receiver Input Common-mode Range Test Circuit
Electrical Specification
13
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
50 W
OUTn_A
VOD
OUTn_B
50 W
VOS
VA
1.2 V
VB
1.0 V
VID
0.2 V
0V
-0.2 V
tpHL
VO
tpLH
VOH
80%
20%
tf
VOL
tr
Figure-5 LVDS Driver Output Voltage Test Circuit
OUTn_A
High or Low Steady
State Logic Input
+
VTEST
OUTn_B
-
-1 V to 3.4 V
Figure-6 LVDS Driver Shorted to Ground
OUTn_A
High or Low Steady
State Logic Input
OUTn_B
Figure-7 LVDS Driver Shorted Together
Electrical Specification
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May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-7 LVDS AC Parameters
Symbol
Parameter
Test Conditions
Min
tr
Rise Time
20% - 80%
tf
Fall Time
20% - 80%
tTSP
Differential Skew
fMM
Frequency
Typ
Max
Unit
150
350
ps
150
350
ps
-50
50
ps
166
MHz
OUTn_A
3.74 kΩ
High or Low Steady
State Logic Input
100 Ω
VT
3.74 kΩ
OUTn_B
+
-
0 V to 2.4 V VTEST
Figure-8 LVDS Output Test Circuit
Electrical Specification
15
May 18, 2006
IDT5V5218
3.2.3
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
M-LVDS TO LVPECL
Table-8 Differential LVPECL DC Parameters
Symbol
Parameter
Min
VIL
Input Low Voltage, Differential Inputs
VIH
Max
Unit
VDD-2.5
VDD-0.5
V
Input High Voltage, Differential Inputs
VDD-2.4
VDD-0.4
V
VID
Input Differential Voltage
0.1
1.4
V
IIH
Input High Current, VID = 1.4 V
-10
10
µA
IIL
Input Low Current, VID = 1.4 V
-10
10
µA
VOL
Output Voltage Low
VDD-2.1
VDD-1.6
V
VOH
Output Voltage High
VDD-1.25
VDD-0.88
V
VOS
Output Differential Voltage
580
950
mV
OUTn_A
Typ
50 Ω
VDD - 2 V
VOS
50 Ω
OUTn_B
VA
1.2 V
VB
1.0 V
VID
0.2 V
0V
-0.2 V
tpHL
VO
tpLH
VOH
80%
20%
tf
tr
VOL
Figure-9 LVPECL Driver Output Test Circuit and Waveforms
Table-9 Differential LVPECL AC Parameters
Symbol
Parameter
Test Conditions
Min
tr
Rise Time
20% - 80%
tf
Fall Time
20% - 80%
tTSP
Differential Skew
fMM
Frequency
Electrical Specification
16
Typ
Max
Unit
150
350
ps
150
350
ps
-50
50
ps
166
MHz
May 18, 2006
IDT5V5218
3.3
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
M-LVDS DRIVER TYPE-1/TYPE-2 RECEIVER CHARACTERISTICS
Table-10 M-LVDS Type-1 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input Voltage
Resulting Common-mode Input Voltage
Receiver Output(1)
0.000
2.400
1.200
High
0.000
2.400
-2.400
1.200
Low
3.425
3.375
0.050
3.4
High
3.375
3.425
-0.050
3.4
Low
-0.975
-1.025
0.050
-1
High
-1.025
-0.975
-0.050
-1
Low
Resulting Differential Input Voltage
Resulting Common-mode Input Voltage
Receiver Output(1)
VA
VB
2.400
1. The receiver is enabled ( The RE1_EN or RE2_EN pin is pulled low).
Table-11 M-LVDS Type-2 Receiver Input Threshold Test Voltages
Applied Voltages
VA
VB
2.400
0.000
2.400
1.200
High
0.000
2.400
-2.400
1.200
Low
3.475
3.325
0.150
3.4
High
3.425
3.375
0.050
3.4
Low
-0.925
-1.075
0.150
-1
High
-0.975
-1.025
0.050
-1
Low
1. The receiver is enabled (The RE1_EN or RE2_EN pin is pulled low).
Electrical Specification
17
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-12 M-LVDS DC Parameters
Symbol
Parameter
Test Conditions
VODM
Differential Output Voltage
∆VODM
Max
Unit
480
650
mV
Change in VODM for Complimentary Output States,
∆VODM = |VODM1 - VODM0|
-50
50
mV
VOSM
Offset Voltage
0.8
1.2
V
∆VOSM
Change in VOSM for Complimentary Output States
-50
50
mV
VOSM(p-p)
Peak-to-peak Common-mode Output Voltage
150
mV
IOM
Output Short Circuit Current
20
mA
IIZM
High Impedance Input Current
10
µA
VTHM
Differential Input High Threshold
Type-1
Type-2
VTLM
Differential Input Low Threshold
Type-1
Type-2
VCMM
Input Common-mode Range
VINA - VINB = 200 mV
IINM
Input Current
Input Voltage = 0 V to 2.4 V
VOSM(p-p)
Min
-10
∆VOSM
Typ
50
150
mV
-50
+50
mV
-1
3.4
V
-20
20
µA
24.9 Ω
Mn_A
VODM
VOSM
VOSM
Mn_B
VAB
0V
VODM0
24.9 Ω
VODM1
Figure-10 M-LVDS Driver Output Voltage Test Circuit
Mn_A
High or Low Steady
State Logic Input
Mn_B
+
- 1 V to 3.4 V VTEST
-
Figure-11 M-LVDS Driver Short-Circuit Test Circuit
Electrical Specification
18
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
10 kΩ
Mn_A
OUTn_A
M-LVDS Interface
10 kΩ
+
VTEST -1 V to 3.4 V
-
VOUT
OUTn_B
Mn_B
1 µF
LVTTL/LVPECL/
LVDS Interface
1 µF
0 ~ 166 MHz
Figure-12 M-LVDS Type-1/Type-2 Receiver Input Common-mode Range Test Circuit
Electrical Specification
19
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-13 M-LVDS Input Current Parameters
Symbol
Parameter
Test Conditions
Min
IA
Receiver or Transceiver with Driver Disabled Input Current
VA = 3.8 V, VB = 1.2 V
IB
Receiver or Transceiver with Driver Disabled Input Current
Typ
Max
Unit
0
32
µA
VA = 0 V or 2.4 V, VB = 1.2 V
-20
20
VA = - 1.4 V, VB = 1.2 V
-32
0
VB = 3.8 V, VA = 1.2 V
0
32
VB = 0 V or 2.4 V, VA = 1.2 V
-20
20
VB = -1.4 V, VA = 1.2 V
-32
0
µA
IAB
Receiver or Transceiver with Driver Differential Current (IA - IB)
VA = VB, -1.4 V < VA < 3.8 V
-4
4
µA
IA(OFF)
Receiver or Transceiver Power-off Input Current
VA = 3.8 V, VB = 1.2 V, 0 V < VDD < 1.5 V
0
32
µA
VA = 0 or 2.4 V, VB = 1.2 V, 0 V < VDD < 1.5 V
-20
20
VA = -1.4 V, VB = 1.2 V, 0 V < VDD < 1.5 V
-32
0
VB = 3.8 V, VA = 1.2 V, 0 V < VDD < 1.5 V
0
32
VB = 0 or 2.4 V, VA = 1.2 V, 0 V < VDD < 1.5 V
-20
20
VB = -1.4 V, VA = 1.2 V, 0 V < VDD < 1.5 V
-32
0
-4
4
µA
4
pF
IB(OFF)
Receiver or Transceiver Power-off Input Current
IAB(OFF)
Receiver or Transceiver Power-off Differential Input Current (IA - IB)
VA = VB, 0 V < VDD< 1.5 V, -1.4 V < VA < 3.8 V
CAB
Transceiver with driver disabled differential input capacitance
VAB = 0.4 sin (30E6πt) V
µA
Mn_A
V
Mn_B
A
V
B
Figure-13 Various Input Currents Test Circuit
Electrical Specification
20
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-14 M-LVDS AC Parameters
Symbol
Parameter
Test Conditions
Min.
tr
Rise Time
10% - 90%
tf
Fall Time
10% - 90%
tTSL
Differential Skew, tTSL = {tTSL1, tTSL2}
fML
Frequency
VA
tTSL1
Typ
Max.
Unit
0.8
1.5
ns
0.8
1.5
ns
-100
100
ps
166
MHz
tTSL2
VB
Figure-14 Differential Skew
3.32 kΩ
Mn_A
VODM
50 Ω
+
-
VTEST -1 V to 3.4 V
Mn_B
3.32 kΩ
Figure-15 M-LVDS Output Voltage Test Circuit
Electrical Specification
21
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-15 M-LVDS Type-1/Type-2 Receiver AC Parameters
Output mode
Symbol
Parameter
LVTTL
tpLH
Delay, Low to High Level
tpHL
Delay, High to Low Level
tsk
Type-1
Test Condition
Input clock: freq = 50 MHz, Impedance = 150 Ω,
Voltage = -200 mV - 200 mV. See Figure-3
Min
Typ
Max
Unit
2.5
5.5
6.5
ns
2.5
5.5
6.5
ns
100
300
ps
300
500
ps
Pulse Skew, tsk = |tpLH - tpHL|
Type-2
Tr (10% - 90%)
Rise Time
1
2.4
ns
Tf (10% - 90%)
Fall Time
1
2.4
ns
Tjit(per)
Period jitter, rms(1 standard deviation)
7
ps
200
ps
4
Output to Output Skew
LVDS
tsk
tpLH
Delay, Low to High Level
tpHL
Delay, High to Low Level
Type-1
Input clock: freq = 50 MHz, Impedance = 150 Ω,
Voltage = -200 mV - 200 mV. See Figure-5
2.5
4.0
5.5
ns
2.5
4.0
5.5
ns
150
300
ps
250
500
ps
Pulse Skew, tsk = |tpLH - tpHL|
Type-2
Tr (20% - 80%)
Rise Time
150
200
350
ps
Tf (20% - 80%)
Fall Time
150
200
350
ps
Tjit(per)
Period jitter, rms(1 standard deviation)
4
7
ps
200
ps
Output to Output Skew
LVPECL
tsk
tpLH
Delay, Low to High Level
tpHL
Delay, High to Low Level
Type-1
Input clock: freq = 50 MHz, Impedance = 150 Ω,
Voltage = -200 mV - 200 mV. See Figure-9
2.5
4
5.5
ns
2.5
4
5.5
ns
150
300
ps
200
500
ps
Pulse Skew, tsk = |tpLH - tpHL|
Type-2
Tr (20% - 80%)
Rise Time
150
250
350
ps
Tf (20% - 80%)
Fall Time
150
250
350
ps
Tjit(per)
Period jitter, rms(1 standard deviation)
4
7
ps
200
ps
Output to Output Skew
Electrical Specification
22
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
Table-16 M-LVDS Receiver output DC Parameters
Output mode
Symbol
Parameter
Test Condition
Min
LVPECL
VOD
Differential Output Voltage
580
LVDS
VOS
Output Offset Voltage
1100
VOD
Differential Output Voltage
250
ISA, ISB
Output Current
VODM
Differential Output Voltage
Typ
Max
Unit
950
mV
1200
1300
mV
350
450
mV
28
mA
650
mV
480
Table-17 M-LVDS Driver AC Parameter
Tsk
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
tpLH
Delay, Low to High Level
2.5
3.7
5.5
ns
tpHL
Delay, High to Low Level
Input clock: freq = 15 MHz, Tr = Tf =
1.2 ns, Impedance = 300 Ω,
Voltage = 0 V - 3.3 V. See Figure-10
2.5
3.7
5.5
ns
40
100
ps
250
400
ps
LVTTL input
Pulse Skew, tsk = |tpLH - tpHL|
LVDS/LVPECL input
Tr (10% - 90%)
Rise Time
0.7
1.1
1.5
ns
Tf (10% - 90%)
Fall Time
0.7
1.1
1.5
ns
Tjit(per)
Period jitter, rms (1 standard deviation)
2
3
ps
100
ps
Output to Output Skew
Input
tpLH
tpHL
Vs
0.8Vs/0.9Vs
Output
tf
tr
0.2Vs/0.1Vs
0 Vs
Figure-16 Timing and Voltage Definitions for the Output Signal
Electrical Specification
23
May 18, 2006
IDT5V5218
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver
ORDERING INFORMATION
IDT
XXXXXXX
Device Type
XX
X
Process/
Temperature
Range
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
I
Industrial (-40 °C to +85 °C)
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Green Thin Shrink Small Outline Package (TSSOP, PGG24)
5V5218
Dual Channel Type-1/Type-2 M-LVDS to
LVTTL/LVPECL/LVDS Transceiver
for SALES:
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fax: 408-284-2775
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24
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