HIGH SPEED 64K (4K X 16 BIT)
IDT70824S/L
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
Features
◆
◆
◆
◆
◆
◆
High-speed access
– Military: 35/45ns (max.)
– Commercial: 20/25/35/45ns (max.)
Low-power operation
– IDT70824S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70824L
Active: 775mW (typ.)
Standby: 1mW (typ.)
4K x 16 Sequential Access Random Access Memory (SARAM™)
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
High speed operation
– 20ns tAA for random access port
– 20ns tCD for sequential port
– 25ns clock cycle time
Architecture based on Dual-Port RAM cells
◆
◆
◆
◆
◆
◆
◆
Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random
Access Memory (SARAM). The SARAM offers a single-chip solution to
buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM
based architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
12
A0-11
CE
OE
R/W
LB LSB
MSB
UB
CMD
Random
Access
Port
Controls
Sequential
Access
Port
Controls
4K X 16
Memory
Array
16
I/O0-15
12
DataL
DataR
AddrL
AddrR
16
12
Reg.
12
16
RST
SCLK
CNTEN
SOE
SSTRT1
SSTRT2
SCE
SR/W
SLD
SI/O0-15
,
RST
12
12
Pointer/
Counter
12
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
EOB1
12
COMPARATOR
EOB2
3099 drw 01
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC-3099/6
6.07
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
The IDT70824 is packaged in a 80-pin Thin Quad Flatpack (TQFP)
or 84-pin Pin Grid Array (PGA). Military grade product is manufactured
in compliance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the highest
level of performance and reliability.
quencing for the sequential (synchronous) access port.
Fabricated using CMOS high-performance technology, this memory
device typically operates on less than 775mW of power at maximum highspeed clock-to-data and Random Access. An automatic power down
feature, controlled by CE, permits the on-chip circuitry of each port to enter
a very low standby power mode.
SI/O2
SI/O3
VCC
SI/O4
SI/O5
SI/O6
SI/O7
GND
SI/O8
SI/O9
SI/O10
SI/O11
VCC
SI/O12
SI/O13
SI/O14
SI/O15
GND
N/C
GND
Pin Configurations(1,2,3)
INDEX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
2
58
3
SI/O1
SI/O0
GND
N/C
SCE
SR/W
RST
SLD
SSTRT2
SSTRT1
GND
GND
CNTEN
SOE
SCLK
GND
EOB2
EOB1
VCC
I/O0
4
57
5
6
56
55
7
54
53
8
52
IDT70824PF
PN80-1(4)
9
10
11
51
50
49
80-Pin TQFP
Top View(5)
12
13
48
14
47
15
46
45
16
17
44
18
43
19
42
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3099 drw 02
I/O1
GND
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
VCC
I/O12
I/O13
I/O14
I/O15
GND
63
I/O1
66
I/O2
67
61
60
VCC
64
58
EOB1
62
55
59
56
65
I/O9
76
48
SR/W NC
50
47
57
53
SCLK GND
SLD
45
43
44
SI/O2 VCC
73
33
70
74
I/O5
77
I/O8
32
31
28
29
26
I/O14
82
7
2
NC
3
5
OE
I/O15 GND
84
12
CMD VCC
NC
1
11
4
8
LB
6
10
A0
9
A2
14
A4
VCC
15
23
13
A7
16
22
20
A10
18
05
04
25
03
24
GND GND
19
06
27
NC SI/O15
17
07
30
SI/O14 SI/O13
83
08
36
SI/O12 VCC SI/O11
80
09
34
SI/O9 SI/O10 SI/O6
84-Pin PGA
Top View(5)
78
35
SI/O8 SI/O7 GND
IDT70824G
G84-3(4)
10
37
SI/O4 SI/O5
I/O6 GND
11
39
41
38
71
NC
40
52
VCC
,
42
SSTRT1
I/O12 I/O13
81
GND
SCE SI/O0 SI/O1 SI/O3
I/O10 I/O11 VCC
79
46
68
I/O7
75
49
51
SSTRT2
I/O0 EOB2 SOE RST
NC
I/O4
72
54
GND CNTEN GND
I/O3 GND
69
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
VCC
VCC
A1
A0
CMD
CE
LB
UB
R/W
OE
1
02
21
R/W
UB
CE
A1
A5
A3
A6
A8
A9
A11
B
C
D
E
F
G
H
J
K
L
01
,,
A
Pin 1
Designator
3099 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Pin Descriptions: Random Access Port(1)
SYMBOL
NAME
I/O
DESCRIPTION
A0-A 11
Address Lines
I
Address inputs to access the 4096-word (16-Bit) memory array.
I/O0-I/O15
Inputs/Outputs
I
Random access data inputs/outputs for 16-Bit wide data.
CE
Chip Enable
I
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE =
VIH, unless it is altered by the sequential port CE and CMD may not be LOW at the same time.
CMD
Control Register Enable
I
When CMD is LOW, address lines A 0-A2, R/W, and inputs and outputs I/O 0-I/O12, are used to access the
control register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the
same time.
R/W
Read/Write Enable
I
If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when
R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and
CMD may not be LOW at the same time.
OE
Output Enable
I
When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in
the High-impedance state.
LB, UB
Lower Byte, Upper Byte
Enables
I
When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0-I/O7 are tristated and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and
is asynchronous
from LB.
VCC
Power Supply
I
Seven +5 power supply pins. All V CC pins must be connected to the same +5V V CC supply.
GND
Ground
I
Ten ground pins. All ground pins must be connected to the same ground supply.
3099 tbl 01
Pin Descriptions: Sequential Access Port(1)
SYMBOL
NAME
I/O
DESCRIPTION
SI/O0-15
Inputs/Outputs
I/O
Sequential data inputs/outputs for 16-bit wide data.
SCLK
Clock
I
SI/O0-SI/O15,SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential
access port address pointer increments by 1 on e ach LOW-TO-HIGH transition of SCLK when CNTEN is LOW.
SCE
Chip Enable
I
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transitio n of SCLK. When SCE
is HIGH, the sequential access port is disabled into powered-d own mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained , unless altered by the random
access port.
CNTEN
Counter Enable
I
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
independent of CE.
SR/W
Read/Write Enable
I
When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/ W is
HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination
o f a write cycle is done on the LOW-to -HIGH transition of SCLK if SR/W or SCE is HIGH.
SLD
Address Pointer Load Control
I
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When
SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of
SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the datain register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD.
SSTRT1,
SSTRT2
Load Start of Address
Register
I
When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is load ed into the address pointer on
the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2
may not be LOW while SLD is LOW or during the cycle following SLD.
EOB1,
EOB2
End of Buffer Flag
O
EOB1 or EOB2 is output low when the address pointer is incremented to match the address stored in the end
of buffer registers. The flags can be cleared by either asserting RST LOW or by writing ze ro into Bit 0 and/or
Bit 1 of the control registe r at address 101. EOB1 and EOB2 are dependent on separate internal registers, and
therefore separate match addresses.
SOE
Output Enable
I
SOE controls the data outputs and is independe nt of SCLK. When SOE is LOW, output buffers and the
se quentially ad dressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state.
SOE is asynchronous to SCLK.
RST
Reset
I
When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the
EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
3099 tbl 02
NOTE:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.42
3
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Absolute Maximum Ratings
Symbol
VTERM(2)
TBIAS
Rating
Commercial
& Industrial
Military
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Temperature
Under Bias
-55 to +125
-65 to +150
Recommended Operating
Temperature and Supply Voltage
Grade
o
-65 to +135
o
-65 to +150
Commercial
C
50
50
mA
0V
5.0V + 10%
0OC to +70OC
0V
5.0V + 10%
0V
5.0V + 10%
O
-40 C to +85 C
Recommended DC Operating
Conditions
Symbol
Capacitance
Parameter
Supply Voltage
GND
Ground
Input Capacitance
Output Capacitance
V IL
Conditions(2)
Max.
Unit
V IN = 3dV
9
pF
VOUT = 3dV
10
Parameter
VCC
VIH
(TA = +25°C, f = 1.0mhz, TQFP only)
COUT
-55OC to +125OC
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact
your sales office.
3099 tbl 03
CIN
Vcc
O
Industrial
C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Symbol
GND
Ambient Temperature
3099 tbl 04
DC Output
Current
IOUT
Military and Commercial Temperature Ranges
Military
Storage
Temperature
TSTG
(1)
Input High Voltage
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
-0.5
(1)
(2)
6.0
____
0.8
V
3099 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
pF
V
3099 tbl 06
NOTES:
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70824S
Symbol
|ILI|
Parameter
Input Leakage Current
Test Conditions
Min.
70824L
Max.
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to V CC
___
5
___
1
µA
5
___
1
µA
V
|ILO|
Output Leakage Current
VOUT = 0V to V CC
___
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
3099 tbl 07
4
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,8) (VCC = 5.0V ± 10%)
70824X20
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
CEL and CER = VIL,
Outputs Disabled
SCE = VIL(5)
f = fMAX(3)
SCE and CE = VIH(7)
CMD = VIH
f = fMAX(3)
CE or SCE = VIH
Active Port Outputs Disabled,
f=fMAX(3)
Both Ports CE and
SCE > VCC - 0.2V(6)
VIN > VCC - 0.2V or
VIN < 0.2V,
f = 0(4)
One Port CE or
SCE > VCC - 0.2V(6,7)
Outputs Disabled (Active Port)
f = fMAX(3)
VIN > VCC - 0.2V or V IN < 0.2V
Version
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Typ.(2)
Max.
Typ. (2)
Max.
Typ. (2)
Max.
Typ.(2)
Max.
Unit
mA
COM'L
S
L
180
180
380
330
170
170
360
310
160
160
340
290
155
155
340
290
MIL &
IND
S
L
____
____
____
____
____
____
____
____
160
160
400
340
155
155
400
340
COM'L
S
L
25
25
70
50
25
25
70
50
20
20
70
50
16
16
70
50
MIL &
IND
S
L
____
____
____
____
____
____
____
____
20
20
85
65
16
16
85
65
COM'L
S
L
115
115
260
230
105
105
250
220
95
95
240
210
90
90
240
210
MIL &
IND
S
L
____
____
____
____
____
____
____
____
95
95
290
250
90
90
290
250
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
MIL &
IND
S
L
____
____
____
____
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
COM'L
S
L
110
110
240
200
100
100
230
190
90
90
220
180
85
85
220
180
MIL &
IND
S
L
____
____
____
____
____
____
____
____
90
90
260
215
85
85
260
215
mA
mA
mA
mA
3099 tbl 08
NOTES
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be - 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and
TTL HIGH = VIH and LOW = VIL.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
___
___
V
µA
VDR
VCC for Data Retention
VCC = 2V
ICCDR
Data Retention Current
CE = VHC
MIL. & IND.
___
100
4000
VIN = VHC or = VLC
COM'L.
___
100
1500
___
___
___
V
tRC(2)
___
___
V
tCDR(3)
Chip Deselect to Data Retention Time
SCE = VHC(4) when SCLK = u
tR(3)
Operation Recovery Time
CMD > VHC
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
6.42
5
3099 tbl 09
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Data Retention Power Down/Up Waveform (Random and Sequential Port)(1,2)
DATA RETENTION MODE
VCC
VDR ≥ 2V
4.5V
4.5V
tCDR
CE
tR
VDR
VIH
VIH
SCLK
SCE
tPD
tPU
ICC
ISB
3099 drw 04
ISB
NOTES :
1. SCE is synchronized to the sequential clock input.
2. CMD > VCC - 0.2V.
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
347Ω
30pF
347Ω
3099 drw 06
3099 drw 05
Figure 1. AC Output Test Load
Input Rise/Fall Times
8
7
GND to 3.0V
6
3ns Max.
Input Timing Reference Levels
1.5V
tAA/tCD/tEB 5
(Typical, ns)
4
Output Reference Levels
1.5V
3
Figures 1,2 and 3
2
Output Load
,
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ, t BHZ,
tOHZ,t WHZ, tCKHZ, and tCKLZ )
(*Including scope and jig.)
AC Test Conditions
Input Pulse Levels
5pF*
1
3099 tbl 10
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
capacitance.
-1
-2
-3
20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
3099 drw 07
Figure 3. Lumped Capacitance Load Typical Derating Curve
6
,
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table I: Random Access Read and Write(1,2)
Inputs/Outputs
CE
CMD
R/W
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
L
H
H
L
L
L
DATAOUT
DATAOUT
L
H
H
L
L
H
DATAOUT
High-Z
Read lower Byte only.
L
H
H
L
Read upper Byte only.
L
L
H
H
L
L
MODE
Read both Bytes.
H
L
High-Z
DATAOUT
(3)
L
L
DATAIN
DATAIN
Write to both Bytes.
(3)
L
H
DATAIN
High-Z
Write to lower Byte only.
(3)
H
H
L
H
L
H
H
L
High-Z
DATAIN
Write to upper Byte only.
H
H
X
X
X
X
High-Z
High-Z
Both Bytes deselected and powered down.
L
H
H
H
X
X
High-Z
High-Z
Outputs disabled but not powered down.
L
H
X
X
H
H
H
H
L
L
L
H
(3)
H
(4)
L
(4)
L
L
High-Z
High-Z
Both Bytes deselected but not powered down.
(4)
DATAIN
DATAIN
Write I/O0-I/O11 to the Buffer Command Register.
(4)
DATAOUT
DATAOUT
Read contents of the Buffer Command Register
via I/O0-I/O12.
L
L
3099 tbl 11
NOTES:
1. H = V IH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT 2, SCLK, SI/O0-SI/O 15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
Truth Table II: Sequential Read(1,2,3,6,8)
Inputs/Outputs
SCLK
SCE
CNTEN
SR/W
EOB1
EOB2
SOE
SI/O
↑
L
L
H
LOW
LAST
L
[EOB1]
↑
L
H
H
LAST
LAST
L
[EOB1 - 1]
↑
L
L
H
LAST
LOW
L
[EOB2]
↑
L
H
H
LAST
LAST
L
[EOB2 - 1]
↑
L
L
H
LOW
LOW
H
High-Z
MODE
Counter Advanced Sequential Read with EOB1 reached.
Non-Counter Advanced Sequential Read, without EOB1 reached
Counter Advanced Sequential Read with EOB2 reched.
Non-Counter Advanced Sequential Read without EOB2 reached
Counter Advanced Sequential Non-Read with EOB1 and EOB2 reached
3099 tbl 12
Truth Table III: Sequential Write(1,2,3,4,5,6,7,8)
Inputs/Outputs
SCLK
SCE
CNTEN
SR/W
EOB1
EOB2
SOE
SI/O
↑
L
H
L
LAST
LAST
H
SI/OIN
Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached.
↑
L
L
L
LOW
LOW
H
SI/OIN
Counter Advanced Sequential Write with EOB1 and EOB2 reached.
↑
H
H
X
LAST
LAST
X
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
↑
H
L
X
NEXT
NEXT
X
High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
MODE
3099 tbl 13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT 1, SSTRT 2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the
sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge
of the clock during the cycle in which SR/W = VIL.
5. SI/O IN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle
after Reset, Read (and write) Cycle".
6.42
7
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table: Sequential Address Pointer Operations(1,2,3,4,5)
Inputs/Outputs
SCLK
SLD
SSTRT 1
SSTRT 1
SOE
↑
H
L
H
X
Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached.
↑
H
H
L
X
Counter Advanced Sequential Write with EOB1 and EOB2 reached.
↑
L
H
H
H(6) No Write or Read due to Sequential port Deselect. No counter advance.
MODE
3099 tbl 14
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST is continuously HIGH. The conditions of SCE CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential
port operation (due to the counter and register control). CMD should be HIGH (CMD = V IH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented
during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
Address Pointer Load Control (SLD)
In SLD mode, there is an internal delay of one cycle before the address
pointer changes in the cycle following SLD. When SLD is LOW, data on
the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-toHIGH transition of SCLK. On the cycle following SLD, the address pointer
changes to the address location contained in the data-in register. SSTRT1,
SSTRT2 may not be low while SLD is LOW, or during the cycle following
SLD. The SSTRT1 and SSTRT2 require only one clock cycle, since these
addresses are pre-loaded in the registers already.
SLD Mode(1)
SLD
(1)
SCLK
B
A
ADDRIN
SI/O0-11
C
DATAOUT
SSTRT(1 or 2)
3099 drw 08
NOTE:
1. At SCLK edge (A), SI/O0-SI/O 11 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B),
SLD and SSTRT1,2 must be HIGH to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge
(B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
Sequential Load of Address into Pointer/Counter(1)
MSB
15
14
13
12
11 -------------------------------------------------------------------------------------------------- 0
H
H
H
L
Address Loaded into Pointer
LSB SI/O BITS
3099 drw 09
NOTE:
1. "H" = VIH and "L" = VIL for the SI/O intput state.
8
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Reset (RST)
Register
Setting RST LOW resets the control state of the SARAM. RST functions
asynchronously of SCLK (i.e. not registered). The default states after a
reset operation are displayed in the adjacent chart.
Contents
Address
0
EOB Flags
Cleared to HIGH state
Buffer Flow Mode
BUFFER CHAINING
Start Address Buffer #1
0 (1)
End Address Buffer #1
4095 (4K)
(1)
Cleared (set at invalid points)
(1)
Cleared (set at invalid points)
Start Address Buffer #2
End Address Buffer #2
Registered State
SCE = VIH, SR/W = VIL
3099 tbl 15
NOTE:
1. Start address and End of address for Buffer #2 and the Flow Control for
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
Buffer Command Mode (CMD)
Buffer Command Mode (CMD) allows the random access port to
control the state of the two buffers. Address pins A0-A2 and I/O pins I/O0I/O11 are used to access the start of buffer and the end of buffer addresses
and to set the flow control mode of each buffer. The Buffer Command Mode
also allows reading and clearing the status of the EOB flags. Seven different
CMD cases are available depending on the conditions of A0-A2 and R/
W. Address bits A3-A11 and data I/O bits I/O12-I/O15 are not used during
this operation.
Random Access Port CMD Mode(1)
Case #
A2-A0
R/W
DESCRIPTIONS
1
000
0 (1)
Write (read) the start address of Buffer #1 through I/O 0-I/O11.
2
001
0 (1)
Write (read) the end address of Buffer #1 through I/O0-I/O11.
3
010
0 (1)
Write (read) the start address of Buffer #2 through I/O 0-I/O11.
4
011
0 (1)
Write (read) the end address of Buffer #2 through I/O0-I/O11.
5
100
0 (1)
Write (read) flow control register.
6
101
0
Write only - clear EOB1 and/or EOB2 flag.
7
101
1
Read only - flag status register.
8
110/111
(X)
(Reserved)
3099 tbl 16
NOTE:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Cases 1 through 4: Start and End of Buffer Register Description(1,2)
MSB
15
14
13
12
11 -------------------------------------------------------------------------------------------------- 0
H
H
H
L
Address Loaded into Buffer
LSB I/O BITS
3099 drw 10
NOTES:
1. "H" = V OH for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = VIL for I/O in the input state.
2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and
CE = VIH.
Case 5: Buffer Flow Modes
Within the SARAM, the user can designate one of two buffer flow modes
for each buffer. Each buffer flow mode defines a unique set of actions for
the sequential port address pointer and EOB flags. In BUFFER CHAINING mode, after the address pointer reaches the end of the buffer, it sets
the corresponding EOB flag and continues from the start address of the
other buffer. In STOP mode, the address pointer stops incrementing after
it reaches the end of the buffer. There is no linear or mask mode available.
6.42
9
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
(1,2)
Flow Control Register Description
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
4
3
2
Counter Release
(STOP Mode Only)
1
0
LSB I/O BITS
Buffer #1 flow control
Buffer #2 flow control
3099 drw 11
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is
also released by RST, SLD, SSTRT1 and SSTRT2 operations.
Flow Control Bits(5)
Flow Control
Bit 1 & Bit 0
(Bit 3 & Bit 2)
Mode
Functional Description
00
BUFFER
CHAINING
01
STOP
EOB1 (EOB2) is asserted (Active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #2).
The pointer value is changed to the start address of Buffer #2 (Buffer #1)(1,3)
EOB1 (EOB2) is asserted when the pointer matches the end address of Butler #1 (Butler #2).
The address pointer will stop inc rementing when it reaches the next address (EOB address + 1), if CNTEN is LOW
on the next clock's rising edge. Otherwise, the address po inter will stop incrementing on EOB. Sequential write
operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow
control register.(1,2,4)
3099 tbl 17
NOTES:
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD flow control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise the flow
control will remain in the stop mode.
5. Flow Control Bit settings of '10' and '11' are reserved.
6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode"
section. RST conditions are not set to valid addresses.
Cases 6 and 7: Flag Status Register Bit Description(1)
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
LSB I/O BITS
End of buffer flag for Buffer #1
NOTE:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
End of buffer flag for Buffer #2
3099 drw 12
Cases 6: Flag Status Register
Write Conditions(1)
Flag Status Bit 0, (Bit 1)
1
Case 7: Flag Status Register Read
Conditions
Functional Description
0
Clears Buffer Flag EOB1, (EOB2).
Flag Status Bit 0, (Bit 1)
1
No chang e to the Buffer Flag. (2)
0
EOB1 (EOB2) flag has not been set, the
Pointer has not reached the End of the
Buffer.
1
EOB1 (EOB2) flag has been set, the
Pointer has reached the end of the
Buffer.
3099 tbl 18
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
cleared while the second is left alone, or both may be cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
Functional Description
3099 tbl 19
Cases 8 and 9: (Reserved)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
10
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port: AC Electrical Characteristics Over
the Operating Temperature and Supply Voltage Range(2,4,5)
70824X20
Com'l Only
Symbol
Parameter
70824X25
Com'l Only
70824X45
Com'l &
Military
70824X35
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
45
____
ns
tAA
Address Access Time
____
20
____
25
____
35
____
45
ns
Chip Enable Access Time
____
20
____
25
____
35
____
45
ns
Byte Enable Access Time
____
20
____
25
____
35
____
45
ns
tOE
Output Enable Access Time
____
10
____
10
____
15
____
20
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
3
____
3
____
3
____
3
____
ns
3
____
3
____
3
____
3
____
ns
2
____
2
____
2
____
2
____
ns
____
10
.____
12
____
15
____
15
ns
____
tACE
tBE
tCLZ
tBLZ
Chip Select Low-Z Time
(1)
Byte Select Low-Z Time
(1)
tOLZ
Output Enable Low-Z Time
tCHZ
Chip Select High-Z Time (1)
tBHZ
Byte Select High-Z Time (1)
tOHZ
Output Select High-Z Time
(1)
(1)
tPU
Chip Select Power-Up Time
tPD
Chip Select Power-Down Time
10
____
12
____
15
____
15
ns
____
9
____
11
____
15
____
15
ns
0
____
0
____
0
____
0
____
ns
____
20
____
25
____
35
____
45
ns
3099 tbl 20
Random Access Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(2,4,5)
70824X20
Com'l Only
Symbol
Parameter
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
20
____
25
____
35
____
45
____
ns
15
____
20
____
25
____
30
____
ns
15
____
20
____
25
____
30
____
ns
0
____
0
____
0
____
0
____
ns
13
____
20
____
25
____
30
____
ns
15
____
20
____
25
____
30
____
ns
ns
WRITE CYCLE
tWC
tCW
Write Cycle Time
Chip Enable to End-of-Write
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
tWP
tBP
(3)
(3)
Write Pulse Width
(3)
Byte Enable Pulse Width
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
tWHZ
Write Enable Output High-Z Time (1)
____
10
____
12
____
15
____
15
ns
tDW
Data Set-up Time
13
____
15
____
20
____
25
____
ns
0
____
0
____
0
____
0
____
ns
3
____
3
____
3
____
3
____
tDH
tOW
Data Hold Time
Output Active from End-of-Write
ns
3099 tbl 21
NOTES:
1. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not
production tested.
2. 'X' in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required t DW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified tWP . For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = V IL).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
11
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Read Cycles: Random Access Port(1,2)
tRC
ADDR
tAA
tOH
(2)
tACS
CE
tCHZ
tCLZ
LB, UB
tBHZ
tBE
tBLZ
OE
tOE
tOHZ
tOLZ
I/OOUT
Valid Data Out
3099 drw 13
NOTES:
1. R/W is HIGH for read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
Waveform of Read Cycles: Buffer Command Mode
tRC
ADDR
tAA
tOH
tACS
(1)
CMD
tCHZ
tCLZ
LB, UB
tBHZ
tBE
tBLZ
OE
tOE
tOLZ
tOHZ
I/OOUT
Valid Data Out
3099 drw 14
NOTE:
1. CE = VIH when CMD = VIL.
12
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycle No.1 (R/W Controlled Timing)
Random Access Port(1,6)
tWC
ADDR
tAW
R/W
(8)
CE, LB, UB
tWR(3)
tWP(2)
tAS
(5)
tDH
tDW
I/OIN
Valid Data In
OE
tOHZ
tWHZ
I/OOUT
Data Out
(4)
(4)
Data Out
tACS
tBE
tOW
3099 drw 15
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
Random Access Port(1,6,7)
tWC
ADDR
tAW
(8)
CE, LB, UB
(5)
tAS
tWR
(2)
tCW
tBP(2)
R/W
tDW
I/OIN
(3)
tDH
Valid Data
3099 drw 16
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = VIL, CE = V IL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required t DW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified tWP . For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
6.42
13
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics Over
the Operating Temperature and Supply Voltage Range(1,3)
70824X20
Com'l Only
Symbol
Parameter
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
25
____
30
____
40
____
50
____
ns
12
____
15
____
18
____
ns
12
____
15
____
18
____
ns
ns
READ CYCLE
tCYC
Sequential Clock Cycle Time
tCH
Clock Pulse HIGH
10
____
tCL
Clock Pulse LOW
10
____
5
____
5
____
6
____
6
____
ns
tES
Count Enab le and Address Pointer Set-up Time
tEH
Count Enable and Address Pointer Hold Time
2
____
2
____
2
____
2
____
tSOE
Output Enable to Data Valid
____
8
____
10
____
15
____
20
ns
tOLZ
Output Enable Low-Z Time (2)
2
____
2
____
2
____
2
____
ns
tOHZ
Output Enable High-Z Time
(2)
____
9
____
11
____
15
____
15
ns
tCD
Clock to Valid Data
____
20
____
25
____
35
____
45
ns
tCKHZ
Clock High-Z Time (2)
____
12
____
14
____
17
____
20
ns
tCKLZ
Clock Low-Z Time
(2)
3
____
3
____
3
____
3
____
ns
tEB
Clock to EOB
____
13
____
15
____
18
____
23
ns
3099 tbl 22
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,3)
70824X20
Com'l Only
Symbol
Parameter
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
25
____
30
____
40
____
50
____
ns
ns
WRITE CYCLE
tCYC
Sequential Clock Cycle Time
tFS
Flow Restart Time
13
____
15
____
20
____
20
____
tWS
Chip Select and Read/Write Set-up Time
5
____
5
____
6
____
6
____
ns
tWH
Chip Select and Read/Write Hold Time
2
____
2
____
2
____
2
____
ns
5
____
5
____
6
____
6
____
ns
2
____
2
____
2
____
2
____
tDS
tDH
Input Data Set-up Time
Input Data Hold Time
ns
3099 tbl 23
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not
production tested.
3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
14
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,2)
70824X20
Com'l Only
Symbol
Parameter
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tRSPW
Reset Pulse Width
13
____
15
____
20
____
20
____
ns
tWERS
Write Enable HIGH to Reset HIGH
10
____
10
____
10
____
10
____
ns
tRSRC
Reset HIGH to Write Enable LOW
10
____
10
____
10
____
10
____
ns
15
____
20
____
25
____
25
____
tRSFV
Re set HIGH to Flag Valid
ns
3099 tbl 24
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Sequential Port: Write, Pointer Load Non-Incrementing Read
tCYC
tCH
tCL
SCLK
tES
(2)
(3)
CNTEN
tEH
tES
(1)
SLD
tDS
SI/OIN
tEH
Dx
tDH
HIGH IMPEDANCE
A0
tWS
tWS
tWH
tWH
SR/W
tWS
tWS
tWH
tWH
SCE
tCSZ
tCKHZ
tCD
SOE
tSOE
tOLZ
tOHZ
D0
SI/OOUT
tCKLZ
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
6.42
15
D0
D0
3099 drw 17
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: Write, Pointer Load, Burst Read
tCH
tCYC
tCL
SCLK
tEH
tES
(3)
CNTEN
tES
SLD
(1)
tDS
SI/OIN
(2)
tEH
Dx
tDS
tDH
HIGH IMPEDANCE
A0
tWS
tWS
tWH
tDH
D2
tWH
SR/W
tWS
tWS
tWH
tWH
SCE
tSD
SOE
tSOP
tOHZ
tOLZ
(2)
SI/OOUT
D0
D1
tCKLZ
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
3099 drw 18
Read STRT/EOB Flag Timing - Sequential Port
tCH
SCLK
tCYC
tCL
tES
CNTEN
tEH
(4)
tES
(2)
tEH
SSTRT1/2
(1)
tDS
SI/OIN
HIGH IMPEDANCE
Dx
tWS
tWS
tWH
tDH
D3
tWH
SR/W
tWS
SCE
tWS
tWH
tWH
(3)
tCD
SOE
tSOE
tOHZ
tOLZ
SI/OOUT
(5)
D0
D1
D2
(2)
tCKLZ
EOB1/2
tEB
3099 drw19
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that
cycle. If SCE = V IL and is clocked in while SR/W = V IL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
contention and permit a write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
16
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port
tCYC
tCH
tCL
SCLK
tES
CNTEN
tES
tEH
(4)
(3)
tES
tEH
SLD
(1)
tDS
SI/OIN
tEH
Dx
tWS
tDH
A0
tDS
tDS
tDH
HIGH IMPEDANCE
D1
D0
tWS
tDH
tWH
tWH
(4)
SR/W
tWS
tWS
tWH
tWH
SCE
tCKHZ
tCD
SOE
(5)
SI/OOUT
tOHZ
HIGH IMPEDANCE
D0
3099 drw 20
tCKLZ
Waveform of Burst Write Cycles: Sequential Port
tCH
tCYC
tCL
SCLK
tES
CNTEN
(3)
(2)
tEH
tES
SLD
(1)
tDS
SI/OIN
tEH
Dx
tWS
A0
tDS
tDH
tDH
D0
tWS
tWH
D1
D2
tWH
SR/W
(5)
tWS
SCE
tWS
tWH
tWH
SOE
(5)
tCKLZ
tCD
SI/OOUT
HIGH IMPEDANCE
D2
3099 drw 21
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is LOW.
4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.42
17
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
tCH
tCL
SCLK
tES
CNTEN
tEH
(2)
(4)
tEH
tES
SSTRT1/2
(1)
tDS
tDH
SI/OIN
D0
Dx
tWS
HIGH IMPEDANCE
D1
D2
D3
tWS
tWH
tWH
SR/W
(5)
tWS
SCE
tWS
tWH
tWH
(3)
SOE
(6)
tCKLZ
tCD
SI/OOUT
HIGH IMPEDANCE
D3
EOB1/2
tEB
3099 drw 22
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that
cycle. If SCE = V IL and is clocked in while SR/W = V IL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
contention and permit a write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
18
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Counter Enable Cycle After Reset, Write Cycle(1,4,6)
SCLK
RST
CNTEN
SI/OIN
(2)
D0
D1
D2
D3
D4
3099 drw 23
Sequential Counter Enable Cycle After Reset, Read Cycle(1,4)
SCLK
RST
SR/W
(3)
CNTEN
(5)
SI/OOUT
D0
(5)
D1
D2
D3
3099 drw 24
NOTES:
1. 'D0' represents data input for Address = 0, 'D1' represents data input for Address = 1, etc.
2. If CNTEN = VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a t CD after the SR/W = V IH is clocked. The RST sets SR/W = LOW internally and therefore disables the output until the next clock.
4. SCE = VIL throughout all cycles.
5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/W = VIL.
6.42
19
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port - Reset Timing
tRSPW
RST
tRSRC
R/W, SR/W CMD
(4)
or (UB + LB)
tWERS
tRSFV
EOB(1 or 2)
Flag Valid
3099 drw 25
Random Access Port Restart Timing of Sequential Port(1)
0.5 x tCYC
tFS
SCLK
R/W
(2)
2-5ns
6-7ns
(3)
CLR
Block
(Internal Signal)
3099 drw 26
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being LOW for tWERS and tRSRC periods or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
20
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Ordering Information
70824
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (–55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
PF
84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
20
25
35
45
Commercial
Commercial
Commercial
Commercial
S
L
Standard Power
Low Power
Only
Only
& Military
& Military
Speed in nanoseconds
70824 64K (4K x 16) Sequential Access Random
Access Memory
3099 drw 27
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For specific speeds, packages and powers contact your sales office.
Datasheet Document History
3/8/99:
6/4/99:
11/10/99:
4/18/00:
5/23/00:
01/29/09:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 Added additional notes to pin configurations
Changed drawing format
Replaced IDT logo
Page 3 Added "Outputs" in Sequential pin description table
Changed ±200mV to 0mV in notes
Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Page 21 Removed "IDT" from orderable part number
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6.42
21
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