IDT70825S/L
HIGH SPEED 128K (8K X 16 BIT)
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
Features
◆
◆
◆
◆
◆
◆
High-speed access
– Commercial: 20/25/35/45ns (max.)
Low-power operation
– IDT70825S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70825L
Active: 775mW (typ.)
Standby: 1mW (typ.)
8K x 16 Sequential Access Random Access Memory
(SARAM™)
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
High speed operation
– 20ns tAA for random access port
– 20ns tCD for sequential port
– 25ns clock cycle time
Architecture based on Dual-Port RAM cells
◆
◆
◆
◆
◆
◆
Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Description
The IDT70825 is a high-speed 8K x 16-Bit Sequential Access
Random Access Memory (SARAM). The SARAM offers a single-chip
solution to buffer data sequentially on one port, and be accessed
randomly (asynchronously) through the other port. The device has a
Dual-Port RAM based architecture with a standard SRAM interface for the
random (asynchronous) access port, and a clocked interface with counter
Functional Block Diagram
13
A0-12
CE
OE
R/W
LB LSB
MSB
UB
CMD
Random
Access
Port
Controls
Sequential
Access
Port
Controls
8K X 16
Memory
Array
16
I/O0-15
13
DataL
DataR
AddrL
AddrR
16
13
Reg.
13
16
RST
SCLK
CNTEN
SOE
SSTRT1
SSTRT2
SCE
SR/W
SLD
,
SI/O0-15
RST
13
13
Pointer/
Counter
13
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
EOB1
13
COMPARATOR
EOB2
3016 drw 01
JANUARY 2009
1
DSC-3016/10
©2009 Integrated Device Technology, Inc.
6.07
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
down feature, controlled by CE, permits the on-chip circuitry of each port
to enter a very low standby power mode.
The IDT70825 is packaged in a 80-pin Thin Quad Flatpack (TQFP)
or 84-pin Pin Grid Array (PGA).
sequencing for the sequential (synchronous) access port.
Fabricated using CMOS high-performance technology, this memory
device typically operates on less than 775mW of power at maximum
high-speed clock-to-data and Random Access. An automatic power
SI/O2
SI/O3
VCC
SI/O4
SI/O5
SI/O6
SI/O7
GND
SI/O8
SI/O9
SI/O10
SI/O11
VCC
SI/O12
SI/O13
SI/O14
SI/O15
GND
N/C
A12
Pin Configurations(1,2,3)
INDEX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
2
58
3
63
I/O1
66
I/O2
4
57
5
56
55
6
54
7
8
53
52
IDT70825PF
PN80-1(4)
9
10
11
51
50
49
80-PinTQFP
Top View(5)
12
13
48
14
47
15
46
45
16
17
44
18
43
19
42
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
61
60
VCC
EOB1 GND CNTEN GND SSTRT2 SR/W NC
GND
64
62
43
NC
58
55
59
56
51
49
57
50
RST SLD
53
48
47
46
45
44
41
52
I/O4
72
38
VCC
71
I/O7
75
I/O9
76
I/O5
77
I/O8
32
28
26
I/O12 I/O13
I/O14
7
2
3
5
4
8
LB
OE
I/O15 GND
84
12
CMD VCC
NC
1
11
6
10
A0
9
A2
14
VCC
15
23
A4
13
A7
16
20
22
A10
18
A12
19
06
30
05
27
04
25
03
24
GND
02
21
NC
R/W
UB
CE
A1
A5
A3
A6
A8
A9
A11
A
B
C
D
E
F
G
H
J
K
L
INDEX
07
36
NC SI/O15
17
08
34
SI/O14 SI/O13
83
82
29
09
37
SI/O12 VCC SI/O11
80
81
31
10
39
SI/O9 SI/O10 SI/O6
84-Pin PGA
Top View(5)
78
35
11
40
SI/O8 SI/O7 GND
IDT70825G
G84-3(4)
74
I/O10 I/O11 VCC
79
NC
SI/O4 SI/O5
33
73
I/O6 GND
70
42
SI/O2 VCC
68
01
3016 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN-80-1 package body is approximately 14mm x 14mm x 1.4mm.
G84-3 package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
,
3016 drw 02
SCE SI/O0 SI/O1 SI/O3
SCLK GND SSTRT1
I/O3 GND
69
54
I/O0 EOB2 SOE
65
67
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
VCC
VCC
A1
A0
CMD
CE
LB
UB
R/W
OE
1
I/O1
GND
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
VCC
I/O12
I/O13
I/O14
I/O15
GND
SI/O1
SI/O0
GND
N/C
SCE
SR/W
RST
SLD
SSTRT2
SSTRT1
GND
GND
CNTEN
SOE
SCLK
GND
EOB2
EOB1
VCC
I/O0
Industrial and Commercial Temperature Ranges
,
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Pin Descriptions: Random Access Port(1)
SYMBOL
NAME
I/O
DESCRIPTIONS
A0-A12
Address Lines
I
Address inputs to access the 8192-word (16-Bit) memory array.
I/O0-I/O15
Inputs/Outputs
I
Random access data inputs/outputs for 16-Bit wide data.
CE
Chip Enable
I
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE =
VIH, unless it is altered by the sequential port. CE and CMD may not be LOW at the same time.
CMD
Control Register
Enable
I
When CMD is LOW, address lines A 0-A2, R/W, and inputs/outputs I/O0-I/O12, are used to access the control
register, the flag register, and the start and end of buffer registers. CMD and CE may not b e LOW at the same
time.
R/W
Read/Write Enable
I
If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read o ut of the array when
R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and
CMD may not be LOW at the same time.
OE
Output Enable
I
When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in
the High-impedance state.
LB, UB
Lower Byte, Upper
Byte Enables
I
When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH I/O0-I/O7 are tristated and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and
is asynchronous from LB.
VCC
Power Supply
I
Seven +5V powe r supply pins. All V CC pins must be connected to the same +5V VCC supply.
GND
Ground
I
Ten ground pins. All ground pins must be connected to the same ground supply.
3016 tbl 01
(1)
Pin Descriptions: Sequential Access Port
SYMBOL
NAME
I/O
DESCRIPTIONS
SI/O0-15
Inputs/Outputs
I
Sequential data inputs/outputs for 16-bit wide data.
SCLK
Clock
I
SI/O0-SI/O15, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential
access port address pointer increments by 1 on each LOW-to-HIGH transition of SCLK when CNTEN is LOW.
SCE
Chip Enable
I
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When SCE
is HIGH, the sequential access port is disabled into powere d-down mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained, unless altered by the random
access port.
CNTEN
Control Enable
I
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
independent of CE.
SR/W
Read/Write Enable
I
SLD
Address Pointer
Load Control
I
SSTRT1,
SSTRT2
Load Start of
Address Register
I
EOB1,
EOB2
End of Buffer Flag
I
EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address stored in the end
of the buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into Bit 0
and/or Bit 1 of the control register at address 101. EOB1 and EOB2 are dependent on separate internal
registers, and therefore separate match addresses.
SOE
Output Enable
I
SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers and the
sequentially addressed d ata is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state.
SOE is asynchronous to SCLK.
RST
Reset
I
When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the
EOB1 and EOB2 flags are set HIGH. Rst is asynchronous to SCLK.
When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/ W is
HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination
of a write cycle is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When
SLD is LOW, data on the inputs SI/O0-SI/O12 is loaded into a data-in registe r on the LOW-to-HIGH transition of
SCLK. On the cycle following SLD, the address pointer changes to the addre ss location contained in the datain register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD.
When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is lo aded into the address pointer on
the LOW-to-HIGH transition of SCLK. The start address are stored in internal registers. SSTRT1 and SSTRT2
may not be LOW while SLD is LOW or during the cycle following SLD.
3016 tbl 02
NOTE:
1. "I/O" is bidirectional input and output. "I" is input and "O" is output.
6.42
3
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Absolute Maximum Ratings(1)
Symbol
VTERM(2)
Rating
Terminal Voltage
with Respect
to GND
Commercial
& Industrial
Unit
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
IOUT
DC Output
Current
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage(1,2)
Grade
Ambient
Temperature
GND
Vcc
Commercial
0OC to +70OC
0V
5.0V + 10%
0V
5.0V + 10%
O
Industrial
O
-40 C to +85 C
3016 tbl 04a
50
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
mA
3016 tbl 03a
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM >
Vcc + 10%.
Recommended DC Operating
Conditions
Symbol
Capacitance
Symbol
CIN
COUT
Conditions(2)
Parameter
Input Capacitance
Output Capacitance
VCC
Supply Voltage
GND
Ground
VIH
(TA = +25°C, f = 1.0mhz, TQFP only)
Max.
VIN = 3dV
9
VOUT = 3dV
10
V IL
Unit
Parameter
Input High Voltage
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
-0.5
(1)
(2)
6.0
____
0.8
pF
V
3016 tbl 05
NOTES:
1. VIL > –1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
pF
V
3016 tbl 06
NOTES:
1. This parameter is determined by device characterization, but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70825S
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current
Output Leakage Current
Test Conditions
70825L
Min.
Max.
Min.
Max.
Unit
VCC = 5.5V, VIN = 0V to V CC
___
5
___
1
µA
VOUT = 0V to VCC
___
5
___
1
µA
0.4
___
0.4
V
___
2.4
___
V
VOL
Output Low Voltage
IOL = +4mA
___
VOH
Output High Voltage
IOH = -4mA
2.4
3016 tbl 07
4
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,8) (VCC = 5.0V ± 10%)
70825X20
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70825X25
Com'l Only
70825X35
Com'l Only
70825X45
Com'l Only
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
Dynamic Operating
Current
(Both Ports Active)
CE = VIL,
Outputs Disabled
SCE = VIL(5)
f = fMAX(3)
COM'L
S
L
180
180
380
330
170
170
360
310
160
160
340
290
155
155
340
290
mA
Standby Current
(Both Ports - TTL
Level Inputs)
SCE and CE > VIH(7)
CMD = VIH
f = fMAX(3)
COM'L
S
L
25
25
70
50
25
25
70
50
20
20
70
50
16
16
70
50
mA
Standby Current
(One Port - TTL
Level Inputs)
CE or SCE = VIH
Active Port Outputs Disabled,
f=fMAX(3)
COM'L
S
L
115
115
260
230
105
105
250
220
95
95
240
210
90
90
240
210
mA
Full Standby Current
(Both Ports CMOS Level Inputs)
Both Ports CE and
SCE > VCC - 0.2V(6,7)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
Full Standby Current
(One Port CMOS Level Inputs)
One Port CE or
SCE > VCC - 0.2V(6)
Outputs Disabled (Active Port)
VIN > VCC - 0.2V or VIN < 0.2V
f = fMAX(3)
COM'L
S
L
110
110
240
200
100
100
230
190
90
90
220
180
85
85
220
180
mA
3016 tbl 08a
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is LOW (SCE=VIL) when clocked in by SCLK.
6. SCE may be - 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and
TTL HIGH = VIH and LOW = V IL.
8. Industrial temperature: for other speeds, packages and powers contact your sales office.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
___
___
V
µA
VDR
VCC for Data Retention
VCC = 2V
ICCDR
Data Retention Current
CE > VHC
IND.
___
100
4000
VIN = VHC or = VLC
COM'L.
___
100
1500
___
___
___
V
___
___
V
tCDR(3)
(3)
tR
Chip Deselect to Data Retention Time
Operation Recovery Time
SCE = VHC(4) when SCLK = ↑
CMD = VHC
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
6.42
5
(2)
tRC
3016 tbl 09a
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Data Retention and Power Down/Up Waveform
(Random and Sequential Port)(1,2)
DATA RETENTION MODE
VDR ≥ 2V
4.5V
VCC
4.5V
tCDR
tR
VDR
CE
VIH
VIH
SCLK
SCE
tPD
tPU
ICC
ISB
3016 drw 04
ISB
NOTES:
1. SCE is synchronized to the sequential clock input.
2. CMD > VCC - 0.2V.
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
347Ω
5pF*
,
3016 drw 06
3016 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ ,
tBHZ , tOHZ, t WHZ, tCKHZ, and tCKLZ )
*Including scope and jig.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
8
6
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
7
GND to 3.0V
tAA/tCD/tEB 5
(Typical, ns)
4
3
Figures 1,2 and 3
2
3016 tbl 10
1
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
capacitance.
-1
-2
-3
20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
3016 drw 07
Figure 3. Lumped Capacitance Load Typical Derating Curve
6
,
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Truth Table I: Random Access Read and Write(1,2)
Inputs/Outputs
CE
CMD
R/W
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
L
H
H
L
L
L
DATAOUT
DATAOUT
L
H
H
L
L
H
DATAOUT
High-Z
Read lower Byte only.
L
H
H
L
H
L
High-Z
DATAOUT
Read upper Byte only.
L
H
L
H(3)
L
L
DATAIN
DATAIN
Write to both Bytes.
L
(3)
L
H
DATAIN
High-Z
Write to lower Byte only.
(3)
L
H
H
Mode
Read both Bytes.
L
H
L
H
H
L
High-Z
DATAIN
Write to upper Byte only.
H
H
X
X
X
X
High-Z
High-Z
Both Bytes deselected and powered down.
L
H
H
H
X
X
High-Z
High-Z
Outputs disabled but not powered down.
L
H
X
X
H
H
H
H
L
L
L
H
(3)
H
(4)
L
(4)
L
L
High-Z
High-Z
Both Bytes deselected but not powered down.
(4)
DATAIN
DATAIN
Write I/O0-I/O11 to the Buffer Command Register.
(4)
DATAOUT
DATAOUT
Read contents of the Buffer Command Register
via I/O0-I/O12.
L
L
3016 tbl 11
NOTES:
1. H = V IH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O 0-SI/O15 , EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
Truth Table II: Sequential Read(1,2,3,6,8)
Inputs/Outputs
SCLK
SCE
CNTEN
SR/W
EOB1
EOB2
SOE
SI/O
↑
L
L
H
LOW
LAST
L
[EOB1]
↑
L
H
H
LAST
LAST
L
[EOB1 - 1]
↑
L
L
H
LAST
LOW
L
[EOB2]
↑
L
H
H
LAST
LAST
L
[EOB2 - 1]
↑
L
L
H
LOW
LOW
H
High-Z
MODE
Counter Advanced Sequential Read with EOB1 reached.
Non-Counter Advanced Sequential Read, without EOB1 reached
Counter Advanced Sequential Read with EOB2 reched.
Non-Counter Advanced Sequential Read without EOB2 reached.
Counter Advanced Sequential Non-Read with EOB1 and EOB2 reached.
3016 tbl 12
Truth Table III: Sequential Write
(1,2,3,4,5,6,7,8)
Inputs/Outputs
SCLK
SCE
CNTEN
SR/W
EOB1
EOB2
SOE
SI/O
↑
L
H
L
LAST
LAST
H
SI/OIN
Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached.
↑
L
L
L
LOW
LOW
H
SI/OIN
Coounte r Advanced Sequential Write with EOB1 and EOB2 reached.
↑
H
H
X
LAST
LAST
X
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
↑
H
L
X
NEXT
NEXT
X
High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
MODE
3016 tbl 13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential
port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock
during the cycle in which SR/W = VIL.
5. SI/O IN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after
Reset, Read (and write) Cycle".
6.42
7
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Truth Table IV: Sequential Address Pointer Operations(1,2,3,4,5)
Inputs/Outputs
SCLK
SLD
SSTRT1
SSTRT2
SOE
↑
H
L
H
X
Start address for Buffer #1 loaded into Address Pointer.
↑
H
H
L
X
Start address for Buffer #2 loaded into Address Pointer.
↑
L
H
H
(6)
H
MODE
Data on SI/O0-SI/O12 loaded into Address Pointer.
3016 tbl 14
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST is continuously HIGH. The conditions of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential port
operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented
during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
Address Pointer Load Control (SLD)
data-in register. SSTRT1, SSTRT2 may not be low while SLD is LOW,
or during the cycle following SLD. The SSTRT1 and SSTRT2 require
only one clock cycle, since these addresses are pre-loaded in the
registers already.
In SLD mode, there is an internal delay of one cycle before the
address pointer changes in the cycle following SLD. When SLD is
LOW, data on the inputs SI/O0-SI/O12 is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following SLD,
the address pointer changes to the address location contained in the
SLD MODE(1)
SLD
(1)
SCLK
B
A
SI/O0-12
ADDRIN
C
DATAOUT
SSTRT(1 or 2)
3016 drw 08
NOTE:
1. At SCLK edge (A), SI/O0-SI/O12 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e. address
pointer changes). At SCLK edge (A), SSTRT1 and SSTRT 2 must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B), SLD and
SSTRT1,2 must be HIGH to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge (B), while data will
not be ready at edge (B) when SLD is used, but will be ready at edge (C).
Sequential Load of Address into Pointer/Counter(1)
MSB
15
14
13
12 ------------------------------------------------------------------------------------------------------------ 0
H
H
H
Address Loaded into Pointer
LSB SI/O BITS
3016 drw 09
NOTE:
1. "H" = VIH for the SI/O intput state.
8
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Reset (RST)
Register
Setting RST LOW resets the control state of the SARAM. RST
functions asynchronously of SCLK, (i.e. not registered). The default
states after a reset operation are as follows:
Contents
Address Pointer
EOB Flags
0
Cleared to High State
Buffer Flow Mode
BUFFER CHAINING
Start Address Buffer #1
0
(1)
End Address Buffer #1
4095
(4K)
Start Address Buffer #2
4096
(4K+1)
End Address Buffer #2
8191
(8K)
Registered State
SCE = VIH, SR/W = VIL
3016 tbl 15
BUFFER COMMAND MODE (CMD)
Buffer Command Mode (CMD) allows the random access port to
control the state of the two buffers. Address pins A0-A2 and I/O pins I/
O0-I/O12 are used to access the start of buffer and the end of buffer
addresses and to set the flow control mode of each buffer. The Buffer
Command Mode also allows reading and clearing the status of the
EOB flags. Seven different CMD cases are available depending on the
conditions of A0-A2 and R/W. Address bits A3-A12 and data I/O bits
I/O13-I/O15 are not used during this operation.
Random Access Port CMD Mode(1)
Case #
A2-A0
R/W
DESCRIPTIONS
1
000
0 (1)
Write (read) the start address of Buffer #1 through I/O 0-I/O12.
2
001
0 (1)
Write (read) the end address of Buffer #1 through I/O0-I/O12.
3
010
0 (1)
Write (read) the start address of Buffer #2 through I/O 0-I/O12.
4
011
0 (1)
Write (read) the end address of Buffer #2 through I/O0-I/O12.
5
100
0 (1)
Write (read) flow control register.
6
101
0
Write only - clear EOB1 and/or EOB2 flag.
7
101
1
Read only - flag status register.
8
110/111
(X)
(Reserved)
3016 tbl 16
NOTES:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Cases 1 through 4: Start and End of Buffer Register Description(1,2)
MSB
15
14
13
12 ------------------------------------------------------------------------------------------------------------ 0
H
H
H
Address Loaded into Buffer
LSB I/O BITS
3016 drw 10
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB 1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and CE = VIH.
Case 5: Buffer Flow Modes
Within the SARAM, the user can designate one of four buffer flow
modes for each buffer. Each buffer flow mode defines a unique set of
actions for the sequential port address pointer and EOB flags. In
BUFFER CHAINING mode, after the address pointer reaches the end
of the buffer, it sets the corresponding EOB flag and continues from the
start address of the other buffer. In STOP mode, the address pointer
stops incrementing after it reaches the end of the buffer. In LINEAR
mode, the address pointer ignores the end of buffer address and
increments past it, but sets the EOB flag. MASK mode is the same as
LINEAR mode except EOB flags are not set.
6.42
9
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Flow Control Register Description(1,2)
0
15
H
MSB
H
H
H
H
H
H
H
H
H
H
4
3
2
Counter Release
(STOP Mode Only)
1
0
LSB I/O BITS
Buffer #1 flow control
3016 drw 11
Buffer #2 flow control
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is also released
by RST, SLD, SSTRT1 and SSTRT2 operations.
Flow Control Bits
Flow Control
Bit 1 & Bit 0
(Bit 3 & Bit 2)
Mode
00
BUFFER
CHAINING
01
STOP
10
LINEAR
11
MASK
Functional Description
EOB1 (EOB2) is asserted (active LOW outp ut) when the pointer matches the end address of Buffe r #1 (Buffer #2). The
pointer value is changed to the start address of Buffer #2 (Buffer #1)(1,3)
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is LOW on the
next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operations are
inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register. (1,2,4)
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2). The pointer keeps
incrementing for further operations. (1)
EOB1 (EOB2) is not asserted when the pointe r reaches the end address of Buffer #1 (Buffer #2), although the flag status
bits will be set. The pointer keeps incrementing for further operations.
3016 tbl 17
NOTES:
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD flow control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise the flow control will
remain in the STOP mode.
Cases 6 and 7: Flag Status Register Bit Description(1)
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
0
LSB I/O BITS
End of buffer flag for Buffer #1
NOTE:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
End of buffer flag for Buffer #2
3016 drw 12
Cases 6: Flag Status Register
Write Conditions(1)
Case 7: Flag Status Register Read
Conditions
Flag Status Bit 0, (Bit 1)
Functional Description
0
Clears Buffer Flag EOB1, (EOB2).
1
No chang e to the Buffer Flag. (2)
Flag Status Bit 0, (Bit 1)
0
EOB1 (EOB2) flag has not been set, the
pointer has not reached the end of the
buffer.
1
EOB1 (EOB2) flag has been set, the
pointer has reached the end of the
buffer.
3016 tbl 18
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
cleared while the second is left alone or cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
Functional Description
3016 tbl 19
Cases 8 and 9: (Reserved)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
10
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Random Access port: AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(2,4,5)
70825X20
Com'l Only
Symbol
Parameter
70825X25
Com'l Only
70825X35
Com'l Only
70825X45
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
35
____
45
____
ns
tAA
Address Access Time
____
20
____
25
____
35
____
45
ns
tACE
Chip Enable Access Time
____
20
____
25
____
35
____
45
ns
Byte Enable Access Time
____
20
____
25
____
35
____
55
ns
Output Enable Access Time
____
10
____
10
____
15
____
20
ns
ns
tBE
tOE
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
tCLZ
Chip Select Low-Z Time (1)
3
____
3
____
3
____
3
____
ns
tBLZ
Byte Enable Low-Z Time (1)
3
____
3
____
3
____
3
____
ns
2
____
2
____
2
____
2
____
ns
tOLZ
Output Enable Low-Z Time
tCHZ
(1)
Chip Select High-Z Time
(1)
(1)
tBHZ
Byte Enable High-Z Time
tOHZ
Output Enable High-Z Time (1)
tPU
Chip Select Power Up Time
tPD
____
10
____
12
____
15
____
15
ns
____
10
____
12
____
15
____
15
ns
____
9
____
11
____
15
____
15
ns
0
____
0
____
0
____
0
____
ns
20
____
25
____
35
____
45
____
Chip Select Power Down Time
ns
3016 tbl 20a
Random Access Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(2,4,5)
70825X20
Com'l Only
Symbol
Parameter
70825X25
Com'l Only
70825X35
Com'l Only
70825X45
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
20
____
25
____
35
____
45
____
ns
15
____
20
____
25
____
30
____
ns
15
____
20
____
25
____
30
____
ns
0
____
0
____
0
____
0
____
ns
13
____
20
____
25
____
30
____
ns
15
____
20
____
25
____
30
____
ns
0
____
0
____
0
____
0
____
ns
____
WRITE CYCLE
tWC
tCW
Write Cycle Time
Chip Enable to End-of-Write
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
tWP
Write Pulse Width(3)
tBP
tWR
Byte Enable Pulse Width
(3)
(3)
Write Recovery Time
(1)
tWHZ
Write Enable Output in High-Z Time
10
____
12
____
15
____
15
ns
tDW
Data Set-up Time
13
____
15
____
20
____
25
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
0
____
ns
3
____
3
____
3
____
3
____
ns
tOW
Output Active from End-of-Write
3016 tbl 21a
NOTES:
1. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production
tested.
2. 'X' in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and
on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP . For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = VIL).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
11
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles: Random Access Port(1,2)
tRC
ADDR
tAA
tOH
tACS(2)
CE
tCHZ
tCLZ
LB, UB
tBHZ
tBE
tBLZ
OE
tOE
tOHZ
tOLZ
Valid Data Out
I/OOUT
3016 drw 13
NOTES:
1. R/W is HIGH for read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
Waveform of Read Cycles: Buffer Command Mode
tRC
ADDR
tAA
CMD
(1)
tOH
tACS
tCHZ
tCLZ
LB, UB
tBHZ
tBE
tBLZ
OE
tOE
tOLZ
tOHZ
I/OOUT
Valid Data Out
3016 drw 14
NOTE:
1. CE = VIH when CMD = VIL.
12
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Waveform of Write Cycle No.1 (R/W Controlled Timing)
Random Access Port(1,6)
tWC
ADDR
tAW
R/W
(2)
tWR
tWP
tAS
(8)
CE, LB, UB
(3)
(5)
tDW
I/OIN
tDH
Valid Data In
OE
tOHZ
tWHZ
(4)
(4)
I/OOUT
Data Out
Data Out
tACS
tBE
tOW
3016 drw 15
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
Random Access Port(1,6,7)
tWC
ADDR
tAW
CE, LB, UB
(8)
(5)
tAS
(3)
tWR
(2)
tCW
(2)
tBP
R/W
tDW
I/OIN
tDH
Valid Data
3016 drw 16
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and
on the data to be placed on the bus for the required t DW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP . For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in HIGH-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = V IH.
6.42
13
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,3)
70825X20
Com'l Only
Symbol
Parameter
70825X25
Com'l Only
70825X35
Com'l Only
70825X45
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tCYC
Sequential Clock Cycle Time
25
____
30
____
40
____
50
____
ns
tCH
Clock Pulse HIGH
10
____
12
____
15
____
18
____
ns
tCL
Clock Pulse LOW
10
____
12
____
15
____
18
____
ns
tES
Count Enable and Address Pointer Set-up Time
5
____
5
____
6
____
6
____
ns
2
____
2
____
2
____
2
____
ns
____
8
____
10
____
15
____
20
ns
2
____
2
____
2
____
2
____
ns
9
____
11
____
15
____
15
ns
Count Enable and Address Pointer Hold Time
tEH
tSOE
tOLZ
tOHZ
Output Enable to Data Valid
Output Enable Low-Z Time
(2)
Output Enable High-Z Time
(2)
____
Clock to Valid Data
tCD
tCKHZ
Clock High-Z Time
tCKLZ
Clock Low-Z Time
tEB
Clock to EOB
____
(2)
20
____
25
____
35
____
45
ns
____
12
____
14
____
17
____
20
ns
3
____
3
____
3
____
3
____
ns
13
____
15
____
18
____
23
(2)
____
ns
3016 tbl 22a
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,3)
70825X20
Com'l Only
Symbol
Parameter
70825X25
Com'l Only
70825X35
Com'l Only
70825X45
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
25
____
30
____
40
____
50
____
ns
13
____
15
____
20
____
20
____
ns
5
____
5
____
6
____
6
____
ns
2
____
2
____
2
____
2
____
ns
5
____
5
____
6
____
6
____
ns
2
____
2
____
2
____
2
____
WRITE CYCLE
tCYC
tFS
tWS
tWH
tDS
tDH
Sequential Clock Cycle Time
Flow Restart Time
Chip Select and Read/Write Set-up Time
Chip Select and Read/Write Hold Time
Input Data Set-up Time
Input Data Hold Time
ns
3016 tbl 23a
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production
tested.
3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
14
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,2)
70825X20
Com'l Only
Symbol
Parameter
70825X25
Com'l Only
70825X35
Com'l Only
70825X45
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
13
____
15
____
20
____
20
____
ns
10
____
10
____
10
____
10
____
ns
10
____
10
____
10
____
10
____
ns
15
____
20
____
25
____
25
____
ns
RESET CYCLE
tRSPW
tWERS
tRSRC
tRSFV
Reset Pulse Width
Write Enable HIGH to Reset HIGH
Reset HIGH to Write Enable LOW
Reset HIGH to Flag Valid
3016 tbl 24a
NOTE:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Sequential Port: Write, Pointer Load Non-Incrementing Read
tCYC
tCH
tCL
SCLK
tES
CNTEN
(2)
(3)
tEH
tES
(1)
SLD
tDS
SI/OIN
tEH
Dx
tDH
HIGH IMPEDANCE
A0
tWS
tWS
tWH
tWH
SR/W
tWS
tWS
tWH
tWH
SCE
tCSZ
tCKHZ
tCD
SOE
tSOE
tOLZ
SI/OOUT
tOHZ
D0
tCKLZ
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
6.42
15
D0
D0
3016 drw 17
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Sequential Port: Write, Pointer Load, Burst Read
tCH
tCYC
tCL
SCLK
tEH
tES
(3)
CNTEN
SLD
(1)
tDS
SI/OIN
(2)
tEH
tES
Dx
tWS
tDS
tDH
HIGH IMPEDANCE
A0
tWS
tDH
D2
tWH
tWH
SR/W
tWS
tWS
tWH
tWH
SCE
tCD
SOE
tSOE
tOLZ
SI/OOUT
tOHZ
D0
(2)
D1
tCKLZ
3016 drw 18
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
Read STRT/EOB Flag Timing - Sequential Port(1)
tCH
SCLK
tCYC
tCL
tES
CNTEN
tEH
(4)
tES
(2)
tEH
SSTRT1/2
(1)
tDS
SI/OIN
Dx
tWS
tDH
HIGH IMPEDANCE
D3
tWS
tWH
tWH
SR/W
tWS
SCE
tWS
tWH
tWH
(3)
tCD
SOE
tSOE
tOHZ
tOLZ
SI/OOUT
(5)
D0
D2
D1
(2)
tCKLZ
EOB1/2
tEB
3016 drw19
NOTES: (Also used in the Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = V IH, the data addressed will be read out within that cycle. If SCE
= VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write
on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
16
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port
tCH
tCYC
tCL
SCLK
tES
CNTEN
tES
tEH
(4)
(3)
tEH
tES
SLD
(1)
tDS
SI/OIN
tEH
Dx
tWS
tDH
A0
tDS
tDS
tDH
HIGH IMPEDANCE
D0
tWS
tWH
tDH
D1
tWH
SR/W
(4)
tWS
SCE
tWS
tWH
tWH
tCKHZ
tCD
SOE
(5)
tOHZ
SI/OOUT
HIGH IMPEDANCE
D0
3016 drw 20
tCKLZ
Waveform of Burst Write Cycles: Sequential Port
tCH
tCYC
tCL
SCLK
tES
CNTEN
(3)
tES
(2)
tEH
SLD
(1)
tDS
SI/OIN
tEH
Dx
tWS
A0
tDS
D0
tWS
tWH
tDH
tDH
D1
D2
tWH
SR/W
(5)
tWS
SCE
tWS
tWH
tWH
SOE
(5)
tCKLZ
tCD
SI/OOUT
HIGH IMPEDANCE
D2
3016 drw 21
NOTES :
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is LOW.
4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.42
17
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
tCH
tCL
SCLK
tES
CNTEN
(4)
tES
(2)
tEH
SSTRT1/2
(1)
tDS
SI/OIN
tEH
D0
Dx
tWS
tDH
D1
tWS
tWH
D2
D3
HIGH IMPEDANCE
tWH
SR/W
(5)
tWS
SCE
tWS
tWH
tWH
(3)
SOE
(6)
tCKLZ
tCD
SI/OOUT
HIGH IMPEDANCE
D3
EOB1/2
tEB
3016 drw 22
NOTES: (Also used in the Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = V IH, the data addressed will be read out within that cycle. If
SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and
permit a write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
18
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Sequential Counter Enable Cycle After Reset, Write Cycle(1,4,6)
SCLK
RST
CNTEN
SI/OIN
(2)
D0
D1
D2
D3
D4
3016 drw 23
Sequential Counter Enable Cycle After Reset, Read Cycle(1,4)
SCLK
RST
SR/W
(3)
CNTEN
(5)
SI/OOUT
D0(5)
D1
D2
D3
3016 drw 24
NOTES:
1. 'D0' represents data input for Address=0, 'D1' represents data input for Address=1, etc.
1. If CNTEN=VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a t CD after the SR/W=VIH is clocked. The RST sets SR/W=LOW internally and therefore disables the output until the next clock.
4. SCE=VIL throughout all cycles.
5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/W=VIL.
6.42
19
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Random Access Port - Reset Timing
tRSPW
RST
tRSRC
R/W, SR/W CMD
(4)
or (UB + LB)
tWERS
tRSFV
EOB(1 or 2)
Flag Valid
3016 drw 25
Random Access Port Restart Timing of Sequential Port(1)
0.5 x tCYC
tFS
SCLK
R/W
(2)
2-5ns
6-7ns
(3)
CLR
Block
(Internal Signal)
3016 drw 26
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A 0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode
(see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being LOW for tWERS and tRSRC periods, or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
20
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory
Industrial and Commercial Temperature Ranges
Ordering Information
70825
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (–55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
PF
84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
20
25
35
45
Commercial Only
Commercial Only
Commercial & Military
Commercial & Military
S
L
Standard Power
Low Power
Speed in nanoseconds
70825 128K (8K x 16) Sequential Access Random
Access Memory
3016 drw 27
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
Datasheet Document History
1/27/99:
6/4/99:
11/10/99:
4/18/00:
5/23/00:
01/29/09:
Initiated datasheet document history
Converted to new format
Changed drawing format
Replaced IDT logo
Page 3 Changed "Clock" to "Inputs/Outputs" in Random pin description table
Added "Outputs" in Sequential pin description table
Changed ±200mV to 0mV in notes
Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Page 21 Removed "IDT" from orderable part number
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6.42
21
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