IDT728981J

IDT728981 TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 FEATURES: • • • • • • • • • outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream. 128 x 128 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS®) 4 RX inputs—32 channels at 64 Kbit/s per serial line 4 TX output—32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) 5V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40°°C to +85°°C FUNCTIONAL DESCRIPTION A functional block diagram of the IDT728981 device is shown below. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125μs wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four output (TX0-3) serial streams are provided in the IDT728981 device allowing a complete 128 x 128 channel non-blocking switch matrix to be constructed. The serial interface (C4i) clock for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 128-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. DESCRIPTION: The IDT728981 is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT728981 can handle as many as 128, 64 Kbit/s input and output channels. Those 128 channels are divided into 4 serial inputs and FUNCTIONAL BLOCK DIAGRAM C4i VCC F0i ODE GND Timing Unit Output MUX RX0 RX1 RX2 RX3 TX0 Receive Serial Data Streams Transmit Serial Data Streams Data Memory Control Register Connection Memory TX1 TX2 TX3 Microprocessor Interface 5703 drw01 DS CS R/W A0/ DTA D0/ A5 D7 JANUARY 2001 1 DSC-5703/1 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range TX1 TX2 DNC(1) 36 35 34 ODE TX0 37 39 RX0 DTA DNC(1) 41 40 38 RX2 RX1 42 40 DNC(1) TX2 DNC(1) 41 44 TX1 42 INDEX 43 ODE TX0 43 DNC(1) 44 DTA 2 1 RX1 RX0 3 RX2 4 DNC(1) 6 INDEX 5 PIN CONFIGURATION RX3 7 39 TX3 RX3 1 33 TX3 VCC 8 38 DNC(1) VCC 2 32 DNC(1) VCC 9 37 VCC 3 31 DNC(1) VCC 10 36 DNC(1) DNC(1) VCC 4 30 DNC(1) VCC 11 35 DNC(1) VCC 5 29 DNC(1) VCC 12 34 GND VCC 6 28 GND D2 24 D3 A2 11 23 D4 PLCC: 0.05in. pitch, 0.65in. x 0.65in. (J44-1, order code: J) TOP VIEW NOTE: 1. DNC - Do Not Connect 38 TX0 4 37 TX1 RX3 5 36 TX2 VCC 6 35 TX3 VCC 7 34 DNC(1) VCC 8 33 DNC(1) VCC 9 32 DNC(1) VCC 10 31 DNC(1) F0i 11 30 GND C4i 12 29 D0 A0 13 28 D1 A1 14 27 D2 A2 15 26 D3 A3 16 25 D4 A4 17 24 D5 A5 18 23 D6 DS 19 22 D7 20 21 CS R/W DNC(1) 3 RX2 D5 RX1 5703 drw03 D6 ODE CS D7 DNC(1) 39 A5 40 2 DS R/W 1 RX0 A4 DTA A3 5703 drw02 DNC(1) 28 DNC(1) 26 27 D5 D6 25 D7 CS DS R/W A5 A4 A3 DNC(1) 24 D4 22 29 23 17 21 A2 20 D3 19 D2 30 18 31 16 22 25 10 15 20 9 A1 A0 A1 21 D0 D1 19 26 17 27 8 18 7 C4i A0 15 F0i D1 16 D0 32 14 33 14 12 13 13 F0i C4i PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW 5703 drw04 PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in. (P40-1, order code: P) TOP VIEW PIN DESCRIPTIONS SYMBOL GND VCC DTA RX0-3 F0i C4i A0-A5 DS R/W CS D0-D7 TX0-3 ODE NAME Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 3 Frame Pulse Clock Address 0 to 5 Data Strobe I/O O I I I I I Read/Write Chip Select Data Bus 0 to 7 I I I/O TX Outputs 0 to 3 (Three-state Outputs) Output Drive Enable O I DESCRIPTION Ground Rail. +5.0 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input identifies frame synchronization signals formatted to ST-BUS® specifications. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT728981 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. 2 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range FUNCTIONAL DESCRIPTION (Cont'd) modes such as: Processor mode or Connection mode and Output Drivers Enabled or in three-state condition. Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is 16 bits wide and is split into two 8-bit blocks—Connection Memory HIGH and Connection Memory LOW. Each location in Connection Memory is associated with a particular channel in an output stream so as to provide a one-to-one correspondence between Connection and Data Memories. This correspondence allows for per channel control for each TX output stream. In Processor Mode, data output on the TX is taken from the Connection Memory Low and originates from the microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is read from Data Memory using the address in Connection Memory. Data destined for a particular channel on the serial output stream is read during the previous channel time slot to allow time for memory access and internal parallel-to-serial conversion. OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master three-state output control pin. If the ODE input is held LOW all TX outputs will be placed in high impedance regardless Connection Memory High programming. However, if ODE is HIGH, the contents of Connection Memory High control the output state on a per-channel basis. DELAY THROUGH THE IDT728981 The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT728981 device varies according to the combination of input and output streams and the movement within the stream from channel to channel. Data received on an input stream must first be stored in Data Memory before it is sent out. As information enters the IDT728981 it must first pass through an internal serial-to-parallel converter. Likewise, before data leaves the device, it must pass through the internal parallel-to-serial converter. This data preparation has an effect on the channel positioning in the frame immediately following the incoming frame—mainly, data cannot leave in the same time slot. Therefore, information that is to be output in the same channel position as the information is input, relative to the frame pulse, will be output in the following frame. Whether information can be output during a following timeslot after the information entered the IDT728981 depends on which RX stream the channel information enters on and which TX stream the information leaves on. This is caused by the order in which input stream information is placed into Data Memory and the order in which stream information is queued for output. Table 1 shows the allowable input/output stream combinations for the minimum two channel delay. CONNECTION MODE In Connection Mode, the addresses of input source for all output channels are stored in the Connection Memory Low. The Connection Memory Low locations are mapped to corresponding 8-bit x 32-channel output. The contents of the Data Memory at the selected address are then transferred to the parallelto-serial converters. By having the output channel to specify the input channel through the Connection Memory, input channels can be broadcast to several output channels. PROCESSOR MODE In Processor Mode the CPU writes data to specific Connection Memory Low locations which are to be output on the TX streams. The contents of the Connection Memory Low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the CPU. CONTROL The Connection Memory High bits (Table 4) control the per-channel functions available in the IDT728981. Output channels are selected into specific RX Receive Serial Data Streams Data Memory Connection Memory Input Output Stream 0 1,2,3 1 3 Table 1. Input Stream to Output Stream Combinations that can Provide the Minimum 2-Channel Delay Transmit Serial Data Streams TX 5703 drw05 A5 A4 A3 A2 A1 A0 Figure 1. Connection Mode Receive Serial Data Streams Data Memory Connection Memory Transmit Serial Data Streams 0 1 1 1 · 1 1 TX HEX ADDRESS LOCATION X 0 0 X 0 0 X 0 0 0 0 0 0 0 1 00-1F 20 21 Control Register(1) Channel 0(2) Channel 1(2) • • • • • • • • • • • • • • • • • • • • • 1 1 1 1 1 3F Channel 31(2) NOTES: 1. Writing to the Control Register is the only fast transaction. 2. Memory and stream are specified by the contents of the Control Register. 5703 drw06 Microprocessor Figure 2. Processor Mode Table 2. Address Mapping 3 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range SOFTWARE CONTROL If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output. If the ODE input pin is LOW, then all the serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) the output stream and channel. If the A5 address line input is LOW then the IDT728981 Internal Control Register is addressed. If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. The address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT728981 Data and Connection memories. The IDT728981 memory mapping is illustrated in Table 2 and Figure 3. The data in the control register (Table 3) consists of Memory Select and Stream Address bits, Split Memory and Processor Mode bits. In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connection Memory as specified by the Memory Select Bits (Bits 4 and 3 of the Control Register). The Memory Select bits allow the Connection Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams. The Processor Enable bit (bit 6) places EVERY output channel on every output stream in Processor mode; i.e., the contents of the Connection Memory LOW (CML, see Table 5)) are output on the TX output streams once every frame unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT728981 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory High (CMH) locations were set to HIGH, regardless of the actual value. Control Register CRb7 CRb6 The Control Register is only accessed when A5=0. All other address bits have no effect when A5=0. When A5 =1, only 32 bytes are randomly accessable via A0-A4 at any one instant. Which 32 bytes are accessed is determined by the state of CRb0 -CRb4. The 32 bytes correlate to 32 channel of one ST-BUS® stream. INITIALIZATION OF THE IDT728981 On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple TX outputs are tied together to form matrices. The ODE pin should be held low on power up to keep all outputs in the high impedance condition until the contents of the CMH are programmed. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two connected TX outputs drive the bus simultaneously. With the CMH setup, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the Connection Memory High bits outputs. CRb5 CRb4 CRb4 0 CRb3 1 1 1 0 1 CRb3 CRb2 CRb1 CRb0 Connection Memory High Connection Memory Low Data Memory Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 100000 100001 100010 CRb1 Channel 31 Channel 31 Channel 31 Channel 31 111111 CRb0 Stream 0 0 0 0 1 1 1 0 2 1 1 3 External Address Bits A5-A0 5703 drw07 Figure 3. Address Mapping 4 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range Mode Control Bits 7 Bit 6 (unused) Memory Select Stream Address Bits (unused) Bits 5 4 Name 3 2 1 0 Description 7 SM (Split Memory) When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. 6 PE (Processor Mode) When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE pin is LOW. When 0, the Connection Memory bits for each channel determine what is output. 5 4-3 unused MS1-MS0 (Memory Select Bits) 2 1-0 0-0 - Not to be used. 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory LOW 1-1 - Connection Memory is HIGH unused STA1-0 (Stream Address Bits) The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the subsection of memory made accessible for subsequent operations. Table 3. Control Register Configuration No Corresponding Memory - These bits give 0s if read 7 Bit 2 5 4 Name CS (Channel Source) 1 0 6 3 CS (unused) OE 2 1 0 Description When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the Data Memory and determine the source of the connection to the location's channel and stream. unused OE (Output Enable) If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it. Table 4. Connection Memory High Register (unused) 7 Bit Stream Address Bits 6 Channel Address Bits 5 4 Name 7 3 2 1 0 Description unused 6-5(1) Stream Address Bits The number expressed in binary notation on these 2 bits are the number of the stream for the source of the connection. Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2. 4-0(1) Channel Address Bits The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19. NOTE: 1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. Table 5. Connection Memory Low Register 5 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min. Max. Unit VCC - GND -0.3 7 V V Vi Voltage on Digital Inputs GND - 0.3 VCC +0.3 VO Voltage on Digital Outputs GND - 0.3 VCC +0.3 V IO Current at Digital Outputs 40 mA TS Storage Temperature +150 °C PD Package Power Dissapation 2 W -65 RECOMMENDED OPERATING CONDITIONS (1) Symbol Parameter Typ.(1) Max. 4.75 ⎯ 5.25 V 0 ⎯ VCC V -40 ⎯ +85 °C Min. VCC Positive Supply VI Input Voltage TOP Operating Temperature Commercial Unit NOTE: 1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Min. Typ.(1) Max. Units Test Conditions 10 mA Outputs Unloaded ICC Supply Current ⎯ 7 VIH Input High Voltage 2.0 ⎯ ⎯ V VIL Input Low Voltage ⎯ ⎯ 0.8 V IIL Input Leakage ⎯ ⎯ 5 μA CI Input Capacitance ⎯ 8 ⎯ pF VOH Output High Voltage 2.4 ⎯ ⎯ V IOH = 10mA IOH Output High Current 10 15 ⎯ mA Sourcing. VOH = 2.4V VOL Output Low Voltage ⎯ ⎯ 0.4 V IOL = 5mA VI between GND and VCC IOL Output Low Current 5 10 ⎯ mA Sinking. VOL = 0.4V IOZ High Impedance Leakage ⎯ ⎯ 5 μA VO between GND and VCC CO Output Pin Capacitance ⎯ 8 ⎯ pF NOTE: 1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Test Point VCC S1 is open circuit except when testing output levels or high impedance states. RL Output Pin S1 S2 S2 is switched to VCC or GND when testing output levels or high impedance states. CL GND GND 5703 drw08 Figure 4. Output Load 6 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range AC ELECTRICAL CHARACTERISTICS ⎯ CLOCK TIMING (1) Symbol Characteristics Min. Typ.(2) Max. Unit tCLK Clock Period(3) 220 244 300 ns tCH Clock Width High 95 122 150 ns tCL Clock Width Low 110 122 150 ns tCTT Clock Transition Time ⎯ 20 ⎯ ns tFPS Frame Pulse Setup Time 20 ⎯ 200 ns tFPH Frame Pulse Hold Time 0.020 ⎯ 50 μs tFPW Frame Pulse Width ⎯ 244 ⎯ ns NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 3. Contents of Connection Memory are not lost if the clock stops, however, TX outputs go into the high impedance state. C4i F0i Channel 31 Bit 0 Bit Cells Channel 0 Bit 7 5703 drw09 Figure 5. Frame Alignment tCLK tCTT tCTT tCHL tCL t CH C4i (( )) tFPH tFPS tFPH tFPS tFPW F0i 5703 drw10 Figure 6. Clock Timing 7 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range AC ELECTRICAL CHARACTERISTICS Symbol Characteristics tTAZ TX0-3 Delay - Active to High Z (1) ⎯ SERIAL STREAM TIMING Min. Typ.(2) Max. Unit Test Conditions 20 30 60 ns RL = 1KΩ(3), CL = 150pF tTZA TX0-3 Delay - High Z to Active 25 45 70 ns CL = 150pF tTAA TX0-3 Delay - Active to Active 30 45 70 ns CL = 150pF tTOH TX0-3 Hold Time 25 ⎯ ⎯ ns CL = 150pF tOED Output Driver Enable Delay ⎯ 45 70 ns RL = 1KΩ(3), CL = 150pF tSIS Serial Input Setup Time ⎯ -40 -20 ns tSIH Serial Input Hold Time 90 ⎯ ⎯ ns NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. ODE tOED Bit Cell Boundary tOED TX0-3 C4i 5703 drw12 tTAZ Figure 8. Output Driver Enable tTOH TX0-3 tTZA Bit Cell Boundaries TX0-3 C4i tTAA tTOH tSIS tSIH TX0-3 RX0-3 5703 drw11 5703 drw13 Figure 7. Serial Outputs and External Control Figure 9. Serial Inputs 8 IDT728981 Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range AC ELECTRICAL CHARACTERISTICS Symbol Characteristics (1) ⎯ PROCESSOR BUS Min. Typ.(2) Max. Unit 10 0 ⎯ ns Test Conditions tCSS Chip Select Setup Time tRWS Read/Write Setup Time 10 ⎯ ⎯ ns tADS Address Setup Time 10 ⎯ ⎯ ns tAKD Acknowledgment Delay Fast ⎯ 30 60 ns CL = 150pF tAKD Acknowledgment Delay Slow 2.7 ⎯ 7.2 cycles C4i cycles(4) tFWS Fast Write Data Setup Time 20 ⎯ ⎯ ns tSWD Slow Write Data Delay ⎯ 2.0 1.7 cycles C4i cycles tRDS Read Data Setup Time ⎯ ⎯ 0.5 cycles C4i cycles, CL = 150pF tDHT Data Hold Time Read 20 ⎯ ⎯ ns RL = 1KΩ(3), CL = 150pF tDHT Data Hold Time Write 20 10 ⎯ ns tRDZ Read Data to High Impedance ⎯ 30 60 ns tCSH Chip Select Hold Time 0 ⎯ ⎯ ns tRWH Read/Write Hold Time 0 ⎯ ⎯ ns tADH Address Hold Time 0 ⎯ ⎯ ns tAKH Acknowledgment Hold Time 10 20 40 ns RL = 1KΩ(3), CL = 150pF RL = 1KΩ(3), CL = 150pF NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i. DS tCSS t CSH tRWS tRWH tADS t ADH CS R/W A5-A0 tAKD tAKH DTA t RDS tSWD tFWS tRDZ tDHT D7-D0 5703 drw14 Figure 10. Processor Bus 9 ORDERING INFORMATION IDT XXXXX Device Type XX X Package Process Blank -40ºC to +85ºC (Commercial) JG PG DBG Green Plastic Leaded Chip Carrier – Green (PLCC, J44-1) Green Plastic Dip – Green (P40-1) Green Plastic Quad Flatpack – Green (PQFP, DB44-1) 728981 128 x 128 – Time Slot Interchange Digital Switch DATASHEET DOCUMENT HISTORY 5/23/2000 8/18/2000 01/24/2001 pgs. 1, 2, and 10. pgs. 1, 2 and 10. pgs. 1 and 6. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* for Tech Support: 408-330-1753 email: FIFOhelp@idt.com P Pkg: www.idt.com/docs/PSC4003.pdf J Pkg: www.idt.com/docs/PSC4008.pdf DB Pkg: www.idt.com/docs/PSC4082.pdf *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. 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