DATASHEET
ISL22316
FN6186
Rev 3.00
August 14, 2015
Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power I2C™
Bus, 128 Taps
The ISL22316 integrates a single digitally controlled
potentiometer (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
Features
• 128 resistor taps
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the
DCP’s IVR to the WR.
The DCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• I2C serial interface
- Two address pins, up to four devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70 typical @ VCC = 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10k total resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T +55°C
• 10 Ld MSOP or 10 Ld TDFN package
• Pb-free (RoHS compliant)
Pinouts
ISL22316
(10 LD TDFN)
TOP VIEW
ISL22316
(10 LD MSOP)
TOP VIEW
VCC
SCL
1 O
10 VCC
9
RH
SDA
2
9 RH
3
8
RW
A1
3
8 RW
A0
4
7
RL
A0
4
7 RL
SHDN
5
6
GND
SHDN
5
6 GND
SCL
10
1
SDA
2
A1
Ordering Information
PART NUMBER
(Note)
PART
MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG. DWG. #
ISL22316UFU10Z*
(No longer available,
recommended
replacement:
(ISL22316WFRT10Z-TK)
316UZ
50
-40 to +125
10 Ld MSOP
M10.118
ISL22316WFU10Z*
316WZ
10
-40 to +125
10 Ld MSOP
M10.118
ISL22316UFRT10Z*
(No longer available,
recommended
replacement:
(ISL22316WFRT10Z-TK)
316U
50
-40 to +125
10 Ld 3x3 TDFN
L10.3x3B
ISL22316WFRT10Z*
316W
10
-40 to +125
10 Ld 3x3 TDFN
L10.3x3B
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN6186 Rev 3.00
August 14, 2015
Page 1 of 16
ISL22316
Block Diagram
VCC
SCL
SDA
A0
I2C
INTERFACE
A1
POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
RH
RW
WR
RL
NON-VOLATILE
REGISTERS
SHDN
GND
Pin Descriptions
MSOP PIN
NUMBER
TDFN PIN
NUMBER
PIN NAME
DESCRIPTION
1
1
SCL
Open drain I2C interface clock input
2
2
SDA
Open drain Serial data I/O for the I2C interface
3
3
A1
Device address input for the I2C interface
4
4
A0
Device address input for the I2C interface
5
5
SHDN
6
6
GND
7
7
RL
“Low” terminal of DCP
8
8
RW
“Wiper” terminal of DCP
9
9
RH
“High” terminal of DCP
10
10
VCC
FN6186 Rev 3.00
August 14, 2015
Shutdown active low input
Device ground pin
Power supply pin
Page 2 of 16
ISL22316
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP Pin with
Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C
ESD Ratings
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV
Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
10 Lead MSOP (Note 2). . . . . . . . . . . .
162
N/A
10 Lead TDFN (Notes 3, 4) . . . . . . . . .
74
7
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper Current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -1V for all pins.
2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions, unless otherwise stated.
PARAMETER
RH to RL Resistance
TEST CONDITIONS
TYP
(Note 5)
MAX
(Note 19)
UNIT
W option
10
k
U option
50
k
RH to RL Resistance Tolerance
End-to-End Temperature Coefficient
MIN
(Note 19)
-20
+20
%
W option
±50
ppm/°C
(Note 18)
U option
±80
ppm/°C
(Note 18)
Wiper Resistance
VCC = 3.3V, wiper current = VCC/RTOTAL
70
VRH, VRL
VRH and VRL Terminal Voltages
VRH and VRL to GND
CH/CL/CW
(Note 18)
Potentiometer Capacitance
RW
ILkgDCP
Leakage on DCP Pins
0
200
VCC
V
10/10/25
Voltage at pin from GND to VCC
0.1
pF
1
µA
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL
(Note 10)
Integral Non-linearity
Monotonic over all tap positions, W and U
option
-1
1
LSB
(Note 6)
DNL
(Note 9)
Differential Non-linearity
Monotonic over all tap positions, W and U
option
-0.5
0.5
LSB
(Note 6)
ZSerror
(Note 7)
Zero-scale Error
W option
0
1
5
U option
0
0.5
2
LSB
(Note 6)
FSerror
(Note 8)
Full-scale Error
W option
-5
-1
0
U option
-2
-1
0
TCV
Ratiometric Temperature Coefficient
(Notes 11, 18)
FN6186 Rev 3.00
August 14, 2015
DCP register set to 40 hex for W and U
option
±4
LSB
(Note 6)
ppm/°C
Page 3 of 16
ISL22316
Analog Specifications
SYMBOL
Over recommended operating conditions, unless otherwise stated. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 19)
TYP
(Note 5)
MAX
(Note 19)
UNIT
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 15)
Integral Non-linearity
DCP register set between 10 hex and 7F
hex; monotonic over all tap positions;
W and U option
-1
1
MI
(Note 12)
RDNL
(Note 14)
Differential Non-linearity
W option
-1
1
MI
(Note 12)
U option
-0.5
0.5
MI
(Note 12)
W option
0
1
5
MI
(Note 12)
U option
0
0.5
2
MI
(Note 12)
Roffset
(Note 13)
Offset
Operating Specifications Over the recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
MAX
(Note 19)
UNIT
0.5
mA
3
mA
VCC = +5.5V @ +85°C, I2C interface in
standby state
5
µA
VCC = +5.5V @ +125°C, I2C interface in
standby state
7
µA
VCC = +3.6V @ +85°C, I2C interface in
standby state
3
µA
VCC = +3.6V @ +125°C, I2C interface in
standby state
5
µA
VCC = +5.5V @ +85°C, I2C interface in
standby state
3
µA
VCC = +5.5V @ +125°C, I2C interface in
standby state
5
µA
VCC = +3.6V @ +85°C, I2C interface in
standby state
2
µA
VCC = +3.6V @ +125°C, I2C interface in
standby state
4
µA
1
µA
TEST CONDITIONS
VCC Supply Current (Volatile Write/Read)
ICC2
VCC Supply Current (Non-volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I2C,
active, read and write states)
ISD
VCC Current (Standby)
VCC Current (Shutdown)
TYP
(Note 5)
fSCL = 400kHz; SDA = Open; (for I2C,
ICC1
ISB
MIN
(Note 19)
active, read and write states)
Leakage Current, at Pins A0, A1, SHDN,
SDA and SCL
Voltage at pin from GND to VCC,
SDA is inactive
tDCP
(Note 18)
DCP Wiper Response Time
SCL falling edge of last bit of DCP data byte
to wiper new position
1.5
µs
tShdnRec
(Note 18)
DCP Recall Time from Shutdown Mode
From rising edge of SHDN signal to wiper
stored position and RH connection
1.5
µs
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
1.5
µs
ILkgDig
Vpor
Power-on Recall Voltage
Minimum VCC at which memory recall occurs
VCCRamp VCC Ramp Rate
tD
Power-up Delay
FN6186 Rev 3.00
August 14, 2015
-1
2.0
2.6
0.2
VCC above Vpor, to DCP Initial Value
Register recall completed and I2C Interface
in standby state
V
V/ms
3
ms
Page 4 of 16
ISL22316
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 19)
TYP
(Note 5)
MAX
(Note 19)
UNIT
EEPROM SPECIFICATION
EEPROM Endurance
EEPROM Retention
tWC
(Note 17)
Temperature T +55°C
1,000,000
Cycles
50
Years
Non-volatile Write Cycle Time
12
20
ms
SERIAL INTERFACE SPECIFICATIONS
VIL
A1, A0, SHDN, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*VCC
V
VIH
A1, A0, SHDN, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC + 0.3
V
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL
Cpin
(Note 18)
fSCL
0.05*VCC
SDA Output Buffer LOW Voltage, Sinking
4mA
V
0
A1, A0, SHDN, SDA, and SCL Pin
Capacitance
0.4
V
10
SCL Frequency
tsp
Pulse Width Suppression Time at SDA and
SCL Inputs
Any pulse narrower than the max spec is
suppressed
tAA
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
pF
400
kHz
50
ns
900
ns
tBUF
Time the Bus Must be Free Before the Start
of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time for Read, or
Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
1300
ns
Output Data Hold Time
From SCL falling edge crossing 30% of
VCC, until SDA enters the 30% to 70% of
VCC window
0
ns
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
tDH
FN6186 Rev 3.00
August 14, 2015
Page 5 of 16
ISL22316
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 19)
TYP
(Note 5)
MAX
(Note 19)
UNIT
1
k
Before START condition
600
ns
After STOP condition
600
ns
Rpu
SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF
For Cb = 400pF, max is about 2k~2.5k
For Cb = 40pF, max is about 15k~20k
tSU:A
A1 and A0 Setup Time
tHD:A
A1 and A0 Hold Time
NOTES:
5. Typical values are for TA = +25°C and 3.3V supply voltage.
6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)127 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
10. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127
Max V RW i – Min V RW i
10 6
11. TC = --------------------------------------------------------------------------------------------- --------------------- for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
V
Max V RW i + Min V RW i 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature
range.
12. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and
00 hex respectively.
13. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW127/MI, when measuring between RW and RH.
14. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 127.
15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 127.
6
for i = 16 to 127, T = -40°C to +125°C. Max() is the maximum value of the resistance and Min () is
Max Ri – Min Ri
10
TC R = ---------------------------------------------------------------- --------------------- the minimum value of the resistance over the temperature range.
Max Ri + Min Ri 2 +165°C
17. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile
write cycle.
16.
18. Limits should be considered typical and are not production tested.
19. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
FN6186 Rev 3.00
August 14, 2015
Page 6 of 16
ISL22316
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tsp
tR
tHD:STO
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0 and A1 Pin Timing
STOP
START
SCL
CLK 1
SDA
tSU:A
tHD:A
A0, A1
Typical Performance Curves
100
1.2
80
70
1.0
60
0.8
ISB (µA)
WIPER RESISITANCE ()
1.4
VCC = 3.3V, T = +125°C
90
50
40
30
0.6
0.4
T = +25°C
VCC = 3.3V, T = -40°C
VCC = 3.3V, T = +20°C
20
0.2
10
0
T = +125°C
0
20
40
60
80
100
TAP POSITION (DECIMAL)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC/RTOTAL ] FOR 10k (W)
FN6186 Rev 3.00
August 14, 2015
120
0
2.7
3.2
3.7
4.2
4.7
5.2
VCC (V)
FIGURE 2. STANDBY ICC vs VCC
Page 7 of 16
ISL22316
Typical Performance Curves
(Continued)
0.2
0.2
T = +25°C
T = +25°C
VCC = 2.7V
0.1
INL (LSB)
DNL (LSB)
0.1
0
-0.1
VCC = 2.7V
0
-0.1
VCC = 5.5V
-0.2
0
20
40
VCC = 5.5V
60
80
100
-0.2
120
0
20
40
60
80
100
120
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
0.0
1.3
10k
1.1
-0.3
ZSERROR (LSB)
ZSERROR (LSB)
0.9
0.7
0.5
VCC = 2.7V
VCC = 5.5V
0.3
0.1
-0.3
-40
-20
0
20
VCC = 5.5V
50k
-0.6
-0.9
10k
-1.2
50k
-0.1
VCC = 2.7V
40
60
80
100
-1.5
-40
120
-20
0
TEMPERATURE (°C)
20
40
60
80
FIGURE 6. FSERROR vs TEMPERATURE
0.4
0.4
T = +25°C
T = +25°C
VCC = 5.5V
0.2
VCC = 5.5V
0.2
0
INL (LSB)
DNL (LSB)
120
TEMPERATURE (ºC)
FIGURE 5. ZSERROR vs TEMPERATURE
-0.2
-0.4
0
-0.2
-0.4
VCC = 2.7V
-0.6
16
100
36
56
VCC = 2.7V
76
96
116
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
FN6186 Rev 3.00
August 14, 2015
-0.6
16
36
56
76
96
TAP POSITION (DECIMAL)
116
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
Page 8 of 16
ISL22316
Typical Performance Curves
(Continued)
105
90
0.5
75
VCC = 2.7V
TCv (ppm/°C)
END TO END RTOTAL CHANGE (%)
1.0
50k
0.0 VCC = 5.5V
10k
-0.5
60
45
50k
30
10k
15
-1.0
-40
-20
0
20
40
60
80
100
120
0
16
36
TEMPERATURE (ºC)
56
76
96
TAP POSITION (DECIMAL)
FIGURE 9. END-TO-END RTOTAL % CHANGE vs
TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
OUTPUT
INPUT
300
TCr (ppm/°C)
250
200
150
50k
10k
100
WIPER AT MID POINT (POSITION 40h)
RTOTAL = 9.5k
50
0
16
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
SCL
SIGNAL AT WIPER
(WIPER UNLOADED)
SIGNAL AT WIPER
(WIPER UNLOADED MOVEMENT
FROM 7Fh TO 00h)
WIPER MID POINT MOVEMENT
FROM 3Fh TO 40h
FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h
FN6186 Rev 3.00
August 14, 2015
FIGURE 14. LARGE SIGNAL SETTLING TIME
Page 9 of 16
ISL22316
maximum of four ISL22316 devices may occupy the I2C serial
bus.
Pin Description
Potentiometers Pins
RH AND RL
Principles of Operation
The high (RH) and low (RL) terminals of the ISL22316 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 127 decimal, the wiper will be closest
to RH, and with the WR set to 0, the wiper is closest to RL.
The ISL22316 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I2C
serial interface providing direct communication between a host
and the potentiometer and memory. The resistor array is
comprised of individual resistors connected in series. At either
end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition on RH and shorts RW to RL. When SHDN is returned
to logic high, the previous latch settings put RWi at the same
resistance setting prior to shutdown. This pin is logically AND
with the SHDN bit in the ACR register. The I2C interface is still
available in shutdown mode and all registers are accessible.
This pin must remain HIGH for normal operation.
RH
RW
RL
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, operation code, wiper
address and data from an I2C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since it is an open drain
input.
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL22316. A
FN6186 Rev 3.00
August 14, 2015
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in IVR
will be maintained in the non-volatile memory. When power is
restored, the contents of the IVR is recalled and loaded into the
WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position of
the wiper terminal within the DCP is controlled by a 7-bit
volatile Wiper Register (WR). When the WR of a DCP contains
all zeroes (WR: 00h), its wiper terminal (RW) is closest to
its “Low” terminal (RL). When the WR register of a DCP
contains all ones (WR: 7Fh), its wiper terminal (RW) is
closest to its “High” terminal (RH). As the value of the WR
increases from all zeroes (0) to all ones (127 decimal), the
wiper moves monotonically from the position closest to RL to
the closest to RH. At the same time, the resistance between
RW and RL increases monotonically, while the resistance
between RH and RW decreases monotonically.
While the ISL22316 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage becomes
large enough for reliable non-volatile memory reading, the WR
will be reload with the value stored in a non-volatile Initial Value
Register (IVR).
The WR and IVR can be read or written to directly using the
I2C serial interface as described in the following sections.
Memory Description
The ISL22316 contains one non-volatile 8-bit register, known as
the Initial Value Register (IVR), and two volatile 8-bit registers,
Wiper Register (WR) and Access Control Register (ACR). Table
1 shows the Memory map of the ISL22316. The non-volatile
Page 10 of 16
ISL22316
register (IVR) at address 0, contain initial wiper position and
volatile registers (WR) contain current wiper position.
TABLE 1. MEMORY MAP
Protocol Conventions
ADDRESS
NON-VOLATILE
VOLATILE
2
—
ACR
1
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22316, the SDA pin is
in the input mode.
Reserved
0
IVR
WR
The non-volatile IVR and volatile WR registers are accessible
with the same address.
The Access Control Register (ACR) contains information and
control bits described in Table 2.
The VOL bit (ACR) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
SHDN
0
WIP
0
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value is
written to IVR register also is written to the WR. The default
value of this bit is 0.
The SHDN bit (ACR) disables or enables Shutdown mode.
This bit is logically AND with SHDN pin. When this bit is 0, DCP is
in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR) is read only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WR or ACR while WIP bit is 1.
Shutdown Mode
The device can be put in Shutdown mode either by pulling the
SHDN pin to GND or setting the SHDN bit in the ACR register to
0. The truth table for Shutdown mode is in Table 3.
TABLE 3.
SHDN pin
SHDN bit
Mode
High
1
Normal operation
Low
1
Shutdown
High
0
Shutdown
Low
0
Shutdown
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The ISL22316 continuously monitors the SDA and
SCL lines for the START condition and does not respond to
any command until this condition is met (see Figure 16). A
START condition is ignored during the power-up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL
is HIGH (see Figure 16). A STOP condition at the end of a read
operation, or at the end of a write operation places the device
in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits of
data (see Figure 17).
The ISL22316 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22316 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present at
pins A1 and A0. The LSB is the Read/Write bit. Its value is “1”
for a Read operation, and “0” for a Write operation (see Table
4).
Logic values at pins A1 and A0 respectively
0
1
0
1
0
A1
A0
(MSB)
I2C Serial Interface
R/W
(LSB)
TABLE 4. IDENTIFICATION BYTE FORMAT
The ISL22316 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both transmit
and receive operations. Therefore, the ISL22316 operates as a
slave device in all applications.
FN6186 Rev 3.00
August 14, 2015
Page 11 of 16
ISL22316
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
A
R
T
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
SIGNALS FROM
THE SLAVE
S
T
O
P
DATA
BYTE
0 0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 18. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
IDENTIFICATION
BYTE WITH
R/W = 0
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 1
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
S
A T
C O
K P
A
C
K
0 1 0 1 0 A1 A0 1
0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 19. READ SEQUENCE
FN6186 Rev 3.00
August 14, 2015
Page 12 of 16
ISL22316
Write Operation
Read Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte, and
a STOP condition. After each of the three bytes, the ISL22316
responds with an ACK. At this time, the device enters its
standby state (see Figure 18).
A Read operation consists of a three byte instruction followed
by one or more Data Bytes (See Figure 19). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL22316 responds with an ACK. Then the ISL22316
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each byte.
The master terminates the read operation (issuing a ACK and
STOP condition) following the last bit of the last Data Byte (see
Figure 19).
The non-volatile write cycle starts after STOP condition is
determined and it requires up to 20ms delay for the next nonvolatile write.
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit is
0. If the WIP bit (ACR[5]) is not 0, the host should repeat its
reading sequence again.
FN6186 Rev 3.00
August 14, 2015
Page 13 of 16
ISL22316
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
August 14, 2015
FN6186.3
- Ordering Information Table on page 1.
- Added Revision History beginning with Rev 1.
- Added About Intersil Verbiage.
-Updated L10.3x3B to most recent revision, changes are as follows:
-Revision 0 to Revision 1 Changes:
Removed from JEDEC format to comply with new standards. Changes include:
Removed table and put dimensions on package outline drawing instead
Added Typical Recommended Land Pattern
Note "Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm
from the terminal tip." changed to "Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
-Revision 1 to Revision 2 changes:
1. Removed mention of "b" from Note 4 since "b" does not exist on the drawing.
2. Added Note 6 callout to lead width on "Bottom View"
3. Corrected the word "indentifier" in Note 6 to read "identifier"
-Revision 2 to Revision 3 changes:
Removed package outline and included center to center distance between lands on recommended land
pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm
and 0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes
accordingly.
-Revision 3 to Revision 4
Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends
-Updated POD M10.118 to most current version change is as follows:
Added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2006-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6186 Rev 3.00
August 14, 2015
Page 14 of 16
ISL22316
Package Outline Drawing
L10.3x3B
10 LEAD THIN DUAL FLAT PACKAGE (TDFN) WITH E-PAD
Rev 4, 4/15
3.00
5
PIN #1 INDEX AREA
A
B
1
2
0.50
3.00
2.38 +0.1/ - 0.15
10
5
PIN 1
INDEX AREA
0.25 +0.05/ - 0.07
6
(4X)
0.15
1.64 +0.1/ -0.15
TOP VIEW
BOTTOM VIEW
10x 0.40 +/- 0.1
SEE DETAIL "X"
(10x0.60)
(10X0.25)
0.75
0.10 C
SEATING PLANE
0.08 C
2.38
0.05
C
SIDE VIEW
(8x 0.50)
1.64
2.80 TYP
TYPICAL RECOMMENDED LAND PATTERN
C
0.20 REF
4
0.05
DETAIL "X"
NOTES:
FN6186 Rev 3.00
August 14, 2015
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
5.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Page 15 of 16
ISL22316
Package Outline Drawing
M10.118
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 4/12
5
3.0±0.05
A
DETAIL "X"
D
10
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
0.50 BSC
B
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.18 - 0.27
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to JEDEC MO-187-BA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.50)
(0.29)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN6186 Rev 3.00
August 14, 2015
Page 16 of 16
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