DATASHEET
ISL23325
FN7870
Rev 1.00
September 23, 2015
Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
The ISL23325 is a volatile, low voltage, low noise, low power,
256-Tap, dual digitally controlled potentiometer (DCP) with an
I2C Bus™ interface. It integrates two DCP cores, wiper switches
and control logic on a monolithic CMOS integrated circuit.
Features
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the I2C
bus interface. Each potentiometer has an associated volatile
Wiper Register (WRi, i = 0, 1) that can be directly written to and
read by the user. The contents of the WRi controls the position
of the wiper. When powered on, the wiper of each DCP will
always commence at mid-scale (128 tap position).
• 10kΩ 50kΩ or 100kΩ total resistance
The low voltage, low power consumption, and small package
of the ISL23325 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23325 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23325 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
• Two potentiometers per package
• 256 resistor taps
• I2C serial interface
- No additional level translator for low bus supply
- Three address pins allow up to eight devices per bus
• Maximum supply current without serial bus activity
(standby)
- 3µA @ VCC and VLOGIC = 5V
- 1.7µA @ VCCand VLOGIC = 1.7V
• Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V I2C bus/logic power supply
• Wiper resistance: 70Ω typical @ VCC = 3.3V
Applications
• Power-on preset to mid-scale (128 tap position)
• Power supply margining
• Extended industrial temperature range: -40°C to +125°C
• Trimming sensor circuits
• 14 Ld TSSOP or 16 Ld µTQFN packages
• Gain adjustment in battery powered instruments
• Pb-free (RoHS Compliant)
• RF power amplifier bias compensation
10000
VREF
RESISTANCE (Ω)
8000
RH1
6000
1 DCP
OF
ISL23325
4000
RW1
VREF_M
+
ISL28114
2000
RL1
0
0
64
128
192
256
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10kΩ DCP
FN7870 Rev 1.00
September 23, 2015
FIGURE 2. VREF ADJUSTMENT
Page 1 of 20
ISL23325
Block Diagram
VLOGIC
VCC
SCL
SDA
A0
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
LEVEL
SHIFTER
I/O
BLOCK
A1
A2
RH0
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
RW0
GND
Pin Configurations
RH1
RL0
RW1
RL1
Pin Descriptions
TSSOP
µTQFN
SYMBOL
DESCRIPTION
1
6, 15
GND
2
16
VLOGIC
3
1
SDA
Logic Pin - Serial bus data
input/open drain output
Ground pin
1
14 VCC
VLOGIC
2
13 RL0
SDA
3
12 RW0
SCL
4
11 RH0
4
2
SCL
Logic Pin - Serial bus clock input
A0
5
10 RH1
5
3
A0
A1
6
9
RW1
A2
7
8
RL1
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
6
4
A1
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
7
5
A2
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
RL0
I2C bus/logic supply. Range 1.2V to
5.5V
GND
8
8
RL1
DCP1 “low” terminal
13
ISL23325
(14 LD TSSOP)
TOP VIEW
9
9
RW1
DCP1 wiper terminal
ISL23325
(16 LD µTQFN)
GND
VCC
14
15
16
VLOGIC
TOP VIEW
10
10
RH1
DCP1 “high” terminal
RH0
11
11
RH0
DCP0 “high” terminal
A0
3
10
RH1
A1
4
9
RW1
12
12
RW0
DCP0 wiper terminal
13
13
RL0
DCP0 “low” terminal
14
14
VCC
Analog power supply.
Range 1.7V to 5.5V
7
NC
Not Connected
RL1
NC
GND
A2
FN7870 Rev 1.00
September 23, 2015
8
RW0
11
7
12
2
6
1
SCL
5
SDA
Page 2 of 20
ISL23325
Ordering Information
PART NUMBER
(Note 5)
PART MARKING
RESISTANCE
OPTION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL23325TFVZ (Notes 1, 3)
23325 TFVZ
100
-40 to +125
14 Ld TSSOP
M14.173
ISL23325UFVZ (Notes 1, 3)
(No longer available, recommended
replacement: ISL23325TFRUZ-TK)
23325 UFVZ
50
-40 to +125
14 Ld TSSOP
M14.173
ISL23325WFVZ (Notes 1, 3)
23325 WFVZ
10
-40 to +125
14 Ld TSSOP
M14.173
ISL23325TFRUZ-T7A (Notes 2, 4)
GBF
100
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23325TFRUZ-TK (Notes 2, 4)
GBF
100
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23325UFRUZ-T7A (Notes 2, 4)
(No longer available, recommended
replacement: ISL23325TFRUZ-TK)
GBE
50
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23325UFRUZ-TK (Notes 2, 4)
(No longer available, recommended
replacement: ISL23325TFRUZ-TK)
GBE
50
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23325WFRUZ-T7A (Notes 2, 4)
GBD
10
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23325WFRUZ-TK (Notes 2, 4)
GBD
10
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
NOTES:
1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23325. For more information on MSL please see techbrief TB363.
FN7870 Rev 1.00
September 23, 2015
Page 3 of 20
ISL23325
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper Current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .4.5kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
14 Ld TSSOP Package (Notes 6, 7) . . . . . .
112
40
16 Ld µTQFN Package (Notes 6, 7) . . . . . .
110
64
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For JC, the “case temp” location is the center top of the package.
Analog Specifications
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL
RTOTAL
PARAMETER
RH to RL Resistance
TEST CONDITIONS
MIN
(Note 20)
RW
UNITS
10
kΩ
U option
50
kΩ
T option
VRH, VRL
MAX
(Note 20)
W option
RH to RL Resistance Tolerance
End-to-End Temperature Coefficient
TYP
(Note 8)
100
-20
W option
±2
kΩ
+20
125
%
ppm/°C
U option
65
ppm/°C
T option
45
ppm/°C
DCP Terminal Voltage
VRH or VRL to GND
0
VCC
V
Wiper Resistance
RH - floating, VRL = 0V, force IW current
to the wiper,
IW = (VCC - VRL)/RTOTAL,
VCC = 2.7V to 5.5V
70
200
Ω
VCC = 1.7V
580
Ω
32/32/32
pF
CH/CL/CW
Terminal Capacitance
See “DCP Macro Model” on page 9
ILkgDCP
Leakage on DCP Pins
Voltage at pin from GND to VCC
Noise
Resistor Noise Density
Wiper at middle point, W option
16
nV/√Hz
Wiper at middle point, U option
49
nV/√Hz
Wiper at middle point, T option
61
nV/√Hz
Digital Feed-through from Bus to Wiper
Wiper at middle point
-65
dB
Power Supply Reject Ratio
Wiper output change if VCC change
±10%; wiper at middle point
-75
dB
Feed Thru
PSRR
FN7870 Rev 1.00
September 23, 2015
-0.4
2V
0
IOL = 1.5mA, VLOGIC < 2V
Cpin
SDA, SCL Pin Capacitance
fSCL
SCL Frequency
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
tAA
0.4
V
0.2 x VLOGIC
V
10
pF
400
kHz
Any pulse narrower than the
max spec is suppressed
50
ns
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30%
of VLOGIC, until SDA exits the
30% to 70% of VLOGIC window
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VLOGIC
during a STOP condition, to
SDA crossing 70% of VLOGIC
during the following START
condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of
VLOGIC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of
VLOGIC crossing
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling
edge; both crossing 70% of
VLOGIC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VLOGIC to SCL
falling edge crossing 70% of
VLOGIC
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to
70% of VLOGIC window, to SCL
rising edge crossing 30% of
VLOGIC
100
ns
FN7870 Rev 1.00
September 23, 2015
Page 7 of 20
ISL23325
Serial Interface Specification
SYMBOL
For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
70% of VLOGIC to SDA entering
the 30% to 70% of VLOGIC
window
0
ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing
70% of VLOGIC, to SDA rising
edge crossing 30% of VLOGIC
600
ns
tHD:STO
STOP Condition Hold Time for Read From SDA rising edge to SCL
or Write
falling edge; both crossing
70% of VLOGIC
1300
ns
0
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VLOGIC, until SDA
enters the 30% to 70% of
VLOGIC window.
IOL = 3mA, VLOGIC > 2V.
IOL = 0.5mA, VLOGIC < 2V
tR
SDA and SCL Rise Time
From 30% to 70% of VLOGIC
20 + 0.1 x Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VLOGIC
20 + 0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
tSU:A
A2, A1, A0 Setup Time
Before START condition
600
ns
tHD:A
A2, A1, A0 Hold Time
After STOP condition
600
ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)255 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255
Max V RW i – Min V RW i
10 6
14. TC = ----------------------------------------------------------------------------- --------------------- For i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
V
V RW i +25°C
+165°C and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00
hex respectively.
16. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW255/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.
19.
6
Max Ri – Min Ri
10
TC R = ------------------------------------------------------- --------------------Ri +25°C
+165°C
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC
first followed by the VCC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 1 and y = 0 to 1.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255 , x = 0 to 1 and y = 0 to 1.
FN7870 Rev 1.00
September 23, 2015
Page 8 of 20
ISL23325
DCP Macro Model
RTOTAL
RH
CL
CH
CW
32pF
RL
32pF
32pF
RW
Timing Diagrams
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tsp
tR
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0, A1, and A2 Pin Timing
STOP
START
SCL
CLK 1
SDA
tSU:A
tHD:A
A0, A1, A2
FN7870 Rev 1.00
September 23, 2015
Page 9 of 20
ISL23325
0.4
0.08
0.2
0.04
DNL (LSB)
DNL (LSB)
Typical Performance Curves
0
-0.2
0.00
-0.04
-0.4
0
64
128
192
-0.08
0
256
64
TAP POSITION (DECIMAL)
0.80
0.16
0.40
0.08
0.00
0.00
-0.08
-0.40
-0.80
0
64
128
192
-0.16
256
0
64
TAP POSITION (DECIMAL)
192
256
FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C
0.40
0.10
0.20
0.05
RDNL (MI)
RDNL (MI)
128
TAP POSITION (DECIMAL)
FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C
0.00
-0.20
-0.40
256
FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C
INL (LSB)
INL (LSB)
FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C
128
192
TAP POSITION (DECIMAL)
0.00
-0.05
0
64
128
192
TAP POSITION (DECIMAL)
FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C
FN7870 Rev 1.00
September 23, 2015
256
-0.10
0
64
128
192
TAP POSITION (DECIMAL)
FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C
Page 10 of 20
256
ISL23325
(Continued)
0.80
0.14
0.40
0.07
RINL (MI)
RINL (MI)
Typical Performance Curves
0.00
0.00
-0.40
-0.80
-0.07
0
64
128
192
TAP POSITION (DECIMAL)
-0.14
256
FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C
+25°C
100
80
WIPER RESISTANCE ()
WIPER RESISTANCE ()
+125°C
60
40
-40°C
20
256
+125°C
80
60
-40°C
40
20
0
0
64
128
192
TAP POSITION (DECIMAL)
0
256
64
128
192
256
TAP POSITION (DECIMAL)
FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V
FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V
400
80
300
60
TCv (ppm/°C)
TCv (ppm/°C)
128
192
TAP POSITION (DECIMAL)
120
+25°C
200
100
0
64
FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C
100
0
0
40
20
15
63
111
159
207
TAP POSITION (DECIMAL)
FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V
FN7870 Rev 1.00
September 23, 2015
255
0
15
63
111
159
TAP POSITION (DECIMAL)
207
FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V
Page 11 of 20
255
ISL23325
Typical Performance Curves
(Continued)
250
800
200
TCr (ppm/°C)
TCr (ppm/°C)
600
400
200
100
50
0
15
63
111
159
TAP POSITION (DECIMAL)
207
0
15
255
111
159
207
255
FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V
150
40
120
TCr (ppm/°C)
50
30
20
10
0
63
TAP POSITION (DECIMAL)
FIGURE 15. 10kΩ TCr vs TAP POSITION
TCv (ppm/°C)
150
90
60
30
15
63
111
159
207
TAP POSITION (DECIMAL)
FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V
255
0
15
63
111
159
207
255
TAP POSITION (DECIMAL)
FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V
SCL CLOCK
WIPER
SCL
9TH CLK OF THE
DATA BYTE (ACK)
RW PIN
CH1: 1V/DIV, 1µs/DIV
CH2: 10mV/DIV, 1µs/DIV
FIGURE 19. WIPER DIGITAL FEED-THROUGH
FN7870 Rev 1.00
September 23, 2015
CH1: 20mV/DIV, 2µs/DIV
CH2: 2V/DIV, 2µs/DIV
FIGURE 20. WIPER TRANSITION GLITCH
Page 12 of 20
ISL23325
Typical Performance Curves
(Continued)
1V/DIV
0.2µs/DIV
0.5V/DIV
20µs/DIV
SCL
9TH CLOCK OF THE
DATA BYTE (ACK)
VCC
WIPER
WIPER
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
CH1: RH TERMINAL
CH2: RW TERMINAL
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
1.8
STANDBY CURRENT ICC (µA)
1.6
1.4
1.2
1.0
VCC = 5.5V, VLOGIC = 5.5V
0.8
0.6
VCC = 1.7V, VLOGIC = 1.2V
0.4
0.2
0
-40
0.5V/DIV, 0.2µs/DIV
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
Potentiometers Pins
RHI AND RLI
The high (RHi, i = 0, 1) and low (RLi, i = 0,1) terminals of the
ISL23325 are equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative position
of the wiper and not the voltage potential on the terminals. With
WRi set to 255 decimal, the wiper will be closest to RHi, and with
the WR set to 0, the wiper is closest to RLi.
RWI
RWi (i = 0,1) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
FN7870 Rev 1.00
September 23, 2015
10
35
60
85
110
TEMPERATURE (°C)
FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY
Functional Pin Descriptions
-15
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
VCC
Power terminal for the potentiometer section analog power
source. Can be any value needed to support voltage range of DCP
pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bi-directional serial data input/output pin for I2C
interface. It receives device address, wiper address and data
from an I2C external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
Page 13 of 20
ISL23325
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23325. A
maximum of eight ISL23325 devices may occupy the I2C serial
bus (see Table 3).
VLOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I2C logic source.
Principles of Operation
The ISL23325 is an integrated circuit incorporating two DCPs with
its associated registers and an I2C serial interface providing direct
communication between a host and the potentiometer. The resistor
array is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap positions.
Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC
level at any conditions during power-up and normal operation.
The VLOGIC pin is the terminal for the logic control digital power
source. It should use the same supply as the I2C logic source
which allows reliable communication with a wide range of
microcontrollers and is independent from the VCC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
The WRi can be read or written to directly using the I2C serial
interface as described in the following sections.
Memory Description
The ISL23325 contains three volatile 8-bit registers: Wiper
Register WR0, Wiper Register WR1, and Access Control Register
(ACR). Memory map of the ISL23325 is shown in Table 1. The
Wiper Register WR0 at address 0, contains current wiper position
of DCP0; The Wiper Register WR1 at address 1 contains current
wiper position of DCP1. The Access Control Register (ACR) at
address 10h contains information and control bits described in
Table 2.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10
ACR
40
1
WR1
80
0
WR0
80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
NAME/
VALUE
0
SHDN
0
0
0
0
0
0
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor as shown in Figure 25. Default value of the
SHDN bit is 1.
RH
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WRi
of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal
(RWi) is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the WRi
increases from all zeroes (0) to all ones (255 decimal), the wiper
moves monotonically from the position closest to RLi to the
position closest to RHi. At the same time, the resistance between
RWi and RLi increases monotonically, while the resistance
between RHi and RWi decreases monotonically.
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2 to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
While the ISL23325 is being powered up, both WR0 and WR1
are reset to 80h (128 decimal), which positions RWi at the center
between RLi and RHi.
FN7870 Rev 1.00
September 23, 2015
Page 14 of 20
WIPER VOLTAGE, VRW (V)
ISL23325
ISL23325 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
POWER-UP
MID SCALE = 80H
USER PROGRAMMED
AFTER SHDN
SHDN ACTIVATED SHDN RELEASED
WIPER RESTORE TO
THE ORIGINAL POSITION
SHDN MODE
0
TIME (s)
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
I2C Serial Interface
The ISL23325 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23325 operates as a slave device
in all applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
The ISL23325 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Address Byte. The ISL23325 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs, and
the following three bits are matching the logic values present at
pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1”
for a Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
Protocol Conventions
LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23325, the SDA pin is in the input mode.
1
0
1
0
A2
(MSB)
A1
A0
R/W
(LSB)
All I2C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
FN7870 Rev 1.00
September 23, 2015
Page 15 of 20
ISL23325
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
S
T
A
R
T
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
WRITE
IDENTIFICATION
BYTE
ADDRESS
BYTE
1 0 1 0 A2A1 A0 0
SIGNALS FROM
THE SLAVE
S
T
O
P
DATA
BYTE
0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 29. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
1 0 1 0 A2A1 A0 0
SIGNALS FROM
THE SLAVE
S
READ
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 1
S
A T
C O
K P
A
C
K
1 0 1 0 A2A1 A0 1
0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 30. READ SEQUENCE
Write Operation
Read Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23325 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and the
device enters its standby state (see Figures 28 and 29).
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23325 responds
with an ACK; then the ISL23325 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
It is possible to perform a sequential Write to all DCP channels
via a single Write operation. The command is initiated by sending
an additional Data Byte after the first Data byte instead of
sending a STOP condition.
FN7870 Rev 1.00
September 23, 2015
Page 16 of 20
ISL23325
Applications Information
VLOGIC Requirements
VLOGIC should be powered continuously during normal operation.
In a case where turning VLOGIC OFF is necessary, it is
recommended to ground the VLOGIC pin of the ISL23325.
Grounding the VLOGIC pin or both VLOGIC and VCC does not affect
other devices on the same bus. It is good practice to put a 1µF
cap in parallel to 0.1µF as close to the VLOGIC pin as possible.
VCC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (
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