DATASHEET
ISL23428
FN7904
Rev 2.00
September 23, 2015
Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
The ISL23428 is a volatile, low voltage, low noise, low power,
128-tap, dual digitally controlled potentiometer (DCP) with an
SPI Bus™ interface. It integrates two DCP cores, wiper switches
and control logic on a monolithic CMOS integrated circuit.
Features
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has an associated
volatile Wiper Register (WRi, i = 0, 1) that can be directly written
to and read by the user. The contents of the WRi controls the
position of the wiper. When powered on, the wiper of each DCP
will always commence at mid-scale (64 tap position).
• 10k 50kor 100k total resistance
The low voltage, low power consumption, and small package
of the ISL23428 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23428 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23428 without passing through a voltage
level shifter.
• Two potentiometers per package
• 128 resistor taps
• SPI serial interface
- No additional level translator for low bus supply
- Daisy Chaining of multiple DCPs
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V SPI bus/logic power supply
• Maximum supply current without serial bus activity
(standby)
- 4µA @ VCC and VLOGIC = 5V
- 1.7µA @ VCC and VLOGIC = 1.7V
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
• Shutdown Mode
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
Applications
• Wiper resistance: 70 typical @ VCC = 3.3V
• Power supply margining
• Power-on preset to mid-scale (64 tap position)
• Trimming sensor circuits
• Extended industrial temperature range: -40°C to +125°C
• Gain adjustment in battery powered instruments
• 14 Ld TSSOP or 16 Ld UTQFN packages
• RF power amplifier bias compensation
• Pb-free (RoHS compliant)
10000
VREF
RESISTANCE (Ω)
8000
6000
RH
-
4000
RW
ISL23428
2000
0
VREF_M
+
ISL28114
RL
0
32
64
96
128
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10kΩ DCP
FN7904 Rev 2.00
September 23, 2015
FIGURE 2. VREF ADJUSTMENT
Page 1 of 21
ISL23428
Block Diagram
VLOGIC
VCC
SCK
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
SDI
SDO
SPI
INTERFACE
CS
RH0
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
RW0
GND
Pin Configurations
RH1
RL0
RW1
RL1
Pin Descriptions
ISL23428
(14 LD TSSOP)
TOP VIEW
TSSOP
UTQFN
SYMBOL
DESCRIPTION
1, 7
5, 6, 15
GND
2
16
VLOGIC
3
1
SDO
Logic Pin - Serial bus data output
(configurable)
Ground pin
SPI bus/logic supply
Range 1.2V to 5.5V
GND
1
14 VCC
VLOGIC
2
13 RL0
SDO
3
12 RW0
4
2
SCK
Logic Pin - Serial bus clock input
SCK
4
11 RH0
5
3
SDI
Logic Pin - Serial bus data input
SDI
5
10 RH1
6
4
CS
Logic Pin - Active low chip select
CS
6
9
RW1
8
8
RL1
DCP1 “low” terminal
GND
7
8
RL1
9
9
RW1
DCP1 wiper terminal
TOP VIEW
12
12
RW0
DCP0 wiper terminal
13
13
RL0
DCP0 “low” terminal
14
14
VCC
Analog power supply.
Range 1.7V to 5.5V
-
7
NC
Not Connected
RL0
DCP0 “high” terminal
13
RH0
VCC
11
GND
11
14
DCP1 “high” terminal
15
RH1
VLOGIC
10
16
10
ISL23428
(16 LD UTQFN)
RH1
CS
4
9
RW1
FN7904 Rev 2.00
September 23, 2015
8
10
RL1
3
7
SDI
6
RH0
NC
RW0
11
GND
12
2
5
1
SCK
GND
SDO
Page 2 of 21
ISL23428
Ordering Information
PART NUMBER
(Note 4)
PART
MARKING
RESISTANCE
OPTION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL23428TFVZ (Note 2)
23428 TFVZ
100
-40 to +125
14 Ld TSSOP
M14.173
ISL23428TFVZ-T7A (Notes 1, 2)
23428 TFVZ
100
-40 to +125
14 Ld TSSOP
M14.173
ISL23428TFVZ-TK (Notes 1, 2)
23428 TFVZ
100
-40 to +125
14 Ld TSSOP
M14.173
ISL23428UFVZ (Note 2)
(No longer available, recommended
replacement: ISL23428TFRUZ-TK)
23428 UFVZ
50
-40 to +125
14 Ld TSSOP
M14.173
ISL23428UFVZ-T7A (Notes 1, 2)
(No longer available, recommended
replacement: ISL23428TFRUZ-TK)
23428 UFVZ
50
-40 to +125
14 Ld TSSOP
M14.173
ISL23428UFVZ-TK (Notes 1, 2)
(No longer available, recommended
replacement: ISL23428TFRUZ-TK)
23428 UFVZ
50
-40 to +125
14 Ld TSSOP
M14.173
ISL23428WFVZ (Note 2)
23428 WFVZ
10
-40 to +125
14 Ld TSSOP
M14.173
ISL23428WFVZ-T7A (Notes 1, 2)
23428 WFVZ
10
-40 to +125
14 Ld TSSOP
M14.173
ISL23428WFVZ-TK (Notes 1, 2)
23428 WFVZ
10
-40 to +125
14 Ld TSSOP
M14.173
ISL23428TFRUZ-T7A (Notes 1, 3)
GBR
100
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23428TFRUZ-TK (Notes 1, 3)
GBR
100
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23428UFRUZ-T7A (Notes 1, 3)
(No longer available, recommended
replacement: ISL23428TFRUZ-TK)
GBP
50
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23428UFRUZ-TK (Notes 1, 3)
(No longer available, recommended
replacement: ISL23428TFRUZ-TK)
GBP
50
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23428WFRUZ-T7A (Notes 1, 3)
GBN
10
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
ISL23428WFRUZ-TK (Notes 1, 3)
GBN
10
-40 to +125
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL23428. For more information on MSL please see techbrief TB363.
FN7904 Rev 2.00
September 23, 2015
Page 3 of 21
ISL23428
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .4.5kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
14 Ld TSSOP Package (Notes 5, 6) . . . . . .
112
40
16 Ld UTQFN Package (Notes 5, 6) . . . . . .
110
64
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For JC, the “case temp” location is the center top of the package.
Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
SYMBOL
RTOTAL
PARAMETER
RH to RL Resistance
TEST CONDITIONS
W option
VRH, VRL
RW
MAX
(Note 19)
UNITS
kΩ
U option
50
kΩ
T option
100
kΩ
-20
W option
±2
+20
125
%
ppm/°C
U option
65
ppm/°C
T option
45
ppm/°C
DCP Terminal Voltage
VRH or VRL to GND
Wiper Resistance
RH - floating, VRL = 0V, force IW current to
the wiper, IW = (VCC - VRL)/RTOTAL,
VCC = 2.7V to 5.5V
0
70
VCC = 1.7V
CH/CL/CW Terminal Capacitance
TYP
(Note 7)
10
RH to RL Resistance Tolerance
End-to-End Temperature Coefficient
MIN
(Note 19)
See “DCP Macro Model” on page 9
V
Ω
580
Ω
32/32/32
pF
ILkgDCP
Leakage on DCP Pins
Voltage at pin from GND to VCC
Noise
Resistor Noise Density
Wiper at middle point, W option
16
Wiper at middle point, U option
49
nV/√Hz
Wiper at middle point, T option
61
nV/√Hz
Feed Thru Digital Feed-through from Bus to Wiper
PSRR
Power Supply Reject Ratio
FN7904 Rev 2.00
September 23, 2015
-0.4
VCC
200
2V
0
IOL = 1.5mA, VLOGIC < 2V
Rpu
SDO Pull-Up Resistor Off-Chip
Maximum is determined by
tRO and tFO with maximum
bus load Cb = 30pF,
fSCK = 5MHz
0.4
V
0.2 x VLOGIC
V
1.5
kΩ
5
MHz
1
MHz
Cpin
SCK, SDO, SDI, CS Pin Capacitance
fSCK
SCK Frequency
VLOGIC = 1.7V to 5.5V
10
tCYC
SPI Clock Cycle Time
VLOGIC ≥ 1.7V
200
ns
tWH
SPI Clock High Time
VLOGIC ≥ 1.7V
100
ns
tWL
SPI Clock Low Time
VLOGIC ≥ 1.7V
100
ns
tLEAD
Lead Time
VLOGIC ≥ 1.7V
250
ns
tLAG
Lag Time
VLOGIC ≥ 1.7V
250
ns
tSU
SDI, SCK and CS Input Setup Time
VLOGIC ≥ 1.7V
50
ns
tH
SDI, SCK and CS Input Hold Time
VLOGIC ≥ 1.7V
50
ns
tRI
SDI, SCK and CS Input Rise Time
VLOGIC ≥ 1.7V
10
tFI
SDI, SCK and CS Input Fall Time
VLOGIC ≥ 1.7V
10
20
ns
100
ns
VLOGIC = 1.2V to 1.6V
pF
ns
tDIS
SDO Output Disable Time
VLOGIC ≥ 1.7V
0
tSO
SDO Output Setup Time
VLOGIC ≥ 1.7V
50
ns
tV
SDO Output Valid Time
VLOGIC ≥ 1.7V
150
ns
tHO
SDO Output Hold Time
VLOGIC ≥ 1.7V
0
ns
FN7904 Rev 2.00
September 23, 2015
Page 7 of 21
ISL23428
Serial Interface Specification
SYMBOL
For SCK, SDI, SDO, CS Unless Otherwise Noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 19)
TYP
(Note 7)
MAX
(Note 19)
UNITS
tRO
SDO Output Rise Time
Rpu = 1.5k, Cbus = 30pF
60
ns
tFO
SDO Output Fall Time
Rpu = 1.5k, Cbus = 30pF
60
ns
tCS
CS Deselect Time
2
µs
NOTES:
7. Typical values are for TA = +25°C and 3.3V supply voltages.
8. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
9. ZS error = V(RW)0/LSB.
10. FS error = [V(RW)127 – VCC]/LSB.
11. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
12. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127
Max V RW i – Min V RW i
10 6
13. TC = ----------------------------------------------------------------------------- --------------------- for i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
V
V RW i +25°C
+165°C and Min( ) is the minimum value of the wiper voltage over the temperature range.
14. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00
hex respectively.
15. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW127/MI, when measuring between RW and RH.
16. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127.
17. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127.
18.
6
Max Ri – Min Ri
10
TC R = ------------------------------------------------------- --------------------Ri +25°C
+165°C
for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
20. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC
first followed by the VCC.
21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
FN7904 Rev 2.00
September 23, 2015
Page 8 of 21
ISL23428
DCP Macro Model
RTOTAL
RH
CL
CH
CW
32pF
RL
32pF
32pF
RW
Timing Diagrams
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
tLAG
...
tWH
tWL
...
MSB
SDI
tRI
tFI
LSB
SDO
Output Timing
CS
SCK
...
tSO
tHO
tDIS
...
MSB
SDO
LSB
tV
SDI
ADDR
XDCP™ Timing (for All Load Instructions)
CS
tDCP
SCK
SDI
...
MSB
...
LSB
VW
SDO
FN7904 Rev 2.00
September 23, 2015
*When CS is HIGH
SDO at Z or Hi-Z state
Page 9 of 21
ISL23428
0.20
0.04
0.10
0.02
DNL (LSB)
DNL (LSB)
Typical Performance Curves
0.00
-0.10
0.00
-0.02
-0.20
0
32
64
96
-0.04
128
0
32
64
0.12
0.15
0.09
INL (LSB)
INL (LSB)
0.30
0.00
0.06
0.03
-0.15
0
32
64
96
0.00
128
0
TAP POSITION (DECIMAL)
32
64
96
128
TAP POSITION (DECIMAL)
FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C
0.20
0.04
0.10
0.02
RDNL (MI)
RDNL (MI)
128
FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C
-0.30
96
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
0.00
-0.10
0.00
-0.02
-0.20
-0.04
0
32
64
96
TAP POSITION (DECIMAL)
FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C
FN7904 Rev 2.00
September 23, 2015
128
0
32
64
96
TAP POSITION (DECIMAL)
FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C
Page 10 of 21
128
ISL23428
(Continued)
0.30
0.08
0.15
0.04
RINL (MI)
RINL (MI)
Typical Performance Curves
0.00
-0.15
-0.30
0.00
-0.04
0
32
64
96
-0.08
128
0
32
+125°C
100
WIPER RESISTANCE ()
WIPER RESISTANCE ()
+25°C
80
60
40
-40°C
20
+125°C
+25°C
80
60
-40°C
40
20
0
32
64
96
TAP POSITION (DECIMAL)
0
128
0
32
64
96
128
TAP POSITION (DECIMAL)
FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V
FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V
200
40
150
30
TCv (ppm/°C)
TCv (ppm/°C)
128
120
100
100
20
10
50
0
96
FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C
FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C
0
64
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
15
43
71
99
TAP POSITION (DECIMAL)
FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V
FN7904 Rev 2.00
September 23, 2015
127
0
15
43
71
99
TAP POSITION (DECIMAL)
FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V
Page 11 of 21
127
ISL23428
Typical Performance Curves
(Continued)
120
500
90
TCr (ppm/°C)
TCr (ppm/°C)
400
300
200
30
100
0
60
15
43
71
99
0
127
15
43
TAP POSITION (DECIMAL)
20
120
15
90
10
5
0
127
FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V
TCr (ppm/°C)
TCv (ppm/°C)
FIGURE 15. 10kΩ TCr vs TAP POSITION
71
99
TAP POSITION (DECIMAL)
60
30
15
43
71
99
TAP POSITION (DECIMAL)
FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V
SCK CLOCK
127
0
15
43
71
99
TAP POSITION (DECIMAL)
127
FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V
WIPER
CS RISING
RW PIN
CH1: 1V/DIV, 1µs/DIV
CH2: 10mV/DIV, 1µs/DIV
FIGURE 19. WIPER DIGITAL FEED-THROUGH
FN7904 Rev 2.00
September 23, 2015
CH1: 20mV/DIV, 2µs/DIV
CH2: 2V/DIV, 2µs/DIV
FIGURE 20. WIPER TRANSITION GLITCH
Page 12 of 21
ISL23428
Typical Performance Curves
(Continued)
1V/DIV
0.2µs/DIV
0.5V/DIV
20µs/DIV
VCC
CS RISING
WIPER
WIPER
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
CH1: RH TERMINAL
CH2: RW TERMINAL
1.8
STANDBY CURRENT ICC (µA)
1.6
1.4
1.2
1.0
VCC = 5.5V, VLOGIC = 5.5V
0.8
0.6
VCC = 1.7V, VLOGIC = 1.2V
0.4
0.2
0.5V/DIV, 0.2µs/DIV
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY
0
-40
-15
10
35
60
85
110
TEMPERATURE (°C)
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Functional Pin Descriptions
Potentiometers Pins
Power Pins
RHI AND RLI
VCC
Power terminal for the potentiometer section analog power
source. Can be any value needed to support voltage range of DCP
pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.
The high (RHi, i = 0, 1) and low (RLi, i = 0, 1) terminals of the
ISL23428 are equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative position
of the wiper and not the voltage potential on the terminals. With
WRi set to 127 decimal, the wiper will be closest to RHi, and with
the WRi set to 0, the wiper is closest to RLi.
RWI
RWi (i = 0, 1) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
FN7904 Rev 2.00
September 23, 2015
Bus Interface Pins
SERIAL CLOCK (SCK)
This input is the serial clock of the SPI serial interface.
SERIAL DATA INPUT (SDI)
The SDI is a serial data input pin for SPI interface. It receives
operation code, wiper address and data from the SPI remote
host device. The data bits are shifted in at the rising edge of the
serial clock SCK, while the CS input is low.
Page 13 of 21
ISL23428
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the data
bits are shifted out on the falling edge of the serial clock SCK and
will be available to the master on the following rising edge of SCK.
The output type is configured through ACR[1] bit for Push-Pull or
Open Drain operation. Default setting for this pin is Push-Pull. An
external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z) depends on the selected configuration.
CHIP SELECT (CS)
CS LOW enables the ISL23428, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23428 is deselected and the SDO pin is at high impedance,
and the device will be in the standby state.
VLOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I2C logic source.
Principles of Operation
The ISL23428 is an integrated circuit incorporating two DCPs
with its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC
level at any conditions during power-up and normal operation.
The VLOGIC pin is the terminal for the logic control digital power
source. It should use the same supply as the SPI logic source
which allows reliable communication with a wide range of
microcontrollers and is independent from the VCC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RHi and RLi pins). The RWi pin of the DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by an 8-bit volatile Wiper Register
(WRi). When the WR of a DCP contains all zeroes
(WRi[7:0] = 00h), its wiper terminal (RWi) is closest to its “Low”
terminal (RLi). When the WRi register of a DCP contains all ones
(WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest to its “High”
terminal (RHi). As the value of the WRi increases from all zeroes
(0) to all ones (127 decimal), the wiper moves monotonically
from the position closest to RLi to the position closest to RHi. At
FN7904 Rev 2.00
September 23, 2015
the same time, the resistance between RWi and RLi increases
monotonically, while the resistance between RHi and RWi
decreases monotonically.
While the ISL23428 is being powered up, both WRi are reset to
40h (64 decimal), which positions RWi at the center between RLi
and RHi.
The WRi can be read or written to directly using the SPI serial
interface, as described in the following sections.
Memory Description
The ISL23428 contains three volatile 8-bit registers: Wiper Register
WR0, Wiper Register WR1, and Access Control Register (ACR).
Memory map of ISL23428 is shown in Table 1. The Wiper Register
WR0 at address 0 contains current wiper position of DCP0; the
Wiper Register WR1 at address 1 contains current wiper position of
DCP1. The Access Control Register (ACR) at address 10h contains
information and control bits described in Table 2.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10
ACR
40
1
WR1
40
0
WR0
40
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
NAME/
VALUE
0
SHDN
0
0
0
0
SDO
0
The SDO bit (ACR[1]) configures type of SDO output pin. The
default value of SDO bit is 0 for Push-Pull output. The SDO pin
can be configured as Open Drain output for some applications. In
this case, an external pull-up resistor is required; reference the
“Serial Interface Specification” on page 7.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., each DCP is
forced to end-to-end open circuit and each RW shorted to RL
through a 2kΩ serial resistor, as shown in Figure 25. Default value
of the SHDN bit is 1.
RH
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
Page 14 of 21
ISL23428
WIPER VOLTAGE, VRW (V)
When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will
return to the previous WR settings after a short settling time
(see Figure 26).
POWER-UP
SHDN ACTIVATED
Protocol Conventions
AFTER SHDN
SHDN RELEASED
WIPER RESTORE TO
THE ORIGINAL POSITION
SHDN MODE
0
The ISL23428 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with data
clocked in on the rising edge of SCK, and clocked out on the
falling edge of SCK. CS must be LOW during communication with
the ISL23428. The SCK and CS lines are controlled by the host or
master. The ISL23428 operates only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
MID SCALE = 40H
USER PROGRAMMED
SPI Serial Interface
The SPI protocol contains Instruction Byte followed by one or more
Data Bytes. A valid Instruction Byte contains instruction as the three
MSBs, with the following five register address bits (see Table 3).
The next byte sent to the ISL23428 is the Data Byte.
TIME (s)
TABLE 3. INSTRUCTION BYTE FORMAT
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
BIT #
7
6
5
4
3
2
1
0
I2
I1
I0
R4
R3
R2
R1
R0
Table 4 contains a valid instruction set for ISL23428.
If the [R4:R0] bits are zero or one, then the read or write is to the
WRi register. If the [R4:R0] are 10000, then the operation is to
the ACR.
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
I2
I1
I0
R4
R3
R2
R1
R0
OPERATION
0
0
0
X
X
X
X
X
NOP
0
0
1
X
X
X
X
X
ACR READ
0
1
1
X
X
X
X
X
ACR WRTE
1
0
0
R4
R3
R2
R1
R0
WRi or ACR READ
1
1
0
R4
R3
R2
R1
R0
WRi or ACR WRTE
Where X means “do not care”.
FN7904 Rev 2.00
September 23, 2015
Page 15 of 21
ISL23428
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
WR INSTRUCTION
SDI
DATA BYTE
ADDR
SDO
FIGURE 27. TWO BYTE WRITE SEQUENCE
CS
1
8
16
24
32
SCK
SDI
RD
NOP
ADDR
RD
SDO
ADDR
READ DATA
FIGURE 28. FOUR BYTE READ SEQUENCE
Write Operation
Read Operation
A write operation to the ISL23428 is a two or more bytes
operation. First, It requires the CS transition from HIGH-to-LOW.
Then the host sends a valid Instruction Byte, followed by one or
more Data Bytes to the SDI pin. The host terminates the write
operation by pulling the CS pin from LOW-to-HIGH. Instruction is
executed on the rising edge of CS (see Figure 27).
A Read operation to the ISL23428 is a four byte operation. First,
It requires the CS transition from HIGH-to-LOW. Then the host
sends a valid Instruction Byte, followed by a “dummy” Data Byte,
NOP Instruction Byte and another “dummy” Data Byte to SDI pin.
The SPI host receives the Instruction Byte (instruction code +
register address) and requested Data Byte from SDO pin on the
rising edge of SCK during third and fourth bytes, respectively. The
host terminates the read by pulling the CS pin from LOW-to-HIGH
(see Figure 28).
FN7904 Rev 2.00
September 23, 2015
Page 16 of 21
ISL23428
Applications Information
The first part starts by HIGH-to-LOW transition on CS line,
followed by N two bytes read instruction on SDI line with reversed
chain access sequence: the instruction byte + dummy data byte
for the last DCP in chain is going first, followed by LOW-to-HIGH
transition on CS line. The read instructions are executed during
the second part of read sequence. It also starts by HIGH-to-LOW
transition on CS line, followed by N number of two bytes NOP
instructions on SDI line and LOW-to-HIGH transition of CS. The
data is read on every even byte during the second part of the
read sequence while every odd byte contains code 111b followed
by address from which the data is being read.
Communicating with ISL23428
Communication with ISL23428 proceeds using SPI interface
through the ACR (address 10000b), WR0 (addresses 00000b)
and WR1 (addresses 00001b) registers.
The wiper of the potentiometer is controlled by the WRi register.
Writes and reads can be made directly to these registers to
control and monitor the wiper position.
Daisy Chain Configuration
Wiper Transition
When an application needs more than one ISL23428, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs as shown in Figure 29. In Daisy Chain
configuration, the SDO pin of the previous chip is connected to
the SDI pin of the following chip, and each CS and SCK pins are
connected to the corresponding microcontroller pins in parallel,
like regular SPI interface implementation. The Daisy Chain
configuration can also be used for simultaneous setting of
multiple DCPs.
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time ( DCP1 -->
DCP2 --> ... --> DCP(N-1). The write instruction is executed on the
rising edge of CS for all N DCPs simultaneously.
VLOGIC Requirements
It is recommended to keep VLOGIC powered all the time during
normal operation. In a case where turning VLOGIC OFF is
necessary, it is recommended to ground the VLOGIC pin of the
ISL23428. Grounding the VLOGIC pin or both VLOGIC and VCC does
not affect other devices on the same bus. It is good practice to put
a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to
the VLOGIC pin.
Daisy Chain Read Operation
VCC Requirements and Placement
The read operation consists of two parts: first, send the read
instructions (N two bytes operation) with valid address; second,
read the requested data while sending NOP instructions (N two
bytes operation) as shown in Figures 31 and 32.
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the VCC pin.
N DCP IN A CHAIN
CS
SCK
DCP0
MOSI
MISO
µC
DCP1
DCP2
CS
CS
CS
SCK
SCK
SCK
SDI
SDO
SDI
SDO
SDI
DCP(N-1)
CS
SCK
SDO
SDI
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
FN7904 Rev 2.00
September 23, 2015
Page 17 of 21
ISL23428
CS
SCK
16 CLKLS
WR
SDI
16 CLKS
16 CLKS
D C P2
SDO 0
WR
D C P1
WR
D C P0
WR
D C P2
WR
D C P1
WR
D C P2
SDO 1
SDO 2
FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 31. TWO BYTE READ INSTRUCTION
CS
SCK
16 CLKS
SDI
RD DCP2
SDO
16 CLKS
RD DCP1
16 CLKS
16 CLKS
16 CLKS
16 CLKS
RD DCP0
NOP
NOP
NOP
DCP2 OUT
DCP1 OUT
DCP0 OUT
FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
FN7904 Rev 2.00
September 23, 2015
Page 18 of 21
ISL23428
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
9/23/15
FN7904.2
Updated the Ordering Information table on page 3.
Replaced the Products section with the About Intersil section.
Updated Package Outline Drawing L16.2.6X1.8A to the latest revision. Changes were as follows:
-Changed in Note 5 0.30 to 0.25.
7/9/12
FN7904.1
Ordering information table: Three part number listed incorrectly. Changed part number from 23425 to
ISL23428.
8/25/11
FN7904.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2011-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7904 Rev 2.00
September 23, 2015
Page 19 of 21
ISL23428
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
FN7904 Rev 2.00
September 23, 2015
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
Page 20 of 21
ISL23428
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
L16.2.6x1.8A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
2X
A
N
SYMBOL
E
0.10 C
1 2
2X
0.10 C
0.10 C
C
A
A1
SIDE VIEW
e
PIN #1 ID
K
1 2
NX L
L1
(DATUM B)
(DATUM A)
BOTTOM VIEW
NOTES
0.45
0.50
0.55
-
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
0.40 BSC
-
K
0.15
-
-
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
NX b 5
16X
0.10 M C A B
0.05 M C
MAX
A
e
SEATING PLANE
NOMINAL
A1
A3
TOP VIEW
0.05 C
MIN
0
-
12
4
Rev. 6 1/14
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
CL
(A1)
NX (b)
L
5
e
SECTION "C-C"
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
TERMINAL TIP
C C
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.20
0.50
0.20
0.40
10 LAND PATTERN
FN7904 Rev 2.00
September 23, 2015
Page 21 of 21
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