ISL28110FBZ-T7

DATASHEET ISL28110, ISL28210 FN6639 Rev 3.00 November 29, 2012 Precision Low Noise JFET Operational Amplifiers The ISL28110, ISL28210, are single and dual JFET amplifiers featuring low noise, high slew rate, low input bias current and offset voltage, making them the ideal choice for high impedance applications where precision and low noise are important. The combination of precision, low noise, and high speed combined with a small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Features • Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 40V • Low voltage noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6nV/Hz • Input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2pA • High slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23V/µs • High bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5MHz Applications for these amplifiers include precision medical and analytical instrumentation, sensor conditioning, precision power supply controls, industrial controls and photodiode amplifiers. • Low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 300µV, Max The ISL28110 single amplifier and the ISL28210 dual amplifiers are available in the 8 Ld SOIC package. All devices are offered in standard pin configurations and operate over the extended temperature range from -40°C to +125°C. • Operating temperature range. . . . . . . . . . . .-40°C to +125°C • Offset drift. . . . . . . . . . . . . . . . . . . . . . . . . . . Grade C 10µV/°C • Low current consumption . . . . . . . . . . . . . . . . . . . . . . . 2.55mA • Small package offerings in single, and dual • No phase reversal • Pb-Free (RoHS compliant) Applications • Precision instruments • Photodiode amplifiers • High impedance buffers • Medical instrumentation • Active filter blocks • Industrial controls Related Literature RF CF V+ PHOTO DIODE RSH CT OUTPUT + VBASIC APPLICATION CIRCUIT - PHOTODIODE AMPLIFIER FIGURE 1. TYPICAL APPLICATION FN6639 Rev 3.00 November 29, 2012 NORMALIZED INPUT BIAS CURRENT (pA) • AN1594 ISL28210SOICEVAL1Z Evaluation Board User’s Guide 10 8 VS = ±15V 6 4 2 0 -2 -4 -6 -8 -10 -15 -10 -5 0 5 10 15 VCM (V) FIGURE 2. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE Page 1 of 23 ISL28110, ISL28210 Pin Configuration ISL28210 (8 LD SOIC) TOP VIEW ISL28110 (8 LD SOIC) TOP VIEW NC 1 8 NC VOUT A 1 -IN A 2 7 V+ -IN A 2 +IN A 3 6 VOUT A +IN A 3 V- 4 5 NC V- 4 - + - + + - 8 V+ 7 VOUT B 6 -IN B 5 +IN B Pin Descriptions ISL28110 (8 LD SOIC) ISL28210 (8 LD SOIC) PIN NAME EQUIVALENT CIRCUIT 3 3 +IN A Circuit 1 Amplifier A non-inverting input 2 2 -IN A Circuit 1 Amplifier A inverting input 6 1 VOUT A Circuit 2 Amplifier A output 4 4 V- Circuit 3 Negative power supply 5 +IN B Circuit 1 Amplifier B non-inverting input 6 -IN B Circuit 1 Amplifier B inverting input 7 VOUT B Circuit 2 Amplifier B output 8 V+ Circuit 3 Positive power supply 7 1, 5, 8 IN- NC No connect PAD Thermal Pad is electrically isolated from active circuitry. Pad can float, connect to Ground or to a potential source that is free from signals or noise sources. V+ V+ IN+ OUT V- V- CIRCUIT 1 FN6639 Rev 3.00 November 29, 2012 DESCRIPTION CIRCUIT 2 V+ CAPACITIVELY TRIGGERED ESD CLAMP VCIRCUIT 3 Page 2 of 23 ISL28110, ISL28210 Ordering Information PART NUMBER (Notes 1, 2, 3) ISL28110FBZ PART MARKING TCVOS (µV/°C) PACKAGE (Pb-free) PKG. DWG. # 28110 FBZ -C 10 (C Grade) 8 Ld SOIC M8.15E ISL28210FBZ 28210 FBZ -C 10 (C Grade) 8 Ld SOIC M8.15E ISL28210SOICEVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28110, ISL28210. For more information on MSL please see techbrief TB363. FN6639 Rev 3.00 November 29, 2012 Page 3 of 23 ISL28110, ISL28210 Absolute Voltage Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Supply Turn On Voltage Slew Rate. . . . . . . . . . . . . . . . . . . 1V/µs Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input Current for Input Voltage >V+ or 33V reverse breakdown voltage which enables the device to function reliably in large signal pulse applications without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. No special input signal restrictions are needed for power supply operation up to ±15V, and input signal distortion caused by nonlinear clamps under high slew rate conditions are avoided. For power supply operation greater than ±16V (>32V), the internal ESD clamp diodes alone cannot clamp the maximum input differential signal to the power supply rails without the risk of exceeding the 33V breakdown of the JFET gate. Under these conditions, differential input voltage limiting is necessary to prevent damage to the JFET input stage. The ISL28110 and ISL28210 are single and dual 12.5 MHz precision JFET input op amps. These devices are fabricated in the PR40 Advanced Silicon-on-Insulator (SOI) bipolar-JFET process to ensure latch-free operation. The precision JFET input stage provides low input offset voltage (300µV max @ +25°C), low input voltage noise (6nV/Hz), and input current noise that is very low with virtually no 1/f component. A high current complementary NPN/PNP emitter-follower output stage provides high slew rate and maintains excellent THD+N performance into heavy loads (0.0003% @ 10VP-P @ 1kHz into 600). Operating Voltage Range The devices are designed to operate over the 9V (±4.5V) to 40V (±20V) range and are fully characterized at 10V (±5V) and 30V (±15V). The JFET input stage maintains high impedance over a maximum input differential voltage range of ±33V. Internal ESD protection diodes clamp the non-inverting and inverting inputs to one diode drop above and below the V+ and V- the power supply rails (“Pin Descriptions” on page 2, CIRCUIT 1). FN6639 Rev 3.00 November 29, 2012 In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current limiting resistors may be needed at each input terminal (see Figure 43 RIN+, RIN-) to limit current through the power supply ESD diodes to 20mA. Page 14 of 23 ISL28110, ISL28210 Output Drive Capability The complementary bipolar emitter follower output stage features low output impedance (Figure 42) and is capable of substantial current drive over the full temperature range (Figures 29, 30) while driving the output voltage close to the supply rails. The output current is internally limited to approximately ±50mA at +25°C. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability. V+ VINVIN+ RIN- - RIN+ + RL V- Output Phase Reversal FIGURE 43. INPUT ESD DIODE CURRENT LIMITING JFET Input Stage Performance The ISL28110, ISL28210 JFET input stage has the linear gain characteristics of the MOSFET but can operate at high frequency with much lower noise. The reversed-biased gate PN gate junction has significantly lower gate capacitance than the MOSFET, enabling input slew rates that rival op amps using bipolar input stages. The added advantage for high impedance, precision amplifiers is the lack of a significant 1/f component of current noise (Figures 15, 16) as there is virtually no gate current. 10 8 INPUT OFFSET VOLTAGE (VOS) VS = ±15V T = +25°C 500 400 6 300 4 200 2 100 0 0 -2 -100 -4 -200 -6 -300 INPUT BIAS (IB) -8 -10 -15 -400 -10 -5 0 5 10 -500 15 VCM (V) FIGURE 44. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs COMMON MODE INPUT VOLTAGE FN6639 Rev 3.00 November 29, 2012 NORMALIZED VOS (uV) NORMALIZED INPUT BIAS CURRENT (pA) The input stage JFETs are bootstrapped to maintain a constant JFET drain to source voltage which keeps the JFET gate currents and input stage frequency response nearly constant over the common mode input range of the device. These enhancements provide excellent CMRR, AC performance and very low input distortion over a wide temperature range. The common mode input performance for offset voltage and bias current is shown in Figure 44. Note that the input bias current remains low even after the maximum input stage common mode voltage is exceeded (as indicated by the abrupt change in input offset voltage). Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28110 and ISL28210 are immune to output phase reversal, out to 0.5V beyond the rail (VABS MAX) limit. Beyond these limits, the device is still immune to reversal to 1V beyond the rails but damage to the internal ESD protection diodes can result unless these input currents are limited. Maximizing Dynamic Signal Range The amplifiers maximum undistorted output swing is a figure of merit for precision, low distortion applications. Audio amplifiers are a good example of amplifiers that require low noise and low signal distortion over a wide output dynamic range. When these applications operate from batteries, raising the amplifier supply voltage to overcome poor output voltage swing has the penalty of increased power consumption and shorter battery life. Amplifiers whose input and output stages can swing closest to the power supply rails while providing low noise and undistorted performance, will provide maximum useful dynamic signal range and longer battery life. Rail-to-rail input and output (RRIO) amplifiers have the highest dynamic signal range but their added complexity degrades input noise and amplifier distortion. Many contain two input pairs, one pair operating to each supply rail. The trade-offs for these are increased input noise and distortion caused by non-linear input bias current and capacitance when amplifying high impedance sources. Their rail-to-rail output stages swing to within a few millivolts of the rail, but output impedances are high so that their output swing decreases and distortion increases rapidly with increasing load current. At heavy load currents the maximum output voltage swing of RRO op amps can be lower than a good emitter follower output stage. The ISL28110 and ISL28210 low noise input stage and high performance output stage are optimized for low THD+N into moderate loads over the full -40°C to +125°C temperature range. Figures 21 and 22 show the 1kHz THD+N unity gain performance vs output voltage swing at load resistances of 2kΩ and 600Ω. Figure 45 shows the unity-gain THD+N performance driving 600Ω from ±5V supplies. Page 15 of 23 ISL28110, ISL28210 ISL28110 and ISL28210 SPICE Model 1 VS = ±5V RL = 600 THD+N (%) 0.1 AV = 1 +125°C +85°C +25°C 0.01 0.001 0°C -40°C 0.0001 0 1 2 3 4 5 6 VP-P (V) 7 8 9 10 Figures 48 through 61 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Small Signal 0.1V Step, Large Signal 5V Step Response, Open Loop Gain Phase, CMRR and Output Voltage Swing for ±5V and ±15V supplies. FIGURE 45. UNITY-GAIN THD+N vs OUTPUT VOLTAGE vs TEMPERATURE AT VS = ±5V FOR 600 LOAD Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: T JMAX = T MAX +  JA xPD MAXTOTAL (EQ. 1) where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S  I qMAX +  V S - V OUTMAX   ---------------------------RL Figure 46 shows the SPICE model schematic and Figure 47 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page 4. The AVOL is adjusted for 125dB with the dominant pole at 7Hz. The CMRR is set 120dB, f = 280kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25°C. (EQ. 2) where: • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance FN6639 Rev 3.00 November 29, 2012 Page 16 of 23 6e-12 21 9 DN D2 DBREAK 19 3 2 +- + - NPN_CASCODE R3 5e11 E En CinDif 5.87E-40 5 0 6 J1 7 PJ110_CASCODE Cin2 7.27e-40 J2 14 4 R7 16 18 DX Vg Vg Vmid Vmid D8 V7 1.18 D4 DBREAK 17 24 G2 PJ110_INPUT 250 R10 5 Vmid G4 1 GAIN = 33 J3 PJ110_CASCODE Cin1 7.27e-40 C4 2.5e-12 V6 1.18 25 V5 1.18 15 J4 R13 200k VC R8 100 GAIN = 1 Q1 NPN_CASCODE Q5 NPN_CASCODE pj110_input GAIN = 1 Q2 Q4 R4 IOS 250 0.3E-12 NPN_CASCODE R12 1e10 26 G3 + G Vmid GAIN = 181.819E-6 1k EOS Vc +- + E Vmid C2 4e-12 D7 R11 23 D3 DBREAK 13 1 DX D1 1.18 DX R2 5e11 R1 Vin+ 12 PNP_MIRROR Q6 8 1 0 110 buffer2 +- + E + - buffer1 + + - E 0.4 V1 20 11 PNP_MIRROR Q7 Vin- G1 + R9 G 22 GAIN = 33 V4 C1 4e-12 DX R6 5.5k R5 5.5k D5 D9 27 G GAIN = 181.819E-6 D6 V-- DX 0.7Vdc I1 240E-6 10 DX V3 + - 0.7Vdc V++ V++ V++ V2 C5 R14 200k E2 + + - E GAIN = 0.5 2.5e-12 D10 V-- V-- VCM INPUT STAGE GAIN STAGE MID SUPPLY REF V V+ E3 + + - E GAIN = 1 L3 L1 5.30532e-10 31 R17 0.001 318.319274232055 318.319274232055 G11 G9 + + G G GAIN = 0.0031415 D11 GAIN = 0.0031415 DX C6 C8 29 10e-12 Vc Vg Vmid VC .523 R23 50 Vout VOUT 38 L4 5.30532e-10 10e-12 GAIN = 0.0031415 R20 R22 318.319274232055 318.319274232055 V-- D13 G13 G14 + + G G GAIN = 1.11e-2 GAIN = 1.11e-2 D16 V-V- COMMON MODE GAIN STAGE WITH ZERO Vout .523 DY 10e-12 GAIN = 0.0031415 V9 36 C9 G12 DY + - + - VCM 32 + - Page 17 of 23 V-- C7 G10 + - GAIN = 1 GAIN = 1 L2 5.30532e-10 G15 Vout GAIN = 20e-3 Vout ISY R18 0.001 G8 V8 37 DX 30 G6 G 35 34 D12 R16 0.001 D15 10e-12 33 2.5E-3 Vmid D14 DX 5.30532e-10 G7 + 28 G R15 0.001 GAIN = 1 V++ R21 DX VCM G5 + G GAIN = 1 V++ R19 V-E4 + + - E GAIN = 1 CORRECTION CURRENT OUTPUT STAGE SOURCES 0 FIGURE 46. SPICE NET LIST Vout G + - 0 ++ - V++ G16 GAIN = 20e-3 Vout R24 50 ISL28110, ISL28210 FN6639 Rev 3.00 November 29, 2012 C3 ISL28110, ISL28210 * source ISL28110_210_presubckt_0 * Revision A, LaFontaine Nov 4th 2010 * Model for Noise 200nV/rtHz@0.1Hx *11nV/rtHz base band, supply current 2.5mA, *CMRR 120dB fcm=281kHz ,AVOL 125dB *fd=7Hz * SR = 20V/us, GBWP 12.6MHz, Output *voltage clamp *Copyright 2010 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * Connections: * +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28110subckt Vin+ Vin- V+ VVOUT * source ISL28110_210_PRESUBCKT_0 * *Voltage Noise * E_En VIN+ 4 2 0 1 V_V1 1 0 0.4 D_D1 1 2 DN R_R1 2 0 110 * *Input Stage * R_R2 VIN- 3 5e11 R_R3 3 4 5e11 C_CinDif 4 VIN- 5.87E-12 C_Cin1 V-- VIN- 7.27e-12 C_Cin2 V-- 4 7.27e-12 I_IOS 4 VIN- DC 0.3E-12 R_R4 5 VIN- 250 J_J1 7 5 6 pj110_input J_J2 15 16 14 pj110_input J_J3 V-- 14 15 PJ110_CASCODE J_J4 V-- 6 7 PJ110_CASCODE Q_Q1 19 13 14 NPN_CASCODE Q_Q2 12 13 6 NPN_CASCODE Q_Q4 8 13 6 NPN_CASCODE Q_Q5 12 13 14 NPN_CASCODE Q_Q6 19 11 20 PNP_MIRROR Q_Q7 8 11 9 PNP_MIRROR V_V2 V++ 10 0.7Vdc V_V3 V++ 21 0.7Vdc R_R5 9 10 5.5k R_R6 20 21 5.5k E_buffer1 11 V++ 8 V++ 1 E_buffer2 13 V-- 12 V-- 1 D_D2 8 19 DBREAK D_D3 19 8 DBREAK I_I1 V++ 12 DC 240E-6 C_C1 19 V++ 4e-12 C_C2 V-- 19 4e-12 R_R7 16 17 250 E_EOS 17 4 VC VMID 1 * *1st Gain Stage * R_R8 18 V++ 100 D_D4 V-- 18 DBREAK D_D5 22 V++ DX D_D6 V-- 24 DX V_V4 22 23 1.18 V_V5 23 24 1.18 G_G1 V++ 23 19 8 33 G_G2 V-- 23 19 8 33 R_R9 23 V++ 1 R_R10 V-- 23 1 R_R11 25 23 1k D_D7 25 VMID DX D_D8 VMID 25 DX R_R12 25 VMID 1e10 G_G3 V++ VG 25 VMID 181.819E-6 G_G4 V-- VG 25 VMID 181.819E-6 D_D9 26 V++ DX D_D10 V-- 27 DX V_V6 26 VG 1.18 V_V7 VG 27 1.18 R_R13 VG V++ 200k R_R14 V-- VG 200k C_C3 8 VG 6e-12 C_C4 VG V++ 2.5e-12 C_C5 V-- VG 2.5e-12 * * Mid Supply Reference * E_E2 VMID V-- V++ V-- 0.5 E_E3 V++ 0 V+ 0 1 E_E4 V-- 0 V- 0 1 I_ISY V+ V- DC 2.5E-3 * *Common Mode Gain Stage 40dB/dec * G_G5 V++ 29 3 VMID 1 G_G6 V-- 29 3 VMID 1 G_G7 V++ VC 29 VMID 1 G_G8 V-- VC 29 VMID 1 L_L1 28 V++ 5.30532e-11 L_L2 30 V-- 5.30532e-11 L_L3 31 V++ 5.30532e-11 L_L4 32 V-- 5.30532e-11 R_R15 29 28 0.001 R_R16 30 29 0.001 R_R17 VC 31 0.001 R_R18 32 VC 0.001 * *Second Pole Stage 40dB/dec * G_G9 V++ 33 VG VMID 0.0031415 G_G10 V-- 33 VG VMID 0.0031415 G_G11 V++ 34 33 VMID 0.0031415 G_G12 V-- 34 33 VMID 0.0031415 R_R19 33 V++ 318.319274232055 R_R20 V-- 33 318.319274232055 R_R21 34 V++ 318.319274232055 R_R22 V-- 34 318.319274232055 C_C6 33 V++ 10e-12 C_C7 V-- 33 10e-12 C_C8 34 V++ 10e-12 C_C9 V-- 34 10e-12 * * Output Stage * D_D11 34 35 DX D_D12 36 34 DX D_D13 V-- 37 DY D_D14 V++ 37 DX D_D15 V++ 38 DX D_D16 V-- 38 DY G_G13 37 V-- VOUT 34 1.11e-2 G_G14 38 V-- 34 VOUT 1.11e-2 G_G15 VOUT V++ V++ 34 20e-3 G_G16 V-- VOUT 34 V-- 20e-3 V_V8 35 VOUT -.384 V_V9 VOUT 36 -.384 R_R23 VOUT V++ 50 R_R24 V-- VOUT 50 * * .model pj110_input pjf + vto=-1.4 + beta=0.0025 + lambda=0.03 + is=2.68e-015 + pb=0.73 + cgd=8.6e-012 + cgs=9.05e-012 + fc=0.5 kf=0 + af=1 + tnom=35 * .model NPN_CASCODE npn + is=5.02e-016 + bf=150 + va=300 + ik=0.017 + rb=0.01 + re=0.011 + rc=900 + cje=2e-013 + cjc=1.6e-028 + kf=0 + af=1 * .model PJ110_CASCODE pjf + vto=-1.4 + beta=0.000617 + lambda=0.03 + is=3.96e-016 + pb=0.73 + cgd=2.2e-012 + cgs=3e-012 + fc=0.5 + kf=0 + af=1 + tnom=35 * .model DBREAK d + bv=43 + rs=1 * .model PNP_MIRROR pnp + is=4e-015 + bf=150 + va=50 + ik=0.138 + rb=0.01 + re=0.101 + rc=180 + cje=1.34e-012 + cjc=4.4e-013 + kf=0 + af=1 * .model DN D(KF=6.69e-12 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28110subckt FIGURE 47. SPICE NET LIST FN6639 Rev 3.00 November 29, 2012 Page 18 of 23 ISL28110, ISL28210 Characterization vs Simulation Results 1000 VS = ±18V INPUT NOISE VOLTAGE 100 100 10 10 1 0.1 1 10 100 1k FREQUENCY (Hz) 1000 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 1000 INPUT NOISE VOLTAGE 100 1 100k 10k VS = ±18V 10 0.1 FIGURE 48. CHARACTERIZED INPUT NOISE VOLTAGE RF = 100kΩ, RG = 100Ω 20 10 0 60 RF = 100kΩ, RG = 1kΩ ACL = 100 VS = ±5V & ±15V CL = 4pF RL = OPEN VOUT = 100mVP-P ACL = 10 RF = 100kΩ, RG = 10kΩ 40 30 20 0 RF = 0, RG = ∞ 10k RF = 100kΩ, RG = 1kΩ 100k 1M 10M ACL = 10 RF = 100kΩ, RG = 10kΩ ACL = 1 -10 1k 100M VS = ±5V & ±15V CL = 4pF RL = OPEN VOUT = 100mVP-P RF = 0, RG = ∞ 10k FREQUENCY (Hz) 1M 10M 100M FIGURE 51. SIMULATED CLOSED LOOP GAIN vs FREQUENCY 0.15 0.15 VS = ±15V 0.10 AV = 1 RL = 2k CL = 4pF 0.05 VS = ±15V AV = 1 RL = 2k CL = 4pF 0.10 VOUT (V) 0.05 VOUT (V) 100k FREQUENCY (Hz) FIGURE 50. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY 0 0 -0.05 -0.05 -0.10 -0.10 -0.15 100k RF = 100kΩ, RG = 100Ω ACL = 100 10 ACL = 1 -10 1k ACL = 1000 50 GAIN (dB) GAIN (dB) 30 10k 70 ACL = 1000 50 40 10 100 1k FREQUENCY (Hz) FIGURE 49. SIMULATED INPUT NOISE VOLTAGE 70 60 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 TIME (µs) FIGURE 52. CHARACTERIZED SMALL SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V FN6639 Rev 3.00 November 29, 2012 -0.15 0 0.2 0.4 0.6 0.8 1.0 TIME (µs) FIGURE 53. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V Page 19 of 23 ISL28110, ISL28210 Characterization vs Simulation Results (Continued) 6 6 VS = ±15V AV = 1 RL = 2k CL = 4pF 4 2 VOUT (V) VOUT (V) 2 0 0 -2 -2 -4 -4 -6 0 1 2 VS = ±15V AV = 1 RL = 2k CL = 4pF 4 3 4 5 6 7 8 9 -6 10 0 2 4 TIME (µs) PHASE GAIN 100 1k 10k 100k 1M 10M 100M 1G 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL=1MΩ -100 0.1 1 10 FREQUENCY (Hz) 1M CMRR (dB) FIGURE 58. SIMULATED (DESIGN) CMRR FN6639 Rev 3.00 November 29, 2012 PHASE GAIN 100 1k 10k 100k 1M 10M 100M 1G FIGURE 57. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs FREQUENCY CMRR (dB) 100 1k 10k 100k FREQUENCY (Hz) 10 FREQUENCY (Hz) FIGURE 56. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs FREQUENCY 130 120 110 100 90 80 70 60 50 40 30 20 VS = ±15V 10 SIMULATION 0 0.1 1 10 8 FIGURE 55. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V GAIN (dB) GAIN (dB) FIGURE 54. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = ±0.9V, ±2.5V 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL=1MΩ -100 0.1 1 10 6 TIME (µs) 10M 100M 130 120 110 100 90 80 70 60 50 40 30 20 VS = ±15V 10 SIMULATION 0 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M FIGURE 59. SIMULATED (SPICE) CMRR Page 20 of 23 ISL28110, ISL28210 Characterization vs Simulation Results (Continued) 15V OUTPUT VOLTAGE SWING (V) 5.0 10V 5V 0V 0 -5V -10V VS = ±5V -15V -5.0 0 0.2 0.4 0.6 0.8 1.0 0 0.2 TIME (m s) FIGURE 60. SIMULATED OUTPUT VOLTAGE SWING ±5V 0.4 0.6 0.8 1.0 TIME (m s) FIGURE 61. SIMULATED OUTPUT VOLTAGE SWING ±15V © Copyright Intersil Americas LLC 2010-2012. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6639 Rev 3.00 November 29, 2012 Page 21 of 23 ISL28110, ISL28210 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 8/31/12 FN6639.3 8/30/12 CHANGE Removed from ordering info MSOP parts ISL28110FUBZ, ISL28110FUZ on page 3. Removed all instances of MSOP throughout document (front page, thermal information, pin descriptions and POD Added "No Phase Reversal" to Features on page 1 Removed from ordering info TDFN parts ISL28110FRTZ, ISL28210FRTZ, ISL28110FRTBZ, ISL28210FRTBZ, ISL28110FBBZ, ISL28210FBBZ on page 3. Figure 47 on page 18 Spice Net List changed -40 to -12 in Input Stage C_CinDif, C_Cin1 and C_Cin2 Removed all instances of TDFN throughout document (front page, thermal information, pin descriptions and POD) 7/14/11 FN6639.2 Converted to new datasheet template. Page 1 Added "Related Literature" and "AN1594: ISL28210SOICEVAL1Z Evaluation Board User’s Guide" Page 3 Ordering Information table: Added ISL28210SOICEVAL1Z Evaluation Board 11/29/10 FN6639.1 Removed label on right side of characterization curve, Figure 48 (Input Noise Current). 11/23/10 9/13/10 Page 1 Updated Trademark statement Page 3 Ordering Information: Removed "coming soon" from ISL28110FBZ Page 4 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS=±5V. Page 5 Electrical Specifications: Changed AVOL limits fro V/mV to dB Page 5 Electrical Specifications, Dynamic Performance, Slew Rate: Added "4V Step" to conditions; changed TYP limit from 23V/µs to 20V/µs Page 6 Electrical Specifications, Dynamic Performance, Slew Rate: Added "10V Step" to conditions; changed TYP limit from 23V/µs to 20V/µs Page 6 Electrical Specifications: Added ISL28110 IB and IOS specs @ VS= ±15V. Changed AVOL limits from V/mV to dB. Changed ts, settling time to 0.1% from 0.9µs to 1.3µs and changed ts, settling time to 0.01% from 1.2µs to 1.6µs. Page 7 Replaced Elect Spec table Notes 8 & 9 (Note 8 "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested./Note 9 Limits established by characterization and are not production tested.)" With: "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." Page 8 Characteristic Curves: Added ISL28110 IB vs Temperature (Fig 4) Page 8 Characteristic Curves: Added ISL28110 IOS vs Temperature (Fig 6) Pages 17-21: Added PSPICE model section FN6639.0 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page. Also, please check the product information page to ensure that you have the most updated datasheet: ISL28110, ISL28210 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php FN6639 Rev 3.00 November 29, 2012 Page 22 of 23 ISL28110, ISL28210 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN6639 Rev 3.00 November 29, 2012 Page 23 of 23