DATASHEET
ISL6522B
FN9150
Rev 2.00
Aug 10, 2015
Buck and Synchronous Rectifier Pulse-Width Modulator (PWM) Controller
The ISL6522B provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous rectified buck topology.
The ISL6522B integrates all of the control, output adjustment,
monitoring and protection functions into a single package.
The output voltage of the converter can be precisely
regulated to as low as 0.8V, with a maximum tolerance of
1% over temperature and line voltage variations.
The ISL6522B provides simple, single feedback loop, voltagemode control with fast transient response. It includes a 200kHz
free-running triangle-wave oscillator that is adjustable from
below 50kHz to over 1MHz. The error amplifier features a
15MHz gain-bandwidth product and 6V/µs slew rate which
enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0-100%.
The ISL6522B protects against overcurrent conditions by
inhibiting PWM operation. The ISL6522B monitors the
current by using the rDS(ON) of the upper MOSFET which
eliminates the need for a current sensing resistor.
Pinouts
ISL6522B (SOIC)
TOP VIEW
RT
1
14 VCC
OCSET
2
13 PVCC
SS
3
12 LGATE
COMP
4
11 PGND
FB
5
10 BOOT
EN
6
9
UGATE
GND
7
8
PHASE
Features
• Drives two N-Channel MOSFETs
• Operates from +5V or +12V input
• Simple single-loop control design
- Voltage-mode PWM control
• Fast transient response
- High-bandwidth error amplifier
- Full 0–100% duty ratio
• Excellent output voltage regulation
- 0.8V internal reference
- 1% over line voltage and temperature
• Overcurrent fault monitor
- Does not require extra current sensing element
- Uses MOSFETs rDS(ON)
• Converter can source and sink current
• Pre-Biased Load Start Up
• Small converter size
- Constant frequency operation
- 200kHz free-running oscillator programmable from
50kHz to over 1MHz
• 14-lead SOIC package and 16-lead 5x5mm QFN Package
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Available (RoHS Compliant)
Applications
NC
OCSET
RT
VCC
ISL6522B (QFN)
TOP VIEW
16
15
14
13
SS 1
• Power supply for Pentium®, Pentium Pro, PowerPC® and
AlphaPC™ microprocessors
• FPGA Core DC/DC Converters
• Low-voltage distributed power supplies
12 PVCC
COMP 2
11 LGATE
FN9150 Rev 2.00
Aug 10, 2015
5
6
7
8
UGATE
9
PAHSE
EN 4
GND
10 PGND
NC
FB 3
BOOT
Page 1 of 16
ISL6522B
Ordering Information
PART NUMBER
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6522BIBZ*
(See Note)
-40 to 85
14 Ld SOIC
(Pb-free)
M14.15
ISL6522BIRZ*
(See Note)
-40 to 85
16 Ld 5x5 QFN
(Pb-free)
L16.5x5B
*Add “-T*” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9150 Rev 2.00
Aug 10, 2015
Page 2 of 16
ISL6522B
Typical Application
12V
+5V OR +12V
VCC
SS
OCSET
MONITOR AND
PROTECTION
EN
BOOT
ISL6522B
RT
OSC
UGATE
PHASE
REF
FB
+
-
-
+VO
+12V
PVCC
LGATE
+
PGND
GND
COMP
Block Diagram
VCC
POWER-ON
RESET (POR)
EN
10A
+
-
OCSET
OVER
CURRENT
SOFTSTART
SS
BOOT
4V
200A
UGATE
PHASE
REFERENCE
FB
0.8VREF
PWM
COMPARATOR
+
-
ERROR
AMP
+
-
INHIBIT
PWM
GATE
CONTROL
LOGIC
PVCC
LGATE
PGND
COMP
GND
RT
FN9150 Rev 2.00
Aug 10, 2015
OSCILLATOR
Page 3 of 16
ISL6522B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . +15.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 1) . . . JA(°C/W) JC(°C/W)
SOIC Package (Note 1) . . . . . . . . . . . . . . . . . . . . . 67
n/a
QFN Package (Notes 2, 3). . . . . . . . . . . . . . . . . . . 36
5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
Ambient Temperature Range, ISL6522BC. . . . . . . . . . . 0°C to 70°C
Ambient Temperature Range, ISL6522BI . . . . . . . . . .-40°C to 85°C
Junction Temperature Range, ISL6522BC . . . . . . . . . 0°C to 125°C
Junction Temperature Range, ISL6522BI . . . . . . . . .-40°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a highs effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
EN = VCC; UGATE and LGATE Open
-
5
-
mA
EN = 0V
-
50
100
A
Rising VCC Threshold
VOCSET = 4.5VDC
-
-
10.4
V
Falling VCC Threshold
VOCSET = 4.5VDC
8.1
-
-
V
Enable-Input Threshold Voltage
ISL6522BC, VOCSET = 4.5VDC
0.8
-
2.0
V
ISL6522BI, VOCSET = 4.5VDC
0.8
-
2.1
V
-
1.27
-
V
ISL6522BC, RT = OPEN, VCC = 12
175
200
230
kHz
ISL6522BI, RT = OPEN, VCC = 12
160
200
230
6k < RT to GND < 200k
-20
-
+20
%
VCC SUPPLY CURRENT
Nominal Supply
ICC
Shutdown Supply
POWER-ON RESET
Rising VOCSET Threshold
OSCILLATOR
Free Running Frequency
Total Variation
Ramp Amplitude
VOSC
RT = OPEN
-
1.9
-
VP-P
VREF
Commercial
-1
-
+1
%
Industrial
-2
-
+1
%
-
0.800
-
V
-
88
-
dB
-
15
-
MHz
-
6
-
V/s
REFERENCE
Reference Voltage Tolerance
Reference Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
FN9150 Rev 2.00
Aug 10, 2015
GBW
SR
COMP = 10pF
Page 4 of 16
ISL6522B
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Soft START
Soft-Start Current
ISS
-
10
-
A
Peak Soft Start Voltage
VSS
-
4.5
-
V
350
500
-
mA
GATE DRIVERS
Upper Gate Source
IUGATE
VBOOT - VPHASE = 12V, VUGATE = 6V
Upper Gate Sink
RUGATE
ISL6522BC, IUGATE = 0.3A
-
5.0
8.75
ISL6522BI, IUGATE = 0.3A
-
5.0
9.25
300
450
-
mA
Lower Gate Source
ILGATE
VCC = 12V, VLGATE = 6V
Lower Gate Sink
RLGATE
ISL6522BC, ILGATE = 0.3A
-
3.2
5.55
ISL6522BI, ILGATE = 0.3A
-
3.2
5.85
170
200
230
A
PROTECTION
OCSET Current Source
IOCSET
VOCSET = 4.5VDC
Typical Performance Curves
80
1000
60
CGATE = 3300pF
IVCC (mA)
RESISTANCE (k)
70
RT PULLUP
TO +12V
100
RT PULLDOWN
TO VSS
50
40
CGATE = 1000pF
30
20
10
CGATE = 10pF
10
10
100
SWITCHING FREQUENCY (kHz)
FIGURE 1. RT RESISTANCE vs FREQUENCY
FN9150 Rev 2.00
Aug 10, 2015
1000
0
100
200
300
400
500
600
700
800
900
1000
SWITCHING FREQUENCY (kHz)
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
Page 5 of 16
ISL6522B
Functional Pin Descriptions
SS
ISL6522B (SOIC)
TOP VIEW
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10A current source, sets the soft-start
interval of the converter.
RT
1
14 VCC
OCSET
2
13 PVCC
COMP and FB
SS
3
12 LGATE
COMP
4
11 PGND
FB
5
10 BOOT
EN
6
9
UGATE
7
8
PHASE
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error amplifier
and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-control feedback loop of the
converter.
GND
EN
This pin is the open-collector enable pin. Pull this pin below 1V
to disable the converter. In shutdown, the soft-start pin is
discharged and the UGATE and LGATE pins are held low.
NC
OCSET
RT
VCC
ISL6522B (QFN)
TOP VIEW
16
15
14
13
SS 1
GND
12 PVCC
COMP 2
11 LGATE
FB 3
10 PGND
EN 4
9
8
UGATE
7
PAHSE
6
GND
NC
5
BOOT
RT
This pin provides oscillator switching frequency adjustment. By
placing a resistor (RT) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
6
5 10
Fs 200kHz + -----------------RT
(RT to GND)
Conversely, connecting a pull-up resistor (RT) from this pin to
VCC reduces the switching frequency according to the
following equation:
PHASE
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET for
overcurrent protection. This pin also provides the return path
for the upper gate drive.
UGATE
Connect UGATE to the upper MOSFET gate. This pin provides
the gate drive for the upper MOSFET. This pin is also monitored
by the adaptive shoot through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT
This pin provides bias voltage to the upper MOSFET driver. A
bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE
7
4 10
Fs 200kHz – -----------------RT
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
(RT to 12V)
OCSET
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 200A current source
(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set
the converter overcurrent (OC) trip point according to the
following equation:
I OCS R OCSET
I PEAK = ------------------------------------------r DS ON
Connect LGATE to the lower MOSFET gate. This pin provides
the gate drive for the lower MOSFET. This pin is also monitored
by the adaptive shoot through protection circuitry to determine
when the lower MOSFET has turned off.
PVCC
Provide a bias supply for the lower gate drive to this pin.
VCC
Provide a 12V bias supply for the chip to this pin.
An overcurrent trip cycles the soft-start function.
FN9150 Rev 2.00
Aug 10, 2015
Page 6 of 16
ISL6522B
Functional Description
VOLTAGE
Initialization
The ISL6522B automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages and the enable (EN) pin. The POR monitors
the bias voltage at the VCC pin and the input voltage (VIN) on
the OCSET pin. The level on OCSET is equal to VIN Less a
fixed voltage drop (see overcurrent protection). With the EN pin
held to VCC, the POR function initiates soft-start operation after
both input supply voltages exceed their POR thresholds. For
operation with a single +12V power source, VIN and VCC are
equivalent and the +12V power source must exceed the rising
VCC threshold before POR initiates operation.
VSOFT START
VOUT
VCOMP
VOSC(MIN)
CLAMP ON VCOMP
RELEASED AT STEADY STATE
t0
The POR function inhibits operation with the chip disabled (EN
pin low). With both input supplies above their POR thresholds,
transitioning the EN pin high initiates a soft-start interval.
C SS V OUT SteadyState
t SoftStart = t 2 – t 1 = ----------- ------------------------------------------------ V OSC
I SS
V IN
The POR function initiates the soft-start sequence. An internal
10A current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft-start clamps the error amplifier output
(COMP pin) to the SS pin voltage. Figure 3 shows the soft-start
interval. At t1 in Figure 3, the SS and COMP voltages reach the
valley of the oscillator’s triangle wave. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitor(s). This interval of increasing pulse
width continues to t2, at which point the output is in regulation
and the clamp on the COMP pin is released. This method
provides a rapid and controlled output voltage rise.
FN9150 Rev 2.00
Aug 10, 2015
Where:
CSS = Soft Start Capacitor
ISS = Soft Start Current = 10A
VOSC(MIN) = Bottom of Oscillator = 1.35V
VIN = Input Voltage
VOSC = Peak to Peak Oscillator Voltage = 1.9V
VOUTSteadyState = Steady State Output Voltage
SOFT-START
FIGURE 3. SOFT-START INTERVAL
OUTPUT INDUCTOR
During Soft Start, the ISL6522B functions as a standard buck
converter by disabling the lower MOSFET. This is done by
holding the LGATE pin LOW. If there is not a diode in parallel
with the lower MOSFET, the body diode of the lower MOSFET
will conduct when the upper MOSFET is off. Once the SS pin
has reached it’s peak value, the lower MOSFET is enabled and
the ISL6522B functions as a synchronous buck converter.
TIME
t2
C SS
t 1 = ----------- V OSC MIN
I SS
Soft-Start
During Soft-Start, the ISL6522B controls the regulator in a
standard buck fashion. The lower MOSFET is not enabled
during soft-start. The body diode of the MOSFET or the
external diode, if used, will conduct when the upper MOSFET
is OFF. Once the output has reached regulation, the lower
MOSFET is enabled and the regulator is controlled as a
synchronous buck regulator. This allows the ISL6522B
regulator to start into a pre-biased output.
t1
4V
2V
0V
15A
10A
5A
0A
TIME (20ms/DIV)
FIGURE 4. OVERCURRENT OPERATION
Page 7 of 16
ISL6522B
The overcurrent function protects the converter from a shorted
output by using the upper MOSFETs on-resistance, rDS(ON) to
monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the overcurrent trip level. An internal 200A (typical)
current sink develops a voltage across ROCSET that is in
reference to VIN. When the voltage across the upper MOSFET
(also referenced to VIN) exceeds the voltage across ROCSET,
the overcurrent function initiates a soft-start sequence. The
soft-start function discharges CSS with a 10A current sink and
inhibits PWM operation. The soft-start function recharges CSS,
and PWM operation resumes with the error amplifier clamped
to the SS voltage. Should an overload occur while recharging
CSS, the soft-start function inhibits PWM operation while fully
charging CSS to 4V to complete its cycle. Figure 4 shows this
operation with an overload condition. Note that the inductor
current increases to over 15A during the CSS charging interval
and causes an overcurrent trip. The converter dissipates very
little power with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
The overcurrent function will trip at a peak inductor current
(IPEAK) determined by:
I OCSET R OCSET
I PEAK = -------------------------------------------------r DS ON
where IOCSET is the internal OCSET current source (200A is
typical). The OC trip point varies mainly due to the MOSFETs
rDS(ON) variations. To avoid overcurrent tripping in the normal
operating load range, find the ROCSET resistor from the
equation above with:
The maximum rDS(ON) at the highest junction temperature.
1. The minimum IOCSET from the specification table.
2. Determine I PEAK for I PEAK I OUT MAX + I 2 ,
where I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled Output Inductor Selection.
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
Current Sinking
The ISL6522B incorporates a MOSFET shoot-through
protection method which allows a converter to sink current as
well as source current. Care should be exercised when
designing a converter with the ISL6522B when it is known that
the converter may sink current.
FN9150 Rev 2.00
Aug 10, 2015
When the converter is sinking current, it is behaving as a boost
converter that is regulating its input voltage. This means that
the converter is boosting current into the VIN rail, the voltage
that is being down-converted. If there is nowhere for this
current to go, such as to other distributed loads on the VIN rail,
through a voltage limiting protection device, or other methods,
the capacitance on the VIN bus will absorb the current. This
situation will cause the voltage level of the VIN rail to increase.
If the voltage level of the rail is boosted to a level that exceeds
the maximum voltage rating of the MOSFETs or the input
capacitors, damage may occur to these parts. If the bias
voltage for the ISL6522B comes from the VIN rail, then the
maximum voltage rating of the ISL6522B may be exceeded
and the IC will experience a catastrophic failure and the
converter will no longer be operational. Ensuring that there is a
path for the current to follow other than the capacitance on the
rail will prevent these failure modes.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
Please note that the capacitors CIN and CO each represent
numerous physical capacitors. Locate the ISL6522B within
three inches of the MOSFETs, Q1 and Q2. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6522B must be sized to handle up to 1A peak current.
ISL6522B
UGATE
VIN
Q1
LO
VOUT
PHASE
LGATE
Q2
D2
CIN
CO
LOAD
Overcurrent Protection
PGND
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 6 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the SS PIN and locate the capacitor, CSS close to the SS pin
Page 8 of 16
ISL6522B
because the internal current source is only 10A. Provide local
VCC decoupling between VCC and GND pins. Locate the
capacitor, CBOOT as close as practical to the BOOT and
PHASE pins.
VIN
OSC
DRIVER
PWM
COMPARATOR
-
DRIVER
+
VOSC
D1
CBOOT
Q1
LO
VOUT
+12V
Q2
CO
LOAD
PHASE
SS
VOUT
PHASE
CO
ESR
(PARASITIC)
+VIN
BOOT
ISL6522B
LO
VCC
ZFB
VE/A
-
ZIN
+
REFERENCE
ERROR
AMP
CVCC
CSS
GND
DETAILED COMPENSATION COMPONENTS
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
C1
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
gain and the output filter (LO and CO), with a double pole break
frequency at FLC and a zero at FESR. The DC gain of the
modulator is simply the input voltage (VIN) divided by the peakto-peak oscillator voltage VOSC.
VOUT
ZIN
C3
R2
R3
R1
COMP
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(VOUT) is regulated to the reference voltage level. The error
amplifier (error amp) output (VE/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of VIN at the PHASE
node. The PWM wave is smoothed by the output filter (LO and
CO).
ZFB
C2
FB
+
ISL6522B
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1
F LC = --------------------------------------2 L O C O
1
F ESR = --------------------------------------------2 ESR C O
The compensation network consists of the error amplifier
(internal to the ISL6522B) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide a
closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin is
the difference between the closed loop phase at f0dB and 180
degrees The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1
F Z1 = ---------------------------------2 R 2 C1
1
F P1 = ------------------------------------------------------C1 C2
2 R2 ----------------------
C1 + C2
1
F Z2 = -----------------------------------------------------2 R1 + R3 C3
1
F P2 = ---------------------------------2 R3 C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole
(~75% FLC)
FN9150 Rev 2.00
Aug 10, 2015
Page 9 of 16
ISL6522B
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer
function and plotting the gain.
100
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
60
40
20
20LOG
(R2/R1)
20LOG
(VIN/VOSC)
0
-40
-60
COMPENSATION
GAIN
MODULATOR
GAIN
-20
CLOSED LOOP
GAIN
FLC
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current. The
load transient requirements are a function of the slew rate
(di/dt) and the magnitude of the transient load current. These
requirements are generally met with a mix of capacitors and
careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
FN9150 Rev 2.00
Aug 10, 2015
and slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium-Pro be composed of at least forty (40) 1.0F ceramic
capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with your
capacitor supplier and measure the capacitor’s impedance with
frequency to select a suitable component. In most cases,
multiple electrolytic capacitors of small case size perform better
than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function of
the ripple current. The ripple voltage and current are
approximated by the following equations:
V IN - V OUT V OUT
I = -------------------------------- ---------------Fs x L
V IN
VOUT= I x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6522B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
Page 10 of 16
ISL6522B
The response time to a transient is different for the application
of load and the removal of load. The following equations give
the approximate response time interval for application and
removal of a transient load:
the switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching losses.
The lower switch realizes most of the switching losses when the
converter is sinking current (see the equations below).
L O I TRAN
t RISE = ------------------------------V IN – V OUT
Losses while Sourcing Current
L O I TRAN
t FALL = -----------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application
or removal of load and dependent upon the output voltage
setting. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
2
1
P UPPER = Io r DS ON D + --- Io V IN t SW F S
2
PLOWER = Io2 x rDS(ON) x (1 - D)
Losses while Sinking Current
PUPPER = Io2 x rDS(ON) x D
2
1
P LOWER = Io r DS ON 1 – D + --- Io V IN t SW F S
2
Where: D is the duty cycle = VOUT / VIN ,
tSW is the switching interval, and
FS is the switching frequency.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors
for high frequency decoupling and bulk capacitors to supply the
current needed each time Q1 turns on. Place the small ceramic
capacitors physically close to the MOSFETs and between the
drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum input
voltage and a voltage rating of 1.5 times is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC load
current.
For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6522B requires two N-Channel power MOSFETs.
These should be selected based upon rDS(ON), gate supply
requirements, and thermal management requirements.
These equations assume linear voltage-current transitions and
do not adequately model power loss due the reverse-recovery
of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6522B and do not
heat the MOSFETs. However, large gate-charge increases the
switching interval, tSW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermalresistance specifications. A separate heatsink may be
necessary depending upon MOSFET power, package type,
ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for use
with the ISL6522B. However, logic-level gate MOSFETs can be
used under special circumstances. The input voltage, upper
gate drive level, and the MOSFETs absolute gate-to-source
voltage rating determine whether logic-level MOSFETs are
appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from VCC . The boot capacitor, CBOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of VCC
less the boot diode drop (VD) when the lower MOSFET, Q2
turns on. A logic-level MOSFET can only be used for Q1 if the
MOSFETs absolute gate-to-source voltage rating exceeds the
maximum voltage applied to VCC . For Q2, a logic-level
MOSFET can be used if its absolute gate-to-source voltage
rating exceeds the maximum voltage applied to PVCC.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed
between the two MOSFETs according to duty factor. The
switching losses seen when sourcing current will be different from
FN9150 Rev 2.00
Aug 10, 2015
Page 11 of 16
ISL6522B
+12V
DBOOT
+
VCC
ISL6522B
VD
+12V
+5V OR LESS
+5V OR +12V
-
VCC
BOOT
CBOOT
UGATE
ISL6522B
Q1
PHASE
UGATE
NOTE:
VG-S VCC - VD
LGATE
PGND
PVCC
Q2
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to VCC . This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and +12VDC
for the bias, the gate-to-source voltage of Q1 is 7V. A logiclevel MOSFET is a good choice for Q1 and a logic-level
MOSFET can be used for Q2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to PVCC .
FN9150 Rev 2.00
Aug 10, 2015
NOTE:
VG-S VCC - 5V
+5V
OR +12V
D2
NOTE:
VG-S PVCC
Q1
PHASE
+5V
PVCC OR +12V
+
BOOT
+
LGATE
PGND
Q2
D2
NOTE:
VG-S PVCC
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
Page 12 of 16
ISL6522B
ISL6522B DC-DC Converter Application Circuit
modifications. Detailed information on the circuit, including a
complete bill of materials and circuit board description, can be
found in Application Note AN9722. See Intersil’s home page on
the web: http://www.intersil.com.
Figure 11 shows a DC-DC converter circuit for a
microprocessor application, originally designed to employ the
HIP6006 controller. Given the similarities between the
HIP6006 and ISL6522B controllers, the circuit can be
implemented using the ISL6522B controller without any
12VCC
VIN
C17-18
2x 1µF
1206
C1-3
3x 680µF
RTN
C12
1µF
1206
R7
10K
C19
VCC
6
ENABLE
2 OCSET
MONITOR AND
PROTECTION
SS 3
10 BOOT
RT 1
OSC
U1
ISL6522B
REF
3.01K
PHASE
TP2
8
PHASE
C20
0.1µF
L1
VOUT
Q2
CR2
MBR
340
11 PGND
7
COMP
C14
UGATE
12 LGATE
4
R2
1K
9
13 PVCC
-+
+
++
--
5
FB
R6
Q1
R1
SPARE
C13
0.1µF
CR1
4148
1000pF
14
GND
C6-9
4x 1000µF
RTN
JP1
33pF
C15
R5
0.01µF
15K
COMP
TP1
C16
R3
1K
SPARE
R4
SPARE
Component Selection Notes:
C1-C3 - Three each 680F 25W VDC, Sanyo MV-GX or equivalent.
C6-C9 - Four each 1000F 6.3W VDC, Sanyo MV-GX or equivalent.
L1 - Core: micrometals T50-52B; winding: ten turns of 17AWG.
CR1 - 1N4148 or equivalent.
CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent.
Q1, Q2 - Fairchild MOSFET; RFP25N05
FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT
FN9150 Rev 2.00
Aug 10, 2015
Page 13 of 16
ISL6522B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
August 10, 2015
FN9150.2
CHANGE
Added Rev History beginning with Rev 2.
Added About Intersil Verbiage.
Updated Ordering Information Table on page 2.
Updated M14.15 and L16.5X5B PODs to most recent revisions. Change for both is as follows:
Added land pattern and moved dimensions from table onto drawing.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2004-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9150 Rev 2.00
Aug 10, 2015
Page 14 of 16
ISL6522B
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
FN9150 Rev 2.00
Aug 10, 2015
Page 15 of 16
ISL6522B
Package Outline Drawing
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/08
4X 2.4
5.00
12X 0.80
A
B
13
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
12
5.00
1
3 . 10 ± 0 . 15
9
(4X)
4
0.15
5
8
TOP VIEW
0.10 M C A B
+0.15
16X 0 . 60
-0.10
4 0.33 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
1.00 MAX
C
BASE PLANE
SEATING PLANE
0.08 C
( 4 . 6 TYP )
(
SIDE VIEW
3 . 10 )
( 12X 0 . 80 )
C
( 16X 0 .33 )
( 16 X 0 . 8 )
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN9150 Rev 2.00
Aug 10, 2015
Page 16 of 16
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