DATASHEET
ISL8282M
15A High Efficiency Hybrid Digital Step-Down Power Module
The ISL8282M is a PMBus enabled DC/DC single
channel step-down power supply featuring the
proprietary Renesas R4™ Technology. The module
supports a wide 4.5V to 16.5V input voltage range and a
wide 0.5V to 5V output range capable of delivering up to
15A of continuous current. The ISL8282M achieves up
to 95% conversion efficiency and is optimized for high
power density. Integrated LDOs provide module bias
voltage allowing for single supply operation. The
ISL8282M includes a SMBus/PMBus/I2C interface for
device configuration, telemetry (VIN, VOUT, IOUT, and
temperature), and fault reporting.
The proprietary Renesas R4 control scheme has extremely
fast transient performance, accurately regulated
frequency control, and all internal compensation. An
efficiency enhancing PFM mode greatly improves
light-load efficiency. The ISL8282M’s serial bus allows
for easy R4 loop optimization that results in fast transient
performance across a wide range of applications
including all ceramic output filters.
The ISL8282M has four 8-bit configuration pins that
provide very flexible configuration options (such as
frequency, VOUT, and AV gain) without the need for
built-in NVM memory. As a result, the design flow
closely matches traditional analog modules while still
offering the design flexibility and feature set of a digital
SMBus/PMBus/I2C interface. The ISL8282M features
remote voltage sensing, completely eliminates any
potential difference between remote and local ground,
and improves regulation and protection accuracy. A
precision enable input coordinates the startup of the
ISL8282M with other voltage rails and is especially
useful for power sequencing.
The ISL8282M integrates all power and most passive
components to minimize the external components and
significantly reduce design complexity and board space.
The ISL8282M is available in a low-profile, thermally
enhanced, compact 12mmx11mmx5.3mm fully
encapsulated HDA package.
Applications
FN9365
Rev.1.00
Feb 14, 2019
Features
• Proprietary Renesas R4 Technology
• Linear control loop for optimal transient response
• Variable frequency and duty cycle control during
load transient for fastest possible response
• Inherent voltage feed-forward for wide range
input
• Input voltage range: 4.5V to 16.5V
• Output voltage range: 0.5V to 5V
• ±1.5% load/line/temperature regulation with remote
sense
• Supports all ceramic solutions
• Integrated LDOs for single input rail solution
• SMBus/PMBus/I2C compatible up to 1.25MHz
• 256 boot-up voltage levels with a configuration pin
• Seven switching frequency options from 300kHz to
1MHz
• PFM operation option for improved light-load
efficiency
• Startup into precharged load
• Power-good monitor for soft-start and fault detection
• Comprehensive fault protection for high system
reliability
• Over-temperature protection
• Output overcurrent and short-circuit protection
• Output overvoltage and undervoltage protection
• Open remote sense protection
• Input UVLO and power sequence, fault reset
• Compatible with Renesas PowerNavigator™
software
• Thermally enhanced 12mmx11mmx5.3mm HDA
package
• Servers, telecom, storage, and datacom
Related Literature
• Industrial/ATE and networking equipment
For a full list of related documents, visit our website:
• Graphics cards
• ISL8282M device page
• General purpose power for ASIC, FPGA, DSP, and
memory
FN9365 Rev.1.00
Feb 14, 2019
Page 1 of 51
ISL8282M
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
1.3
1.4
1.5
2.
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
5
7
8
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
2.2
2.3
2.4
3.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.5
4.
Efficiency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Startup and Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Derating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
19
20
21
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Configuring Internal Bias and LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling and Disabling the ISL8282M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming the Resistor Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Starting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot-Up Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitoring and Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGOOD Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus, PMBus, and I2C Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
27
28
35
36
38
38
38
5.
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1
7.2
7.3
7.4
PCB Layout Pattern Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FN9365 Rev.1.00
Feb 14, 2019
47
47
47
48
Page 2 of 51
ISL8282M
8.
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FN9365 Rev.1.00
Feb 14, 2019
Page 3 of 51
ISL8282M
1.
1.1
1. Overview
Overview
Typical Application Circuit
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For VOUT = 3.3V, minimum VIN is 5.5V; for VOUT = 5V, minimum VIN is 8V.
R35: see Table 2 on page 9.
R2 and R3: to program output voltage, see Table 4 on page 25 for typical VOUT.
R10 and R11: to program PFM/PWM mode, temperature compensation, and PMBus address, see Table 5 on page 25 for
typical applications.
• R8 and R9: to program fSW, AV gain, OCP retry/latch off, and ultrasonic PFM enable, see Table 6 on page 26 for typical
applications.
• R5 and R6: to program soft-start ramp rate, RR impedance, and AV gain multiplier (1x or 2x), see Table 7 on page 27 for
typical applications.
• R14: IOUT pull-up resistor. See Table 2 on page 9.
Figure 1. Wide Range Input and Output Application
5.3mm
11mm
12mm
Figure 2. Small Package for High Power Density
FN9365 Rev.1.00
Feb 14, 2019
Page 4 of 51
ISL8282M
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1. Overview
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Ordering Information
Part Number
(Notes 2, 3)
Part Marking
Temp Range (°C)
Tape and Reel
(Units) (Note 1)
Package (RoHS Compliant)
Pkg. Dwg. #
ISL8282MFRZ
ISL8282M
-40 to +125
-
83 Ld 12x11 HDA Module
Y83.12x11
ISL8282MFRZ-T
ISL8282M
-40 to +125
720
83 Ld 12x11 HDA Module
Y83.12x11
ISL8282MFRZ-T1
ISL8282M
-40 to +125
100
83 Ld 12x11 HDA Module
Y83.12x11
ISL8282MEVAL1Z
Evaluation Board
Notes:
1. See TB347 for details about reel specifications.
2. These plastic packaged products are RoHS compliant by EU exemption 7C-I and employ special Pb-free material sets; molding
compounds/die attach materials and NiPdAu plate - e4 termination finish which is compatible with both SnPb and Pbfree soldering
operations. RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL8282M device page. For more information about MSL, see TB363.
FN9365 Rev.1.00
Feb 14, 2019
Page 5 of 51
ISL8282M
1. Overview
Table 1. Key Differences Between Family of Parts
Parameters
ISL8282M
ISL8280M
ISL8212M
ISL8210M
Load Current (A)
15
10
15
10
Minimum VIN (V)
4.5
4.5
4.5
4.5
Maximum VIN (V)
16.5
16.5
16.5
16.5
Minimum VOUT (min) (V)
0.5
0.5
0.5
0.5
Maximum VOUT (V)
5
5
5
5
Peak Efficiency (%)
95.2
95.2
95.2
95.2
POR
Yes
Yes
Yes
Yes
Minimum Switching
Frequency (kHz)
255
255
255
255
Maximum Switching
Frequency (kHz)
1130
1130
1130
1130
Control Type
R4
R4
R4
R4
Sync Capability
No
No
No
No
Load Sharing
No
No
No
No
PMBus
Yes
Yes
No
No
FN9365 Rev.1.00
Feb 14, 2019
Page 6 of 51
ISL8282M
1.4
1. Overview
Pin Configuration
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FN9365 Rev.1.00
Feb 14, 2019
Page 7 of 51
ISL8282M
1.5
1. Overview
Functional Pin Descriptions
Pin Number
Symbol
A5, A6, A7
NC
No connection pads. The pads dissipate the inductor heat and provide good thermal performance.
Do not connect to any other circuits.
A9, A10, A11, A12,
B9, B10, B11, B12
PGND2
Power ground. The pads are connected to the source of the low-side MOSFET inside the module.
F7, F9,
G7, G8, G9,
H7, H8, H9,
J7, J8, J9
VIN
F10, G10,
H10, J10,
K7, K8, K9, K10, K11,
L7, L8, L9, L10, L11
PHASE
Phase node connection. The pads are connected to the junction of the high-side MOSFET’s source,
output filter inductor, low-side MOSFET’s drain, and return path for the UGATE high-side MOSFET
driver.
F12,
G11, G12,
H11, H12,
J11, J12,
K12, L12
PGND1
Power ground. The pads are the sources of the lower MOSFET inside the module and should be
connected to the (-) terminals of the external input capacitors and output capacitors.
K1, K2, K3, K4, K5,
L1, L2, L3, L4, L5
VOUT
Regulated power module output. Apply the output load between VOUT and PGND1.
A1
SCLK
SMBus/PMBus/I2C synchronous clock signal input. A pull-up resistor is required for this application.
A2
VDD
Logic bias supply. Connect the pin externally to the PVCC rail.
A3, A4
EN
B1
Description
Power input. Connect the pads directly to an input rail in the range of 4.5V to 16.5V. Connect the
input ceramic capacitors between VIN and PGND1 as close as possible to the module.
Precision enable input. Pulling EN above the rising threshold voltage initiates the soft-start
sequence. Pulling EN below the failing threshold voltage suspends module operation.
SALERT Output pin for transferring the active low signal driven asynchronously from the module to
SMBus/PMBus. A pull-up resistor is required for this application.
I/O pin for transferring data signals between the SMBus/PMBus/I2C host and the module. A pull-up
resistor is required for this application.
C1
SDA
C4
7VLDO
C5
VIN1
Input voltage pin for the R4 loop (5V) and LDO (7V). Place a high quality low ESR ceramic capacitor
(1.0μF, X7R) in close proximity to the pin.
C6
PVCC
Output of the 5V LDO to bias internal control circuits and MOSFETs drivers of ISL8282M. Place a
high quality low ESR ceramic capacitor (4.7μF, X7R) in close proximity to the pin.
C7
TP1
D1
RGND
Monitors the negative rail of the module output. Connect to ground at the point of regulation.
E1
VSEN
Monitors the positive rail of the module output. Connect to the point of regulation.
E2
PGOOD
Open-drain indicator output. The PGOOD signal is asserted when the output voltage is within
±12.5% of the nominal set output voltage and is deasserted when the output voltage is outside of the
stated range or the EN pin is pulled low.
E3, E4, E5,
F3, F4, F5
SGND
Signal ground pads. The small-signal ground is common to all control circuitry and all voltage levels
are measured with respect to this pin. Tie SGND to a solid low noise GND plane.
F2
CSRTN
Monitors the negative flow of output current for overcurrent protection and telemetry.
F11
TP2
7V LDO used to bias the current sensing amplifier.
Test pad. Leave this pin open.
Test pad. Leave this pin open.
G2
CSEN
Monitors the positive flow of output current for overcurrent protection and telemetry.
G4
IOUT
Output current monitor pin. An internal resistor sets the gain and an internal capacitor provides the
averaging function; an external pull-up resistor to VDD is recommended to calibrate the no load
offset.
G5
PROG3
FN9365 Rev.1.00
Feb 14, 2019
Programming pin for ultrasonic PFM operation, fault behavior, switching frequency, and R4 (AV)
control loop gain.
Page 8 of 51
ISL8282M
1. Overview
Pin Number
Symbol
Description
G6
PROG1
H2
NTC
Input pin for temperature measurement. An NTC thermistor and a decoupling capacitor inside the
module are connected between this pin and SGND. Connect this pin through a resistor (1.54kΩ)to a
VDD pad externally. The voltage at this pin is inversely proportional to the module temperature.
H5
PROG4
Programming pin for modulator (R4) RR impedance and output slew rate during soft-start (SS). This
pin also sets the AV gain multiplier to 1x or 2x and determines the AV gain on PROG3.
H6
PROG2
Programming pin for PWM/PFM mode, temperature compensation, and serial bus
(SMBus/PMBus/I2C) address.
Programming pin for boot-up voltage.
Table 2. ISL8282M Design Guide Matrix of Typical Applications
VOUT (V)
VIN (V)
Frequency
(kHz)
AV Gain
RR (Ω)
TCOMP (°C)
R14 (MΩ)
R35 (Ω)
0.5
5
400
49
200k
5
1.2
0
0.6
0.75
10
2
12
2
15
3
5
400
49
200k
5
10
2
12
2
15
3
5
400
49
200k
5
10
0.9
1
1.2
1.5
1.8
FN9365 Rev.1.00
Feb 14, 2019
1.2
1.2
3
15
open
400
49
200k
5
1.2
10
3
12
open
15
open
5
400
49
200k
5
1.2
10
3
12
open
15
open
5
400
26
200k
5
1.2
10
3
12
open
15
open
5
500
26
200k
5
1.2
10
3
12
open
15
open
5
0
3
12
5
0
500
26
200k
5
1.2
10
3
12
open
15
open
0
0
0
0
0
Page 9 of 51
ISL8282M
1. Overview
Table 2. ISL8282M Design Guide Matrix of Typical Applications (Continued)
VOUT (V)
VIN (V)
Frequency
(kHz)
AV Gain
RR (Ω)
TCOMP (°C)
R14 (MΩ)
R35 (Ω)
2.5
5
600
26
200k
5
1.2
0
10
3
12
open
15
3.3
5.5
open
700
26
200k
5
10
3
12
open
15
5
1.2
8
850
26
200k
5
0
open
121 (Note 4)
0.909
0
10
1.2
12
4.02
15
open
121 (Note 4)
Note:
4. A 121Ω resistor is needed only when OCP behavior is set to Retry. When a 121Ω resistor is connected between VIN and VIN1, the
READ_VIN command in PowerNavigator reads back the VIN1 voltage.
FN9365 Rev.1.00
Feb 14, 2019
Page 10 of 51
ISL8282M
2.
2. Specifications
Specifications
2.1
Absolute Maximum Ratings
Parameter
Minimum
Maximum
Unit
VDD, PVCC, VSEN
-0.3
+7
V
Module Input Voltage, VIN
-0.3
+20
V
Module Input Voltage, VIN1
-0.3
+20
V
7VLDO
-0.3
+7.75
V
Output Voltage, VOUT
-0.3
+5.5
V
BOOT Voltage (VBOOT-GND)
-0.3
+30
V
BOOT to PHASE Voltage (VBOOT-PHASE) (DC)
-0.3
+7
V
BOOT to PHASE Voltage (VBOOT-PHASE) ( UVLO
Bias UVLO
VDD, PVCC, 7VLDO UVLO
Shut down and recover when Bias > UVLO
Startup OVP
Higher than VBOOT. See “Electrical Specifications” on
page 12.
Output OVP
Rising = 116%; Falling = 100%
Latch OFF, reset by VDD or toggling Enable (including
the EN pin and/or OPERATION command based on the
ON_OFF_CONFIG setting)
Output UVP
74% of VOUT, Latch OFF
Short-Circuit and
OCP Protection
Peak load current = 18.8A typical
Latch OFF, reset by VDD or toggling Enable (including
the EN pin and/or OPERATION command based on the
ON_OFF_CONFIG setting), or retry every 9ms; option is
programmable by PROG3 or D3[0]
OTP
Rising = 22.31%VDD (~+136°C)
Falling = 27.79%VDD (~+122°C)
Shut down above +136°C and recover when
temperature drops below +122°C
FN9365 Rev.1.00
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Page 36 of 51
ISL8282M
4. Functional Description
Input UVLO and OTP faults respond to the current state with hysteresis. Output OVP and output UVP faults are
latch events. Output OCP and output short-circuit faults can be latch or retry events depending on the PROG3 or
D3[0] setting. All fault latch events can be reset by VDD cycling, toggling the EN pin, or with the serial bus
OPERATION command based on the ON_OFF_CONFIG setting. The OCP retry event has a hiccup time of 9ms
and the module can be recovered when the fault is removed.
4.7.1
Overvoltage Protection
The Overvoltage Protection (OVP) fault detection circuit triggers when the voltage between VSEN+ and VSEN- is
above the rising overvoltage threshold. When an OVP fault is declared, the module latches off and the PGOOD
pin is asserted low. The fault remains latched and can be reset by VDD cycling, toggling the EN pin, and/or the
serial bus OPERATION command based on the ON_OFF_CONFIG setting.
Although the module latches off in response to an OVP fault, the Low-Side Gate Driver (LGATE) retains the
ability to toggle the low-side MOSFET on and off in response to the output voltage transversing the OVP rising
and falling thresholds. The LGATE turns on the low-side MOSFET to discharge the output voltage, protecting
the load. The LGATE turns off the low-side MOSFET when the sensed output voltage is lower than the falling
overvoltage threshold (typically 100%). If the output voltage rises again, the LGATE turns on the low-side
MOSFET when the output voltage is above the rising overvoltage threshold (typically 120%). This process
protects the load when there is a consistent overvoltage condition.
In addition to normal OVP operation, the startup OVP circuits are enabled to protect against OVP events
5.5ms (typical, worst 6.5ms) after all rails (VDD, PVCC, 7VLDO, VIN) POR and before the end of soft-start
while the OVP level is set higher than VBOOT. See “Electrical Specifications” on page 12.
4.7.2
Undervoltage Protection
The Undervoltage Protection (UVP) fault detection circuit triggers if the output voltage is below the
undervoltage threshold (typically 74% of DAC). When an UVP fault is declared, the module latches off, forcing
the LGATE and High-Side Gate Driver (UGATE) outputs low, and the PGOOD pin is asserted low. The fault
remains latched and can be reset by VDD cycling, toggling the EN pin, and/or with the serial bus OPERATION
command based on the ON_OFF_CONFIG setting.
4.7.3
Overcurrent and Short-Circuit Protection
Inductor DCR sensing is used for current sense and senses current continuously for fast response. The current
sense amplifier uses the CSEN and CSRTN inputs to reproduce a signal proportional to the inductor current, IL.
The reproduced signal is used for current reporting and overcurrent protection.
The Overcurrent Protection (OCP) is triggered when the load current is typically 18.8A. OCP protects inductor
saturation from short-circuit events and provides a more robust power train and system protection. When an
OCP or short-circuit fault is declared, the module latches off, forcing the both the high-side and low-side gate
driver outputs low, or it retries with a hiccup time of 9ms. The fault response is programmable by PROG3 or
D3[0]. However, the latched off event can be reset by VDD cycling, toggling the EN pin, and/or with the serial
bus OPERATION command based on the ON_OFF_CONFIG setting.
4.7.4
Over-Temperature Protection
An NTC inside the module senses the inductor temperature for both over-temperature and current sense
temperature compensation. The NTC is connected to the NTC pin and SGND pad and results in lower NTC pin
voltage at higher temperatures. A comparator with hysteresis compares the NTC pin voltage to the threshold
set. At +136°C (typical), Over-Temperature Protection (OTP) is triggered and the ISL8282M operation is
disabled. When the sensed temperature is around +122.4°C, the ISL8282M resumes normal operation. When an
OTP fault is declared, the module forces the LGATE and UGATE outputs low.
FN9365 Rev.1.00
Feb 14, 2019
Page 37 of 51
ISL8282M
4.8
4. Functional Description
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of supplying regulated voltage. PGOOD is asserted low if
there is a fault condition of a rail’s (VDD, PVCC, 7VLDO, or VIN) UVLO, output Overcurrent (OCP), output
Overvoltage (OVP), output Undervoltage (UVP), or Over-Temperature (OTP). Note: the PGOOD pin is an
undefined impedance with insufficient VDD (typically VOUT_MAX, or VOUT OPEN
SENSE)
Page 42 of 51
ISL8282M
4. Functional Description
Table 12. SMBus, PMBus, and I2C Supported Commands (Continued)
Command
Code
Access
Word
Length
(Byte)
88h[15:0]
R
Two
READ_VIN
Input voltage (N = - 4, Max = 31.9375V)
VIN (V) = HEX2DEC(88 hex data - E000h) x 0.0625V
8Bh[15:0]
R
Two
READ_VOUT
Module output voltage, resolution = 7.8125mV = 2-7
VOUT (V) = HEX2DEC(8B hex data) x 2-7
8Ch[15:0]
R
Two
READ_IOUT
Module output current (N = -3, IMAX = 63.875A)
IOUT (A) = HEX2DEC(8C hex data-E800) x 0.125A when
IOUT pin voltage = 2.5V at 63.875A load.
8Dh[15:0]
R
Two
READ_TEMP
Module temperature
98h[7:0]
R
One
02h
Default Value
Command Name
PMBUS_REVISION
Indicates PMBus revision 1.2
AD[15:0]
Block R
Two
0xD000
AE[15:0]
Block R
Two
0x000A
D0[0:0]
R/W
One
PROG2[7:7]
ENABLE_PFM
PFM OPERATION
0h = PFM Enabled
1h = PFM Disabled (always CCM mode)
D1[1:0]
R/W
One
PROG2[6:5]
TEMP_COMP
Thermal compensation:
0h = +30°C
01h = +15°C
02h = +5°C
03h = OFF
D2[0:0]
R/W
One
PROG3[7:7]
D3[0:0]
R/W
One
PROG3[6:6]
OCP_BEHAVIOR
D4[2:0]
R/W
One
PROG3[2:0]
AV_GAIN
D5{2:0]
R/W
One
PROG4[7:5]
RAMP_RATE
FN9365 Rev.1.00
Feb 14, 2019
IC_DEVICE_ID
Description
ISL8282M device ID
IC_DEVICE_REVISION ISL8282M device revision
ENABLE_ULTRASONIC Ultrasonic PFM enable
0h = 25kHz clamp disabled
1h = 25kHz clamp enabled
Set latch or infinite retry for OCP fault:
0h = Retry every 9ms
01 = Latch-OFF
R4 AV GAIN (PROG4, AV Gain Multiplier = 2x)
0h = 84
1h = 73
2h = 61
3h = 49
4h = 38
5h = 26
6h = 14
7h = 2
R4 AV GAIN (PROG4, AV Gain Multiplier = 1x)
0h = 42
1h = 36.5
2h = 30.5
3h = 29.5
4h = 19
5h = 13
6h = 7
7h = 1
Soft-start rate (mV/µs)
0h = 1.25
1h = 2.5
2h = 5
3h = 10
5h = 0.157
6h = 0.315
7h = 0.625;
Page 43 of 51
ISL8282M
4. Functional Description
Table 12. SMBus, PMBus, and I2C Supported Commands (Continued)
Command
Code
D6[1:0]
Access
Word
Length
(Byte)
Default Value
Command Name
R/W
One
PROG4[4:3]
SET_RR
Description
Sets RR
0h = 200k
01h = 400k
02h = 600k
03h = 800k
DC[7:0]
R
One
READ_PROG1
Reads PROG1
DD{7:0]
R
One
READ_PROG2
Reads PROG2
DE[7:0]
R
One
READ_PROG3
Reads PROG3
DF[7:0]
R
One
READ_PROG4
Reads PROG4
Note: Serial bus communication is valid 5.5ms (typical, worst 6.5ms) after VDD, VIN, 7VLDO, and PVCC above POR. The telemetry
update rate is 108µs.
FN9365 Rev.1.00
Feb 14, 2019
Page 44 of 51
ISL8282M
5.
5. Layout Guidelines
Layout Guidelines
Careful attention to layout requirements is necessary for a successful implementation of the ISL8282M power module.
The ISL8282M switches at a very high frequency. Therefore, the switching times are very short. At these switching
frequencies, even the shortest trace has significant impedance. The peak gate drive current also rises significantly in an
extremely short time. Current transition from one MOSFET to another causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, generate EMI, and increase
MOSFET voltage stress and ringing. Careful component selection and proper PCB layout minimize the magnitude of
these voltage spikes. Use the ISL8282MEVAL1Z as a example and reference for the PCB layout.
The following are layout considerations:
• Renesas recommends using a six-layer PCB board. Use the top and bottom layer to route VIN and VOUT. Use a full
ground plane in the internal layers (underneath the module) with shared SGND and PGND to simplify the layout
design. Use another full ground plane directly above the bottom layer. Use the other internal layers to route the
remote sense, PGOOD, SCL, SDA, and SALERT signals.
• Place the input capacitors and high frequency decoupling ceramic capacitors between VIN and PGND as close to the
module as possible. The loop formed by the input capacitors, VIN, and PGND must be as small as possible to
minimize high frequency noise. Place the output ceramic capacitors close to VOUT. Use a copper plane to connect
the output ceramic capacitors to the load to avoid any parasitic inductances and resistances. An example layout is
illustrated in Figures 50 and 51.
• Use large copper planes for power paths (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
Also, use multiple vias to connect the power planes in different layers.
• Do not oversize the copper planes for the PHASE planes. Because the PHASE planes are subjected to very high
dv/dt, the parasitic capacitor formed between these planes and the surrounding circuitry tends to couple the switching
noise. Ensure that none of the sensitive signal traces are routed close to the PHASE plane.
• Place the PVCC and VIN1 bypass capacitors underneath the PVCC and VIN1 pins and connect their grounds to the
SGND. For the external pin-strap resistor dividers connected to PROG1, PROG2, PROG3, and PROG4, connect the
low side dividers’ ground to the SGND. If a local decoupling capacitor is used to bias these resistor dividers, place
the decoupling capacitor close to the dividers, and connect the capacitor’s ground to the SGND. An example layout is
illustrated in Figure 51.
• Connect remote sensing traces to the regulation point to achieve a tight output voltage regulation. Route the remote
sensing traces in parallel underneath the PGND layer and avoid routing the sensing trace near noisy planes such as
PHASE. Place 2Ω resistors close to VSEN and RGND, respectively, to dampen the noise on the traces.
Figure 50. Layout Example - Top Layer
FN9365 Rev.1.00
Feb 14, 2019
Figure 51. Layout Example - Bottom Layer
Page 45 of 51
ISL8282M
6.
6. Thermal Considerations
Thermal Considerations
Use the experimental power loss and θJA from thermal modeling analysis to evaluate the thermal consideration for the
module. The derating curves are derived from the maximum power allowed while maintaining the temperature below
the maximum junction temperature of +125°C. The derating curves are derived based on tests of the ISL8282M
evaluation board, which is a 6-layer board 3 x 3.4 inches in size with 2oz Cu on all layers and multiple via
interconnects. In the actual application, other heat sources and design margins should be considered.
FN9365 Rev.1.00
Feb 14, 2019
Page 46 of 51
ISL8282M
7.
7. Package Description
Package Description
The structure of the ISL8282M belongs to the High Density Array no-lead package (HDA). The HDA package has
good thermal and electrical conductivity, low weight, and small size and is applicable for surface mounting technology
that is being more readily used in the industry. The ISL8282M contains several types of devices, including resistors,
capacitors, inductors, MOSFETs, and control ICs. The ISL8282M is a copper leadframe-based package with exposed
copper thermal pads that have good electrical and thermal conductivity. The copper leadframe and multicomponent
assembly is overmolded with a polymer mold compound to protect these devices.
The package outline, typical Printed Circuit Board (PCB) layout pattern design, and typical stencil pattern design are
shown in the “Package Outline Drawing” on page 50. The module has a small size of 12mmx11mmx5.3mm.
7.1
PCB Layout Pattern Design
The bottom of the ISL8282M is a leadframe footprint attached to the PCB by a surface mounting process. The PCB
layout pattern is shown in the “Package Outline Drawing” on page 50. The PCB layout pattern is an array of solder
mask defined PCB lands that align with the perimeters of the HDA exposed pads and I/O termination dimensions.
The thermal lands on the PCB layout also feature an array of solder mask defined lands and should match 1:1 with
the package exposed die pad perimeters. The exposed solder mask defined PCB land area should be 50-80% of the
available module I/O area.
7.2
Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias drops down and connects to buried copper plane(s). Place the grid
under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about
1.0 oz. of copper. Although adding more vias (by decreasing via pitch) improves the thermal performance,
increasing the number of vias eventually yields diminishing returns. Use as many vias as practical for the thermal
land size allowed by your board design rules.
7.3
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should have about a 50µm to 75µm (2mil to 3mil) standoff
height. The solder paste stencil design is the first step in developing optimized, reliable solder joints. The stencil
aperture size to solder mask defined PCB land size ratio should typically be 1:1. The aperture width can be reduced
slightly to help prevent solder bridging between adjacent I/O lands. A typical solder stencil pattern is shown in the
“Package Outline Drawing” on page 50. Consider the symmetry of the whole stencil pattern when designing its
pads. A laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. Electropolishing
“smooths” the aperture walls resulting in reduced surface friction and better paste release, which reduces voids.
Using a Trapezoidal Section Aperture (TSA) also promotes paste release and forms a brick-like paste deposit that
assists in firm component placement. A 0.1mm to 0.15mm stencil thickness is recommended for this large pitch
HDA.
FN9365 Rev.1.00
Feb 14, 2019
Page 47 of 51
ISL8282M
7.4
7. Package Description
Reflow Parameters
Due to the low mount height of the HDA, “No-Clean” Type 3 solder paste per ANSI/J-STD-005 is recommended.
A nitrogen purge is also recommended during reflow. A system board reflow profile depends on the thermal mass
of the entire populated board, so it is not practical to define a specific soldering profile just for the HDA. The
profile given in Figure 52 is a guideline that can be adapted for varying manufacturing practices and applications.
300
Peak Temperature ~+245°C;
Typically 60s-150s Above +217°C
Keep Less Than 30s Within 5°C of Peak Temp.
Temperature (°C)
250
200
Slow Ramp (3°C/s Max)
and Soak from +150°C
to +200°C for 60s~180s
150
100
Ramp Rate 1.5°C from +70°C to +90°C
50
0
0
100
150
200
250
300
350
Duration (s)
Figure 52. Typical Reflow Profile
FN9365 Rev.1.00
Feb 14, 2019
Page 48 of 51
ISL8282M
8.
8. Revision History
Revision History
Rev.
Date
1.00
Feb 14, 2019
Updated Title on page 1.
Updated VOUT, SALERT, and SDA pin descriptions on page 8.
Updated Figure 28 label on page 20.
Updated the ENABLE_PFM command description on page 43.
Removed subheading on page 45.
Updated Disclaimer.
0.00
Dec 14, 2018
Initial release.
FN9365 Rev.1.00
Feb 14, 2019
Description
Page 49 of 51
Package Outline Drawing
Y83.12x11
83 I/O 12mmx11mmx5.3mm HDA Module
Rev 0, 3/18
For the most recent package outline drawing, see Y83.12x11.
ISL8282M
FN9365 Rev.1.00
Feb 14, 2019
9.
9. Package Outline Drawing
Page 50 of 51
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