ISL84781IVZ-T

DATASHEET ISL84781 FN6095 Rev 4.00 October 28, 2010 Ultra Low ON-Resistance, Low-Voltage, Single Supply, 8-to-1 Analog Multiplexer The Intersil ISL84781 device contains precision, bidirectional, analog switches configured as an 8-channel multiplexer/demultiplexer. It is designed to operate from a single +1.6V to +3.6V supply. The device has an inhibit pin to simultaneously open all signal paths. ON-resistance is 0.4 with a +3.0V supply and 0.55 with a single +1.8V supply. Each switch can handle rail-to-rail analog signals. The off-leakage current is only 4nA max at +25°C or 40nA max at +85°C with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL84781 is a 8-to-1 multiplexer device that is offered in a 16 Ld TSSOP package, and a 16 Ld thin QFN package. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANCE ISL84781 Configuration 8:1 Mux 3V rON  3V tON/tOFF 16ns/13ns 1.8V rON 0.55 1.8V tON/tOFF 24ns/16ns Packages 16 Ld TSSOP, 16 Ld 3x3 thin QFN Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” • Pin Compatible Replacement for the MAX4781, and MAX4617 • ON-resistance (rON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 • rON Matching Between Channels . . . . . . . . . . . . . . . . 0.12 • rON Flatness Across Signal Range . . . . . . . . . . . . . . .0.056 • Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V • Low Power Consumption (PD). . . . . . . . . . . . . . . . . . 4kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . >1000V Thermal Resistance (Typical, Note 6) JA (°C/W) 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 16 Ld 3x3 Thin QFN Package . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Signals on NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 7), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP MIN (°C) (Notes 8, 11) TYP MAX (Notes 8, 11) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-resistance, rON Full V+ = 2.7V, ICOM = 100mA, VNO = V to V+, (See Figure 5) 0 - V+ V 25 - 0.41 0.75  Full - - 0.8  rON Matching Between Channels, rON V+ = 2.7V, ICOM = 100mA, VNO = Voltage at max rON, (Note 9) 25 - 0.12 0.2  Full - - 0.2  rON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO = V to V+, (Note 10) 25 - 0.056 0.15  Full - - 0.15  NO OFF Leakage Current, INO(OFF) V+ = 3.3V, VCOM = 0.3V, 3V, VNO = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 3.3V, VCOM = VNO = 0.3V, 3V 25 -4 - 4 nA Full -40 - 40 nA 25 -15 - 15 nA Full -70 - 70 nA Full 1.4 - - V DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL V+ = 3.6V, VINH = VADD = 0V or V+ (Note 12) Full - - 0.5 V Full -0.5 - 0.5 µA DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 2.7V, VNO = V, RL = 50, CL = 35pF, (See Figure 1, Note 12) V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 12) V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 12) V+ = 3.3V, VNO = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 12) 25 - 16 25 ns Full - - 27 ns 25 - 14 23 ns Full - - 25 ns 25 - 19 28 ns Full - - 30 ns 25 - 4 - ns Full 1 - - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - -39 - pC Input OFF Capacitance, COFF f = 1MHz, VNO = VCOM = 0V, (See Figure 6) 25 - 65 - pF FN6095 Rev 4.00 October 28, 2010 Page 3 of 12 ISL84781 Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 7), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER COM OFF Capacitance, COFF TEST CONDITIONS f = 1MHz, VNO = VCOM = 0V, (See Figure 6) TEMP MIN (°C) (Notes 8, 11) 25 TYP - 470 MAX (Notes 8, 11) UNITS - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO = VCOM = 0V, (See Figure 6) 25 - 485 - pF OFF-Isolation RL = 50, CL = 35pF, f = 100kHz, (See Figure 4) 25 - 65 - dB Total Harmonic Distortion (THD) f = 20Hz to 20kHz, 0.5VP-P, RL = 32 25 - 0.014 - % Full 1.6 - 3.6 V 25 - - 0.05 µA Full - - 1.2 µA POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off NOTES: 7. VIN = Input voltage to perform proper function. 8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 9. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value. 10. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 12. Limits established by characterization and are not production tested. Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 7), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER TEST CONDITIONS TEMP MIN MAX (°C) (Notes 8, 11) TYP (Notes 8, 11) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-resistance, rON V+ = 1.8V, ICOM = 10.0mA, VNO = 1.0V, (See Figure 5) rON Matching Between Channels, rON) V+ = 1.8V, ICOM = 10.0mA, VNO = 1.0V, (See Figure 5) rON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 10.0mA, VNO = 0V, 0.9V, 1.6V, (See Figure 5) Full 0 - V+ V 25 - 0.55 0.85  Full - - 0.9  25 - 0.1 -  Full - 0.13 -  25 - 0.14 -  Full - 0.16 -  Full 1 - - V DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL Full - - 0.4 V V+ = 1.8V, VINH, VADD = 0V or V+ (Note 12) Full -0.5 - 0.5 A V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 12) 25 - 24 33 ns Full - - 35 ns DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 12) V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 12) 25 - 16 25 ns Full - - 27 ns 25 - 25 34 ns Full - - 36 ns Break-Before-Make Time, tBBM V+ = 1.8V, VNO = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 12) 25 - 9 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0(See Figure 2) 25 - -20 - pC FN6095 Rev 4.00 October 28, 2010 Page 4 of 12 ISL84781 Test Circuits and Waveforms V+ C V+ LOGIC INPUT 50% VNO0 0V NO0 tON NO1-NO7 INH VNO0 SWITCH OUTPUT C tr < 5ns tf < 5ns 90% VOUT 90% LOGIC INPUT VOUT COM GND ADD2-0 CL 35pF RL 50 0V tOFF Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V NOx -----------------------R L + r ON FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS V+ LOGIC INPUT tr < 5ns tf < 5ns 50% V+ C C 0V tTRANS VNO0 NO1-NO7 VOUT VNO0 NO0 90% SWITCH OUTPUT ADD2-0 GND VOUT COM INH CL 35pF RL 50 LOGIC INPUT 10% VNO7 0V tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V NOx R + r L ON FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES V+ C V+ LOGIC INPUT OFF OFF ON RG 0V VOUT COM NOx 0 SWITCH OUTPUT VOUT VOUT VG CHANNEL SELECT ADD2 ADD1 ADD0 GND INH LOGIC INPUT CL 1000pF Q = VOUT x CL FIGURE 2A. Q MEASUREMENT POINTS Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION FN6095 Rev 4.00 October 28, 2010 Page 5 of 12 ISL84781 Test Circuits and Waveforms (Continued) V+ C C tr < 5ns tf < 5ns V+ LOGIC INPUT NO0-NO7 VNOx 0V SWITCH OUTPUT VOUT COM RL 50 ADD2-0 LOGIC INPUT 90% VOUT GND 0V CL 35pF INH tBBM Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME V+ V+ 10nF C rON = V1/100mA SIGNAL GENERATOR NOx NOx ADD2 ADD1 ADD0 COM ANALYZER VNX 0V OR V+ 100mA 0V OR V+ GND 0V OR V+ V1 CHANNEL SELECT ADD2 ADD1 ADD0 COM INH GND CHANNEL SELECT INH RL Off-Isolation is measured between COM and “Off” NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT V+ C NOx 0V OR V+ 1MHz IMPEDANCE ANALYZER ADD2 ADD1 ADD0 COM GND CHANNEL SELECT INH FIGURE 6. CAPACITANCE TEST CIRCUIT FN6095 Rev 4.00 October 28, 2010 Page 6 of 12 ISL84781 Detailed Description Power-Supply Considerations The ISL84781 analog multiplexer offers precise switching capability from a single 1.6V to 3.6V supply with ultra low ON-resistance (0.41) and high speed operation (tON = 16ns, tOFF = 13ns) with +3V supply. The device is especially well-suited for portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.2µW), and low leakage currents (70nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. The ISL84781 construction is typical of most single supply CMOS analog multiplexers, in that it has two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set its analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL84781 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (See Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1k OPTIONAL PROTECTION DIODE V+ LOGIC VNOx VCOM GND OPTIONAL PROTECTION DIODE FIGURE 7. OVERVOLTAGE PROTECTION FN6095 Rev 4.00 October 28, 2010 The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the electrical specification tables and “Typical Performance Curves” beginning on page 8 for details. V+ and GND power the internal logic and level shifters. The level shifters convert the logic levels to switched V+ and GND signals to drive the analog switch gate terminals. These multiplexers cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This device is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (See Figure 12). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50 systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 52MHz (See Figure 16). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off-Isolation is the resistance to this feed-through. Figure 17 details the high Off Isolation provided by these devices. At 100kHz, Off Isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Page 7 of 12 ISL84781 Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog- signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Typical Performance Curves TA = +25°C, Unless Otherwise Specified 0.55 0.75 V+ = 3V ICOM = 100mA ICOM = 100mA 0.70 V+ = 1.65V 0.50 0.65 +85°C 0.55 rON () rON () 0.60 V+ = 1.8V 0.50 0.45 0.35 -40°C V+ = 3V V+ = 3.6V 0 1 +25°C 0.40 0.35 V+ = 2.7V 0.40 0.45 2 3 0.30 4 0 0.5 1.0 VCOM (V) FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 0.70 2.0 2.5 3.0 FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE -10 V+ = 1.8V ICOM = 100mA 0.65 1.5 VCOM (V) -20 -30 0.60 -40 +85°C 0.50 +25°C 0.45 0.40 -60 -70 -80 -90 -40°C -100 0.35 0.30 V+ = 1.8V -50 Q (pC) rON () 0.55 V+ = 3V -110 0 0.5 1.0 1.5 VCOM (V) FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FN6095 Rev 4.00 October 28, 2010 2.0 -120 0 0.5 1.0 1.5 2.0 2.5 VCOM (V) FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE Page 8 of 12 3.0 ISL84781 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 60 1.6 50 1.2 tRANS (ns) VINH AND VINL (V) 1.4 VINH 1.0 VINL 0.8 40 30 +85°C 20 0.6 1.0 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 FIGURE 12. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE -40°C 10 1.0 4.5 +25°C 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5 FIGURE 13. ADDRESS TRANS TIME vs SUPPLY VOLTAGE 25 60 50 tOFF (ns) tON (ns) 20 40 30 +85°C +25°C +85°C +25°C 15 -40°C -40°C 20 10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 1.0 4.5 1.5 2.0 V+ (V) -10 -10 0 20 40 0.1 1 10 FREQUENCY (MHz) GND (QFN Paddle Connection: To Ground or Float) 10 V+ = 3V 20 -20 30 -30 40 -40 50 -50 -60 60 ISOLATION 70 80 -80 90 100 -90 100 -100 1k FIGURE 16. FREQUENCY RESPONSE SUBSTRATE POTENTIAL (POWERED UP): 4.5 80 100 Die Characteristics 4.0 -70 60 RL = 50 VIN = 0.2VP-P to 2VP-P OFF ISOLATION (dB) GAIN PHASE (°) NORMALIZED GAIN (dB) 0 V+ = 3V PHASE 3.5 FIGURE 15. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE FIGURE 14. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE 0 2.5 3.0 V+ (V) 10k 100k 1M 10M FREQUENCY (Hz) 110 100M 500M FIGURE 17. OFF-ISOLATION TRANSISTOR COUNT: 228 PROCESS: Submicron CMOS FN6095 Rev 4.00 October 28, 2010 Page 9 of 12 ISL84781 © Copyright Intersil Americas LLC 2004-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6095 Rev 4.00 October 28, 2010 Page 10 of 12 ISL84781 Package Outline Drawing M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 5/10 A 1 3 5.00 ±0.10 SEE DETAIL "X" 9 16 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 0.20 C B A 1 8 B 0.65 0.09-0.20 END VIEW TOP VIEW H 1.00 REF - 0.05 C 1.20 MAX SEATING PLANE 0.90 +0.15/-0.10 GAUGE PLANE 0.25 +0.05/-0.06 5 0.10 M C B A 0.10 C 0°-8° 0.05 MIN 0.15 MAX SIDE VIEW 0.25 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153. FN6095 Rev 4.00 October 28, 2010 Page 11 of 12 ISL84781 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) ) 2X A L16.3x3A 0.15 C A D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE 9 D/2 MILLIMETERS D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E/2 E1 0.15 C B A2 0 4X B TOP VIEW A 0.70 0.75 0.80 - - - 0.05 - A2 - - 0.80 9 0.30 5, 8 0.20 REF 0.18 A3 SIDE VIEW 9 5 NX b 4X P D 3.00 BSC - 2.75 BSC 9 1.35 - E1 2.75 BSC 9 1.35 1.65 7, 8, 10 - k 0.20 - - - L 0.30 0.40 0.50 8 2 4 3 NX k Ne 1 2 3 6 INDEX AREA E2/2 NX L N e 9  - - 12 9 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. A1 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. SECTION "C-C" C L 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. L e 0.60 2. N is the number of terminals. NX b 10 - 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 8 BOTTOM VIEW C L 3 - NOTES: 9 CORNER OPTION 4X (Nd-1)Xe REF. 4 P Rev. 0 6/04 (Ne-1)Xe REF. E2 7 FN6095 Rev 4.00 October 28, 2010 1.50 0.50 BSC 16 D2 2 N FOR ODD TERMINAL/SIDE 7, 8, 10 N (DATUM A) C C 1.65 3.00 BSC Nd 7 L1 1.50 E 8 4X P 8 9 0.10 M C A B D2 (DATUM B) A1 0.23 D1 e SEATING PLANE NOTES A E2 0.08 C MAX A1 D2 / / 0.10 C C NOMINAL b 9 0.15 C A MIN A3 E 2X 2X SYMBOL L1 10 L e TERMINAL TIP FOR EVEN TERMINAL/SIDE 9. Features and dimensions A2, A3, D1, E1, P &  are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension. 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