DATASHEET
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
FN6320
Rev 3.00
April 18, 2007
High Performance Industry Standard Single-Ended Current Mode PWM Controller
The ISL884xA is a high performance drop-in replacement for
the popular 28C4x and 18C4x PWM controllers suitable for a
wide range of power conversion applications including
boost, flyback, and isolated output configurations. Its fast
signal propagation and output switching characteristics
make this an ideal product for existing and new designs.
Features include 30V operation, low operating current, 90A
start-up current, adjustable operating frequency to 2MHz,
and high peak current drive capability with 20ns rise and fall
times.
Features
• 1A MOSFET gate driver
• 90A start-up current, 125A maximum
• 35ns propagation delay current sense to output
• Fast transient response with peak current mode control
• 30V operation
• Adjustable switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
PART NUMBER
RISING UVLO
MAX. DUTY CYCLE
ISL8840A
7.0
100%
• Trimmed timing capacitor discharge current for accurate
deadtime/maximum duty cycle control
ISL8841A
7.0
50%
• 1.5MHz bandwidth error amplifier
ISL8842A
14.4V
100%
ISL8843A
8.4V
100%
• Tight tolerance voltage reference over line, load and
temperature
ISL8844A
14.4V
50%
• ±3% current limit threshold
ISL8845A
8.4V
50%
• Pb-free plus anneal available and ELV, WEEE, RoHS
Compliant
Pinout
Applications
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
(8 LD SOIC, MSOP)
TOP VIEW
• Telecom and datacom power
COMP 1
8 VREF
• Wireless base station power
• File server power
FB 2
7 VDD
• Industrial power systems
CS 3
6 OUT
• PC power supplies
RTCT 4
5 GND
• Isolated buck and flyback regulators
• Boost regulators
FN6320 Rev 3.00
April 18, 2007
Page 1 of 15
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
Ordering Information (Continued)
Ordering Information
PART
NUMBER*
ISL8840AABZ
(See Note)
PART
MARKING
8840 AABZ
TEMP.
PACKAGE PKG.
RANGE (°C) (Pb-free) DWG. #
-40 to +105 8 Ld SOIC
M8.15
PART
NUMBER*
PART
MARKING
TEMP.
PACKAGE PKG.
RANGE (°C) (Pb-free) DWG. #
ISL8843AMBZ 8843 AMBZ
(See Note)
-55 to +125 8 Ld SOIC
M8.15
ISL8840AAUZ 40AAZ
(See Note)
-40 to +105 8 Ld MSOP M8.118
ISL8843AMUZ 43AMZ
(See Note)
-55 to +125 8 Ld MSOP M8.118
ISL8840AMBZ 8840 AMBZ
(See Note)
-55 to +125 8 Ld SOIC
ISL8844AABZ
(See Note)
-40 to +105 8 Ld SOIC
ISL8840AMUZ 40AMZ
(See Note)
-55 to +125 8 Ld MSOP M8.118
ISL8844AAUZ 44AAZ
(See Note)
-40 to +105 8 Ld MSOP M8.118
ISL8841AABZ
(See Note)
-40 to +105 8 Ld SOIC
ISL8844AMBZ 8844 AMBZ
(See Note)
-55 to +125 8 Ld SOIC
8841 AABZ
M8.15
M8.15
8844 AABZ
M8.15
M8.15
ISL8841AAUZ 41AAZ
(See Note)
-40 to +105 8 Ld MSOP M8.118
ISL8844AMUZ 44AMZ
(See Note)
-55 to +125 8 Ld MSOP M8.118
ISL8841AMBZ 8841 AMBZ
(See Note)
-55 to +125 8 Ld SOIC
ISL8845AABZ
(See Note)
-40 to +105 8 Ld SOIC
ISL8841AMUZ 41AMZ
(See Note)
-55 to +125 8 Ld MSOP M8.118
ISL8845AAUZ 45AAZ
(See Note)
-40 to +105 8 Ld MSOP M8.118
ISL8842AABZ
(See Note)
-40 to +105 8 Ld SOIC
ISL8845AMBZ 8845 AMBZ
(See Note)
-55 to +125 8 Ld SOIC
-55 to +125 8 Ld MSOP M8.118
8842 AABZ
M8.15
M8.15
8845 AABZ
M8.15
M8.15
ISL8842AAUZ 42AAZ
(See Note)
-40 to +105 8 Ld MSOP M8.118
ISL8845AMUZ 45AMZ
(See Note)
ISL8842AMBZ 8842 AMBZ
(See Note)
-55 to +125 8 Ld SOIC
ISL8842AMUZ 42AMZ
(See Note)
-55 to +125 8 Ld MSOP M8.118
ISL8843AABZ
(See Note)
-40 to +105 8 Ld SOIC
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
8843 AABZ
ISL8843AAUZ 43AAZ
(See Note)
FN6320 Rev 3.00
April 18, 2007
M8.15
M8.15
-40 to +105 8 Ld MSOP M8.118
Page 2 of 15
VDD
+
-
VREF
VREF
5.00V
START/STOP
UV COMPARATOR
ENABLE
VDD OK
VREF FAULT
+-
+
2.5V
A
4.65V
4.80V
+-
VREF
UV COMPARATOR
GND
A = 0.5
PWM
COMPARATOR
+-
CS
100mV
2R
+
-
FB
VF TOTAL = 1.15V
ERROR
AMPLIFIER
+
-
1.1V
CLAMP
ONLY
ISL8841A/
ISL8844A/
ISL8845A
R
Q
T
COMP
Q
OUT
S Q
36k
R Q
RESET
DOMINANT
VREF
100k
2.9V
1.0V
ON
150k
OSCILLATOR
COMPARATOR
1. An
under-damped condition may result in current loop instability.
1
Q = ------------------------------------------------ m c 1 – D – 0.5
(EQ. 9)
where D is the percent of on time during a switching cycle.
Setting Q = 1 and solving for Se yields
1
1
S e = S n --- + 0.5 ------------- – 1
1 –D
(EQ. 10)
Gate Drive
The ISL884xA is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole output
of the IC (OUT pin) and the gate of the MOSFET. This small
series resistor also damps any oscillations caused by the
resonant tank of the parasitic inductances in the traces of the
board and the FET’s input capacitance.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale current
feedback signal. For applications where the duty cycle is
greater than 50%, slope compensation is required to prevent
instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback error
signal. Adding the external ramp to the current feedback signal
is the more popular method.
FN6320 Rev 3.00
April 18, 2007
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied by
tON to obtain the voltage change that occurs during tON.
1
1
V e = V n --- + 0.5 ------------- – 1
1 –D
(EQ. 11)
where Vn is the change in the current feedback signal (I)
during the on time and Ve is the voltage that must be added by
the external ramp.
For a flyback converter, Vn can be solved for in terms of input
voltage, current transducer components, and primary
inductance, yielding
D T SW V IN R CS 1
1
V e = ---------------------------------------------------- --- + 0.5 ------------- – 1
1–D
Lp
V
(EQ. 12)
where RCS is the current sense resistor, fsw is the switching
frequency, Lp is the primary inductance, VIN is the minimum
input voltage, and D is the maximum duty cycle.
Page 11 of 15
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
The current sense signal at the end of the ON time for CCM
operation is:
1 – D VO f
N S R CS
sw
V CS = ------------------------ I O + --------------------------------------------
NP
2L s
V
(EQ. 13)
Since the peak current limit threshold is 1.00V, the total current
feedback signal plus the external ramp voltage must sum to
this value when the output load is at the current limit threshold.
V e + V CS = 1
R9
CS
R6
ISL8843
where VCS is the voltage across the current sense resistor, Ls
is the secondary winding inductance, and IO is the output
current at current limit. Equation 13 assumes the voltage drop
across the output rectifier is negligible.
VREF
RTCT
C4
FIGURE 6. SLOPE COMPENSATION
(EQ. 14)
Substituting Equations 12 and 13 into Equation 14 and solving
for RCS yields
1
R CS = ----------------------------------------------------------------------------------------------------------------------------------------------------1
1 – D V O f sw
D f sw V IN --- + 0.5 N s
------------------------------ ------------------ – 1 + ------- I O + --------------------------------------------
1–D
N
Lp
2L s
p
(EQ. 15)
Adding slope compensation is accomplished in the ISL884xA
using an external buffer transistor and the RTCT signal. A
typical application sums the buffered RTCT signal with the
current sense feedback and applies the result to the CS pin as
shown in Figure 6.
Assuming the designer has selected values for the RC filter
(R6 and C4) placed on the CS pin, the value of R9 required to
add the appropriate external ramp can be found by
superposition.
2.05D R 6
V e = ---------------------------R6 + R9
(EQ. 16)
V
The factor of 2.05 in Equation 16 arises from the peak
amplitude of the sawtooth waveform on RTCT minus a
base-emitter junction drop. That voltage multiplied by the
maximum duty cycle is the voltage source for the slope
compensation. Rearranging to solve for R9 yields:
2.05D – V e R 6
R 9 = ---------------------------------------------Ve
(EQ. 17)
The value of RCS determined in Equation 15 must be rescaled
so that the current sense signal presented at the CS pin is that
predicted by Equation 13. The divider created by R6 and R9
makes this necessary.
R6 + R9
R CS = --------------------- R CS
R9
FN6320 Rev 3.00
April 18, 2007
(EQ. 18)
Page 12 of 15
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
Example:
Fault Conditions
VIN = 12V
VO = 48V
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds 4.80V,
the Fault condition clears, and OUT is enabled.
Ls = 800H
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. VDD should be
bypassed directly to GND with good high frequency capacitors.
Ns/Np = 10
Lp = 8.0H
IO = 200mA
Switching Frequency, fsw = 200kHz
References
Duty Cycle, D = 28.6%
R6 = 499
Solve for the current sense resistor, RCS, using Equation 15.
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power Electronics,
Vol. 6, No. 2, April 1991.
RCS = 295m
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 12.
Ve = 92.4mV
Using Equation 17, solve for the summing resistor, R9, from CT
to CS.
R9 = 2.67k
Determine the new value of RCS (R’CS) using Equation 18.
R’CS = 350m
Additional slope compensation may be considered for design
margin. The above discussion determines the minimum
external ramp that is required. The buffer transistor used to
create the external ramp from RTCT should have a sufficiently
high gain (>200) so as to minimize the required base current.
Whatever base current is required reduces the charging
current into RTCT and will reduce the oscillator frequency.
© Copyright Intersil Americas LLC 2005-2007. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6320 Rev 3.00
April 18, 2007
Page 13 of 15
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
8
0°
8
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN6320 Rev 3.00
April 18, 2007
Page 14 of 15
ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X
A2
A1
b
-H-
0.10 (0.004)
L1
SEATING
PLANE
C
D
0.20 (0.008)
C
a
CL
E1
0.20 (0.008)
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
-B-
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
SIDE VIEW
MIN
A
L1
-A-
e
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
FN6320 Rev 3.00
April 18, 2007
Page 15 of 15
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