ISL9500CVZ

ISL9500 ® Data Sheet December 2, 2005 Precision Multi-Phase Buck PWM Controller FN9248.0 Features The ISL9500 multi-phase Buck PWM control IC, with integrated half bridge gate drivers, provides a precision voltage regulation system for microprocessors in notebook computers. Two-phase operation eases the thermal management issues and load demand of high performance processors. This control IC also features both input voltage feed-forward and average current mode control for excellent dynamic response, “Loss-less” current sensing using MOSFET rDS(ON) and user selectable switching frequencies from 250kHz to 1MHz per phase. The ISL9500 includes a 6-bit digital-to-analog converter (DAC) that dynamically adjusts the CORE PWM output voltage. The ISL9500 also has logic inputs to select Active, Deep Sleep and Deeper Sleep modes of operation. A precision reference, remote sensing and proprietary architecture, with integrated, processor-mode, compensated “Droop”, provide excellent static and dynamic CORE voltage regulation. To improve efficiency at light loading, the ISL9500 can be configured to run in single phase PWM in Active, Deep or Deeper Sleep modes of operation. Also, in Deep and Deeper sleep modes the ISL9500 will operate in diode emulation. Another feature of this IC controller is the PGOOD monitor circuit that is held low until CORE voltage increases, during its soft-start sequence, to within 12% of the “Boot” voltage. This PGOOD signal is masked during VID changes. Output overcurrent, overvoltage and undervoltage are monitored and result in the converter latching off and PGOOD signal being held low. The overvoltage and undervoltage thresholds are 112% and 84% of the VID, Deep or Deeper Sleep setpoint, respectively. Overcurrent protection features a 32 cycle overcurrent shutdown. PGOOD, overvoltage, undervoltage and overcurrent provide monitoring and protection for the microprocessor and power system. The ISL9500 IC is available in a 38 lead TSSOP. • Diode Emulation Functionality in Deep and Deeper Sleep Modes for Improved Light Load Efficiency • Single and/or Two-phase Power Conversion • “Loss-less” Current sensing for Improved Efficiency and Reduced Board Area - Optional Discrete Precision Current Sense Resistor • Internal Gate-Drive and Boot-Strap Diodes • Precision CORE Voltage Regulation - 0.8% System Accuracy Over Temperature • 6-Bit Microprocessor Voltage Identification Input • Programmable “Droop” and CORE Voltage Slew Rate • Direct Interface with System Logic for Deep and Deeper Sleep modes of operation • Easily Programmable Voltage Setpoints for Initial “Boot”, Deep Sleep and Deeper Sleep Modes • Excellent Dynamic Response - Combined Voltage Feed-Forward and Average Current Mode Control • Overvoltage, Undervoltage and Overcurrent Protection • Power-Good Output with Internal Blanking during VID and Mode Changes • User programmable Switching Frequency of 250kHz 1MHz • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER PART MARKING TEMP RANGE (°C) PACKAGE PKG. DWG. # 38 Ld TSSOP (Pb-free) M38.173 38 Ld TSSOP ISL9500CVZ-T ISL9500CVZ -10 to 85 Tape and Reel (See Note) (Pb-free) M38.173 ISL9500CVZ (See Note) ISL9500CVZ -10 to 85 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL9500 Pinout ISL9500 (38 LD TSSOP) TOP VIEW VDD 1 38 VBAT DACOUT 2 37 ISEN1 36 PHASE1 DSV 3 35 UG1 FSET 4 PWRCH 5 34 BOOT1 EN 6 33 VSSP1 DRSEN 7 32 LG1 DSEN# 8 31 VDDP VID0 9 30 LG2 VID1 10 29 VSSP2 VID2 11 28 BOOT2 VID3 12 27 UG2 VID4 13 26 PHASE2 VID5 14 25 ISEN2 PGOOD 15 24 VSEN EA+ 16 23 DRSV 22 STV COMP 17 21 OCSET FB 18 20 VSS SOFT 19 2 FN9248.0 December 2, 2005 ISL9500 Absolute Voltage Ratings Thermal Information Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . -0.3-+7V Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V Boot1, 2 and UGATE1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V Phase1, 2 and ISEN1, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V Boot1, 2 with Respect to Phase1, 2. . . . . . . . . . . . . . . . . . . . . +6.5V UGATE1,2 . . . . . . . . . . . . . . .(Phase1, 2 - 0.3V) to (Boot1,2 + 0.3V) All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V) Thermal Resistance (Typical, Note 1) θJA (°C/W) TSSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . . 72 Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Recommended Operating Conditions Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 85°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 125°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. Electrical Specifications VDD = 5V, TA = -10° to 85°C, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS EN = 3.3V, DSEN# = 0, DRSEN = 0, PWRCH = 0 - 1.4 - mA EN = 0V - 1 - µA VDD Rising 4.35 4.45 4.5 V VDD Falling 4.05 4.20 4.40 V Percent system deviation from programmed VID Codes @ 1.356 -0.8 - 0.8 % - - 0.3 V 0.7 - - V Maximum Output Voltage (VID = 000000) - 1.708 - V Minimum Output Voltage (VID = 111111) - 0.70 - V INPUT POWER SUPPLY Input Supply Current, I(VDD) POR (Power-On Reset) Threshold REFERENCE AND DAC System Accuracy DAC (VID0 - VID5) Input Low Voltage DAC Programming Input Low Threshold Voltage DAC (VID0 - VID5) Input High Voltage DAC Programming Input High Threshold Voltage CHANNEL GENERATOR Frequency, FSW RFset = 243K, ±1% 225 250 275 kHz Adjustment Range Guaranteed by Design 0.25 - 1.0 MHz - 100 - dB ERROR AMPLIFIER DC Gain Gain-Bandwidth Product CL = 20pF - 18 - MHz Slew Rate CL = 20pF - 4.0 - V/µs - 32 - µA - 64 - µA - 31 - µA 27 28.5 30 µA - 1 1.5 Ω ISEN Full Scale Input Current Overcurrent Threshold ROCSET = 124K Soft-Start Current Droop Current GATE DRIVER UGATE Source Resistance 500mA Source Current 3 FN9248.0 December 2, 2005 ISL9500 Electrical Specifications VDD = 5V, TA = -10° to 85°C, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS UGATE Source Current VUGATE-PHASE = 2.5V - 2 - A UGATE Sink Resistance 500mA Sink Current - 1 1.5 Ω UGATE Sink Current VUGATE-PHASE = 2.5V - 2 - A LGATE Source Resistance 500mA Source Current - 1 1.5 Ω LGATE Source Current VLGATE = 2.5V - 2 - A LGATE Sink Resistance 500mA Sink Current - 0.5 0.8 Ω LGATE Sink Current VLGATE = 2.5V - 4 - A 0.58 0.68 0.76 V 2.43 - - mA 56 63 82 Ω BOOTSTRAP DIODE Forward Voltage VDDP = 5V, Forward Bias Current = 10mA POWER GOOD MONITOR PGOOD Sense Current PGOOD Pull Down MOSFET rDS(ON) (See Figure 10) Undervoltage Threshold (Vsen/Vref) VSEN Rising - 85.0 - % Undervoltage Threshold (Vsen/Vref) VSEN Falling - 84.0 - % PGOOD Low Output Voltage IPGOOD = 4mA - 0.26 0.4 V EN, DSEN#, DRSEN Low - - 1 V EN, DSEN#, DRSEN High 2 - - V - 112.0 - % LOGIC THRESHOLD PROTECTION Overvoltage Threshold (Vsen/Vref) VSEN Rising DELAY TIME Delay Time from LGATE Falling to UGATE Rising VDDP = 5V, BOOT to PHASE = 5V, UGATE – PHASE = 1V, LGATE = 1V 10 18 30 ns Delay Time from UGATE Falling to LGATE Rising VDDP = 5V, BOOT to PHASE = 5V, UGATE – PHASE = 1V, LGATE = 1V 10 18 30 ns 4 FN9248.0 December 2, 2005 ISL9500 Functional Pin Description VDD - This pin is used to connect +5V to the IC to supply all power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. DACOUT - This pin provides access to the output of the Digital-to-Analog converter. DSV - The voltage on this pin provides the set point for output voltage during Deep Sleep mode of operation. FSET - A resistor from this pin to ground programs the switching frequency. PWRCH - This pin selects the number of power channels. A HIGH logic level on this pin enables 2 channel operation, and a LOW logic signal enables single channel operation. EN - This pin is connected to the system signal VR_ON and provides the enable/disable function for the PWM controller. DRSEN - This pin enables Deeper Sleep mode of operation when a logic HIGH is detected on this pin. DSEN# - This pin enables Deep Sleep mode of operation when a logic LOW signal is detected on this pin. VID0, VID1, VID2, VID3, VID4, VID5 - These pins are used as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0 is the least significant bit and VID5 is the most significant bit. The VID step size is 16mV. PHASE1, PHASE2 - These pins are connected to the phase nodes of channels 1 and 2, respectively. UG1, UG2 - These pins are the gate-drive outputs to the high side MOSFETs for channels 1 and 2, respectively. BOOT1, BOOT2 - These pins are connected to the bootstrap capacitors, for upper gate-drive, for channels 1 and 2, respectively. VSSP1, VSSP2 - These pins are connected to the power ground of channels 1 and 2, respectively. LG1, LG2 - These pins are the gate-drive outputs to the low side MOSFETs for channels 1 and 2, respectively. VDDP - This pin provides a low-ESR bypass connection to the internal gate drivers for the +5V source. VSEN - This pin is used for remote sensing of the microprocessor CORE voltage. DRSV - The voltage on this pin provides the set point for output voltage during Deeper Sleep mode of operation. OCSET - A resistor from this pin to ground sets the overcurrent protection threshold. The current from this pin should be between 10µA and 25µA (70kΩ - 175kΩ equivalent) pull-down resistance. STV - The voltage on this pin sets the initial start-up or “Boot” voltage. VSS - This pin provides connection for signal ground. PGOOD - This pin is used as an input and an output, and is tied to the Vccp and Vcc_mch PGOOD signals. During startup, this pin is recognized as an input and prevents further slewing of the output voltage from the “Boot” level until PGOOD from Vccp and Vcc_mch is enabled High. After start-up, this pin has an open drain output used to indicate the status of the CORE output voltage. This pin is pulled low when the system output is outside of the regulation limits. PGOOD includes a timer for power-on delay. EA+ - This pin is connected to the non-inverting input of the error amplifier and is used for setting the “Droop” voltage. COMP - This pin provides connection to the error amplifier output. FB - This pin is connected to the inverting input of the error amplifier. SOFT - This pin programs the slew rate of VID changes, Deep Sleep and Deeper Sleep transitions and soft-start after initializing. This pin is connected to ground via a capacitor, and to EA+ through an external “Droop” resistor. VBAT - Voltage on this pin provides feed-forward battery information which adjusts the oscillator ramp amplitude. ISEN1, ISEN2 - These pins are used as current sense inputs from the individual converter channel phase nodes. 5 FN9248.0 December 2, 2005 ISL9500 Block Diagram VSEN PGOOD VDD EN 1.3V + POWER-ON - RESET (POR) + CONTROL AND FAULT LOGIC OVP - VBAT CLOCK AND SAWTOOTH GENERATOR 1.75V FS HIGH-IMPEDANCE STATE + 112% RISING 102% FALLING 88% RISING 84% FALLING + + PWM1 PWM - - HIGH-IMPEDANCE STATE UV + PWRCH + 32 COUNT CLOCK CYCLE PWM2 PWM - BOOT1 VDDP UG1 DACOUT VSOFT SOFT PWM1 SOFTSTART PHASE LOGIC PHASE1 VDDP EA+ LG1 VID0 PWM2 VID1 VID2 VID3 VSSP1 PHASE LOGIC VDDP + VID D/A BOOT2 E/A - VID4 UG2 CHANNEL CURRENT BALANCE VID5 PWRCH PHASE2 COMP VDDP FB 1.75V + OCSET IDROOP + DSV MUX DRSV VCORE VSSP2 1 2N IOCSET STV LG2 0.435 OC -2µA SAMPLE & HOLD 8µA CHANNEL CURRENT SENSE 32 COUNT CLOCK CYCLE REF ISEN2 VSS DSEN# DRSEN 6 ISEN1 PWRCH FN9248.0 December 2, 2005 ISL9500 Typical Application - 2-Phase Converter Figure 1 shows a 2-Phase Synchronous Buck Converter circuit used to provide “CORE” voltage regulation. The ISL9500 PWM controller can be configured for two or one channel operation, and the ISL9500 can change the number of power channels in operation, dynamically. The number of channels of operation can be changed through the PWRCH pin. The ISL9500 can be configured for two +5VDC +5VDC channel operation in “Active” mode and one channel operation in “Deep” and “Deeper Sleep” modes through logic connections to the PWRCH pin. The following configuration uses two channel operation in “Active” mode and one channel operation in “Deep” and “Deeper Sleep” modes. The circuit shows pin connections for the ISL9500 PWM controller in the 38 lead TSSOP package. Vbattery VDD VBAT DACOUT ISEN1 DSV PHASE1 FSET UG1 PWRCH BOOT1 EN VSSP1 DRSEN LG1 DSEN# VDDP VID0 ISL9500 LG2 VID1 TSSOP VSSP2 VID2 BOOT2 VID3 UG2 VID4 PHASE2 VID5 ISEN2 PGOOD VSEN EA+ DRSV COMP STV FB OCSET VSS SOFT VID +Vcc_core FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR ISL9500 MULTI-PHASE PWM CONTROLLER 7 FN9248.0 December 2, 2005 ISL9500 VID Capture VID Code 10µs -12% VCC-CORE t2 t1 PGOOD PGOOD Vccp / Vcc_mch 3ms to 12ms Vcc_core FIGURE 2. TIMING DIAGRAM SHOWING VR_ON, VCC_CORE AND PGOOD FOR VCC_CORE, VCCP AND VCC_MCH Operation Soft-Start Interval Initialization Once the +5VDC supply voltage, when connected to the ISL9500 VDD pin, reaches the Power-On Reset (POR) rising threshold, the PWM drive signals are held in “highimpedance state” or high impedance mode. This results in both high and low side MOSFETs being held low. Once the supply voltage exceeds the POR rising threshold, the controller will respond to a logic level high on the EN pin and initiate the soft-start interval. If the supply voltage drops below the POR falling threshold, POR shutdown is triggered and the PWM signals are again driven to “high-impedance state”. The system signal, VR_ON is directly connected to the EN pin of the ISL9500. Once the voltage on the EN pin rises above 2.0V, the chip is enabled and soft-start begins. The EN pin of the ISL9500 is also used to reset the ISL9500, for cases when an undervoltage or overcurrent fault condition has latched the IC off. A toggling of the state of this pin to a level below 1.0V will re-enable the IC. For the case of an overvoltage fault, the VDD pin must be reset. During start-up, the ISL9500 regulates to the voltage on the STV pin. This is referred to as the “Boot” voltage and is labelled VBOOT in Figure 2. Once power good signals are received from the Vccp and Vcc_mch regulators, the ISL9500 will capture the VID code and regulate to this command voltage within 3ms to 12ms. The PGOOD pin of the ISL9500 is both an input and an output and is further described in the “Fault Protection” section of this document. 8 Once VDD rises above the POR rising threshold and the EN pin voltage is above the threshold of 2.0V, a soft-start interval is initiated. Refer to Figure 2 and Figure 3. The voltage on the EA+ pin is the reference voltage for the regulator. The voltage on the EA+ pin is equal to the voltage on the SOFT pin minus the “Droop” resistor voltage, VDROOP. During start-up, when the voltage on SOFT is less than the “Boot” voltage VBOOT, a small 30µA current source, I1, is used to slowly ramp up the voltage on the softstart capacitor CSOFT. This slowly ramps up the reference voltage for the controller, and therefore, controls the slew rate of the output voltage. The STV pin is externally programmable and sets the start-up, or “Boot” voltage, VBOOT. The programming of this voltage level is explained in the “STV, DSV and DRSV” section of this document. The ISL9500 PGOOD pin is both an input and an output. The system signal power good signal is connected to power good signals from the Vccp and Vcc_mch supplies. The Intersil ISL6227, Dual Voltage Regulator, is an ideal choice for the Vccp and Vcc_mch supplies. Once the output voltage is within the “Boot” level regulation limits and a logic high PGOOD signal from the Vccp and Vccp_mch regulators is received, the ISL9500 is enabled to capture the VID code and regulate to that command voltage. Refer to Figure 2 and Figure 3. A second current source, I2, is added to I1, after the initial start-up transition. I2 is approximately 100µA, and raises the total SOFT pin sinking and sourcing current to 130µA. This increased current is used to increase the slew rate of the reference. FN9248.0 December 2, 2005 ISL9500 250 I1 FSET RESISTOR VALUE (kΩ) ISL9500 I2 ERROR AMPLIFIER I DROOP + SOFT EA+ R DROOP + V DROOP 200 150 100 50 0 C SOFT 250 500 750 1000 CHANNEL SWITCHING FREQUENCY (Fsw) FIGURE 3. SOFT-START TRACKING CIRCUITRY SHOWING INTERNAL CURRENT SOURCES AND "DROOP" FOR ACTIVE, DEEP AND DEEPER SLEEP MODES OF OPERATION The “Droop” current source, IDROOP, is proportional to load current. This current source is used to reduce the reference voltage on EA+ by the voltage drop across the “Droop” resistor. A more in-depth explanation of “Droop”, and the sizing of this resistor, can be found in the “Droop Compensation” section of this document. The choice of value for soft-start capacitor is determined by the maximum slew rate required for the application. An example calculation is shown below. Using the combined I1 and I2 current sources on the SOFT pin as 130µA, and the worst case slew rate of (10mV/µs), the SOFT capacitor is calculated as follows: I 1µs CSOFT = SOURCE = 130µA × = 0.013µF ≈ 0.012µF SlewRate 10mV (EQ. 1) Gate-Drive Signals The ISL9500 provides internal gate-drive for a two channel, synchronous buck, core regulator. During two channel mode of operation, the PWM drive signals are switched 180° out of phase to reduce ripple current delivered from the DC rail and to the load. The ISL9500 was designed with a 4A, low-side gate current sink ability, and a 2A low-side gate current source ability, to efficiently drive the latest, high-performance MOSFETs. This feature will provide the system designer with flexibility in MOSFET selection, as well as optimum efficiency during Active mode of operation. FIGURE 4. CHANNEL SWITCHING FREQUENCY vs RFSET PWRCH pin A HIGH logic level on this pin enables two channel operation and a LOW logic signal enables single channel operation. By tying this pin to the DSEN# pin, single channel operation will be invoked during the light loading of both Deep and Deeper Sleep. If single channel operation is desired only during Deeper Sleep, the inversion of DRSEN can be connected to this pin. The aggressive gate-drive capability and diode emulation of ISL9500, coupled with the single channel operation feature results in superior efficiency performance over both light and heavy loads. Frequency Setting Both channel switching frequencies are set up by a resistor from the FSET pin to ground. The choice of FSET resistance for a desired switching frequency can be approximated using Figure 4. The switching frequency is designed to operate between 250kHz and 1MHz per phase. CORE Voltage Programming The voltage identification pins (VID0, VID1, VID2, VID3, VID4 and VID5) set the DAC output voltage. These pins do not have internal pull-up or pull-down capability. These pins will recognize 1.0V, 3.3V or 5.0V CMOS logic. The IC responds to VID code changes as shown in Figure 5. PGOOD is masked between these transitions. Active, Deep Sleep and Deeper Sleep Modes The ISL9500 multi-phase controller can operate in Active, Deep Sleep, and Deeper Sleep Modes. After initial start-up, a logic high signal on DSEN# and a logic low signal on DRSEN signals the ISL9500 to operate in Active mode. Refer to Table 1. This mode will recognize VID code changes and regulate the output voltage to these command voltages. 9 FN9248.0 December 2, 2005 ISL9500 TABLE 1. OUTPUT VOLTAGE AS A FUNCTION OF DSEN# AND DRSEN LOGIC STATES DSEN# STP_CPU# DRSEN DPRSLPVR MODE OF OPERATION OUTPUT VOLTAGE 1 0 Active VID 0 0 Deep Sleep DSV 0 1 Deeper Sleep DRSV 1 1 Deeper Sleep DRSV CURRENT VID CODE VID[0..5] NEW VID CODE