DATASHEET
KAD5512HP
FN6808
Rev 4.00
May 31, 2016
High Performance 12-Bit, 250/210/170/125MSPS ADC
Features
The KAD5512HP is the high performance member of the
KAD5512 family of 12-bit analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates of
up to 250MSPS. The KAD5512HP is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS.
• Pin-compatible with the KAD5512P Family, offering 2.2dB
higher SNR
• Programmable gain, offset and skew control
• 950MHz analog input bandwidth
• 60fs Clock jitter
A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
• Over-range indicator
• Selectable clock divider: ÷1, ÷2 or ÷4
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512HP is available in 72 and 48 Ld QFN
packages with an exposed paddle. Operating from a 1.8V
supply, performance is specified across the full industrial
temperature range (-40°C to +85°C).
• Clock phase selection
Key Specifications
• Programmable built-in test patterns
• SNR = 68.2dBFS for fIN = 105MHz (-1dBFS)
• Pb-free (RoHS compliant)
• SFDR = 81.1dBc for fIN = 105MHz (-1dBFS)
Applications
• Nap and sleep modes
• Two’s complement, gray code or binary data format
• DDR LVDS-compatible or LVCMOS outputs
• Single-supply 1.8V operation
• Power Consumption
- 429/345mW at 250/125MSPS (SDR Mode)
- 390/309mW at 250/125MSPS (DDR Mode)
• Power Amplifier linearization
• Radar and satellite antenna array processing
• Broadband communications
• High-performance data acquisition
• Communications test equipment
CLKP
OVDD
AVDD
CLKDIV
• WiMAX and microwave receivers
CLKOUTP
CLOCK
GENERATION
CLKN
CLKOUTN
D[11:0]P
12-BIT
250 MSPS
ADC
VINN
VCM
AVSS
NAPSLP
1.25V
+
–
SPI
CONTROL
D[11:0]N
DIGITAL
ERROR
CORRECTION
ORP
ORN
LVDS/CMOS
DRIVERS
CSB
SCLK
SDIO
SDO
SHA
OUTFMT
OUTMODE
OVSS
VINP
FIGURE 1. BLOCK DIAGRAM
FN6808 Rev 4.00
May 31, 2016
Page 1 of 34
KAD5512HP
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions - 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration - 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Descriptions - 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration - 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User-Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
19
20
20
20
20
20
20
21
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
24
24
24
25
26
27
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
72 Ld/48 Ld Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
30
30
30
30
30
30
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
L48.7x7E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
L72.10x10D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN6808 Rev 4.00
May 31, 2016
Page 2 of 34
KAD5512HP
Ordering Information
PART NUMBER
(Note 3)
PART MARKING
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
KAD5512HP-25Q72 (Note 1)
KAD5512HP-25 Q72EP-I
250
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512HP-21Q72 (Note 1)
KAD5512HP-21 Q72EP-I
210
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512HP-17Q72 (Note 1)
KAD5512HP-17 Q72EP-I
170
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512HP-12Q72 (Note 1)
KAD5512HP-12 Q72EP-I
125
-40 to +85
72 Ld QFN
L72.10x10D
KAD5512HP-25Q48 (Note 2)
KAD5512HP-25 Q48EP-I
250
-40 to +85
48 Ld QFN
L48.7x7E
KAD5512HP-21Q48 (Note 2)
KAD5512HP-21 Q48EP-I
210
-40 to +85
48 Ld QFN
L48.7x7E
KAD5512HP-17Q48 (Note 2)
KAD5512HP-17 Q48EP-I
170
-40 to +85
48 Ld QFN
L48.7x7E
KAD5512HP-12Q48 (Note 2)
KAD5512HP-12 Q48EP-I
125
-40 to +85
48 Ld QFN
L48.7x7E
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for KAD5512HP-12, KAD5512HP-17, KAD5512HP-21, KAD5512HP-25.
For more information on MSL, please see tech brief TB363.
TABLE 1. PIN-COMPATIBLE FAMILY
RESOLUTION
SPEED
(MSPS)
KAD5514P-25
14
250
KAD5514P-21
14
210
KAD5514P-17
14
170
KAD5514P-12
14
125
KAD5512P-50
12
500
KAD5512P-25, KAD5512HP-25
12
250
KAD5512P-21, KAD5512HP-21
12
210
KAD5512P-17, KAD5512HP-17
12
170
KAD5512P-12, KAD5512HP-12
12
125
KAD5510P-50
10
500
MODEL
FN6808 Rev 4.00
May 31, 2016
Page 3 of 34
KAD5512HP
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld QFN (Note 4). . . . . . . . . . . . . . . . . . . .
25
72 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . . .
24
0.8
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = maximum conversion rate (per speed grade).
PARAMETER
SYMBOL
TEST
CONDITIONS
KAD5512HP-25
(Note 6)
KAD5512HP-21
(Note 6)
KAD5512HP-17
(Note 6)
KAD5512HP-12
(Note 6)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
1.40
1.47
1.54
1.40
1.47
1.54
1.40
1.47
1.54
1.40
1.47
1.54
VP-P
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
VFS
Differential
Input Resistance
RIN
Differential
500
500
500
500
Ω
Input Capacitance
CIN
Differential
2.6
2.6
2.6
2.6
pF
Full-Scale Range
Temperature Drift
AVTC
Full Temperature
90
90
90
90
ppm/
°C
Input Offset Voltage
VOS
Gain Error
-10
±2
10
-10
±2
10
-10
±2
10
-10
±2
10
mV
EG
±2
±2
±2
±2
%
VCM
0.535
0.535
0.535
0.535
V
Inputs
Common-Mode
Voltage
0.9
0.9
0.9
0.9
V
CLKP, CLKN Input
Swing
1.8
1.8
1.8
1.8
V
Common-Mode
Output Voltage
Clock Inputs
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
170
190
157
176
145
163
129
147
mA
1.8V Digital Supply
Current (SDR)
(Note 7)
IOVDD
68
76
66
74
64
72
62
70
mA
FN6808 Rev 4.00
May 31, 2016
3mA LVDS
Page 4 of 34
KAD5512HP
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
KAD5512HP-25
(Note 6)
MIN
TYP
MAX
KAD5512HP-21
(Note 6)
MIN
TYP
MAX
KAD5512HP-17
(Note 6)
MIN
TYP
MAX
KAD5512HP-12
(Note 6)
MIN
TYP
MAX
UNIT
1.8V Digital Supply
Current (DDR)
(Note 7)
IOVDD
3mA LVDS
46
44
43
42
mA
Power Supply
Rejection Ratio
PSRR
30MHz, 200mVP-P
signal on AVDD
-36
-36
-36
-36
dB
Total Power Dissipation
Normal Mode (SDR)
PD
3mA LVDS
429
Normal Mode (DDR)
PD
3mA LVDS
390
Nap Mode
PD
Sleep Mode
PD
463
402
433
378
363
406
345
339
376
mW
309
mW
148
170.2
142
164.2
136
158.2
129
150.2
mW
CSB at logic high
2
6
2
6
2
6
2
6
mW
Nap Mode Wake-up
Time (Note 8)
Sample clock
running
1
1
1
1
µs
Sleep Mode Wake-up
Time (Note 8)
Sample clock
running
1
1
1
1
ms
AC SPECIFICATIONS
Differential
Nonlinearity
Integral Nonlinearity
DNL
-0.75
±0.2
0.75
-0.75
±0.2
0.75
-0.75
±0.2
0.75
-0.75
±0.2
0.75
INL
-2.0
±0.6
2.0
-2.0
±1.1
2.0
-2.0
±1.1
2.0
-2.5
±1.4
2.5
LSB
40
MSPS
Minimum
Conversion Rate
(Note 9)
fS MIN
Maximum
Conversion Rate
fS MAX
Signal-to-Noise Ratio
SNR
40
250
fIN = 10MHz
fIN = 105MHz
Signal-to-Noise and
Distortion
Effective Number of
Bits
FN6808 Rev 4.00
May 31, 2016
SINAD
210
68.3
65.9
68.2
40
170
68.8
66.4
68.7
125
69.1
67.1
68.9
67.1
MSPS
69.3
dBFS
69.1
dBFS
fIN = 190MHz
67.8
68.3
68.6
68.7
dBFS
fIN = 364MHz
66.8
67.3
67.8
67.7
dBFS
fIN = 695MHz
64.4
64.9
65.7
65.2
dBFS
fIN = 995MHz
62.4
62.9
63.8
63.1
dBFS
fIN = 10MHz
68.2
68.7
69.0
69.2
dBFS
68.9
dBFS
fIN = 105MHz
ENOB
40
LSB
65.6
68.0
66.1
68.7
66.6
68.7
66.6
fIN = 190MHz
67.5
68.0
68.2
68.4
dBFS
fIN = 364MHz
66.0
66.4
66.7
66.8
dBFS
fIN = 695MHz
59.1
59.1
60.0
59.8
dBFS
fIN = 995MHz
48.6
48.2
49.2
50.5
dBFS
fIN = 10MHz
11.0
11.1
11.2
11.2
Bits
11.1
Bits
fIN = 105MHz
10.6
11.0
10.7
11.1
10.8
11.1
10.8
fIN = 190MHz
10.9
11.0
11.0
11.1
Bits
fIN = 364MHz
10.7
10.7
10.8
10.8
Bits
fIN = 695MHz
9.5
9.5
9.7
9.6
Bits
fIN = 995MHz
7.8
7.7
7.9
8.1
Bits
Page 5 of 34
KAD5512HP
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
PARAMETER
TEST
CONDITIONS
SYMBOL
Spurious-Free
Dynamic Range
Intermodulation
Distortion
SFDR
MIN
fIN = 10MHz
TYP
MAX
MIN
86.4
fIN = 105MHz
IMD
KAD5512HP-21
(Note 6)
KAD5512HP-25
(Note 6)
70
81.1
TYP
MAX
KAD5512HP-17
(Note 6)
MIN
87.2
70
85.5
TYP
MAX
KAD5512HP-12
(Note 6)
MIN
87.3
70
82.0
70
TYP
MAX
UNIT
84.9
dBc
81.7
dBc
fIN = 190MHz
79.6
80.0
79.2
80.3
dBc
fIN = 364MHz
75.0
75.6
75.1
75.5
dBc
fIN = 695MHz
60.8
60.0
61.3
61.6
dBc
fIN = 995MHz
48.3
47.9
48.7
50.2
dBc
fIN = 70MHz
-89.0
-92.2
-94.6
-94.8
dBFS
fIN = 170MHz
-91.4
-86.9
-91.7
-85.7
dBFS
10-12
10-12
10-12
950
950
950
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
950
MHz
NOTES:
6. Parameters with MIN and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C).
7. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
8. See “Nap/Sleep” on page 20 for more detail.
9. The DLL Range setting must be changed for low speed operation. See Table 15 on page 26.
Digital Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Current High (SDIO, RESETN)
IIH
VIN = 1.8V
0
1
10
µA
Input Current Low (SDIO, RESETN)
IIL
VIN = 0V
-25
-12
-5
µA
Input Voltage High (SDIO, RESETN)
VIH
Input Voltage Low (SDIO, RESETN)
VIL
Input Current High (OUTMODE,
NAPSLP, CLKDIV, OUTFMT)
(Note 10)
IIH
15
Input Current Low (OUTMODE,
NAPSLP, CLKDIV, OUTFMT)
IIL
-40
Input Capacitance
CDI
INPUTS
1.17
V
.63
V
25
40
µA
25
-15
µA
3
pF
620
mVP-P
LVDS OUTPUTS
Differential Output Voltage
VT
3mA Mode
Output Offset Voltage
VOS
3mA Mode
950
965
980
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
FN6808 Rev 4.00
May 31, 2016
Page 6 of 34
KAD5512HP
Timing Diagrams
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
LATENCY = L CYCLES
tCPD
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
CLKOUTN
CLKOUTP
tDC
tDC
tPD
D[10/8/6/4/2/0]P
D[10/8/6/4/2/0]N
ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS
N-L
N-L
N-L + 1 N-L + 1 N-L + 2
N-L + 2
EVEN BITS
N
D[11/0]P
D[11/0]N
FIGURE 2A. DDR
tPD
DATA
N-L + 1
DATA
N-L
DATA
N
FIGURE 2B. SDR
FIGURE 2. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 20)
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
tCPD
LATENCY = L CYCLES
CLKOUT
CLKOUT
tDC
tDC
tPD
tPD
D[10/8/6/4/2/0]
LATENCY = L CYCLES
ODD BITS
N-L
EVEN BITS
N-L
ODD BITS
N-L + 1
EVEN BITS
N-L + 1
ODD BITS
N-L + 2
FIGURE 3A. DDR
EVEN BITS
N-L + 2
EVEN BITS
N
D[11/0]
DATA
N-L
DATA
N-L + 1
DATA
N
FIGURE 3B. SDR
FIGURE 3. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 20
FN6808 Rev 4.00
May 31, 2016
Page 7 of 34
KAD5512HP
Switching Specifications
PARAMETER
TEST CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
Output Clock to Data Propagation Delay,
LVDS Mode
(Note 11)
Output Clock to Data Propagation Delay,
CMOS Mode
(Note 11)
DDR Rising Edge
tDC
-260
-50
120
ps
DDR Falling Edge
tDC
-160
10
230
ps
SDR Falling Edge
tDC
-260
-40
230
ps
DDR Rising Edge
tDC
-220
-10
200
ps
DDR Falling Edge
tDC
-310
-90
110
ps
SDR Falling Edge
tDC
-310
-50
200
ps
Latency (Pipeline Delay)
Overvoltage Recovery
L
8.5
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 12, 13)
SCLK Period
Write Operation
t
CLK
16
cycles
(Note 12)
Read Operation
tCLK
66
cycles
SCLK Duty Cycle (tHI/tCLK or tLO/tCLK)
Read or Write
CSBto SCLK Set-Up Time
Read or Write
tS
1
cycles
CSBafter SCLK Hold Time
Read or Write
tH
3
cycles
Data Valid to SCLK Set-Up Time
Write
tDSW
1
cycles
Data Valid after SCLK Hold Time
Write
tDHW
3
cycles
Data Valid after SCLK Time
Read
tDVR
Data Invalid after SCLK Time
Read
tDHR
3
cycles
Sleep Mode CSBto SCLK Set-Up Time
(Note 14)
Read or Write in Sleep Mode
tS
150
µs
25
50
75
16.5
%
cycles
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
11. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact factory for more info if needed.
12. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period and must be scaled
proportionally for lower sample rates.
13. The SPI may operate asynchronously with respect to the ADC sample clock.
14. The CSB set-up time increases in sleep mode due to the reduced power state, CSB set-up time in Nap mode is equal to normal mode CSB set-up time
(4ns min).
FN6808 Rev 4.00
May 31, 2016
Page 8 of 34
KAD5512HP
Pin Descriptions - 72 Ld QFN
LVDS [LVCMOS] FUNCTION
SDR MODE
PIN NUMBER
LVDS [LVCMOS] NAME
1, 6, 12, 19, 24, 71
AVDD
1.8V Analog Supply
2-5, 13, 14, 17, 18, 28-31
DNC
Do Not Connect
7, 8, 11, 72
AVSS
Analog Ground
9, 10
VINN, VINP
15
VCM
16
CLKDIV
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Output Mode (LVDS, LVCMOS)
23
NAPSLP
Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low, see “User-Initiated Reset”
on page 18)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
32
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
DDR Logical Bits 1, 0 (LVDS)
33
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[LVCMOS Bit 0]
DDR Logical Bits 1, 0 (LVDS or
CMOS)
34
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
NC in DDR
35
D1P
[D1]
LVDS Bit 1 Output True
[LVCMOS Bit 1]
NC in DDR
37
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
DDR Logical Bits 3, 2 (LVDS)
38
D2P
[D2]
LVDS Bit 2 Output True
[LVCMOS Bit 2]
DDR Logical Bits 3, 2 (LVDS or
CMOS)
39
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
NC in DDR
40
D3P
[D3]
LVDS Bit 3 Output True
[LVCMOS Bit 3]
NC in DDR
41
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
DDR Logical Bits 5, 4 (LVDS)
42
D4P
[D4]
LVDS Bit 4 Output True
[LVCMOS Bit 4]
DDR Logical Bits 5, 4 (LVDS or
CMOS)
43
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
NC in DDR
44
D5P
[D5]
LVDS Bit 5 Output True
[LVCMOS Bit 5]
NC in DDR
46
RLVDS
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
49
D6N
[NC]
FN6808 Rev 4.00
May 31, 2016
DDR MODE COMMENTS
Analog Input Negative, Positive
Common-Mode Output
Clock Divider Control
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1%
resistor)
LVDS Bit 6 Output Complement
[NC in LVCMOS]
DDR Logical Bits 7, 6 (LVDS)
Page 9 of 34
KAD5512HP
Pin Descriptions - 72 Ld QFN
(Continued)
LVDS [LVCMOS] FUNCTION
SDR MODE
PIN NUMBER
LVDS [LVCMOS] NAME
DDR MODE COMMENTS
50
D6P
[D6]
LVDS Bit 6 Output True
[LVCMOS Bit 6]
DDR Logical Bits 7, 6 (LVDS or
CMOS)
51
D7N
[NC]
LVDS Bit 7 Output Complement
[NC in LVCMOS]
NC in DDR
52
D7P
[D7]
LVDS Bit 7 Output True
[LVCMOS Bit 7]
NC in DDR
53
D8N
[NC]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
DDR Logical Bits 9, 8 (LVDS)
54
D8P
[D8]
LVDS Bit 8 Output True
[LVCMOS Bit 8]
DDR Logical Bits 9, 8 (LVDS or
CMOS)
57
D9N
[NC]
LVDS Bit 9 Output Complement
[NC in LVCMOS]
NC in DDR
58
D9P
[D9]
LVDS Bit 9 Output True
[LVCMOS Bit 9]
NC in DDR
59
D10N
[NC]
LVDS Bit 10 Output Complement
[NC in LVCMOS]
DDR Logical Bits 11, 10 (LVDS)
60
D10P
[D10]
LVDS Bit 10 Output True
[LVCMOS Bit 10]
DDR Logical Bits 11, 10 (LVDS
or CMOS)
61
D11N
[NC]
LVDS Bit 11 Output Complement
[NC in LVCMOS]
NC in DDR
62
D11P
[D11]
LVDS Bit 11 Output True
[LVCMOS Bit 11]
NC in DDR
63
ORN
[NC]
LVDS Over-Range Complement
[NC in LVCMOS]
64
ORP
[OR]
LVDS Over-Range True
[LVCMOS Over-Range]
66
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is
required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
Exposed Paddle
AVSS
Output Data Format (Two’s Compliment, Gray Code,
Offset Binary)
Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection), SDR is the default state at power-up for the 72 Ld package
FN6808 Rev 4.00
May 31, 2016
Page 10 of 34
KAD5512HP
Pin Configuration - 72 Ld QFN
AVSS
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D11P
D11N
D10P
D10N
D9P
D9N
OVDD
OVSS
KAD5512HP
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD
1
54 D8P
DNC
2
53 D8N
DNC
3
52 D7P
DNC
4
51 D7N
DNC
5
50 D6P
AVDD
6
49 D6N
AVSS
7
48 CLKOUTP
AVSS
8
47 CLKOUTN
VINN
9
46 RLVDS
EXPOSED PADDLE
VINP
10
AVSS
11
44 D5P
AVDD
12
43 D5N
DNC
13
42 D4P
DNC
14
41 D4N
VCM
15
40 D3P
CLKDIV
16
39 D3N
DNC
17
DNC
18
FN6808 Rev 4.00
May 31, 2016
45 OVSS
38 D2P
CONNECT THERMAL PAD TO AVSS
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
CLKP
CLKN
OUTMODE
NAPSLP
AVDD
RESETN
OVSS
OVDD
DNC
DNC
DNC
DNC
D0N
D0P
D1N
D1P
OVDD
37 D2N
Page 11 of 34
KAD5512HP
Pin Descriptions - 48 Ld QFN
PIN NUMBER
LVDS [LVCMOS] NAME
1, 9, 13, 17, 47
AVDD
LVDS [LVCMOS] FUNCTION
1.8V Analog Supply
2-4, 11, 21, 22
DNC
Do Not Connect
5, 8, 12, 48
AVSS
Analog Ground
6, 7
VINN, VINP
10
VCM
14, 15
CLKP, CLKN
16
NAPSLP
Power Control (Nap, Sleep modes)
Power-On Reset (Active Low, see “User-Initiated Reset” on page 18)
Analog Input Negative, Positive
Common-Mode Output
Clock Input True, Complement
18
RESETN
19, 29, 42
OVSS
20, 37
OVDD
1.8V Output Supply
23
D0N
[NC]
LVDS DDR Logical Bits 1, 0 Output Complement
[NC in LVCMOS]
24
D0P
[D0]
LVDS DDR Logical Bits 1, 0 Output True
[CMOS DDR Logical Bits 1, 0 in LVCMOS]
25
D1N
[NC]
LVDS DDR Logical Bits 3, 2 Output Complement
[NC in LVCMOS]
26
D1P
[D1]
LVDS DDR Logical Bits 3, 2 Output True
[CMOS DDR Logical Bits 3, 2 in LVCMOS]
27
D2N
[NC]
LVDS DDR Logical Bits 5, 4 Output Complement
[NC in LVCMOS]
28
D2P
[D2]
LVDS DDR Logical Bits 5, 4 Output True
[CMOS DDR Logical Bits 5, 4 in LVCMOS]
30
RLVDS
31
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
32
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
33
D3N
[NC]
LVDS DDR Logical Bits 7, 6 Output Complement
[NC in LVCMOS]
34
D3P
[D3]
LVDS DDR Logical Bits 7, 6 Output True
[CMOS DDR Logical Bits 7, 6 in LVCMOS]
35
D4N
[NC]
LVDS DDR Logical Bits 9, 8 Output Complement
[NC in LVCMOS]
36
D4P
[D4]
LVDS DDR Logical Bits 9, 8 Output True
[CMOS DDR Logical Bits 9, 8 in LVCMOS]
38
D5N
[NC]
LVDS DDR Logical Bits 11, 10 Output Complement
[NC in LVCMOS]
39
D5P
[D5]
LVDS DDR Logical Bits 11, 10 Output True
[CMOS DDR Logical Bits 11, 10 in LVCMOS]
40
ORN
[NC]
LVDS Over-Range Complement
[NC in LVCMOS]
41
ORP
[OR]
LVDS Over-Range True
[LVCMOS Over-Range]
43
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
44
CSB
SPI Chip Select (active low)
45
SCLK
SPI Clock
46
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
Output Ground
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
NOTE: LVCMOS output mode functionality is shown in brackets (NC = No Connection)
FN6808 Rev 4.00
May 31, 2016
Page 12 of 34
KAD5512HP
Pin Configuration - 48 Ld QFN
FN6808 Rev 4.00
May 31, 2016
AVSS
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D5P
D5N
OVDD
KAD5512HP
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
AVDD
1
36 D4P
DNC
2
35 D4N
DNC
3
34 D3P
DNC
4
33 D3N
AVSS
5
32 CLKOUTP
VINN
6
31 CLKOUTN
EXPOSED PADDLE
30 RLVDS
VINP
7
AVSS
8
29 OVSS
AVDD
9
28 D2P
VCM
10
27 D2N
DNC
11
AVSS
12
26 D1P
CONNECT THERMAL PAD TO AVSS
17
18
19
20
CLKP
CLKN
NAPSLP
AVDD
RESETN
OVSS
OVDD
21
22
23
24
D0P
16
D0N
15
DNC
14
DNC
13
AVDD
25 D1N
Page 13 of 34
KAD5512HP
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = maximum conversion rate (per speed grade).
-50
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
SFDR AT 250MSPS
85
80
SFDR AT 125MSPS
75
SNR AT 125MSPS
70
65
60
SNR AT 250MSPS
55
50
0M
200M
400M
600M
800M
HD3 AT 250MSPS
-55
HD3 AT 125MSPS
-60
-65
-70
-75
-80
HD2 AT 250MSPS
-85
HD2 AT 125MSPS
-90
-95
-100
0M
1G
200M
INPUT FREQUENCY (Hz)
-20
90
-30
SNR AND SFDR
HD2 AND HD3 MAGNITUDE
100
SFDRFS (dBFS)
70
60
SNRFS (dBFS)
50
SFDR (dBc)
40
SNR (dBc)
30
20
-60
-20
-10
0
HD3 (dBFS)
-60
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
FIGURE 7. HD2 AND HD3 vs AIN
FIGURE 6. SNR AND SFDR vs AIN
95
-60
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
0
-90
-100
INPUT AMPLITUDE (dBFS)
90
SFDR
85
80
75
SNR
70
65
60
40
-10
HD2 (dBFS)
-80
-110
-30
HD3 (dBc)
-70
-120
-40
HD2 (dBc)
-50
0
-50
1G
-40
10
-60
800M
FIGURE 5. HD2 AND HD3 vs fIN
FIGURE 4. SNR AND SFDR vs fIN
80
400M
600M
INPUT FREQUENCY (Hz)
70
100
130
160
190
SAMPLE RATE (MSPS)
FIGURE 8. SNR AND SFDR vs fSAMPLE
FN6808 Rev 4.00
May 31, 2016
220
250
-70
HD3
-80
-90
HD2
-100
-110
-120
40
70
100
130
160
190
220
SAMPLE RATE (MSPS)
FIGURE 9. HD2 AND HD3 vs fSAMPLE
Page 14 of 34
250
KAD5512HP
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
450
0.5
0.4
0.3
SDR
350
0.2
DNL (LSBs)
TOTAL POWER (mW)
400
DDR
300
250
0.1
0.0
-0.1
-0.2
200
-0.3
150
-0.4
100
40
70
100
130
160
190
220
-0.5
250
0
512
1024
1536
1.0
SNR (dBFS) AND SFDR (dBc)
0.6
0.4
INL (LSBs)
3072
3584
4096
90
0.8
0.2
0.0
-0.2
-0.4
-0.6
-0.8
0
512
1024
1536
2048
2560
3072
3584
85
SFDR
80
75
70
SNR
65
60
55
50
300
4096
400
CODE
FIGURE 12. INTEGRAL NONLINEARITY
750000
0
600000
-20
450000
300000
150000
0
2050
500
600
700
INPUT COMMON-MODE (mV)
800
FIGURE 13. SNR AND SFDR vs VCM
AMPLITUDE (dBFS)
NUMBER OF HITS
2560
FIGURE 11. DIFFERENTIAL NONLINEARITY
FIGURE 10. POWER vs fSAMPLE IN 3mA LVDS MODE
-1.0
2048
CODE
SAMPLE RATE (MSPS)
Ain = -1.0dBFS
SNR = 68.2dBFS
SFDR = 91.9dBc
SINAD = 68.2dBFS
-40
-60
-80
-100
2051
2052
2053
CODE
2054
FIGURE 14. NOISE HISTOGRAM
FN6808 Rev 4.00
May 31, 2016
2055
2056
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 15. SINGLE-TONE SPECTRUM AT 10MHz
Page 15 of 34
KAD5512HP
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
0
AIN = -1.0dBFS
SNR = 68.0dBFS
-20 SFDR = 82.6dBc
SINAD = 67.8dBFS
-40
AIN = -1.0dBFS
SNR = 67.3dBFS
SFDR = 77.2dBc
SINAD = 66.8dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
-60
-80
-40
-60
-80
-100
-100
-120
0M
20M
40M
60M
80M
100M
-120
120M
0M
20M
40M
0
AMPLITUDE (dBFS)
-60
-80
-40
-60
-80
-100
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
-120
0M
120M
FIGURE 18. SINGLE-TONE SPECTRUM AT 495MHz
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 19. SINGLE-TONE SPECTRUM AT 995MHz
0
IMD = -89.0dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
120M
AIN = -1.0dBFS
SNR = 59.9dBFS
SFDR = 47.0dBc
SINAD = 47.4dBFS
-20
-100
-40
-60
-80
IMD = -91.4dBFS
-20
-40
-60
-80
-100
-100
-120
100M
0
AMPLITUDE (dBFS)
AIN = -1.0dBFS
SNR = 64.5dBFS
SFDR = 69.2dBc
SINAD = 63.4dBFS
-40
0
80M
FIGURE 17. SINGLE-TONE SPECTRUM AT 190MHz
FIGURE 16. SINGLE-TONE SPECTRUM AT 105MHz
-20
60M
FREQUENCY (Hz)
FREQUENCY (Hz)
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
FIGURE 20. TWO-TONE SPECTRUM AT 70MHz
FN6808 Rev 4.00
May 31, 2016
120M
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 21. TWO-TONE SPECTRUM AT 170MHz
Page 16 of 34
KAD5512HP
Theory of Operation
voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
Functional Description
The KAD5512HP is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive approximation
architecture (Figure 22). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. The converter pipeline
requires six samples to produce a result. Digital error correction
is also applied, resulting in a total latency of eight and one half
clock cycles. This is evident to the user as a time lag between the
start of a conversion and the data being available on the digital
outputs.
The KAD5512HP family offers 2.5dB improvement in SNR over
the KAD5512P by simultaneously sampling the input signal with
two ADC cores in parallel and summing the digital result. Since
the input signal is correlated between the two cores and noise is
not, an increase in SNR is achieved. As a result of this
architecture, indexed SPI operations must be executed on each
core in series. Refer to “Indexed Device Configuration/Control”
on page 24 for more details.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal
Power-On Reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled up or
down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the previous conditions cannot be met at power-up.
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If the
SDO pin is pulled low externally during power-up, calibration will
not be executed properly.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
required, the RESETN pin should be connected to an open-drain
driver with a drive strength of less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 23. The Over-Range (OR) output is
set high once RESETN is pulled low, and remains in that state
until calibration is complete. The OR output returns to normal
operation at that time, so it is important that the analog input be
within the converter’s full-scale range to observe the transition. If
the input is in an over-range condition the OR pin will stay high,
and it will not be possible to detect the end of the calibration
cycle.
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 22. ADC CORE BLOCK DIAGRAM
FN6808 Rev 4.00
May 31, 2016
Page 17 of 34
KAD5512HP
CLKN
CLKP
CALIBRATION
TIME
3
SNR CHANGE (dBfs)
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set
low. Normal operation of the output clock resumes at the next input
clock edge (CLKP/CLKN) after RESETN is deasserted. At 250MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
CAL DONE AT
+85°C
2
1
0
-1
-2
RESETN
-4
-40
CALIBRATION
BEGINS
CAL DONE AT
+25°C
CAL DONE AT
-40°C
-3
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 24. SNR PERFORMANCE vs TEMPERATURE
ORP
CALIBRATION
COMPLETE
15
FIGURE 23. CALIBRATION TIMING
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength of less than 0.5mA is
recommended, RESETN has an internal high impedance pull-up
to OVDD. As is the case during power-on reset, the SDO, RESETN
and DNC pins must be in the proper state for the calibration to
successfully execute.
The performance of the KAD5512HP changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the ADC under the environmental conditions at
which it will operate.
A supply voltage variation of
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