M2004-01-666.5140

Product Data Sheet Integrated Circuit Systems, Inc. M2004-01/-11 FREQUENCY TRANSLATION PLL 27 26 25 24 23 22 21 20 19 The M2004 variants -01 and -11 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation in a high-speed data communications system. The clock multiplication ratio and output divider ratio are pin selectable and also configurable through serial programming. External loop components allow the tailoring of PLL loop response. The M2004-11 adds Hitless Switching with Phase Build-out (HS/PBO) to ensure that reference clock reselection does not disrupt the output clock. M0 GND REF_SEL REF_CLK0 REF_CLK1 nP_LOAD S_LOAD S_DATA VCC PIN ASSIGNMENT (9 x 9 mm SMT) M1 M2 M3 M4 M5 VCC DNC DNC DNC 28 29 30 31 32 33 34 35 36 S_CLOCK MR nFOUT FOUT GND N1 N0 VCC GND 18 17 16 15 14 13 12 11 10 M2004-01 M2004-11 (Top View) 1 2 3 4 5 6 7 8 9 GENERAL DESCRIPTION GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN Also read about device variants -21, -31, -41, and -51 in the M2004-x1 Preliminary Information sheet. FEATURES Figure 1: Pin Assignment ◆ Ideal for OC-48/192 data clock ◆ Integrated SAW (surface acoustic wave) delay line Example Input / Output Frequency Combinations ◆ VCSO frequency from 300 to 700MHz (Specify VCSO center frequency at time of order) Input Clock VCSO 1 Output Freq (MHz) Freq (MHz) (MHz) ◆ Low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) 19.44 ◆ Pin-selectable or serially programmed configuration ◆ The M2004-11 adds Hitless Switching with Phase Build-out (HS/PBO) to ensure SONET/SDH MTIE and TDEV compliance during reference clock reselection ◆ Reference clock inputs support single-ended LVCMOS, LVTTL Application 77.76 38.80 622.08 155.52 77.76 311.04 155.52 622.08 25.00 625.00 156.25 OC-12 / 48 /192 Gigabit Ethernet Table 1: Example Input / Output Frequency Combinations ◆ Industrial temperature available Note 1: Specify VCSO center frequency at time of order ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package SIMPLIFIED BLOCK DIAGRAM Loop Filter M2004-01/-11 REF_CLK1 1 REF_CLK0 0 VCSO REF_SEL M Divider S_DATA S_CLOCK S_LOAD nP_LOAD 6 M5:0 FOUT N Divider Pin Configuration Register with Serial Programming Option 2 N1:0 nFOUT MR Figure 2: Simplified Block Diagram M2004-01/-11 Datasheet Rev 1.0 Revised 03Jul2003 M2004-01/-11 Frequency Translation PLL Integrated Circuit Systems, Inc. ● Communications Modules ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet PIN DESCRIPTIONS Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC I/O 11, 19, 33 VCC Power 12 13 N0 N1 Input 15 16 FOUT nFOUT Configuration Ground Input External loop filter connections. See Figure 5, External Loop Filter, on pg. 6. Output Input Output Power supply connection, connect to +3.3V. N divider (output divider) inputs N1:0. Internal pull-down resistor1 LVCMOS/LVTTL. See Table 5, Pin Selection of N Divider Using N1:0 Pins, on pg. 3. No internal terminator 17 MR Input Internal pull-down resistor1 18 20 21 S_CLOCK S_DATA S_LOAD Input Internal pull-down resistors1 22 nP_LOAD Input Internal pull-down resistor1 23 REF_CLK1 24 REF_CLK0 25 REF_SEL 27 28 29 30 31 M0 M1 M2 M3 M4 32 M5 34, 35, 36 DNC Description Power supply ground connections. Input Input Input Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Clock output pair. Differential LVPECL. Reset: Logic 1 resets M and N dividers and forces FOUT to LOW and nFOUT to HIGH. Logic 0 enables the outputs. LVCMOS/LVTTL. See Table 7, Pin Configuration & Serial Programming Functions, on pg. 5. Serial programming input pins. LVCMOS/LVTTL. See Table 7, Pin Configuration & Serial Programming Functions, on pg. 5 for how these three pins are used in combination. Pin-configuration vs. serial programming control. Determines when data present at M5:0 and N1:0 is loaded into M and N dividers vs. when serial programming occurs. LVCMOS/LVTTL. See Table 7, Pin Configuration & Serial Programming Functions, on pg. 5 for how this pin is used. Reference clock inputs. LVCMOS/LVTTL. Reference clock input selection. LVCMOS/LVTTL. See Table 3, Reference Clock Input Selection, on pg. 3. For the M2004-11, REF_SEL triggers Hitless Switching (HS/PBO) when toggled. M divider (feedback divider) inputs M5:0. See Internal pull-down resistor1 Table 4, Pin Selection of M Divider Using M5:0 Pins, on pg. 3. See also Table 7, Pin Configuration & Serial Programming Functions, on pg. 5 1 Internal pull-up resistor Do Not Connect. Table 2: Pin Descriptions Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 7. M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 2 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet DETAILED BLOCK DIAGRAM RLOOP CLOOP RPOST External Loop Filter Components CPOST CPOST RLOOP M2004-01 M2004-11 MUX REF_CLK1 1 REF_CLK0 0 OP_IN Phase Detector CLOOP nOP_IN RPOST OP_OUT nOP_OUT nVC VC SAW Delay Line RIN RIN Loop Filter Amplifier REF_SEL Phase Shifter VCSO M Divider M = 3-511 6 FOUT nFOUT N Divider M8:0 Pin Configuration Register (M5:0, N1:0) with Serial Programming Option (M8:0, N1:0) S_DATA S_CLOCK S_LOAD nP_LOAD N = 1,2,4,8 2 M5:0 N1:0 MR Figure 3: Detailed Block Diagram DEVICE CONFIGURATION TABLES Reference Clock Input Selection REF_SEL Pin Setting (Pin 25) 0 1 M and N Pin Selection Option (Continued) Pin Selection of N Divider Using N1:0 Pins Reference Input Selection REF_CLK0 REF_CLK1 Table 3: Reference Clock Input Selection M and N Pin Selection Option Pin Selection of M Divider Using M5:0 Pins Sample Input Clock M5:0 Pin Freq (MHz) Settings1 Definition (Pins 32 - 27) FVCSO= FVCSO= M5 - M0 622.082, 625.003 5 4 4 3 2 1 0 Feedback Divider Value “M” 0 00011 M = 3 minimum 0 0 0 1 0 .0 M=4 155.52 .. 0 01000 M=8 77.76 0 1 0 0 0 .0 M = 16 38.80 0 1 1 0 0 .1 M = 25 1 0 0 0 0 .0 M = 32 1 11111 M = 63 .. . .. .. .. 156.25 N1:0 Settings N Divider (Pin 13 and 12) Value N1 N0 0 0 1 0 1 2 1 0 4 1 1 8 Table 5: Pin Selection of N Divider Using N1:0 Pins Note 1: FVCSO = 622.08MHz (e.g., M2004-01-622.0800) Serial Programming Alternative (Using S_DATA Pin) Serial Settings per Bits Bit T1:0 Normal/Test Mode 10 00 Output Divider Value “N” 11 M8:0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1. 1 .. Bits M8:6 default to 0. FVCSO = 622.08 MHz (e.g., M2004-01-622.0800) FVCSO = 625.00 MHz (e.g., M2004-01-625.0000) M5 pin has a pull-up resister; M4-M0, pull-down. M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. N=1 minimum N=8 maximum Feedback Divider Value “M” M=3 0 0 0 1 0 0 0 0. 0 M = 32 000111111 M = 63 111111111 M = 511 .. Table 4: Pin Selection of M Divider Using M5:0 Pins Note 1: Note 2: Note 3: Note 4: 10 00 .. . 19.44 Definition Normal Operation * *Note: T1 and T0, used for test automation, must be set to 0 N1:0 25.00 Sample Output Frequency (MHz) 1 (FOUT, nFOUT) 622.08 311.04 155.52 77.76 .. . maximum Table 6: Serial Programming Alternative (Using S_DATA Pin) 3 of 10 ● minimum Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet FUNCTIONAL DESCRIPTION N Divider and Outputs The M2004-01/-11 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high “Q” SAW delay line provides a low jitter clock signal. The device can be pin-configured for feedback divider and output divider values. These divider values can also be set through serial programming. Output is LVPECL compatible. External loop filter component values set the PLL bandwidth to optimize jitter attenuation characteristics. The M2004-11 adds Hitless Switching with Phase Build-out (HS/PBO) to provide SONET/SDH MTIE and TDEV compliance during a reference clock reselection using the internal mux or when using an external mux. The M2004-01/-11 is ideal for clock jitter attenuation and frequency translation in 2.5 or 10 Gb optical network line card applications. Input Reference Clocks An internal input MUX is provided for input reference clock selection. One input reference clock is selected from between two single-ended LVCMOS / LVTTL clock inputs. The maximum input frequency is 175MHz. PLL Operation The M2004-01/-11 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. The “M Divider” divides the VCSO output frequency, feeding the result into the phase detector. The selected input reference clock is fed into the other input of the phase detector. The phase detector compares its two inputs. It then causes the VCSO to increase or decrease in speed as needed to phase- and frequencylock the VCSO to the reference input. The value of M directly affects closed loop bandwidth. The M2004-01/-11 provides one differential LVPECL output pair: FOUT, nFOUT. By using the N divider, the output frequency can be the VCSO center frequency (Fvcso) or 1/2, 1/4, or 1/8 Fvcso. The N1 and N0 pins select the value for the N divider. See Table 5, Pin Selection of N Divider Using N1:0 Pins, on pg. 3. When the N divider is included, the complete relationship for the output frequency (Fout) is defined as: M Fvcso = Fref_clk × -------Fout = ------------------N N Configuration of M and N Dividers The M and N dividers can be set by pin configuration or serial programming. The divider configuration of the M2004-01/-11 is reset when the input pin MR is set HIGH. MR is set LOW for divider configuration to be operational. See Table 7, Pin Configuration & Serial Programming Functions, on pg. 5. Pin Configuration M and N Dividers The M2004-01/-11 can be pin-configured with the input pins M0 - M5, N0, and N1. Pin configuration of dividers occurs when nP_LOAD is LOW. The data on pins M5:0 and pins N1:0 is passed transparently (directly) to the M and N dividers. On the LOW-to-HIGH (rising edge) transition of the nP_LOAD input, the data is latched. With nP_LOAD set HIGH, the pin-configured values remain loaded in the M and N dividers; the dividers are unaffected by any change to the M5:0 or N1:0 inputs. As a result, the M5:0 and N1:0 pins can be used to set the power-up default values for M and N. (The dividers are also unaffected by any S_DATA serial input as long as there is no rising edge transition of S_LOAD.) See Table 7, Pin Configuration & Serial Programming Functions, on pg. 5. See also Figure 8, Times for M5:0 and N1:0, on pg. 9. The M Divider The relationship between the VCSO center frequency (Fvcso), the M divider, and the input reference frequency (Fref_clk) is: Fvcso = Fref_clk × M The product of M and the input frequency must be such that it falls within the “lock” range of the VCSO. See APR in AC Characteristics on pg. 8. M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 4 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet Serial Programming of M and N Dividers If S_LOAD is held HIGH, any S_DATA input is passed transparently (directly) to the M and N dividers on each rising edge of S_CLOCK. The M2004-01/-11 is serially programmed with S_DATA, S_CLOCK, and S_LOAD. See Figure 4, Serial Configuration Timing Diagram, below. The data is latched on the falling edge transition of the S_LOAD input (at point “c” in the timing diagram). With S_LOAD set LOW, the serially programmed values remain in the M and N dividers, unaffected by any serial pin input. Serial input mode is enabled when nP_LOAD is HIGH and S_LOAD is LOW (at point “a” in the the timing diagram, Figure 4). Data on the S_DATA input pin is serially loaded into the configuration shift register with each rising edge of the S_CLOCK input. (The T1 bit is input first, M0 last.) See Table 7, Pin Configuration & Serial Programming Functions, below. See also Figure 8, Times for M5:0 and N1:0, on pg. 9. When the shift register is full, its entire contents is loaded in parallel into the M and N dividers. This occurs on the rising edge of the S_LOAD input (at point “b” in the timing diagram). This load is transparent; the dividers immediately contain the serially programmed values. Pin Configuration & Serial Programming Functions L = Low; H = High; X = Don't care; K = Rising Edge Transition; L = Falling Edge Transition MR nP_LOAD M5:0 H X X Pins N1:0 S_LOAD X Function S_CLOCK S_DATA X X X Resets the dividers and forces FOUT to LOW and nFOUT to HIGH. Pin Configuration of M and N Dividers L L Data Data X X X Data on M5:0 and N1:0 input pins is passed directly (and become immediately transparent) to the M and N dividers respectively. L K Data Data L X X Data is latched into M and N dividers and remains loaded until next HIGH-to-LOW transition of nP_LOAD or a serial load occurs. Serial Programming of M and N Dividers L H X X L K Data Serial input mode. Data on the S_DATA pin is serially loaded into the shift register on each rising clock of S_CLOCK. (However, serial input does not affect the values in the M and N dividers.) L H X X K L Data Entire contents of the shift register are passed (and become immediately transparent) to the M and N dividers. L H X X L L Data M and N divider values are latched. L H X X L X X Serial input does not affect the values in the M and N dividers. L H X X H K Data Serial input affects dividers: S_DATA passed directly to M and N dividers as it is clocked. Table 7: Pin Configuration & Serial Programming Functions Serial Configuration Timing Diagram S_DATA T1 T0 Null N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S_CLOCK KL S_LOAD b c a Points a, b, and c referred to in “Serial Programming of M and N Dividers” description above. The T1 bit is loaded first, M0 last. Figure 4: Serial Configuration Timing Diagram M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 5 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet Hitless Switching and Phase Build-out * A proprietary automatic Hitless Switching (HS) function is included in the M2004-11. The HS function provides SONET/SDH MTIE and TDEV compliance during a reference clock reselection using the internal mux or when using an external mux (through detection of the resulting phase transient).** A Phase Build-out (PBO) function is also incorporated to absorb most of the phase change in the reference clock input. The combined HS/PBO function is armed after the device locks to the input clock reference. Once armed, HS/PBO is triggered by either: When the PLL locks to within 2 ns of the input clock phase, the PLL returns to normal loop bandwidth and the HS/PBO function is re-armed. External Loop Filter To provide stable PLL operation, and thereby a low jitter output clock, the M2004-01/-11 requires the use of an external loop filter components. These are connected to the provided filter pins (see Figure 5). Due to the differential signal path design, the implementation consists of two identical complementary RC filters as shown in Figure 5, below. • Changing REF_SEL to switch the input reference clock. • Detection at the phase detector of an input phase RLOOP CPOST transient beyond 4 ns. Once triggered, the HS function narrows loop bandwidth to control MTIE during locking to the new input phase. With proper configuration of the external loop filter, the output clocks will comply with MTIE and TDEV specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock changes. The Phase Build-out (PBO) function enables the PLL to absorb most of the phase change of the input clock. The PBO function selects a new VCSO clock edge for the phase detector feedback clock, selecting the edge closest in phase to the new input clock phase. This reduces re-lock time, the generation of wander, and extra output clock cycles. Note *: The M2004-01 does not include HS/PBO. Note **:Transient-triggered HS/PBO is not suitable for use with an unstable reference clock that would induce phase jitter beyond 2 ns at the phase detector (e.g., Stratum DPLL clock sources and unstable recovered network clocks intended for loop timing configuration). Therefore, the M2004-11 also offers the internal mux-triggered HS/PBO capability. RPOST CLOOP CPOST RLOOP OP_IN nOP_IN 4 RPOST CLOOP OP_OUT 9 nOP_OUT 8 nVC 5 VC 6 7 Figure 5: External Loop Filter PLL bandwidth is affected by the “M” value as well as the VCSO frequency. See Table 8, External Loop Filter Component Values M2004-01/-11, on pg. 6. PLL Simulator Tool Available A free PC software utility is available on the ICS website (www.icst.com). The M2000 Timing Modules PLL Simulator is a downloadable application that simulates PLL jitter and wander transfer characteristics. This enables the user to set appropriate external loop component values in a given application. External Loop Filter Component Values 1 M2004-01/-11 VCSO Parameters: KVCO = 800kHz/V, RIN = 16kΩ, VCSO Bandwidth = 700kHz. See AC Characteristics on pg. 8 for PLL Loop Constants. Device Configuration Example External Loop Filter Component Values Nominal Performance Using These Values R loop C loop R post PLL Loop Bandwidth 32 13kΩ 0.47µF 33kΩ 220pF 3.8kHz 5.6 0.06 622.08 32 39kΩ 0.022µF 20kΩ 220pF 12.7kHz 7.7 0.03 FRef FVCSO M Divider Value (MHz) 19.44 622.08 19.44 (MHz) C post Damping Passband Factor Peaking (dB) 19.44 622.08 32 2.2kΩ 10.0µF 22kΩ 3300pF 710Hz 4.4 0.10 155.52 622.08 4 3.9kΩ 0.47µF 39kΩ 100pF 11.0kHz 4.7 0.09 155.52 622.08 4 750Ω 10.0µF 7.5kΩ 1000pF 1.6kHz 4.2 0.10 Table 8: External Loop Filter Component Values M2004-01/-11 Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com. M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 6 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Rating Unit VI Inputs -0.5 to VCC +0.5 V VO Outputs -0.5 to VCC +0.5 V VCC Power Supply Voltage 4.6 V TS Storage Temperature -45 to +100 o C Table 9: Absolute Maximum Ratings Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings ard stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. RECOMMENDED CONDITIONS OF OPERATION Symbol Parameter VCC Positive Supply Voltage TA Ambient Operating Temperature Commercial Industrial Min Typ Max Unit 3.135 3.3 3.465 V oC +70 +85 0 -40 oC Table 10: Recommended Conditions of Operation ELECTRICAL SPECIFICATIONS DC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 622-675MHz, Outputs terminated with 50Ω to VCC - 2V TA = -40 oC to +85 oC (industrial) Symbol Parameter Power Supply VCC Positive Supply Voltage ICC Power Supply Current LVCMOS / LVTTL Inputs VIH Input High Voltage VIL Input Low Voltage Inputs with Pull-down IIH Input High Current IIL Input Low Current Typ Max Unit Conditions 3.135 3.3 3.465 V 162 REF_CLK0, REF_CLK1, REF_SEL, MR, nP_LOAD, S_LOAD, S_CLOCK, S_DATA, N0:N1, M0:M5 Rpulldown Internal Pull-down Resistor Inputs with Pull-up Min IIH Input High Current IIL Input Low Current Rpullup Internal Pull-up Resistor All Inputs CIN Input Capacitance Differential Outputs VOH Output High Voltage REF_CLK0, REF_CLK1, REF_SEL, MR, nP_LOAD, S_LOAD, S_CLOCK, S_DATA, N0:N1, M0:M4 mA Vcc + 0.3 V 2 -0.3 1.3 V 150 µA µA -5 kΩ 51 5 M5 All Inputs Output Low Voltage VP-P Peak to Peak Output Voltage 1 4 Integrated Circuit Systems, Inc. Vcc - 1.0 V Vcc - 2.0 Vcc - 1.7 V 0.4 0.85 Communications Modules V Table 11: DC Characteristics 7 of 10 ● pF Vcc - 1.4 Note 1: Single-ended measurement. See Figure 6, Output Rise and Fall Time on pg. 9. M2004-01/-11 Datasheet Rev 1.0 VCC = 3.456V VIN = 0 V kΩ 51 VOL µA µA -150 FOUT, nFOUT VCC = VIN = 3.456V Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet ELECTRICAL SPECIFICATIONS (CONTINUED) AC Characteristics Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), FVCSO = FOUT = 622-675MHz, Outputs terminated with 50Ω to VCC - 2V TA = -40 oC to +85 oC (industrial) Symbol Parameter FIN Min Input Frequency REF_CLK0, REF_CLK1 Typ 1 S_CLOCK PLL Loop Constants 1 Max Unit Conditions 175 MHz MHz MHz 50 FOUT Output Frequency APR VCSO Pull-Range KVCO VCO Gain 800 ppm ppm kHz/V RIN Internal Loop Resistor 16 kΩ 700 kHz -72 -94 -123 FOUT, nFOUT 38 ±120 ±50 Commercial Industrial BWVCSO VCSO Bandwidth Φn Phase Noise and Jitter J(t) odc Single Side Band Phase Noise @622.08MHz 1kHz Offset Output Duty Cycle Output Rise Time 2 tR tF for FOUT, nFOUT Output Fall Time for FOUT, nFOUT N = 2, 4, or 8 45 50 55 N=1 40 50 60 % FOUT =155.52MHz N = 4 (N1:0 = 10) 350 450 550 ps FOUT =311.04MHz N = 2 (N1:0 = 01) 325 425 500 ps FOUT =622.08MHz N = 1 (N1:0 = 00) 200 275 350 ps FOUT =155.52MHz N = 4 (N1:0 = 10) 350 450 550 ps FOUT =311.04MHz N = 2 (N1:0 = 01) 325 425 500 ps FOUT =622.08MHz N = 1 (N1:0 = 00) 200 275 350 ps 10kHz Offset 2 ±200 ±150 dBc/Hz dBc/Hz dBc/Hz ps ps % 100kHz Offset Jitter (rms) 700 12kHz to 20MHz 0.5 50kHz to 80MHz 0.5 20% to 80% 2 M5:0, N1:0 to nP_LOAD tSETUP Setup Time 3 tHOLD Hold Time 3 tIPW Input Pulse Width 4 tLOCK PLL Lock Time MTIE Mean Time Interval Error 5 M2004-11 5 ns 5 ns S_DATA to S_CLOCK 20% to 80% M5:0, N1:0 to nP_LOAD S_DATA to S_CLOCK S_CLOCK to S_LOAD S_LOAD ns 10 100 ms Compliant with GR-253-CORE Table 12: AC Characteristics Note 1: Note 2: Note 3: Note 4: Note 5: Parameters needed for PLL Simulator software; see Table 8, External Loop Filter Component Values M2004-01/-11 on pg. 6. See Parameter Measurement Information on pg. 9. See Figure 8, Times for M5:0 and N1:0 and Figure 9, Times for S_DATA on pg. 9. See Figure 9, Times for S_DATA on pg. 9. Requires proper loop filter settings. Consult factory. M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 8 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. FREQUENCY TRANSLATION PLL Product Data Sheet PARAMETER MEASUREMENT INFORMATION Output Rise and Fall Time Output Duty Cycle nFOUT FOUT 80% 80% VP-P Clock Output tPW (Output Pulse Width) 20% tF 20% tR tPERIOD odc = tPW tPERIOD Figure 7: Output Duty Cycle Figure 6: Output Rise and Fall Time Times for M5:0 and N1:0 M5:0, N1:0 tHOLD tSET-UP nP_LOAD Figure 8: Times for M5:0 and N1:0 Times for S_DATA Times for S_CLOCK and S_LOAD S_DATA M0 S_DATA tHOLD tHOLD tSET-UP tSET-UP S_CLOCK S_CLOCK Figure 9: Times for S_DATA tSET-UP S_LOAD tIPW (Input Pulse Width) Figure 10: Times for S_CLOCK and S_LOAD M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 9 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400 M2004-01/-11 Integrated Circuit Systems, Inc. Product Data Sheet FREQUENCY TRANSLATION PLL DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER Mechanical Dimensions: Figure 11: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier ORDERING INFORMATION Part Number: Device Variant -01 -11 -21 -31 -41 -51 M2004- x1 - xxx.xxxx Added Features none (base) HS/PBO Fixed NBW HS/PBO Fixed NBW HS/PBO HS/PBO Fixed NBW Feature Key HS/PBO = Hitless Switching with Phase Build-out See M2004-x1 Preliminary Information Temperature “ - ” = 0 to +70 oC (commercial) I = - 40 to +85 oC (industrial) Frequency (MHz) Consult ICS for available VCSO frequencies Figure 12: Ordering Information Example Part Numbers For VCSO Freq (MHz) Temperature commercial industrial 622.08 Part Number M2004-01 - 622.0800 or M2004-11 - 622.0800 M2004-01I 622.0800 or M2004-11I 622.0800 Table 13: Example Part Numbers Consult ICS for the availability of other VCSO frequencies. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. M2004-01/-11 Datasheet Rev 1.0 Integrated Circuit Systems, Inc. 10 of 10 ● Communications Modules Revised 03Jul2003 ● w w w. i c s t . c o m ● tel (508) 852-5400