M2041-11-622.0800

M2041 Integrated Circuit Systems, Inc. VCSO BASED CLOCK PLL WITH AUTOSWITCH FEATURES • Integrated SAW (surface acoustic wave) delay line; output frequencies of 125 to 700 MHz;* outputs VCSO frequency or 1/4; pin-configurable dividers • Loss of Lock (LOL) indicator output • Narrow Bandwidth control input (NBW pin); Initialization (INIT) input overrides NBW at power-up • Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL • AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure; Hitless Switching (HS) options with or without Phase Build-out (PBO) enable SONET (GR-253) /SDH (G.813) MTIE and TDEV compliance • Acknowledge pin (REF_ACK pin) indicates the actively selected reference input • Dual differential LVPECL outputs • Low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) • Single 3.3V power supply • Small 9 x 9 mm SMT (surface mount) package 27 26 25 24 23 22 21 20 19 FIN_SEL0 MR_SEL REF_ACK LOL NBW VCC DNC DNC DNC 28 29 30 31 32 33 34 35 36 M2041 (Top View) P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 The M2041 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL. It is designed for clock protection, frequency translation and jitter attenuation in optical networking systems supporting 2.5-10Gb data rates. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response. FIN_SEL1 GND AUTO DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC PIN ASSIGNMENT (9 x 9 mm SMT) GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN GENERAL DESCRIPTION Example I/O Clock Frequency Combinations Using M2041-11-622.0800 PLL Ratio Input Reference Clock (MHz) (Pin Selectable) 19.44 77.76 155.52 622.08 32 8 4 1 Output Clock (MHz) (Pin Selectable) 622.08 or 155.52 * Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM Loop Filter M2041 NBW PLL Phase Detector MUX DIF_REF0 nDIF_REF0 0 DIF_REF1 nDIF_REF1 1 R Div (1 or 8) VCSO REF_ACK REF_SEL 0 1 AUTO M Divider Mfin Divider (1 or 8) (1, 4, 8, or 32) LOL Phase Detector Auto Ref Sel INIT LOL M / R Divider MR_SEL FIN_SEL1:0 P Divider (1 or 4) LUT 2 P_SEL M2041 VCSO Based Clock PLL with AutoSwitch Mfin Divider LUT FOUT0 nFOUT0 FOUT1 nFOUT1