M32C83T

REJ09B0034-0131 16/32 M32C/83 Group (M32C/83, M32C/83T) Hardware Manual RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES Before using this material, please visit our website to verify that this is the most current document available. Rev. 1.31 Revision Date: Jan. 31, 2006 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M32C/83 Group (M32C/83, M32C/83T) microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 00 Symbol XXX Bit Symbol XXX0 XXX bit XXX1 Address XXX After Reset 0016 Bit Name b1 b0 Function 0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX RW *2 RW RW (b2) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Reserved bit Set to "0" *3 WO (b4 - b3) XXX5 XXX bit XXX6 *4 Function varies depending on mode of operation RW RW XXX bit 0: XXX 1: XXX XXX7 RO *1 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 RW: RO: WO: –: *3 • Reserved bit Reserved bit. Set to specified value. *4 • Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit. • Do not set a value The operation is not guaranteed when a value is set. • Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode. Read and write Read only Write only Nothing is assigned 3. M16C Family Documents The following documents were prepared for the M16C family. (1) Document Short Sheet Data Sheet Hardware Manual Contents Hardware overview Hardware overview and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note • Application examples of peripheral functions • Sample programs • Introduction to the basic functions in the M16C family • Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to confirm that this is the most current document available. Table of Contents Quick Reference by Address _____________________ B-1 1. Overview _____________________________________ 1 1.1 1.2 1.3 1.4 1.5 1.6 Applications ................................................................................................................ 1 Performance Overview .............................................................................................. 2 Block Diagram ............................................................................................................ 4 Product Information ................................................................................................... 5 Pin Assignment .......................................................................................................... 6 Pin Description ......................................................................................................... 14 2. Central Processing Unit (CPU) __________________ 18 2.1 General Registers .................................................................................................... 19 2.1.1 Data Registers (R0, R1, R2 and R3) ................................................................. 19 2.1.2 Address Registers (A0 and A1) ....................................................................... 19 2.1.3 Static Base Register (SB) ................................................................................. 19 2.1.4 Frame Base Register (FB) ................................................................................ 19 2.1.5 Program Counter (PC) ...................................................................................... 19 2.1.6 Interrupt Table Register (INTB) ........................................................................ 19 2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................... 19 2.1.8 Flag Register (FLG) ........................................................................................... 19 2.2 High-Speed Interrupt Registers .............................................................................. 20 2.3 DMAC-Associated Registers ................................................................................... 20 3. Memory _____________________________________ 21 4. Special Function Registers (SFR)________________ 22 5. Reset _______________________________________ 44 5.1 Hardware Reset ........................................................................................................ 44 5.1.1 Reset on a Stable Supply Voltage ................................................................... 44 5.1.2 Power-on Reset ................................................................................................. 44 5.2 Software Reset ......................................................................................................... 46 5.3 Watchdog Timer Reset ............................................................................................ 46 5.4 Internal Space ........................................................................................................... 47 6. Processor Mode ______________________________ 48 6.1 Types of Processor Mode ........................................................................................ 48 6.1.1 Single-chip Mode .............................................................................................. 48 6.1.2 Memory Expansion Mode ................................................................................. 48 6.1.3 Microprocessor Mode ....................................................................................... 48 A-1 6.2 Setting Processor Mode .......................................................................................... 48 6.2.1 Applying VSS to CNVSS Pin ............................................................................ 48 6.2.2 Applying VCC to CNVSS Pin ............................................................................ 48 7. Bus................................................................................... 52 7.1 Bus Settings ............................................................................................................. 52 7.1.1 Selecting External Address Bus ...................................................................... 53 7.1.2 Selecting External Data Bus ............................................................................ 53 7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 53 7.2 Bus Control ............................................................................................................... 55 7.2.1 Address Bus and Data Bus .............................................................................. 55 7.2.2 Chip-Select Signal ............................................................................................ 55 7.2.3 Read and Write Signals ..................................................................................... 57 7.2.4 Bus Timing ......................................................................................................... 58 7.2.5 ALE Signal ......................................................................................................... 62 _______ 7.2.6 RDY Signal ......................................................................................................... 62 _________ 7.2.7 HOLD Signal ...................................................................................................... 63 7.2.8 External Bus State when Accessing Internal Space...................................... 64 7.2.9 BCLK Output ..................................................................................................... 64 _______ __________ __________ _____ 7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW) .................................. 64 8. Clock Generation Circuit _______________________ 65 8.1 Types of Clock Generation Circuits........................................................................ 65 8.1.1 Main Clock ......................................................................................................... 74 8.1.2 Sub Clock .......................................................................................................... 75 8.1.3 On-chip Oscillator Clock .................................................................................. 76 8.1.4 PLL Clock .......................................................................................................... 77 8.2 CPU Clock and BCLK .............................................................................................. 79 8.3 Peripheral Function Clock ....................................................................................... 79 8.3.1 f1, f8, f32 and f2n ......................................................................................................................... 79 8.3.2 fAD .................................................................................................................................................... 79 8.3.3 fC32 .................................................................................................................................................. 80 8.4 Clock Output Function ............................................................................................ 80 8.5 Power Consumption Control .................................................................................. 80 8.5.1 Normal Operation Mode ................................................................................... 81 8.5.2 Wait Mode .......................................................................................................... 82 8.5.3 Stop Mode .......................................................................................................... 84 9. Protection ___________________________________ 88 A-2 10. Interrupts___________________________________ 89 10.1 Types of Interrupts ................................................................................................. 89 10.2 Software Interrupts ................................................................................................ 89 10.2.1 Undefined Instruction Interrupt ..................................................................... 89 10.2.2 Overflow Interrupt ........................................................................................... 89 10.2.3 BRK Interrupt .................................................................................................. 89 10.2.4 BRK2 Interrupt ................................................................................................ 90 10.2.5 INT Instruction Interrupt ................................................................................. 90 10.3 Hardware Interrupts ............................................................................................... 90 10.3.1 Special Interrupts ............................................................................................ 90 10.3.2 Peripheral Function Interrupt ........................................................................ 91 10.4 High-Speed Interrupt ............................................................................................. 91 10.5 Interrupts and Interrupt Vectors ........................................................................... 91 10.5.1 Fixed Vector Tables ........................................................................................ 92 10.5.2 Relocatable Vector Tables .............................................................................. 92 10.6 Interrupt Request Reception ................................................................................. 95 10.6.1 I Flag and IPL ................................................................................................... 95 10.6.2 Interrupt Control Register and RLVL Register ............................................. 95 10.6.3 Interrupt Sequence ......................................................................................... 99 10.6.4 Interrupt Response Time .............................................................................. 100 10.6.5 IPL Change when Interrupt Request is Acknowledged ............................. 101 10.6.6 Saving a Register .......................................................................................... 102 10.6.7 Restoration from Interrupt Routine ............................................................. 102 10.6.8 Interrupt Priority ............................................................................................ 103 10.6.9 Interrupt Priority Level Select Circuit ......................................................... 103 ______ 10.7 INT Interrupt .......................................................................................................... 105 ______ 10.8 NMI Interrupt ......................................................................................................... 106 10.9 Key Input Interrupt ............................................................................................... 106 10.10 Address Match Interrupt .................................................................................... 107 10.11 Intelligent I/O Interrupt and CAN Interrupt ....................................................... 108 11. Watchdog Timer ____________________________ 111 12. DMAC_____________________________________ 114 12.1 Transfer Cycles .................................................................................................... 121 12.1.1 Effect of Source and Destination Addresses ............................................. 121 12.1.2 Effect of the DS Register .............................................................................. 121 12.1.3 Effect of Software Wait State ....................................................................... 121 ________ 12.1.4 Effect of RDY Signal ..................................................................................... 121 A-3 12.2 DMAC Transfer Cycles ......................................................................................... 123 12.3 Channel Priority and DMA Transfer Timing ....................................................... 123 13. DMAC II ___________________________________ 125 13.1 DMAC II Settings .................................................................................................. 125 13.1.1 RLVL Register................................................................................................ 125 13.1.2 DMAC II Index ................................................................................................ 127 13.1.3 Interrupt Control Register for the Peripheral Function ............................. 129 13.1.4 Relocatable Vector Table for the Peripheral Function .............................. 129 13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 11)..................................................... 129 13.2 DMAC II Performance .......................................................................................... 129 13.3 Transfer Data ........................................................................................................ 129 13.3.1 Memory-to-Memory Transfer ....................................................................... 129 13.3.2 Immediate Data Transfer .............................................................................. 130 13.3.3 Calculation Transfer ..................................................................................... 130 13.4 Transfer Modes ..................................................................................................... 130 13.4.1 Single Transfer .............................................................................................. 130 13.4.2 Burst Transfer ............................................................................................... 130 13.4.3 Multiple Transfer ........................................................................................... 130 13.4.4 Chained Transfer........................................................................................... 131 13.4.5 End-of-Transfer Interrupt ............................................................................. 131 13.5 Execution Time ..................................................................................................... 132 14. Timer _____________________________________ 133 14.1 Timer A .................................................................................................................. 135 14.1.1 Timer Mode .................................................................................................... 141 14.1.2 Event Counter Mode ..................................................................................... 143 14.1.3 One-shot Timer Mode ................................................................................... 147 14.1.4 Pulse Width Modulation Mode ..................................................................... 149 14.2 Timer B .................................................................................................................. 152 14.2.1 Timer Mode .................................................................................................... 155 14.2.2 Event Counter Mode ..................................................................................... 156 14.2.3 Pulse Period/Pulse Width Measurement Mode .......................................... 158 15. Three-Phase Motor Control Timer Functions ____ 161 16. Serial I/O __________________________________ 172 16.1 Clock Synchronous Serial I/O Mode .................................................................. 182 16.1.1 Selecting CLK Polarity ................................................................................. 186 16.1.2 Selecting LSB First or MSB First ................................................................. 186 16.1.3 Continuous Receive Mode ........................................................................... 187 16.1.4 Serial Data Logic Inverse ............................................................................. 187 A-4 16.2 Clock Asynchronous Serial I/O (UART) Mode ................................................... 188 16.2.1 Bit Rate .......................................................................................................... 192 16.2.2 Selecting LSB First or MSB First ................................................................. 193 16.2.3 Serial Data Logic Inverse ............................................................................. 193 16.2.4 TxD and RxD I/O Polarity Inverse ................................................................ 194 16.3 Special Mode 1 (I2C Mode) .................................................................................. 195 16.3.1 Detecting Start Condition and Stop Condition .......................................... 200 16.3.2 Start Condition or Stop Condition Output .................................................. 201 16.3.3 Arbitration ...................................................................................................... 202 16.3.4 Transfer Clock ............................................................................................... 202 16.3.5 SDA Output .................................................................................................... 202 16.3.6 SDA Input ....................................................................................................... 203 16.3.7 ACK, NACK .................................................................................................... 203 16.3.8 Transmit and Receive Reset ........................................................................ 203 16.4 Special Mode 2 ..................................................................................................... 204 ______ 16.4.1 SSi Input Pin Function (i=0 to 4) .................................................................. 207 16.4.2 Clock Phase Setting Function ..................................................................... 208 16.5 Special Mode 3 (GCI Mode) ................................................................................. 210 16.6 Special Mode 4 (IE Mode) .................................................................................... 214 16.7 Special Mode 5 (SIM Mode) ................................................................................. 218 16.7.1 Parity Error Signal ........................................................................................ 222 16.7.2 Format ............................................................................................................ 223 17. A/D Converter ______________________________ 224 17.1 Mode Description ................................................................................................. 234 17.1.1 One-shot Mode .............................................................................................. 234 17.1.2 Repeat Mode .................................................................................................. 234 17.1.3 Single Sweep Mode ...................................................................................... 235 17.1.4 Repeat Sweep Mode 0 .................................................................................. 235 17.1.5 Repeat Sweep Mode 1 .................................................................................. 236 17.2 Function ................................................................................................................ 236 17.2.1 Resolution Select Function .......................................................................... 236 17.2.2 Sample and Hold ........................................................................................... 236 17.2.3 Trigger Select Function ................................................................................ 236 17.2.4 Two-Circuit Simultaneous Start (Software Trigger) ................................... 237 17.2.5 Pin Input Replacement Function ................................................................. 237 17.2.6 Extended Analog Input Pins ........................................................................ 238 17.2.7 External Operation Amplifier (Op-Amp) Connection Mode....................... 238 17.2.8 Power Consumption Reducing Function ................................................... 239 17.2.9 Analog Input Pin and External Sensor Equivalent Circuit ........................ 239 A-5 18. 19. 20. 21. D/A Converter ______________________________ CRC Calculation ____________________________ X/Y Conversion _____________________________ Intelligent I/O_______________________________ 240 243 245 248 21.1 Base Timer ............................................................................................................ 264 21.2 Time Measurement Function (Group 0 and 1) ................................................... 269 21.3 Waveform Generation Function .......................................................................... 274 21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3) ............................... 276 21.3.2 Phase-Delayed Waveform Output Mode (Group 0 to 3) ............................ 278 21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3) .... 280 21.3.4 Bit Modulation PWM Output Mode (Group 2 and 3) .................................. 283 21.3.5 Real-Time Port (RTP) Output Mode (Group 2 and 3) ................................. 285 21.3.6 Parallel Real-Time Port Output Mode (Group 2 and 3) .............................. 287 21.4 Communication Unit 0 and 1 Communication Function .................................. 289 21.4.1 Clock Synchronous Serial I/O Mode (Groups 0 and 1) .............................. 296 21.4.2 Clock Asynchronous Serial I/O Mode (UART) (Groups 0 and 1) .............. 299 21.4.3 HDLC Data Processing Mode (Group 0 and 1) ........................................... 303 21.5 Group 2 Communication Function ..................................................................... 306 21.5.1 Variable Clock Synchronous Serial I/O Mode (Group 2) ........................... 310 21.5.2 IEBus Mode (Group 2) .................................................................................. 314 21.6 Group 3 Communication Function ..................................................................... 317 21.6.1 8-bit or 16-bit Clock Synchronous Serial I/O Mode (Group 3) .................. 320 22. CAN Module _______________________________ 324 22.1 CAN-Associated Registers .................................................................................. 326 22.1.1 CAN0 Control Register 0 (C0CTLR0 Register) ............................................... 326 22.1.2 CAN0 Control Register 1 (C0CTLR1 Register) ........................................... 329 22.1.3 CAN0 Sleep Control Register (C0SLPR Register) ..................................... 330 22.1.4 CAN0 Status Register (C0STR Register) .................................................... 331 22.1.5 CAN0 Extended ID Register (C0IDR Register) ........................................... 333 22.1.6 CAN0 Configuration Register (C0CONR Register) .................................... 334 22.1.8 CAN0 Transmit Error Count Register (C0TEC Register) ........................... 336 22.1.7 CAN0 Time Stamp Register (C0TSR Register) ........................................... 336 22.1.9 CAN0 Receive Error Count Register (C0REC Register) ............................ 337 22.1.10 CAN0 Baud Rate Prescaler (C0BRP Register) ......................................... 337 22.1.11 CAN0 Slot Interrupt Status Register (C0SISTR Register) ....................... 338 22.1.12 CAN0 Slot Interrupt Mask Register (C0SIMKR Register) ........................ 340 A-6 22.1.13 CAN0 Error Interrupt Mask Register (C0EIMKR Register) ...................... 341 22.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register) ..................... 342 22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask Register B (C0GMRj (j=0 to4), C0LMARj and C0LMBRj Registers) .......... 343 22.1.16 CAN0 Message Slot i Control Register (C0MCTLi Register) (i=0 to 15) ... 346 22.1.17 CAN0 Slot Buffer Select Register (C0SBS Register) ............................... 349 22.1.18 Message Slot Buffer ................................................................................... 349 22.1.19 CAN0 Acceptance Filter Support Register (C0AFS Register)................. 354 22.2.2 CAN Transmit Timing ................................................................................... 355 22.2 Timing with CAN-Associated Registers ............................................................. 355 22.2.1 CAN Module Reset Timing ........................................................................... 355 22.2.3 CAN Receive Timing ..................................................................................... 356 22.2.4 CAN Bus Error Timing .................................................................................. 357 22.3 CAN Interrupts ...................................................................................................... 357 23. DRAMC ___________________________________ 359 23.1 DRAMC Multiplexed Address Output ................................................................. 361 23.2 Refresh .................................................................................................................. 361 23.2.1 Refresh ........................................................................................................... 361 23.2.2 Self-Refresh ................................................................................................... 361 24. Programmable I/O Ports _____________________ 366 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 Port Pi Direction Register (PDi Register, i=0 to 15)........................................... 366 Port Pi Register (Pi Register, i=0 to 15) .............................................................. 366 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9) ............................. 366 Function Select Register Bk (PSLk Register) (k=0 to 3) ................................... 366 Function Select Register C (PSC Register) ....................................................... 367 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) .............................. 367 Port Control Register (PCR Register) ................................................................ 367 Input Function Select Register (IPS Register) ................................................... 367 Analog Input and Other Peripheral Function Input ........................................... 367 25. Flash Memory Version _______________________ 390 25.1 Memory Map ......................................................................................................... 391 25.1.1 Boot Mode ..................................................................................................... 392 25.2 Functions to Prevent the Flash Memory from Rewriting ................................. 392 25.2.1 ROM Code Protect Function ........................................................................ 392 25.2.2 ID Code Verify Function ............................................................................... 392 A-7 25.3 CPU Rewrite Mode ............................................................................................... 394 25.3.1 Flash Memory Control Register 0 (FMR0 Register) ................................... 395 25.3.2 Status Register.............................................................................................. 397 25.3.3 Data Protect Function ................................................................................... 398 25.3.4 How to Enter and Exit CPU Rewrite Mode .................................................. 399 25.3.5 Software Commands .................................................................................... 400 25.3.6 Full Status Check .......................................................................................... 406 25.3.7 Precautions in CPU Rewrite Mode .............................................................. 408 25.4 Standard Serial I/O Mode ..................................................................................... 409 25.4.1 Pin Function .................................................................................................. 409 25.4.2 ID Code Verify Function ............................................................................... 409 25.4.3 Precautions in Standard Serial I/O Mode .................................................... 414 25.4.4 Circuit Application in Standard Serial I/O Mode ........................................ 414 25.5 Parallel I/O Mode .................................................................................................. 415 25.5.1 Boot ROM Area.............................................................................................. 415 25.5.2 ROM Code Protect Function ........................................................................ 415 25.5.3 Precautions on Parallel I/O Mode ................................................................ 415 26. Electrical Characteristics ____________________ 416 26.1 Electrical Characteristics (M32C/83) .................................................................. 416 26.2 Electrical Characteristics (M32C/83T) ................................................................ 453 27. Precautions ________________________________ 462 27.1 Processor Mode ................................................................................................... 462 27.1.1 Microprocessor Mode ................................................................................... 462 27.2 Bus ........................................................................................................................ 463 __________ 27.2.1 HOLD Signal .................................................................................................. 463 27.2.2 External Bus .................................................................................................. 463 27.3 SFR ........................................................................................................................ 464 27.3.1 100-Pin Package ............................................................................................ 464 27.3.2 Register Settings .......................................................................................... 464 27.4 Clock Generation Circuit ..................................................................................... 465 27.4.1 PLL Frequency Synthesizer ......................................................................... 465 27.4.2 Power Consumption Control ....................................................................... 465 27.4.3 Wait Mode ...................................................................................................... 466 27.4.4 Stop Mode ...................................................................................................... 466 27.5 Protection ............................................................................................................. 467 27.6 Interrupts .............................................................................................................. 468 27.6.1 ISP Setting ..................................................................................................... 468 _______ 27.6.2 NMI Interrupt .................................................................................................. 468 A-8 ______ 27.6.3 INT Interrupt .................................................................................................. 468 27.6.4 Watchdog Timer Interrupt ............................................................................ 469 27.6.5 Changing Interrupt Control Register .......................................................... 469 27.6.6 Changing IIOiIR Register (i = 0 to 11) .......................................................... 469 27.6.7 Changing RLVL Register .............................................................................. 469 27.7 DMAC .................................................................................................................... 470 27.8 Timer...................................................................................................................... 471 27.8.1 Timers A and B .............................................................................................. 471 27.8.2 Timer A ........................................................................................................... 471 27.8.3 Timer B ........................................................................................................... 473 27.9 Three-Phase Motor Control Timer Functions .................................................... 474 27.9.1 Changing TAi and TAi1 (i=1, 2, 4) Registers ............................................... 474 27.10 Serial I/O .............................................................................................................. 475 27.10.1 Clock Synchronous Serial I/O Mode ......................................................... 475 27.10.2 UART Mode ................................................................................................. 476 27.10.3 Special Mode 2 ............................................................................................ 476 27.11 A/D Converter .................................................................................................... 477 27.12 Intelligent I/O ...................................................................................................... 479 27.12.1 Register Setting .......................................................................................... 479 27.12.2 BTSR Register Setting ................................................................................ 479 27.13 Programmable I/O Port ...................................................................................... 480 27.14 Flash Memory Version ....................................................................................... 481 27.14.1 Differences Between Flash Memory Version and Masked ROM Version ... 481 27.15 Noise ................................................................................................................... 482 27.16 Low Voltage Operations .................................................................................... 483 Package Dimensions ___________________________ 484 Register Index _________________________________ 486 A-9 Quick Reference by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 Register Page Address Register 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 DRAM Control Register (DRAMCONT) 004116 DRAM Refresh Interval Set Register (REFCNT) 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 Flash Memory Control Register 0 (FMR0) 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 Page Processor Mode Register 0 (PM0) Processor Mode Register 1 (PM1) System Clock Control Register 0 (CM0) System Clock Control Register 1 (CM1) Wait Control Register 1 (WCR) Address Match Interrupt Enable Register (AIER) Protect Register (PRCR) External Data Bus Width Control Register (DS) Main Clock Division Register (MCD) Oscillation Stop Detect Register (CM2) Watchdog Timer Start Register (WDTS) Watchdog Timer Control Register (WDC) Address Match Interrupt Register 0 (RMAD0) 49 50 67 68 58 107 88 52 69 70 112 360 107 Address Match Interrupt Register 1 (RMAD1) VDC Control Register for PLL (PLV) Address Match Interrupt Register 2 (RMAD2) VDC Control Register 0 (VDC0) Address Match Interrupt Register 3 (RMAD3) 107 72 107 107 395 Blank spaces are reserved. No access is allowed. B-1 Quick Reference by Address Address 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 008016 Intelligent I/O Interrupt Control Register 11 (IIO11IC)/ 008116 CAN Interrupt 2 Control Register (CAN2IC) 008216 008316 008416 008516 008616 A/D1 Conversion Interrupt Control Register (AD1IC) 008716 008816 DMA1 Interrupt Control Register (DM1IC) 008916 UART2 Transmit /NACK Interrupt Control Register (S2TIC) 008A16 DMA3 Interrupt Control Register (DM3IC) 008B16 UART3 Transmit /NACK Interrupt Control Register (S3TIC) 008C16 Timer A1 Interrupt Control Register (TA1IC) 008D16 UART4 Transmit /NACK Interrupt Control Register (S4TIC) 008E16 Timer A3 Interrupt Control Register (TA3IC) 008F16 UART2 Bus Conflict Detect Interrupt Control Register (BCN2IC) 96 Register Page Address Register Page 009016 UART0 Transmit /NACK Interrupt Control Register (S0TIC) UART1 Bus Conflict Detect Interrupt Control Register (BCN1IC)/ 009116 UART4 Bus Conflict Detect Interrupt Control Register (BCN4IC) 009216 UART1 Transmit/NACK Interrupt Control Register (S1TIC) 009316 Key Input Interrupt Control Register (KUPIC) 009416 Timer B0 Interrupt Control Register (TB0IC) 96 009516 Intelligent I/O Interrupt Control Register 1 (IIO1IC) 009616 Timer B2 Interrupt Control Register (TB2IC) 009716 Intelligent I/O Interrupt Control Register 3 (IIO3IC) 009816 Timer B4 Interrupt Control Register (TB4IC) 009916 Intelligent I/O Interrupt Control Register 5 (IIO5IC) 009A16 INT4 Interrupt Control Register (INT4IC) 97 009B16 Intelligent I/O Interrupt Control Register 7 (IIO7IC) 96 009C16 INT2 Interrupt Control Register (INT2IC) 97 Intelligent I/O Interrupt Control Register 9 (IIO9IC)/ 009D16 96 CAN Interrupt 0 Control Register (CAN0IC) 009E16 INT0 Interrupt Control Register (INT0IC) 97 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 Exit Priority Control Register (RLVL) Interrupt Request Register 0 (IIO0IR) Interrupt Request Register 1 (IIO1IR) Interrupt Request Register 2 (IIO2IR) Interrupt Request Register 3 (IIO3IR) Interrupt Request Register 4 (IIO4IR) Interrupt Request Register 5 (IIO5IR) Interrupt Request Register 6 (IIO6IR) Interrupt Request Register 7 (IIO7IR) Interrupt Request Register 8 (IIO8IR) Interrupt Request Register 9 (IIO9IR) Interrupt Request Register 10 (IIO10IR) Interrupt Request Register 11 (IIO11IR) 98 DMA0 Interrupt Control Register (DM0IC) Timer B5 Interrupt Control Register (TB5IC) DMA2 Interrupt Control Register (DM2IC) UART2 Receive /ACK Interrupt Control Register (S2RIC) Timer A0 Interrupt Control Register (TA0IC) UART3 Receive /ACK Interrupt Control Register (S3RIC) Timer A2 Interrupt Control Register (TA2IC) UART4 Receive /ACK Interrupt Control Register (S4RIC) Timer A4 Interrupt Control Register (TA4IC) UART0 Bus Conflict Detect Interrupt Control Register (BCN0IC)/ UART3 Bus Conflict Detect Interrupt Control Register (BCN3IC) UART0 Receive/ACK Interrupt Control Register (S0RIC) A/D0 Conversion Interrupt Control Register (AD0IC) UART1 Receive/ACK Interrupt Control Register (S1RIC) Intelligent I/O Interrupt Control Register 0 (IIO0IC) Timer B1 Interrupt Control Register (TB1IC) Intelligent I/O Interrupt Control Register 2 (IIO2IC) Timer B3 Interrupt Control Register (TB3IC) Intelligent I/O Interrupt Control Register 4 (IIO4IC) INT5 Interrupt Control Register (INT5IC) Intelligent I/O Interrupt Control Register 6 (IIO6IC) INT3 Interrupt Control Register (INT3IC) Intelligent I/O Interrupt Control Register 8 (IIO8IC) INT1 Interrupt Control Register (INT1IC) Intelligent I/O Interrupt Control Register 10 (IIO10IC)/ CAN Interrupt 1 Control Register (CAN1IC) 96 109 97 96 97 96 97 96 96 Interrupt Enable Register 0 (IIO0IE) Interrupt Enable Register 1 (IIO1IE) Interrupt Enable Register 2 (IIO2IE) Interrupt Enable Register 3 (IIO3IE) Interrupt Enable Register 4 (IIO4IE) Interrupt Enable Register 5 (IIO5IE) Interrupt Enable Register 6 (IIO6IE) Interrupt Enable Register 7 (IIO7IE) Interrupt Enable Register 8 (IIO8IE) Interrupt Enable Register 9 (IIO9IE) Interrupt Enable Register 10 (IIO10IE) Interrupt Enable Register 11 (IIO11IE) 110 96 Blank spaces are reserved. No access is allowed. B-2 Quick Reference by Address Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 Register Page Group 0 Time Measurement Register 0 (G0TM0)/ Group 0 Waveform Generation Register 0 (G0PO0) Group 0 Time Measurement Register 1 (G0TM1)/ Group 0 Waveform Generation Register 1 (G0PO1) Group 0 Time Measurement Register 2 (G0TM2)/ Group 0 Waveform Generation Register 2 (G0PO2) Group 0 Time Measurement Register 3 (G0TM3)/ Group 0 Waveform Generation Register 3 (G0PO3) 259/ Group 0 Time Measurement Register 4 (G0TM4)/ 261 Group 0 Waveform Generation Register 4 (G0PO4) Group 0 Time Measurement Register 5 (G0TM5)/ Group 0 Waveform Generation Register 5 (G0PO5) Group 0 Time Measurement Register 6 (G0TM6)/ Group 0 Waveform Generation Register 6 (G0PO6) Group 0 Time Measurement Register 7 (G0TM7)/ Group 0 Waveform Generation Register 7 (G0PO7) Group 0 Waveform Generation Control Register 0 (G0POCR0) Group 0 Waveform Generation Control Register 1 (G0POCR1) Group 0 Waveform Generation Control Register 2 (G0POCR2) Group 0 Waveform Generation Control Register 3 (G0POCR3) 259 Group 0 Waveform Generation Control Register 4 (G0POCR4) Group 0 Waveform Generation Control Register 5 (G0POCR5) Group 0 Waveform Generation Control Register 6 (G0POCR6) Group 0 Waveform Generation Control Register 7 (G0POCR7) Group 0 Time Measurement Control Register 0 (G0TMCR0) Group 0 Time Measurement Control Register 1 (G0TMCR1) Group 0 Time Measurement Control Register 2 (G0TMCR2) Group 0 Time Measurement Control Register 3 (G0TMCR3) 258 Group 0 Time Measurement Control Register 4 (G0TMCR4) Group 0 Time Measurement Control Register 5 (G0TMCR5) Group 0 Time Measurement Control Register 6 (G0TMCR6) Group 0 Time Measurement Control Register 7 (G0TMCR7) Group 0 Base Timer Register (G0BT) Group 0 Base Timer Control Register 0 (G0BCR0) Group 0 Base Timer Control Register 1 (G0BCR1) Group 0 Time Measurement Prescaler Register 6 (G0TPR6) Group 0 Time Measurement Prescaler Register 7 (G0TPR7) Group 0 Function Enable Register (G0FE) Group 0 Function Select Register (G0FS) Group 0 SI/O Receive Buffer Register (G0RB) Group 0 Transmit Buffer/Receive Data Register (G0TB/G0DR) Group 0 Receive Input Register (G0RI) Group 0 SI/O Communication Mode Register (G0MR) Group 0 Transmit Output Register (G0TO) Group 0 SI/O Communication Control Register (G0CR) 253 254 258 262 291 294 289 291 289 290 Address 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 Register Group 0 Data Compare Register 0 (G0CMP0) Group 0 Data Compare Register 1 (G0CMP1) Group 0 Data Compare Register 2 (G0CMP2) Group 0 Data Compare Register 3 (G0CMP3) Group 0 Data Mask Register 0 (G0MSK0) Group 0 Data Mask Register 1 (G0MSK1) Page 295 Group 0 Receive CRC Code Register (G0RCRC) 295 Group 0 Transmit CRC Code Register (G0TCRC) Group 0 SI/O Extended Mode Register (G0EMR) Group 0 SI/O Extended Receive Control Register (G0ERC) Group 0 SI/O Special Communication Interrupt Detect Register (G0IRF) Group 0 SI/O Extended Transmit Control Register (G0ETC) Group 1 Time Measurement Register 0 (G1TM0)/ Group 1 Waveform Generation Register 0 (G1PO0) Group 1 Time Measurement Register 1 (G1TM1)/ Group 1 Waveform Generation Register 1 (G1PO1) Group 1 Time Measurement Register 2 (G1TM2)/ Group 1 Waveform Generation Register 2 (G1PO2) Group 1 Time Measurement Register 3 (G1TM3)/ Group 1 Waveform Generation Register 3 (G1PO3) Group 1 Time Measurement Register 4 (G1TM4)/ Group 1 Waveform Generation Register 4 (G1PO4) Group 1 Time Measurement Register 5 (G1TM5)/ Group 1 Waveform Generation Register 5 (G1PO5) Group 1 Time Measurement Register 6 (G1TM6)/ Group 1 Waveform Generation Register 6 (G1PO6) Group 1 Time Measurement Register 7 (G1TM7)/ Group 1 Waveform Generation Register 7 (G1PO7) Group 1 Waveform Generation Control Register 0 (G1POCR0) Group 1 Waveform Generation Control Register 1 (G1POCR1) Group 1 Waveform Generation Control Register 2 (G1POCR2) Group 1 Waveform Generation Control Register 3 (G1POCR3) Group 1 Waveform Generation Control Register 4 (G1POCR4) Group 1 Waveform Generation Control Register 5 (G1POCR5) Group 1 Waveform Generation Control Register 6 (G1POCR6) Group 1 Waveform Generation Control Register 7 (G1POCR7) Group 1 Time Measurement Control Register 0 (G1TMCR0) Group 1 Time Measurement Control Register 1 (G1TMCR1) Group 1 Time Measurement Control Register 2 (G1TMCR2) Group 1 Time Measurement Control Register 3 (G1TMCR3) Group 1 Time Measurement Control Register 4 (G1TMCR4) Group 1 Time Measurement Control Register 5 (G1TMCR5) Group 1 Time Measurement Control Register 6 (G1TMCR6) Group 1 Time Measurement Control Register 7 (G1TMCR7) 292 293 294 292 259/ 261 259 258 Blank spaces are reserved. No access is allowed. B-3 Quick Reference by Address Address 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 Register Group 1 Base Timer Register (G1BT) Group 1 Base Timer Control Register 0 (G1BCR0) Group 1 Base Timer Control Register 1 (G1BCR1) Group 1 Time Measurement Prescaler Register 6 (G1TPR6) Group 1 Time Measurement Prescaler Register 7 (G1TPR7) Group 1 Function Enable Register (G1FE) Group 1 Function Select Register (G1FS) Group 1 SI/O Receive Buffer Register (G1RB) Group 1 Transmit Buffer/Receive Data Register (G1TB/G1DR) Group 1 Receive Input Register (G1RI) Group 1 SI/O Communication Mode Register (G1MR) Group 1 Transmit Output Register (G1TO) Group 1 SI/O Communication Control Register (G1CR) Group 1 Data Compare Register 0 (G1CMP0) Group 1 Data Compare Register 1 (G1CMP1) Group 1 Data Compare Register 2 (G1CMP2) Group 1 Data Compare Register 3 (G1CMP3) Group 1 Data Mask Register 0 (G1MSK0) Group 1 Data Mask Register 1 (G1MSK1) Page 253 254 258 262 291 294 289 291 289 290 Address 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 017916 017A16 017B16 017C16 017D16 017E16 017F16 Register Page Group 2 Waveform Generation Control Register 0 (G2POCR0) Group 2 Waveform Generation Control Register 1 (G2POCR1) Group 2 Waveform Generation Control Register 2 (G2POCR2) Group 2 Waveform Generation Control Register 3 (G2POCR3) 260 Group 2 Waveform Generation Control Register 4 (G2POCR4) Group 2 Waveform Generation Control Register 5 (G2POCR5) Group 2 Waveform Generation Control Register 6 (G2POCR6) Group 2 Waveform Generation Control Register 7 (G2POCR7) Group 2 Base Timer Register (G2BT) Group 2 Base Timer Control Register 0 (G2BCR0) Group 2 Base Timer Control Register 1 (G2BCR1) Base Timer Start Register (BTSR) Group 2 Function Enable Register (G2FE) Group 2 RTP Output Buffer Register (G2RTP) 253 255 257 262 263 295 Group 1 Receive CRC Code Register (G1RCRC) 295 Group 1 Transmit CRC Code Register (G1TCRC) Group 1 SI/O Extended Mode Register (G1EMR) Group 1 SI/O Extended Receive Control Register (G1ERC) Group 1 SI/O Special Communication Interrupt Detect Register (G1IRF) Group 1 SI/O Extended Transmit Control Register (G1ETC) Group 2 Waveform Generation Register 0 (G2PO0) Group 2 Waveform Generation Register 1 (G2PO1) Group 2 Waveform Generation Register 2 (G2PO2) Group 2 Waveform Generation Register 3 (G2PO3) 261 Group 2 Waveform Generation Register 4 (G2PO4) Group 2 Waveform Generation Register 5 (G2PO5) Group 2 Waveform Generation Register 6 (G2PO6) Group 2 Waveform Generation Register 7 (G2PO7) 292 293 294 292 Group 2 SI/O Communication Mode Register (G2MR) Group 2 SI/O Communication Control Register (G2CR) Group 2 SI/O Transmit Buffer Register (G2TB) 307 306 Group 2 SI/O Receive Buffer Register (G2RB) Group 2 IEBus Address Register (IEAR) Group 2 IEBus Control Register (IECR) Group 2 IEBus Transmit Interrupt Cause Detect Register (IETIF) Group 2 IEBus Receive Interrupt Cause Detect Register (IERIF) 308 309 Input Function Select Register (IPS) Group 3 SI/O Communication Mode Register (G3MR) Group 3 SI/O Communication Control Register (G3CR) Group 3 SI/O Transmit Buffer Register (G3TB) 383 318 317 Group 3 SI/O Receive Buffer Register (G3RB) Blank spaces are reserved. No access is allowed. B-4 Quick Reference by Address Address 018016 018116 018216 018316 018416 018516 018616 018716 018816 018916 018A16 018B16 018C16 018D16 018E16 018F16 019016 019116 019216 019316 019416 019516 019616 019716 019816 019916 019A16 019B16 019C16 019D16 019E16 019F16 01A016 01A116 01A216 01A316 01A416 01A516 01A616 01A716 01A816 01A916 01AA16 01AB16 01AC16 01AD16 01AE16 01AF16 Register Group 3 Waveform Generation Register 0 (G3PO0) Group 3 Waveform Generation Register 1 (G3PO1) Group 3 Waveform Generation Register 2 (G3PO2) Group 3 Waveform Generation Register 3 (G3PO3) 261 Group 3 Waveform Generation Register 4 (G3PO4) Group 3 Waveform Generation Register 5 (G3PO5) Group 3 Waveform Generation Register 6 (G3PO6) Group 3 Waveform Generation Register 7 (G3PO7) Group 3 Waveform Generation Control Register 0 (G3POCR0) Group 3 Waveform Generation Control Register 1 (G3POCR1) Group 3 Waveform Generation Control Register 2 (G3POCR2) Group 3 Waveform Generation Control Register 3 (G3POCR3) Group 3 Waveform Generation Control Register 4 (G3POCR4) Group 3 Waveform Generation Control Register 5 (G3POCR5) Group 3 Waveform Generation Control Register 6 (G3POCR6) Group 3 Waveform Generation Control Register 7 (G3POCR7) Group 3 Waveform Generation Mask Register 4 (G3MK4) Group 3 Waveform Generation Mask Register 5 (G3MK5) 261 Group 3 Waveform Generation Mask Register 6 (G3MK6) Group 3 Waveform Generation Mask Register 7 (G3MK7) Group 3 Base Timer Register (G3BT) Group 3 Base Timer Control Register 0 (G3BCR0) Group 3 Base Timer Control Register 1 (G3BCR1) Page Address 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 01C016 01C116 01C216 01C316 01C416 01C516 01C616 01C716 01C816 01C916 01CA16 01CB16 01CC16 01CD16 01CE16 01CF16 01D016 01D116 01D216 01D316 01D416 01D516 01D616 01D716 01D816 01D916 01DA16 01DB16 01DC16 01DD16 01DE16 01DF16 Register Page A/D1 Register 0 (AD10) A/D1 Register 1 (AD11) A/D1 Register 2 (AD12) A/D1 Register 3 (AD13) 233 A/D1 Register 4 (AD14) A/D1 Register 5 (AD15) A/D1 Register 6 (AD16) A/D1 Register 7 (AD17) 260 253 256 A/D1 Control Register 2 (AD1CON2) A/D1 Control Register 0 (AD1CON0) A/D1 Control Register 1 (AD1CON1) 233 231 232 Group 3 Function Enable Register 1 (G3FE) Group 3 RTP Output Buffer Register 1 (G3RTP) 262 263 Group 3 SI/O Communication Flag Register (G3FLG) 319 Blank spaces are reserved. No access is allowed. B-5 Quick Reference by Address Address 01E016 01E116 01E216 01E316 01E416 01E516 01E616 01E716 01E816 01E916 01EA16 01EB16 01EC16 01ED16 01EE16 01EF16 01F016 01F116 01F216 01F316 01F416 01F516 01F616 01F716 01F816 01F916 01FA16 01FB16 01FC16 01FD16 01FE16 01FF16 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 Register Page CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0) 350 CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1) CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2) 351 CAN0 Message Slot Buffer 0 Extended ID1 (C0SLOT0_3) CAN0 Message Slot Buffer 0 Extended ID2 (C0SLOT0_4) 352 CAN0 Message Slot Buffer 0 Data Length Code (C0SLOT0_5) CAN0 Message Slot Buffer 0 Data 0 (C0SLOT0_6) CAN0 Message Slot Buffer 0 Data 1 (C0SLOT0_7) CAN0 Message Slot Buffer 0 Data 2 (C0SLOT0_8) CAN0 Message Slot Buffer 0 Data 3 (C0SLOT0_9) CAN0 Message Slot Buffer 0 Data 4 (C0SLOT0_10) 353 CAN0 Message Slot Buffer 0 Data 5 (C0SLOT0_11) CAN0 Message Slot Buffer 0 Data 6 (C0SLOT0_12) CAN0 Message Slot Buffer 0 Data 7 (C0SLOT0_13) CAN0 Message Slot Buffer 0 Time Stamp High-Order (C0SLOT0_14) CAN0 Message Slot Buffer 0 Time Stamp Low-Order (C0SLOT0_15) CAN0 Message Slot Buffer 1 Standard ID0 (C0SLOT1_0) 350 CAN0 Message Slot Buffer 1 Standard ID1 (C0SLOT1_1) CAN0 Message Slot Buffer 1 Extended ID0 (C0SLOT1_2) 351 CAN0 Message Slot Buffer 1 Extended ID1 (C0SLOT1_3) CAN0 Message Slot Buffer 1 Extended ID2 (C0SLOT1_4) 352 CAN0 Message Slot Buffer 1 Data Length Code (C0SLOT1_5) CAN0 Message Slot Buffer 1 Data 0 (C0SLOT1_6) CAN0 Message Slot Buffer 1 Data 1 (C0SLOT1_7) CAN0 Message Slot Buffer 1 Data 2 (C0SLOT1_8) CAN0 Message Slot Buffer 1 Data 3 (C0SLOT1_9) CAN0 Message Slot Buffer 1 Data 4 (C0SLOT1_10) 353 CAN0 Message Slot Buffer 1 Data 5 (C0SLOT1_11) CAN0 Message Slot Buffer 1 Data 6 (C0SLOT1_12) CAN0 Message Slot Buffer 1 Data 7 (C0SLOT1_13) CAN0 Message Slot Buffer 1 Time Stamp High-Order (C0SLOT1_14) CAN0 Message Slot Buffer 1 Time Stamp Low-Order (C0SLOT1_15) CAN0 Control Register0 (C0CTLR0) CAN0 Status Register (C0STR) CAN0 Extended ID Register (C0IDR) CAN0 Configuration Register (C0CONR) CAN0 Time Stamp Register (C0TSR) CAN0 Transmit Error Count Register (C0TEC) CAN0 Receive Error Count Register (C0REC) CAN0 Slot Interrupt Status Register (C0SISTR) 326 331 333 334 Address 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 Register CAN0 Slot Interrupt Mask Register (C0SIMKR) Page 340 CAN0 Error Interrupt Mask Register (C0EIMKR) CAN0 Error Interrupt Status Register (C0EISTR) CAN0 Baud Rate Prescaler (C0BPR) 341 342 337 CAN0 Global Mask Register Standard ID0 (C0GMR0) CAN0 Global Mask Register Standard ID1 (C0GMR1) CAN0 Global Mask Register Extended ID0 (C0GMR2) CAN0 Global Mask Register Extended ID1 (C0GMR3) CAN0 Global Mask Register Extended ID2 (C0GMR4) 343 344 345 336 337 338 CAN0 Message Slot 0 Control Register (C0MCTL0)/ CAN0 Local Mask Register A Standard ID0 (C0LMAR0) CAN0 Message Slot 1 Control Register (C0MCTL1)/ CAN0 Local Mask Register A Standard ID1 (C0LMAR1) CAN0 Message Slot 2 Control Register (C0MCTL2)/ CAN0 Local Mask Register A Extended ID0 (C0LMAR2) CAN0 Message Slot 3 Control Register (C0MCTL3)/ CAN0 Local Mask Register A Extended ID1 (C0LMAR3) CAN0 Message Slot 4 Control Register (C0MCTL4)/ CAN0 Local Mask Register A Extended ID2 (C0LMAR4) CAN0 Message Slot 5 Control Register (C0MCTL5) CAN0 Message Slot 6 Control Register (C0MCTL6) CAN0 Message Slot 7 Control Register (C0MCTL7) CAN0 Message Slot 8 Control Register (C0MCTL8)/ CAN0 Local Mask Register B Standard ID0 (C0LMBR0) 346/ 343 344/ 346/ 345 346/ 346 346/ 343 Blank spaces are reserved. No access is allowed. B-6 Quick Reference by Address Address 023916 023A16 023B16 023C16 Register Page CAN0 Message Slot 9 Control Register (C0MCTL9)/ CAN0 Local Mask Register B Standard ID1 (C0LMBR1) 344 CAN0 Message Slot 10 Control Register (C0MCTL10)/ 346/ CAN0 Local Mask Register B Extended ID0 (C0LMBR2) CAN0 Message Slot 11 Control Register (C0MCTL11)/ CAN0 Local Mask Register B Extended ID1 (C0LMBR3) 345 CAN0 Message Slot 12 Control Register (C0MCTL12)/ 346/ CAN0 Local Mask Register B Extended ID2 (C0LMBR4) CAN0 Message Slot 13 Control Register (C0MCTL13) CAN0 Message Slot 14 Control Register (C0MCTL14) 346 CAN0 Message Slot 15 Control Register(C0MCTL15) CAN0 Slot Buffer Select Register (C0SBS) 349 CAN0 Control Register 1 (C0CTLR1) 329 CAN0 Sleep Control Register (C0SLPR) 330 Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 Register X0 Register Y0 Register (X0R,Y0R) X1 Register Y1 Register (X1R,Y1R) X2 Register Y2 Register (X2R,Y2R) X3 Register Y3 Register (X3R,Y3R) X4 Register Y4 Register (X4R,Y4R) X5 Register Y5 Register (X5R,Y5R) X6 Register Y6 Register (X6R,Y6R) X7 Register Y7 Register (X7R,Y7R) 246 X8 Register Y8 Register (X8R,Y8R) X9 Register Y9 Register (X9R,Y9R) X10 Register Y10 Register (X10R,Y10R) X11 Register Y11 Register (X11R,Y11R) X12 Register Y12 Register (X12R,Y12R) X13 Register Y13 Register (X13R,Y13R) X14 Register Y14 Register (X14R,Y14R) X15 Register Y15 Register (X15R,Y15R) XY Control Register (XYC) 245 Page 023D16 023E16 023F16 024016 024116 024216 024316 024416 CAN0 Acceptance Filter Support Register (C0AFS) 024516 354 UART1 Special Mode Register 4 (U1SMR4) UART1 Special Mode Register 3 (U1SMR3) UART1 Special Mode Register 2 (U1SMR2) UART1 Special Mode Register (U1SMR) UART1 Transmit/Receive Mode Register (U1MR) UART1 Baud Rate Register (U1BRG) UART1 Transmit Buffer Register (U1TB) UART1 Transmit/Receive Control Register 0 (U1C0) UART1 Transmit/Receive Control Register 1 (U1C1) UART1 Receive Buffer Register (U1RB) 180 179 178 177 175 174 176 177 174 Blank spaces are reserved. No access is allowed. B-7 Quick Reference by Address Address 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 Register Page Address 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 Register Page UART4 Special Mode Register 4 (U4SMR4) UART4 Special Mode Register 3 (U4SMR3) UART4 Special Mode Register 2 (U4SMR2) UART4 Special Mode Register (U4SMR) UART4 Transmit/Receive Mode Register (U4MR) UART4 Baud Rate Register (U4BRG) UART4 Transmit Buffer Register (U4TB) UART4 Transmit/Receive Control Register 0 (U4C0) UART4 Transmit/Receive Control Register 1 (U4C1) UART4 Receive Buffer Register (U4RB) Timer B3,B4,B5 Count Start Flag (TBSR) 180 179 178 177 175 174 176 177 174 154 UART3 Special Mode Register 4 (U3SMR4) UART3 Special Mode Register 3 (U3SMR3) UART3 Special Mode Register 2 (U3SMR2) UART3 Special Mode Register (U3SMR) UART3 Transmit/Receive Mode Register (U3MR) UART3 Baud Rate Register (U3BRG) UART3 Transmit Buffer Register (U3TB) UART3 Transmit/Receive Control Register 0 (U3C0) UART3 Transmit/Receive Control Register 1 (U3C1) UART3 Receive Buffer Register (U3RB) 180 179 178 177 175 174 176 177 174 Timer A1-1 Register (TA11) Timer A2-1 Register (TA21) Timer A4-1 Register (TA41) Three-Phase PWM Control Register 0 (INVC0) Three-Phase PWM Control Register 1 (INVC1) Three-Phase Output Buffer Register 0 (IDB0) Three-Phase Output Buffer Register 1 (IDB1) Dead Time Timer (DTT) Timer B2 Interrupt Generation Frequency Set Counter (ICTB2) 164 165 166 167 167 UART2 Special Mode Register 4 (U2SMR4) UART2 Special Mode Register 3 (U2SMR3) UART2 Special Mode Register 2 (U2SMR2) UART2 Special Mode Register (U2SMR) UART2 Transmit/Receive Mode Register (U2MR) UART2 Baud Rate Register (U2BRG) UART2 Transmit Buffer Register (U2TB) UART2 Transmit/Receive Control Register 0 (U2C0) UART2 Transmit/Receive Control Register 1 (U2C1) UART2 Receive Buffer Register (U2RB) Count Start Flag (TABSR) Clock Prescaler Reset Flag (CPSRF) One-Shot Start Flag (ONSF) Trigger Select Register (TRGSR) Up-Down Flag (UDF) 180 179 178 177 175 174 176 177 174 137 71 138 139 138 Timer B3 Register (TB3) Timer B4 Register (TB4) Timer B5 Register (TB5) 152 Timer A0 Register (TA0) Timer A1 Register (TA1) Timer A2 Register (TA2) Timer A3 Register (TA3) Timer A4 Register (TA4) 136 Timer B3 Mode Register (TB3MR) Timer B4 Mode Register (TB4MR) Timer B5 Mode Register (TB5MR) External Interrupt Cause Select Register (IFSR) 153 105 Blank spaces are reserved. No access is allowed. B-8 Quick Reference by Address Address 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Register Timer B0 Register (TB0) Timer B1 Register (TB1) Timer B2 Register (TB2) Timer A0 Mode Register (TA0MR) Timer A1 Mode Register (TA1MR) Timer A2 Mode Register (TA2MR) Timer A3 Mode Register (TA3MR) Timer A4 Mode Register (TA4MR) Timer B0 Mode Register (TB0MR) Timer B1 Mode Register (TB1MR) Timer B2 Mode Register (TB2MR) Timer B2 Special Mode Register (TB2SC) Count Source Prescaler Register (TCSPR) 152 Page Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 Register A/D0 Register0 (AD00) A/D0 Register1 (AD01) A/D0 Register2 (AD02) A/D0 Register3 (AD03) 230 A/D0 Register4 (AD04) A/D0 Register5 (AD05) A/D0 Register6 (AD06) A/D0 Register7 (AD07) Page 137 153 167 71 UART0 Special Mode Register 4 (U0SMR4) UART0 Special Mode Register 3 (U0SMR3) UART0 Special Mode Register 2 (U0SMR2) UART0 Special Mode Register (U0SMR) UART0 Transmit/Receive Mode Register (U0MR) UART0 Baud Rate Register (U0BRG) UART0 Transmit Buffer Register (U0TB) UART0 Transmit/Receive Control Register 0 (U0C0) UART0 Transmit/Receive Control Register 1 (U0C1) UART0 Receive Buffer Register (U0RB) 180 179 178 177 175 174 176 177 174 A/D0 Control Register 2 (AD0CON2) A/D0 Control Register 0 (AD0CON0) A/D0 Control Register 1 (AD0CON1) D/A Register 0 (DA0) D/A Register 1 (DA1) D/A Control Register (DACON) 230 228 229 242 242 242 PLL Control Register 0 (PLC0) PLL Control Register 1 (PLC1) DMA0 Cause Select Register (DM0SL) DMA1 Cause Select Register (DM1SL) DMA2 Cause Select Register (DM2SL) DMA3 Cause Select Register (DM3SL) CRC Data Register (CRCD) CRC Input Register (CRCIN) 72 73 116 243 Blank spaces are reserved. No access is allowed. B-9 Quick Reference by Address Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 Register Function Select Register A8 (PS8) Function Select Register A9 (PS9) Page 376 377 Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register Port P14 Register (P14) Port P15 Register (P15) Port P14 Direction Register (PD14) Port P15 Direction Register (PD15) Page 372 371 Pull-Up Control Register 2 (PUR2) Pull-Up Control Register 3 (PUR3) Pull-Up Control Register 4 (PUR4) 381 382 Function Select Register C (PSC) Function Select Register A0 (PS0) Function Select Register A1 (PS1) Function Select Register B0 (PSL0) Function Select Register B1 (PSL1) Function Select Register A2 (PS2) Function Select Register A3 (PS3) Function Select Register B2 (PSL2) Function Select Register B3 (PSL3) Function Select Register A5 (PS5) 380 373 378 374 379 Port P14 Register (P0) Port P14 Register (P1) Port P14 Direction Register (PD0) Port P14 Direction Register (PD1) Port P14 Register (P2) Port P14 Register (P3) Port P14 Direction Register (PD2) Port P14 Direction Register (PD3) Port P14 Register (P4) Port P14 Register (P5) Port P14 Direction Register (PD4) Port P14 Direction Register (PD5) 372 371 372 371 372 371 375 Function Select Register A6 (PS6) Function Select Register A7 (PS7) 375 376 Port P6 Register (P6) Port P7 Register (P7) Port P6 Direction Register (PD6) Port P7 Direction Register (PD7) Port P8 Register (P8) Port P9 Register (P9) Port P8 Direction Register (PD8) Port P9 Direction Register (PD9) Port P10 Register (P10) Port P11 Register (P11) Port P10 Direction Register (PD10) Port P11 Direction Register(PD11) Port P12 Register (P12) Port P13 rRegister (P13) Port P12 Direction Register (PD12) Port P13 Direction Register (PD13) 372 371 372 371 372 371 372 371 Pull-Up Control Register 0 (PUR0) Pull-Up Control Register 1 (PUR1) 381 Port Control Register (PCR) 383 Blank spaces are reserved. No access is allowed. B-10 M32C/83 Group (M32C/83, M32C/83T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/83 Group (M32C/83, M32C/83T) microcomputer is a single-chip control unit that utilizes highperformance silicon gate CMOS technology with the M32C/80 Series CPU core. The M32C/83 Group (M32C/83, M32C/83T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office automation, communication devices and industrial equipments, and other high-speed processing applications. 1.1 Applications Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 1 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview 1.2 Performance Overview Tables 1.1 and 1.2 list performance overview of the M32C/83 Group (M32C/83, M32C/83T). Table 1.1 M32C/83 Group (M32C/83, M32C/83T) Performance (144-Pin Package) Characteristic CPU Basic Instructions M32C/83 108 instructions Performance M32C/83T Minimum Instruction Execution Time 31.3 ns (f(BCLK)=32 MHz, VCC=4.2 to 5.5 V)(3) 31.3 ns (f(BCLK)=32 MHz, VCC=4.2 to 5.5 V)(3) 50 ns (f(BCLK)=20 MHz, VCC=3.0 to 5.5 V) Operating Mode Address Space Memory Capacity Peripheral I/O Port Function Multifunction Timer Intelligent I/O Single-chip mode, Memory expansion Single-chip mode mode and Microprocessor mode 16 Mbytes See Table 1.3 123 I/O pins and 1 input pin Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Time measurement function: 16 bits x 12 channels Waveform generating function: 16 bits x 28 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1), 8-bit or 16-bit Clock synchronous serial I/O) 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) 1 channel Supporting CAN 2.0B specification 10-bit A/D converter: 2 circuit, 34 channels 8 bits x 2 channels 4 channels Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CAS before RAS refresh, Self-reflesh, EDO, EP CRC-CCITT 16 bits x 16 bits 15 bits x 1 channel (with prescaler) 42 internal and 8 external sources, 5 software sources, Interrupt priority level: 7 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Main clock oscillation stop detect function 4.2 to 5.5 V (f(BCLK)=32 MHz) 4.2 to 5.5 V (f(BCLK)=32 MHz) 3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC) 3.0 to 3.6 V (f(BCLK)=20 MHz, not through VDC) 41 mA (VCC=5 V, f(BCLK)=32 MHz) 41 mA (VCC=5 V, f(BCLK)=32 MHz) 38 mA (VCC=5 V, f(BCLK)=30 MHz) 38 mA (VCC=5 V, Vf(BCLK)=30 MHz) 26 mA (VCC=3.3 V, f(BCLK)=20 MHz) 470 µA (VCC=5 V, f(XCIN)=32 kHz, 470 µA (VCC=5 V, f(XCIN)=32 kHz, in wait mode) in wait mode) 0.4 µA (VCC=5 V, stop mode) 340 µA (VCC=3.3 V, f(XCIN)=32 kHz, through VDC, in wait mode) 5.0 µA (VCC=3.3 V, f(XCIN)=32 kHz, not through VDC, in wait mode) 0.4 µA (VCC=5 V, stop mode) 0.4 µA (VCC=3.3 V, stop mode) 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V 100 times –20 to 85oC, –40 to 85oC (optional) –40 to 85oC (T version) 144-pin plastic molded LQFP Serial I/O CAN Module A/D Converter D/A Converter DMAC DMAC II DRAM CRC Calculation Circuit X/Y Converter Watchdog Timer Interrupt Clock Generation Circuit Oscillation Stop Detect Function Electrical Supply Voltage Characteristics Power Consumption Flash Program/Erase Supply Voltage Memory Program and Erase Endurance Operating Ambient Temperature Package NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. Contact our sales office if 30-MHz or higher frequency is required. All options are on a request basis. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 2 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance (100-Pin Package) Characteristic M32C/83 CPU Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space Memory Capacity I/O Port Multifunction Timer Intelligent I/O Performance M32C/83T 108 instructions 31.3 ns (f(BCLK) = 32 MHz, VCC = 4.2 to 5.5 V) 31.3 ns (f(BCLK) = 32 MHz, V CC=4.2 to 5.5 V) 50 ns (f(BCLK) = 20 MHz, VCC = 3.0 to 5.5 V) Single-chip mode, Memory expansion Single-chip mode mode and Microprocessor mode 16 Mbytes See Table 1.3 87 I/O pins and 1 input pin Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Time measurement function: 16 bits x 5 channels Waveform generating function: 16 bits x 10 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1)) 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) 1 channel Supporting CAN 2.0B specification 10-bit A/D converter: 2 circuits, 26 channels 8 bits x 2 channels 4 channels Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC-CCITT 16 bits x 16 bits 15 bits x 1 channel (with prescaler) 42 internal and 8 external sources, 5 software sources Interrupt priority level: 7 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Main clock oscillation stop detect function 4.2 to 5.5 V (f(BCLK)=32 MHz) 4.2 to 5.5 V (f(BCLK)=32 MHz) 3.0 to 5.5 V (f(BCLK)=20 MHz, through VDC) 3.0 to 3.6 V (f(BCLK)=20 MHz, not through VDC) 41 mA (VCC=5 V, f(BCLK)=32 MHz) 41 mA (VCC=5 V, f(BCLK)=32 MHz) 38 mA (VCC=5 V, f(BCLK)=30 MHz) 38 mA (VCC=5 V, Vf(BCLK)=30 MHz) 26 mA (VCC=3.3 V, f(BCLK)=20 MHz) 470 µA (VCC=5 V, f(XCIN)=32 kHz, in wait mode) 470 µA (VCC=5 V, f(XCIN)=32 kHz, in wait mode) 0.4 µA (VCC=5 V, stop mode) 340 µA (VCC=3.3 V, f(XCIN)=32 kHz, through VDC, in wait mode) 5.0 µA (VCC=3.3 V, f(XCIN)=32 kHz, not through VDC, in wait mode) 0.4 µA (VCC=5 V, stop mode) 0.4 µA (VCC=3.3 V, stop mode) 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V 100 times –20 to 85oC, –40 to 85oC (optional) –40 to 85oC (T version) 100-pin plastic molded LQFP/QFP Peripheral Function Serial I/O CAN Module A/D Converter D/A Converter DMAC DMAC II CRC Calculation Circuit X/Y Converter Watchdog Timer Interrupt Clock Generation Circuit Oscillation Stop Detect Function Electrical Supply Voltage Characteristics Power Consumption Flash Program/Erase Supply Voltage Memory Program and Erase Endurance Operating Ambient Temperature Package NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. Contact our sales office if 30-MHz or higher frequency is required. All options are on a request basis. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 3 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview 1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/83 Group (M32C/83, M32C/83T) microcomputer. 8 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Peripheral Functions Timer (16 bits) Timer A: 5 channels Timer B: 6 channels Three-phase Motor Control Circuit Watchdog Timer (15 bits) D/A Converter (8 bits x 2 channels) A/D Converter: 2 circuits Standard: 18 inputs(2) Maximum: 34 inputs(2) UART/Clock Synchronous Serial I/O: 5 channels X/Y Converter: 16 bits x 16 bits CRC Calculation Circuit (CCITT): X16+X12+X5+1 Clock Generation Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer DMAC DMACII DRAMC Intelligent I/O ( 4 Groups ) Time Measurement: 12 channels(2) Wave Generating: 28 channels(2) Communication Functions: Clock Synchronous Serial I/O, UART, IEBus, HDLC Data Processing, 8-bit or 16-bit Clock Synchronous Serial I/O(3) CAN Module M32C/80 Series CPU Core R0H R1H R2 R3 A0 A1 FB SB R0L R1L FLG INTB ISP USP PC SVF SVP VCT Memory ROM RAM Multiplier Port P15 Port P14 Port P13 Port P12 Port P11 Port P10 Port P9 P85 Port P8 8 7 8 8 5 8 8 7 (Note1) NOTES: 1. Ports P11 to P15 are provided only in the 144-pin package. 2. Included only in the 144-pin package. 3. Can be used only in the 144-pin package. Figure 1.1 M32C/83 Group (M32C/83, M32C/83T) Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 4 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview 1.4 Product Information Table 1.3 lists the product information. Figure 1.2 shows the product numbering system. Table 1.3 M32C/83 Group (1) (M32C/83) Type Number M30835FJGP M30833FJGP M30833FJFP Package Type PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) 512K 31K Flash Memory ROM Capacity As of January, 2006 RAM Capacity Remarks Table 1.3 M32C/83 Group (2) (T Version, M32C/83T) Type Number Package Type ROM Capacity As of January, 2006 RAM Capacity Remarks Flash Memory T Version (High-reliability 85oC Version) M30833FJTGP PLQP0100KB-A (100P6Q-A) 512K 31K Please contact our sales office for V version information. M30 83 3 F J GP Package Type: FP = Package PRQP0100JB-A (100P6S-A) GP = Package PLQP0100KB-A (100P6Q-A) Package PLQP0144KA-A (144P6Q-A) Classification: Blank = General Industrial Use T = T Version ROM Capacity: J = 512 Kbytes Memory Type: F = Flash Memory Version RAM Capacity, Pin Count, etc. (Value itself has no specific meaning) M32C/83 Group M16C Family Figure 1.2 Product Numbering System Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 5 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview 1.5 Pin Assignment Figures 1.3 to 1.5 show pin assignments (top view). 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 D8 / P10 AN07 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC13 / P113 BE1IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1OUT / ISTxD1 / OUTC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 INPC07 / AN157 / P157 INPC06 / AN156 / P156 OUTC05 / INPC05 / AN155 / P155 OUTC04 / INPC04 / AN154 / P154 INPC03 / AN153 / P153 BE0IN / ISRxD0 / INPC02 / AN152 / P152 ISCLK0 / OUTC01 / INPC01 / AN151 / P151 Vss BE0OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150 Vcc KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN3 / P103 AN2 / P102 AN1 / P101 AVss AN0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 73 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss P30 / A8 ( MA0 ) ( / D8 ) Vcc P120 / OUTC30 / ISTxD3 P121 / OUTC31 / ISCLK3 P122 / OUTC32 / ISRxD3 P123 / OUTC33 P124 / OUTC34 P31 / A9 ( MA1 ) ( / D9 ) P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) Vss P42 / A18 ( MA10 ) Vcc P43 / A19 ( MA11 ) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 11 1 2 3 4 5 6 7 8 9 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 M32C/83 GROUP (M32C/83, M32C/83T) 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 / OUTC35 P126 / OUTC36 P127 / OUTC37 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P130 / OUTC24 P131 / OUTC25 Vcc P132 / OUTC26 Vss P133 / OUTC23 P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P134 / OUTC20 / ISTxD2 / IEOUT P135 / OUTC22 / ISRxD2 / IEIN P136 / OUTC21 / ISCLK2 P137 / OUTC27 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 Vss P66 / RxD1 / SCL1 / STxD1 Vcc P67 / TxD1 / SDA1 / SRxD1 P70(2, 3) NOTES: 1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P70 and P71 are ports for the N-channel open drain output. SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC17 / INPC17 / P143 OUTC16 / INPC16 / P142 OUTC15 / P141 OUTC14 / P140 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 CANIN / INT1 / P83 ISRxD3 / OUTC32 / CANOUT / INT0 / P82 ISTxD3 / OUTC30 / U / TA4IN / P81 BE0IN / ISRxD0 / INPC02 / U / TA4OUT / P80 CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3) IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 PLQP0144KA-A (144P6Q-A) Figure 1.3 Pin Assignment for 144-Pin Package Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 6 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VCC 40 41 VSS 42 43 44 45 Control Pin Port P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 BYTE CNVSS XCIN/VCONT Interrupt Timer Pin Pin UART/CAN Pin TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 Intelligent I/O Pin Analog Pin ANEX1 ANEX0 DA1 DA0 Bus Control Pin(1) TB4IN TB3IN TB2IN TB1IN TB0IN OUTC20/IEOUT/ISTxD2 IEIN/ISRxD2 INPC17/OUTC17 INPC16/OUTC16 OUTC15 OUTC14 XCOUT RESET XOUT VSS XIN VCC P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TB5IN/TA0IN TA0OUT CANIN CANOUT OUTC32/ISRxD3 OUTC30/ISTxD3 INPC02/ISRxD0/BE0IN INPC01/OUTC01/ISCLK0 INPC00/OUTC00/ISTxD0/BE0OUT INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 OUTC10/ISTxD1/BE1OUT OUTC22/ISRxD2/IEIN OUTC20/ISTxD2/IEOUT CANIN CANOUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC21/ISCLK2 P61 46 P60 47 P137 48 NOTES: 1. Bus control pins in M32C/83T cannot be used. OUTC27 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 7 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin No Control Pin Port Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin OUTC21/ISCLK2 OUTC22/ISRxD2/IEIN OUTC20/ISTxD2/IEOUT RDY ALE/RAS HOLD HLDA/ALE OUTC23 OUTC26 OUTC25 OUTC24 CLKOUT/BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL OUTC37 OUTC36 OUTC35 CS0/A23 CS1/A22 CS2/A21 CS3/A20(MA12) A19(MA11) A18(MA10) A17(MA9) A16(MA8) A15(MA7)(/D15) A14(MA6)(/D14) A13(MA5)(/D13) A12(MA4)(/D12) A11(MA3)(/D11) A10(MA2)(/D10) A9(MA1)(/D9) OUTC34 OUTC33 OUTC32/ISRxD3 OUTC31/ISCLK3 OUTC30/ISTxD3 A8(MA0)(/D8) AN27 AN26 AN25 A7(/D7) A6(/D6) A5(/D5) Analog Pin Bus Control Pin(1) 49 P136 P135 50 P134 51 P57 52 P56 53 P55 54 P54 55 P133 56 57 VSS P132 58 59 VCC P131 60 P130 61 P53 62 P52 63 P51 64 P50 65 P127 66 P126 67 P125 68 P47 69 P46 70 P45 71 P44 72 P43 73 74 VCC P42 75 76 VSS P41 77 P40 78 P37 79 P36 80 P35 81 P34 82 P33 83 P32 84 P31 85 P124 86 P123 87 P122 88 P121 89 P120 90 91 VCC P30 92 93 VSS P27 94 P26 95 P25 96 NOTES: 1. Bus control pins in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 8 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin No 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC 133 134 135 136 137 138 139 Control Pin Port P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 KI3 KI2 KI1 KI0 OUTC13 INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 OUTC10/ISTxD1/BE1OUT AN03 AN02 AN01 AN00 AN157 AN156 AN155 AN154 AN153 AN152 AN151 AN150 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 D3 D2 D1 D0 AN07 AN06 AN05 AN04 INT5 INT4 INT3 Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin AN24 AN23 AN22 AN21 AN20 Bus Control Pin(1) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 INPC07 INPC06 INPC05/OUTC05 INPC04/OUTC04 INPC03 INPC02/ISRxD0/BE0IN INPC01/OUTC01/ISCLK0 INPC00/OUTC00/ISTxD0/BE0OUT P101 140 AVSS 141 P100 142 VREF 143 AVCC RxD4/SCL4/STxD4 144 P97 NOTES: 1. Bus control pins in M32C/83T cannot be used. ADTRG Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 9 of 488 KI0 / AN4 / P104 KI1 / AN5 / P105 KI2 / AN6 / P106 KI3 / AN7 / P107 D0 / AN00 / P00 D1 / AN01 / P01 D2 / AN02 / P02 D3 / AN03 / P03 D4 / AN04 / P04 D5 / AN05 / P05 D6 / AN06 / P06 D7 / AN07 / P07 AN1 / P101 AN2 / P102 AN3 / P103 AN0 / P100 (2)P97 VREF AVss 88 81 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 AVcc 99 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 100 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 44 31 32 34 35 36 37 38 39 40 41 42 43 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P10 / D8 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss VCONT / XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc NMI / P85 INT2 / P84 CANIN / INT1 / P83 ISRxD3 / OUTC32 / CANOUT / INT0 / P82 ISTxD3 / OUTC30 / U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (3)IEIN P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss P30 / A8 ( MA0 ) ( / D8 ) Vcc P31 / A9 ( MA1 ) ( / D9 ) P32 / A10 ( MA2 ) ( / D10 ) P33 / A11 ( MA3 ) ( / D11 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P37 / A15 ( MA7 ) ( / D15 ) P40 / A16 ( MA8 ) P41 / A17 ( MA9 ) P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) M32C/83 Group (M32C/83, M32C/83T) NOTES: 1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P97 / ADTRG / RxD4 / STxD4 / SCL4 3. P70 and P71 are ports for the N-channel open drain output. Figure 1.4 Pin Assignment for 100-Pin Package Page 10 of 488 M32C/83 GROUP (M32C/83, M32C/83T) / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70 (3)IEOUT P64(1) P65 / CLK1 P57 / RDY P45 / CS2 / A21 P54 / HLDA / ALE P61 / CLK0 P55 / HOLD P52 / RD / DW P46 / CS1 / A22 P47 / CS0 / A23 P56 / ALE / RAS P44 / CS3 / A20 (MA12) P50 / WRL / WR / CASL P60 / CTS0 / RTS0 / SS0 P51 / WRH / BHE / CASH PRQP0100JB-A (100P6S-A) P66 / RxD1 / SCL1 / STxD1 P62 / RxD0 / SCL0 / STxD0 P67 / TxD1 / SDA1 / SRxD1 P63 / TxD0 / SDA0 / SRxD0 P53 / CLKOUT / BCLK / ALE 1. Overview M32C/83 Group (M32C/83, M32C/83T) 1. Overview P32 / A10 ( MA2 ) ( / D10 ) P34 / A12 ( MA4 ) ( / D12 ) P35 / A13 ( MA5 ) ( / D13 ) P36 / A14 ( MA6 ) ( / D14 ) P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 P30 / A8 ( MA0 ) ( / D8 ) P31 / A9 ( MA1 ) ( / D9 ) P37 / A15 ( MA7 ) ( / D15 ) 53 P33 / A11 ( MA3 ) ( / D11 ) P40 / A16 ( MA8 ) 52 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 59 58 57 56 54 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 66 D10 / P12 D9 / P11 D8 / P10 D7 / AN07 / P07 D6 / AN06 / P06 D5 / AN05 / P05 D4 / AN04 / P04 D3 / AN03 / P03 D2 / AN02 / P02 D1 / AN01 / P01 D0 / AN00 / P00 KI3 / AN37 / P107 KI2 / AN36 / P106 KI1 / AN35 / P105 KI0 / AN34 / P104 AN33 / P103 AN32 / P102 AN31 / P101 AVss AN30 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 55 P41 / A17 ( MA9 ) P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P14 / D12 P13 / D11 Vss Vcc 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42 / A18 ( MA10 ) P43 / A19 ( MA11 ) P44 / CS3 / A20 (MA12) P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR / CASL P51 / WRH / BHE / CASH P52 / RD / DW P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE / RAS P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64(1) P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70(2, 4) P71(3, 4) P72 / TA1OUT / V / CLK2 M32C/83 GROUP (M32C/83, M32C/83T) 10 12 13 14 15 16 17 19 20 21 23 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 24 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BYTE Vss SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 IEOUT/ ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92 IEIN/ ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 VCONT / XCIN / P87 XCOUT / P86 RESET Vcc XIN NMI / P85 INT2 / P84 CANIN / INT1 / P83 ISRxD3 / OUTC32 / CANOUT / INT0 / P82 ISTxD3 / OUTC30 / U / TA4IN / P81 BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80 CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77 CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76 NOTES: 1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2 2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT 3. P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22 / ISRxD2 / IEIN 4. P70 and P71 are ports for the N-channel open drain output. Figure 1.5 Pin Assignment for 100-Pin Package Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 11 of 488 BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CNVss XOUT 25 18 22 11 1 2 3 4 5 6 7 8 9 PLQP0100KB-A (100P6Q-A) M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.5 Pin Characteristics for 100-Pin Package Package Pin No FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2 3 Control Pin Port P96 P95 P94 P93 P92 P91 P90 Interrupt Pin Timer Pin UART/CAN Pin TxD4/SDA4/SRxD4 Intelligent I/O Pin Analog Bus Control Pin(1) Pin ANEX1 ANEX0 DA1 DA0 TB4IN TB3IN TB2IN TB1IN TB0IN CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 OUTC20/IEOUT/ISTxD2 IEIN/ISRxD2 4 5 6 BYTE 7 CNVSS 8 XCIN/VCONT 9 XCOUT 10 RESET 11 XOUT 12 VSS 13 XIN 14 VCC 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TB5IN/TA0IN TA0OUT CANIN CANOUT OUTC32/ISRxD3 OUTC30/ISTxD3 INPC02/ISRxD0/BE0IN CANIN CANOUT INPC01/OUTC01/ISCLK0 INPC00/OUTC00/ISTxD0/BE0OUT INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 OUTC10/ISTxD1/BE1OUT OUTC22/ISRxD2/IEIN OUTC20/ISTxD2/IEOUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 OUTC21/ISCLK2 RDY ALE/RAS HOLD HLDA/ALE CLKOUT/BCLK/ALE RD/DW WRH/BHE/CASH WRL/WR/CASL CS0/A23 CS1/A22 CS2/A21 CS3/A20(MA12) NOTES: 1. Bus control pins in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 12 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.5 Pin Characteristics for 100-Pin Package (Continued) Package Pin No FP GP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 VCC P30 VSS P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 AVSS P100 VREF AVCC P97 RxD4/SCL4/STxD4 ADTRG AN0 INT5 INT4 INT3 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A8(MA0)(/D8) A19(MA11) A18(MA10) A17(MA9) A16(MA8) A15(MA7)(/D15) A14(MA6)(/D14) A13(MA5)(/D13) A12(MA4)(/D12) A11(MA3)(/D11) A10(MA2)(/D10) A9(MA1)(/D9) Control Pin Port Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin Bus Control Pin(1) KI3 KI2 KI1 KI0 AN07 AN06 AN05 AN04 AN03 AN02 AN01 AN00 AN7 AN6 AN5 AN4 AN3 AN2 AN1 NOTES: 1. Bus control pins in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 13 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview 1.6 Pin Description Table 1.6 Pin Description (100-Pin and 144-Pin Packages) Classsfication Power Supply Analog Power Supply Reset Input CNVSS Symbol VCC VSS AVCC AVSS ____________ RESET CNVSS I/O Type I I I I I Function Apply 3.0 to 5.5V to both VCC pin. Apply 0V to the VSS pin. (1) Supplies power to the A/D converter. Connect the AVCC pin to VCC and the AVSS pin to VSS ___________ The microcomputer is in a reset state when "L" is applied to the RESET pin Switches processor mode. Connect the CNVSS pin to VSS to start up in singlechip mode or to VCC to start up in microprocessor mode Switches data bus width in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Set to either. Connect the BYTE pin to VSS to use the microcomputer in Input to Switch BYTE External Data Bus Width(2) Bus Control Pins(2) D 0 to D 7 D8 to D15 A0 to A22 ______ A23 A0/D0 to A7/D7 A8/D8 to A15/D15 ______ ______ I/O I/O O O I/O single-chip mode Inputs and outputs data (D0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits A0 to A22 Outputs inversed address bit A23 Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus I/O Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with 16-bit multiplexed bus _______ _______ _________ ______ ________ _____ ________ _________ _________ CS0 to CS3 ______ ________ WRL / WR WRH / BHE _____ RD O O Outputs CS0 to CS3 that are chip-select signals specifying an external space Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH can be ______ _______ switched with WR and BHE by program ________ _________ _____ WRL, WRH and RD selected: If external data bus is 16 bits wide, data is written to an even address in ________ external memory space when WRL is held "L". _________ ________ ________ Data is written to an odd address when WRH is held "L". _____ Data is read when RD is held "L". ______ ________ _____ WR, BHE and RD selected: ______ Data is written to external memory space when WR is held "L". _____ Data in an external memory space is read when RD is held "L". ________ An odd address is accessed when BHE is held "L". ______ ________ _____ ALE __________ O I O I O O Select WR, BHE and RD for external 8-bit data bus. ALE is a signal latching the address __________ HOLD __________ HLDA ________ The microcomputer is placed in a hold state while the HOLD pin is held "L" Outputs an "L" signal while the microcomputer is placed in a hold state ________ DRAM Bus Control Pin(2) RDY MA0 to MA12 ______ __________ __________ ________ Bus is placed in a wait state while the RDY pin is held "L" When DRAM area is accessed, outputs column and row addresses by time-sharing. ______ __________ __________ DW CASL The DW signal becomes "L" when data is written to the DRAM area. CASL and CASH are __________ signals indicating the timing to latch column addresses. The CASL signal becomes "L" when __________ CASH RAS an even address is accessed. The CASH signal becomes "L" when an odd address is ________ accessed. RAS is a signal latching row addresses. I : Input O : Output I/O : Input and output NOTES: 1. Apply 4.2 to 5.5V to the VCC pin when using M32C/83T. 2. Bus control pins in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 14 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol Main Clock Input XIN Main Clock Output XOUT Sub Clock Input XCIN Sub Clock Output XCOUT Low-Pass Filter Connect Pin for PLL Frequency Synthesizer Pin BCLK Output (1) BCLK Clock Output CLKOUT ______ ________ ________ I/O Type Function I/O pins for the main clock oscillation circuit. Connect a ceramic resonator I O I O or crystal oscillator between XIN and XOUT. To apply external clock, apply it to XIN and leave XOUT open I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply external clock, apply it to XCIN and leave XCOUT open Connects the low-pass filter to the VCONT pin when using the PLL frequency synthesizer. Connect P86 to VSS to stabilize the PLL frequency. VCONT O O I I I I/O I I O I O I/O I O I/O Outputs BCLK signal Outputs the clock having the same frequency as fC, f8 or f32 ______ Input pins for the INT interrupt _______ INT Interrupt Input INT0 to INT5 _______ _______ NMI Interrupt Input NMI _____ _____ Key Input Interrupt KI0 to KI3 Timer A TA0OUT to TA4OUT TA0IN to Timer B TA4IN TB0IN to Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 Output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for the N-channel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the N-channel open drain output.) TB5IN ___ ___ Three-phase Motor U, U, V, V, ___ Control Timer Output W, W _________ ________ Serial I/O CTS0 to CTS4 _________ _________ RTS0 to RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to TxD4 I2C Mode SDA0 to SDA4 SCL0 to SCL4 I : Input NOTE: O : Output I/O : Input and output 1. Bus control pins in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 15 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol I/O Type O I I I I Function Outputs serial data when slave mode is selected Inputs serial data when slave mode is selected Input pins to control serial I/O special function Applies reference voltage to the A/D converter and D/A converter Analog input pins for the A/D converter STxD0 to Serial I/O Special Function STxD4 SRxD0 to SRxD4 _______ _______ SS0 to SS4 Reference Voltage Input A/D Converter VREF AN0 to AN7 AN00 to AN07 AN20 to AN27 AN150 to AN157 ___________ ADTRG ANEX0 ANEX1 D/A Converter Intelligent I/O DA0, DA1 INPC00 to INPC02 INPC03 to INPC07(1) INPC11 to INPC12 INPC16 to INPC17(1) OUTC00 to OUTC02 OUTC04 to OUTC05(1) OUTC10 to OUTC12 OUTC13 to OUTC17(1) OUTC20 to OUTC22 OUTC23 to OUTC27(1) OUTC30 to OUTC32 OUTC31, OUTC33 to OUTC37(1) ISCLK0 to ISCLK2 ISCLK3(1) ISRXD0 to ISRXD3 ISTXD0 to ISTXD3 BE0IN, BE1IN BE0OUT, BE1OUT IEIN CAN I : Input IEOUT CANIN CANOUT O : Output I I/O I O I Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter Input pins for the time measurement function O Output pins for the waveform generating function (OUTC20 and OUTC22 assigned to P70 and P71 are pins for the N-channel open drain output.) I/O I O I O I O I O Inputs and outputs the clock for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Inputs data for the intelligent I/O communication function Outputs data for the intelligent I/O communication function Input pin for the CAN communication function Output pin for the CAN communication function I/O : Input and output NOTE: 1. Available in the 144-pin package only. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 16 of 488 M32C/83 Group (M32C/83, M32C/83T) 1. Overview Table 1.6 Pin Description (144-Pin Package only) (Continued) Classsfication I/O Ports Symbol P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P100 to P107 P110 to P114 P120 to P127 P130 to P137 P140 to P146 P150 to P157 (1) I/O Type I/O Function 8-bit I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units (P70 and P71 are ports for the N-channel open drain output.) I/O I/O ports having equivalent functions to P0 P80 to P84 P86, P87 Input Port I : Input P85 O : Output I/O I I/O ports having equivalent functions to P0 _______ _______ Shares a pin with NMI. NMI input state can be got by reading P8 5 I/O : Input and output NOTE: 1. Available in the 144-pin package only. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 17 of 488 M32C/83 Group (M32C/83, M32C/83T) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. A register bank comprises 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two sets of register banks are provided. b31 b15 b0 General Register R2 R3 R0H R1H R2 R0L R1L Data Register(1) b23 R3 A0 A1 SB FB USP ISP INTB PC FLG Address Register(1) Static Base Register(1) Frame Base Register(1) User Stack Pointer Interrupt Stack Pointer Interrupt Table Register Program Counter Flag Register b0 b15 b8 b7 IPL U I OBSZDC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Space Processor Interrupt Priority Level Reserved space b15 b0 High-Speed Interrupt Register b23 SVF SVP VCT b7 b0 Flag Save Register PC Save Register Vector Register DMAC Associated Register b15 DMD0 DMD1 DCT0 DCT1 DRC0 b23 DMA Mode Register DMA Transfer Count Register DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1 DMA Transfer Count Reload Register DMA Memory Address Register DMA Memory Address Reload Register DMA SFR Address Register NOTES: 1. A register bank comprises these registers. Two sets of register banks are provided. Figure 2.1 CPU Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 18 of 488 M32C/83 Group (M32C/83, M32C/83T) 2. Central Processing Unit (CPU) 2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3. 2.1.2 Address Registers (A0 and A1) A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations. 2.1.3 Static Base Register (SB) SB is a 24-bit register for SB-relative addressing. 2.1.4 Frame Base Register (FB) FB is a 24-bit register for FB-relative addressing. 2.1.5 Program Counter (PC) PC, 24 bits wide, indicates the address of an instruction to be executed. 2.1.6 Interrupt Table Register (INTB) INTB is a 24-bit register indicating the starting address of an interrupt vector table. 2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to "2.1.8 Flag Register (FLG)" for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently. 2.1.8 Flag Register (FLG) FLG is a 16-bit register indicating a CPU state. 2.1.8.1 Carry Flag (C) The C flag indicates whether carry or borrow has occurred after executing an instruction. 2.1.8.2 Debug Flag (D) The D flag is for debug only. Set to "0". 2.1.8.3 Zero Flag (Z) The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0". 2.1.8.4 Sign Flag (S) The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0". Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 19 of 488 M32C/83 Group (M32C/83, M32C/83T) 2. Central Processing Unit (CPU) 2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1". 2.1.8.6 Overflow Flag (O) The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged. 2.1.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.1.8.9 Processor Interrupt Priority Level (IPL) IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled. 2.1.8.10 Reserved Space When writing to a reserved space, set to "0". When read, its content is indeterminate. 2.2 High-Speed Interrupt Registers Registers associated with the high-speed interrupt are as follows. Refer to 10.4 High-Speed Interrupt for details. - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT) 2.3 DMAC-Associated Registers Registers associated with DMAC are as follows. Refer to 12. DMAC for details. - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 20 of 488 M32C/83 Group (M32C/83, M32C/83T) 3. Memory 3. Memory Figure 3.1 shows a memory map of the M32C/83 group (M32C/83, M32C/83T). M32C/83 group (M32C/83, M32C/83T) provides 16-Mbyte address space from addresses 00000016 to FFFFFF16. The internal ROM is allocated lower addresses beginning with address FFFFFF16. For example, a 64Kbyte internal ROM is allocated addresses FF000016 to FFFFFF16. The fixed interrupt vectors are allocated addresses FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine. Refer to 10. Interrupts for details. The internal RAM is allocated higher addresses beginning with address 00040016. For example, a 10Kbyte internal RAM is allocated addresses 00040016 to 002BFF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged. SFR, consisting of control registers for peripheral functions such as I/O port, A/D conversion, serial I/O, and timers, is allocated addresses 00000016 to 0003FF16. All addresses, which have nothing allocated within SFR, are reserved space and cannot be accessed by users. The special page vectors are allocated addresses FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication Software Manual for details. In memory expansion mode and microprocessor mode, some space are reserved and cannot be accessed by users. 00000016 SFR 00040016 007FFF16 00800016 Internal RAM Reserved Space FFFE00 16 Special Page Vector Table External Space(1) FFFFDC 16 Undefined Instruction Overflow BRK Instruction Address Match F0000016 F8000016 Internal ROM(3) FFFFFF16 FFFFFF 16 Reserved Space(2) Watchdog Timer(4) NMI Reset NOTES: 1. In memory expansion and microprocessor modes 2. In memory expansion mode. This space becomes external space in microprocessor mode. 3. This space can be used in single-chip mode and memory expansion mode. This space becomes external space in microprocessor mode. 4. Watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt share vectors. Figure 3.1 Memory Map Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 21 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) 4. Special Function Registers (SFR) Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 Register Symbol Value after RESET Processor Mode Register 0(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Wait Control Register(2) Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register(2) Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 1000 00002 (CNVss pin ="L") PM0 PM1 CM0 CM1 WCR AIER PRCR DS MCD CM2 WDTS WDC RMAD0 0000 00112 (CNVss pin ="H") 0X00 00002 0000 X0002 0010 00002 1111 11112 XXXX 00002 XXXX 00002 XXXX 10002 (BYTE pin ="L") XXXX 00002 (BYTE pin ="H") XXX0 10002 0016 XX16 000X XXXX2 00 00 0016 Address Match Interrupt Register 1 VDC Control Register for PLL Address Match Interrupt Register 2 VDC Control Register 0 Address Match Interrupt Register 3 RMAD1 PLV RMAD2 VDC0 RMAD3 00 00 0016 XXXX XX012 00 00 0016 0016 00 00 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The PM00 and PM01 bits in the PM1 register maintain values set before reset even if software reset or watchdog timer reset is performed. 2. These registers in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 22 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address Register 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 DRAM Control Register (1) 004116 DRAM Refresh Interval Set Register (1) 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 Symbol Value after RESET DRAMCONT REFCNT XX16 XX16 Flash Memory Control Register 0 FMR0 XX00 00012 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. These registers in M32C/83T cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 23 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 008016 Register Symbol Value after RESET DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive /ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive /ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive /ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detect Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 0 Timer B1 Interrupt Control Register Intelligent I/O Interrupt Control Register 2 Timer B3 Interrupt Control Register Intelligent I/O Interrupt Control Register 4 INT5 Interrupt Control Register Intelligent I/O Interrupt Control Register 6 INT3 Interrupt Control Register Intelligent I/O Interrupt Control Register 8 INT1 Interrupt Control Register Intelligent I/O Interrupt Control Register 10/ CAN Interrupt 1 Control Register Intelligent I/O Interrupt Control Register 11/ DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC IIO0IC TB1IC IIO2IC TB3IC IIO4IC INT5IC IIO6IC INT3IC IIO8IC INT1IC IIO10IC CAN1IC IIO11IC CAN2IC XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 CAN Interrupt 2 Control Register XXXX X0002 A/D1 Conversion Interrupt Control Register DMA1 Interrupt Control Register UART2 Transmit /NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit /NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit /NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detect Interrupt Control Register AD1IC DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 24 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 Register UART0 Transmit /NACK Interrupt Control Register UART1/UART4 Bus Conflict Detect Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register Intelligent I/O Interrupt Control Register 1 Timer B2 Interrupt Control Register Intelligent I/O Interrupt Control Register 3 Timer B4 Interrupt Control Register Intelligent I/O Interrupt Control Register 5 INT4 Interrupt Control Register Intelligent I/O Interrupt Control Register 7 INT2 Interrupt Control Register Intelligent I/O Interrupt Control Register 9/ CAN Interrupt 0 Control Register INT0 Interrupt Control Register Exit Priority Control Register Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Request Register 2 Interrupt Request Register 3 Interrupt Request Register 4 Interrupt Request Register 5 Interrupt Request Register 6 Interrupt Request Register 7 Interrupt Request Register 8 Interrupt Request Register 9 Interrupt Request Register 10 Interrupt Request Register 11 Symbol S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC IIO1IC TB2IC IIO3IC TB4IC IIO5IC INT4IC IIO7IC INT2IC IIO9IC CAN0IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Value after RESET XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX 00002 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Enable Register 4 Interrupt Enable Register 5 Interrupt Enable Register 6 Interrupt Enable Register 7 Interrupt Enable Register 8 Interrupt Enable Register 9 Interrupt Enable Register 10 Interrupt Enable Register 11 IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 25 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 Register Group 0 Time Measurement/Waveform Generating Register 0 Group 0 Time Measurement/Waveform Generating Register 1 Group 0 Time Measurement/Waveform Generating Register 2 Group 0 Time Measurement/Waveform Generating Register 3 Group 0 Time Measurement/Waveform Generating Register 4 Group 0 Time Measurement/Waveform Generating Register 5 Group 0 Time Measurement/Waveform Generating Register 6 Group 0 Time Measurement/Waveform Generating Register 7 Group 0 Waveform Generating Control Register 0 Group 0 Waveform Generating Control Register 1 Group 0 Waveform Generating Control Register 2 Group 0 Waveform Generating Control Register 3 Group 0 Waveform Generating Control Register 4 Group 0 Waveform Generating Control Register 5 Group 0 Waveform Generating Control Register 6 Group 0 Waveform Generating Control Register 7 Group 0 Time Measurement Control Register 0 Group 0 Time Measurement Control Register 1 Group 0 Time Measurement Control Register 2 Group 0 Time Measurement Control Register 3 Group 0 Time Measurement Control Register 4 Group 0 Time Measurement Control Register 5 Group 0 Time Measurement Control Register 6 Group 0 Time Measurement Control Register 7 Group 0 Base Timer Register Group 0 Base Timer Control Register 0 Group 0 Base Timer Control Register 1 Group 0 Time Measurement Prescaler Register 6 Group 0 Time Measurement Prescaler Register 7 Group 0 Function Enable Register Group 0 Function Select Register Group 0 SI/O Receive Buffer Register Group 0 Transmit Buffer/Receive Data Register Group 0 Receive Input Register Group 0 SI/O Communication Mode Register Group 0 Transmit Output Register Group 0 SI/O Communication Control Register Symbol G0TM0/G0PO0 G0TM1/G0PO1 G0TM2/G0PO2 G0TM3/G0PO3 G0TM4/G0PO4 G0TM5/G0PO5 G0TM6/G0PO6 G0TM7/G0PO7 G0POCR0 G0POCR1 G0POCR2 G0POCR3 G0POCR4 G0POCR5 G0POCR6 G0POCR7 G0TMCR0 G0TMCR1 G0TMCR2 G0TMCR3 G0TMCR4 G0TMCR5 G0TMCR6 G0TMCR7 G0BT G0BCR0 G0BCR1 G0TPR6 G0TPR7 G0FE G0FS G0RB G0TB/G0DR G0RI G0MR G0TO G0CR Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0016 0016 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 0016 0016 XXXX XXXX2 XX00 XXXX2 XX16 XX16 0016 XX16 0000 X0002 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 26 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 Register Group 0 Data Compare Register 0 Group 0 Data Compare Register 1 Group 0 Data Compare Register 2 Group 0 Data Compare Register 3 Group 0 Data Mask Register 0 Group 0 Data Mask Register 1 Symbol G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1 Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 Group 0 Receive CRC Code Register Group 0 Transmit CRC Code Register Group 0 SI/O Extended Mode Register Group 0 SI/O Extended Receive Control Register Group 0 SI/O Special Communication Interrupt Detect Register Group 0 SI/O Extended Transmit Control Register Group 1 Time Measurement/Waveform Generating Register 0 Group 1 Time Measurement/Waveform Generating Register 1 Group 1 Time Measurement/Waveform Generating Register 2 Group 1 Time Measurement/Waveform Generating Register 3 Group 1 Time Measurement/Waveform Generating Register 4 Group 1 Time Measurement/Waveform Generating Register 5 Group 1 Time Measurement/Waveform Generating Register 6 Group 1 Time Measurement/Waveform Generating Register 7 Group 1 Waveform Generating Control Register 0 Group 1 Waveform Generating Control Register 1 Group 1 Waveform Generating Control Register 2 Group 1 Waveform Generating Control Register 3 Group 1 Waveform Generating Control Register 4 Group 1 Waveform Generating Control Register 5 Group 1 Waveform Generating Control Register 6 Group 1 Waveform Generating Control Register 7 Group 1 Time Measurement Control Register 0 Group 1 Time Measurement Control Register 1 Group 1 Time Measurement Control Register 2 Group 1 Time Measurement Control Register 3 Group 1 Time Measurement Control Register 4 Group 1 Time Measurement Control Register 5 Group 1 Time Measurement Control Register 6 Group 1 Time Measurement Control Register 7 G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 XX16 0016 0016 0016 0016 0000 00XX2 0000 0XXX2 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0016 0016 0016 0016 0016 0016 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 27 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 Register Group 1 Base Timer Register Group 1 Base Timer Control Register 0 Group 1 Base Timer Control Register 1 Group 1 Time Measurement Prescaler Register 6 Group 1 Time Measurement Prescaler Register 7 Group 1 Function Enable Register Group 1 Function Select Register Group 1 SI/O Receive Buffer Register Group 1 Transmit Buffer/Receive Data Register Group 1 Receive Input Register Group 1 SI/O Communication Mode Register Group 1 Transmit Output Register Group 1 SI/O Communication Control Register Group 1 Data Compare Register 0 Group 1 Data Compare Register 1 Group 1 Data Compare Register 2 Group 1 Data Compare Register 3 Group 1 Data Mask Register 0 Group 1 Data Mask Register 1 Symbol G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1RB G1TB/G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1 Value after RESET XX16 XX16 0016 0016 0016 0016 0016 0016 XXXX XXXX2 XX00 XXXX2 XX16 XX16 0016 XX16 0000 X0002 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Group 1 Receive CRC Code Register Group 1 Transmit CRC Code Register Group 1 SI/O Extended Mode Register Group 1 SI/O Extended Receive Control Register Group 1 SI/O Special Communication Interrupt Detect Register Group 1 SI/O Extended Transmit Control Register Group 2 Waveform Generating Register 0 Group 2 Waveform Generating Register 1 Group 2 Waveform Generating Register 2 Group 2 Waveform Generating Register 3 Group 2 Waveform Generating Register 4 Group 2 Waveform Generating Register 5 Group 2 Waveform Generating Register 6 Group 2 Waveform Generating Register 7 G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7 XX16 0016 0016 0016 0016 0000 00XX2 0000 0XXX2 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 28 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 017916 017A16 017B16 017C16 017D16 017E16 017F16 Register Group 2 Waveform Generating Control Register 0 Group 2 Waveform Generating Control Register 1 Group 2 Waveform Generating Control Register 2 Group 2 Waveform Generating Control Register 3 Group 2 Waveform Generating Control Register 4 Group 2 Waveform Generating Control Register 5 Group 2 Waveform Generating Control Register 6 Group 2 Waveform Generating Control Register 7 Symbol G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7 Value after RESET 0016 0016 0016 0016 0016 0016 0016 0016 XX16 Group 2 Base Timer Register Group 2 Base Timer Control Register 0 Group 2 Base Timer Control Register 1 Base Timer Start Register Group 2 Function Enable Register Group 2 RTP Output Buffer Register G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP XX16 0016 0016 XXXX 00002 0016 0016 Group 2 SI/O Communication Mode Register Group 2 SI/O Communication Control Register Group 2 SI/O Transmit Buffer Register Group 2 SI/O Receive Buffer Register Group 2 IEBus Address Register Group 2 IEBus Control Register Group 2 IEBus Transmit Interrupt Cause Detect Register Group 2 IEBus Receive Interrupt Cause Detect Register G2MR G2CR G2TB G2RB IEAR IECR IETIF IERIF 00XX X0002 0000 X0002 XX16 XX16 XX16 XX16 XX16 XX16 00XX X0002 XXX0 00002 XXX0 00002 Input Function Select Register Group 3 SI/O Communication Mode Register Group 3 SI/O Communication Control Register Group 3 SI/O Transmit Buffer Register Group 3 SI/O Receive Buffer Register IPS G3MR G3CR G3TB G3RB 0016 00XX 00002 0000 X0002 XX16 XX16 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 29 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 018016 018116 018216 018316 018416 018516 018616 018716 018816 018916 018A16 018B16 018C16 018D16 018E16 018F16 019016 019116 019216 019316 019416 019516 019616 019716 019816 019916 019A16 019B16 019C16 019D16 019E16 019F16 01A016 01A116 01A216 01A316 01A416 01A516 01A616 01A716 01A816 01A916 01AA16 01AB16 01AC16 01AD16 01AE16 01AF16 Register Group 3 Waveform Generating Register 0 Group 3 Waveform Generating Register 1 Group 3 Waveform Generating Register 2 Group 3 Waveform Generating Register 3 Group 3 Waveform Generating Register 4 Group 3 Waveform Generating Register 5 Group 3 Waveform Generating Register 6 Group 3 Waveform Generating Register 7 Group 3 Waveform Generating Control Register 0 Group 3 Waveform Generating Control Register 1 Group 3 Waveform Generating Control Register 2 Group 3 Waveform Generating Control Register 3 Group 3 Waveform Generating Control Register 4 Group 3 Waveform Generating Control Register 5 Group 3 Waveform Generating Control Register 6 Group 3 Waveform Generating Control Register 7 Group 3 Waveform Generating Mask Register 4 Group 3 Waveform Generating Mask Register 5 Group 3 Waveform Generating Mask Register 6 Group 3 Waveform Generating Mask Register 7 Group 3 Base Timer Register Group 3 Base Timer Control Register 0 Group 3 Base Timer Control Register 1 Symbol G3PO0 G3PO1 G3PO2 G3PO3 G3PO4 G3PO5 G3PO6 G3PO7 G3POCR0 G3POCR1 G3POCR2 G3POCR3 G3POCR4 G3POCR5 G3POCR6 G3POCR7 G3MK4 G3MK5 G3MK6 G3MK7 G3BT G3BCR0 G3BCR1 Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 0016 0016 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 Group 3 Function Enable Register Group 3 RTP Output Buffer Register G3FE G3RTP 0016 0016 Group 3 SI/O Communication Flag Register G3FLG XXXX XXX02 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 30 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 01C016 01C116 01C216 01C316 01C416 01C516 01C616 01C716 01C816 01C916 01CA16 01CB16 01CC16 01CD16 01CE16 01CF16 01D016 01D116 01D216 01D316 01D416 01D516 01D616 01D716 01D816 01D916 01DA16 01DB16 01DC16 01DD16 01DE16 01DF16 Register Symbol Value after RESET A/D1 Register 0 A/D1 Register 1 A/D1 Register 2 A/D1 Register 3 A/D1 Register 4 A/D1 Register 5 A/D1 Register 6 A/D1 Register 7 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 A/D1 Control Register 2 A/D1 Control Register 0 A/D1 Control Register 1 AD1CON2 AD1CON0 AD1CON1 X00X X0002 0016 XX00 00002 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 31 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 01E016 01E116 01E216 01E316 01E416 01E516 01E616 01E716 01E816 01E916 01EA16 01EB16 01EC16 01ED16 01EE16 01EF16 01F016 01F116 01F216 01F316 01F416 01F516 01F616 01F716 01F816 01F916 01FA16 01FB16 01FC16 01FD16 01FE16 01FF16 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 Register CAN0 Message Slot Buffer 0 Standard ID0 CAN0 Message Slot Buffer 0 Standard ID1 CAN0 Message Slot Buffer 0 Extended ID0 CAN0 Message Slot Buffer 0 Extended ID1 CAN0 Message Slot Buffer 0 Extended ID2 CAN0 Message Slot Buffer 0 Data Length Code CAN0 Message Slot Buffer 0 Data 0 CAN0 Message Slot Buffer 0 Data 1 CAN0 Message Slot Buffer 0 Data 2 CAN0 Message Slot Buffer 0 Data 3 CAN0 Message Slot Buffer 0 Data 4 CAN0 Message Slot Buffer 0 Data 5 CAN0 Message Slot Buffer 0 Data 6 CAN0 Message Slot Buffer 0 Data 7 CAN0 Message Slot Buffer 0 Time Stamp High-Order CAN0 Message Slot Buffer 0 Time Stamp Low-Order CAN0 Message Slot Buffer 1 Standard ID0 CAN0 Message Slot Buffer 1 Standard ID1 CAN0 Message Slot Buffer 1 Extended ID0 CAN0 Message Slot Buffer 1 Extended ID1 CAN0 Message Slot Buffer 1 Extended ID2 CAN0 Message Slot Buffer 1 Data Length Code CAN0 Message Slot Buffer 1 Data 0 CAN0 Message Slot Buffer 1 Data 1 CAN0 Message Slot Buffer 1 Data 2 CAN0 Message Slot Buffer 1 Data 3 CAN0 Message Slot Buffer 1 Data 4 CAN0 Message Slot Buffer 1 Data 5 CAN0 Message Slot Buffer 1 Data 6 CAN0 Message Slot Buffer 1 Data 7 CAN0 Message Slot Buffer 1 Time Stamp High-Order CAN0 Message Slot Buffer 1 Time Stamp Low-Order CAN0 Control Register 0 CAN0 Status Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Time Stamp Register CAN0 Transmit Error Count Register CAN0 Receive Error Count Register CAN0 Slot Interrupt Status Register Symbol C0SLOT0_0 C0SLOT0_1 C0SLOT0_2 C0SLOT0_3 C0SLOT0_4 C0SLOT0_5 C0SLOT0_6 C0SLOT0_7 C0SLOT0_8 C0SLOT0_9 C0SLOT0_10 C0SLOT0_11 C0SLOT0_12 C0SLOT0_13 C0SLOT0_14 C0SLOT0_15 C0SLOT1_0 C0SLOT1_1 C0SLOT1_2 C0SLOT1_3 C0SLOT1_4 C0SLOT1_5 C0SLOT1_6 C0SLOT1_7 C0SLOT1_8 C0SLOT1_9 C0SLOT1_10 C0SLOT1_11 C0SLOT1_12 C0SLOT1_13 C0SLOT1_14 C0SLOT1_15 C0CTLR0 C0STR C0IDR C0CONR C0TSR C0TEC C0REC C0SISTR Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX01 0X012(1) XXXX 00002(1) 0000 00002(1) X000 0X012(1) 0016(1) 0016(1) 0000 XXXX2(1) 0000 00002(1) 00161) 0016(1) 0016(1) 0016(1) 0016(1) 0016(1) X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 32 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 Register CAN0 Slot Interrupt Mask Register Symbol C0SIMKR Value after RESET 0016(2) 0016(2) CAN0 Error Interrupt Mask Register CAN0 Error Interrupt Status Register CAN0 Baud Rate Prescaler C0EIMKR C0EISTR C0BRP XXXX X0002(2) XXXX X0002(2) 0000 00012(2) CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 CAN0 Global Mask Register Extended ID2 C0GMR0 C0GMR1 C0GMR2 C0GMR3 C0GMR4 XXX0 00002(2) XX00 00002(2) XXXX 00002(2) 0016(2) XX00 00002(2) (Note 1) CAN0 Message Slot 0 Control Register / CAN0 Local Mask Register A Standard ID0 CAN0 Message Slot 1 Control Register / CAN0 Local Mask Register A Standard ID1 CAN0 Message Slot 2 Control Register / CAN0 Local Mask Register A Extended ID0 CAN0 Message Slot 3 Control Register / CAN0 Local Mask Register A Extended ID1 CAN0 Message Slot 4 Control Register / CAN0 Local Mask Register A Extended ID2 CAN0 Message Slot 5 Control Register CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register CAN0 Message Slot 8 Control Register / CAN0 Local Mask Register B Standard ID0 C0MCTL0/ C0LMAR0 C0MCTL1/ C0LMAR1 C0MCTL2/ C0LMAR2 C0MCTL3/ C0LMAR3 C0MCTL4/ C0LMAR4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8/ C0LMBR0 0000 XXX0 00002(2) 0000 0000 2(2) XX00 00002(2) 0000 00002(2) XXXX 00002(2) 0016(2) 0016(2) 0000 0000 2(2) XX00 00002(2) 0016(2) 0016(2) 0016(2) 0000 0000 2(2) XXX0 00002(2) 00002(2) X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 33 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 023916 023A16 023B16 023C16 023D16 023E16 023F16 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 026016 026116 to 02BF16 Register CAN0 Message Slot 9 Control Register / CAN0 Local Mask Register B Standard ID1 CAN0 Message Slot 10 Control Register / CAN0 Local Mask Register B Extended ID0 CAN0 Message Slot 11 Control Register / CAN0 Local Mask Register B Extended ID1 CAN0 Message Slot 12 Control Register / CAN0 Local Mask Register B Extended ID2 CAN0 Message Slot 13 Control Register CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register CAN0 Slot Buffer Select Register CAN0 Control Register 1 CAN0 Sleep Control Register Symbol C0MCTL9/ C0LMBR1 C0MCTL10/ C0LMBR2 C0MCTL11/ C0LMBR3 C0MCTL12/ C0LMBR4 C0MCTL13 C0MCTL14 C0MCTL15 C0SBS C0CTLR1 C0SLPR Value after RESET 0000 00002(2) XX00 00002(2) 0000 00002(2) XXXX 00002(2) 0016(2) 0016(2) 0000 00002(2) XX00 00002(2) 0016(2) 0016(2) 0016(2) 0016(2) XX00 00XX2(2) XXXX XXX02 0016(2) 0116(2) (Note 1) CAN0 Acceptance Filter Support Register C0AFS X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a clock to the CAN module after reset. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 34 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 X0 Register Y0 Register X1 Register Y1 Register X2 Register Y2 Register X3 Register Y3 Register X4 Register Y4 Register X5 Register Y5 Register X6 Register Y6 Register X7 Register Y7 Register X8 Register Y8 Register X9 Register Y9 Register Register Symbol X0R,Y0R X1R,Y1R X2R,Y2R X3R,Y3R X4R,Y4R X5R,Y5R X6R,Y6R X7R,Y7R X8R,Y8R X9R,Y9R X10R,Y10R X11R,Y11R X12R,Y12R X13R,Y13R X14R,Y14R X15R,Y15R XYC Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XXXX XX002 X10 Register Y10 Register X11 Register Y11 Register X12 Register Y12 Register X13 Register Y13 Register X14 Register Y14 Register X15 Register Y15 Register XY Control Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 35 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 Register Symbol Value after RESET UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Flag U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 000X XXXX2 XX16 Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase output Buffer Register 0 Three-Phase output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generating Frequency Set Counter TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 XX16 XX16 XX16 XX16 XX16 0016 0016 XX11 11112 XX11 11112 XX16 XX16 XX16 Timer B3 Register Timer B4 Register Timer B5 Register TB3 TB4 TB5 XX16 XX16 XX16 XX16 XX16 Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Cause Select Register TB3MR TB4MR TB5MR IFSR 00XX 00002 00XX 00002 00XX 00002 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 36 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address Register 032016 032116 032216 032316 032416 UART3 Special Mode Register 4 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register Symbol Value after RESET U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up-Down Flag U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 0016 0XXX XXXX2 0016 0016 0016 XX16 Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register TA0 TA1 TA2 TA3 TA4 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 37 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address Register 035016 Timer B0 Register 035116 035216 Timer B1 Register 035316 035416 Timer B2 Register 035516 035616 Timer A0 Mode Register 035716 Timer A1 Mode Register 035816 Timer A2 Mode Register 035916 Timer A3 Mode Register 035A16 Timer A4 Mode Register 035B16 Timer B0 Mode Register 035C16 Timer B1 Mode register 035D16 Timer B2 Mode Register 035E16 Timer B2 Special Mode Register 035F16 Count Source Prescaler Register(1) 036016 036116 036216 036316 036416 UART0 Special Mode Register 4 036516 UART0 Special Mode Register 3 036616 UART0 Special Mode Register 2 036716 UART0 Special Mode Register 036816 UART0 Transmit/Receive Mode Register 036916 UART0 Baud Rate Register 036A16 UART0 Transmit Buffer Register 036B16 036C16 UART0 Transmit/Receive Control Register 0 036D16 UART0 Transmit/Receive Control Register 1 036E16 UART0 Receive Buffer Register 036F16 037016 037116 037216 037316 037416 037516 037616 PLL Control Register 0 037716 PLL Control Register 1 037816 DMA0 Cause Select Register 037916 DMA1 Cause Select Register 037A16 DMA2 Cause Select Register 037B16 DMA3 Cause Select Register 037C16 CRC Data Register 037D16 037E16 CRC Input Register 037F16 Symbol TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 0000 0X002 0000 0X002 0000 0X002 0000 0X002 0000 0X002 00XX 00002 00XX 00002 00XX 00002 XXXX XXX02 0XXX 00002 U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 PLC0 PLC1 DM0SL DM1SL DM2SL DM3SL CRCD CRCIN 0011 X1002 XXXX 00002 0X00 00002 0X00 00002 0X00 00002 0X00 00002 XX16 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The TCSPR register maintains the values set before reset even if software reset or watchdog timer reset is performed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 38 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7 Register Symbol AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 A/D0 Control Register 2 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register AD0CON2 AD0CON0 AD0CON1 DA0 DA1 DACON X000 00002 0016 0016 XX16 XX16 XXXX XX002 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 39 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 Register Function Select Register A8 Function Select Register A9 Symbol PS8 PS9 Value after RESET X000 00002 0016 Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 Function Select Register A5 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 PS5 00X0 00002 0016 0016 0016 0016 00X0 00002 0016 00X0 00002 0016 XXX0 00002 Function Select Register A6 Function Select Register A7 PS6 PS7 0016 0016 Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16 XX16 0016 XXX0 00002 XX16 XX16 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 40 of 488 M32C/83 Group (M32C/83, M32C/83T) 4. Special Function Registers (SFR) Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register Port P14 Register Port P15 Register Port P14 Direction Register Port P15 Direction Register Symbol P14 P15 PD14 PD15 Value after RESET XX16 XX16 X000 00002 0016 Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4 PUR2 PUR3 PUR4 0016 0016 XXXX 00002 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 Pull-Up Control Register 0 Pull-Up Control Register 1 PUR0 PUR1 0016 XXXX 00002 Port Control Register PCR XXXX XXX02 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 41 of 488 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 98 6 4 21 7 5 32 0 8 65 1 1 98 6 4 21 7 5 32 0 8 65 1 1 98 6 4 21 7 5 32 0 8 65 1 1 98 6 4 21 7 5 32 0 8 65 1 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 4037251300988674615947343212009785736098463421192714329280776553409826140199877432524037251309886746159473221 1 98 6 4 219 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 2109 7 5 32 0 8 6543 1 403725130098867461594734321200978573609846342119271432928077655340982614019987743252403725130098867461594734321 9 2 5 0 3 6 9 2 43210987654321098765432121098765432109876543210987654321 403725130098867461594734321200978573609846342119271432928077655340982614019987743252403725130098867461594734321 9 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 219 7 5 32 0 8 652 1 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 98 6 4 21 403725130098867461594734321200978573609846342119271432928077655340982614019987743252403725130098867461594734321 1 98 6 4 219 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 219 7 5 32 0 8 652 1 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 0X00 00002 0016 0016 0016 0016 00X0 00002 0016 00X0 00002 0016 M32C/83 Group (M32C/83, M32C/83T) Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 Register Symbol Value after RESET Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 4321 4533211 642 654321 654321 Blank spaces are reserved. No access is allowed. NOTES: X: Indeterminate 1. 2. in the 100-pin package. Port P10 Direction Register Set address spaces 03CB16, 03CE16 and 03CF16 to "FF16" in the 100-pin package. Address spaces 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16 and 03CD16 are not provided Page 42 of 488 PD10 4. Special Function Registers (SFR) 0016 (Note 1) (Note 2) (Note 1) (Note 2) (Note 2) (Note 2) (Note 2) 76543210987654321210987654321098765432109876543212109876543210987654321098765432 765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 765432109876543212109876543210987654321098765432121098765432109876543210987654321 Pull-up Control Register 2 Pull-up Control Register 3 PUR2 PUR3 0016 0016 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 M32C/83 Group (M32C/83, M32C/83T) Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 1 98 6 4 21 7 5 32 0 8 65 1 1 98 6 4 21 7 5 32 0 8 65 1 1 98 6 4 21 7 5 32 0 8 65 1 1 98 6 4 21 7 5 32 0 8 65 1 1098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 4037251300988674615947343212009785736098463421192714329280776553409826140199877432524037251309886746159473221 1 98 6 4 219 7 5 32 0 8 652 1 1 98 6 4 215 7 5 32 0 8 650 1 1 98 6 4 213 7 5 32 0 8 656 1 1 98 6 4 2109 7 5 32 0 8 6543 1 403725130098867461594734321200978573609846342119271432928077655340982614019987743252403725130098867461594734321 9 2 5 0 3 6 9 2 43210987654321098765432121098765432109876543210987654321 43210987654321098765432121098765432109876543210987654321 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 654321 654321 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. 2. 4321 4321 54321 42 5543211 63 3. Port Control Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Set address spaces 03D216 and 03D316 to "FF16" in the 100-pin package. Set address spaces 03DC16 to "0016" in the 100-pin package. Address spaces 03D016 and 03D116 are not provided in the 100-pin package. Page 43 of 488 Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 PCR PUR0 PUR1 Symbol 4. Special Function Registers (SFR) Value after RESET XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XXXX XXX02 0016 XXXX 00002 (Note 2) (Note 1) (Note 3) M32C/83 Group (M32C/83, M32C/83T) 5. Reset 5. Reset Hardware reset, software reset, and watchdog timer reset are available to reset the microcomputer. 5.1 Hardware Reset 5.1.1 Reset on a Stable Supply Voltage The microcomputer resets pins, the CPU and SFR when the supply voltage meets the recommended ___________ performance conditions while an "L" signal is applied to the RESET pin (see Table 5.1). Apply an "H" ____________ signal to the RESET pin again after 20 or more clock cycles are input to the XIN pin while applying an "L" ____________ to the RESET pin. The CPU and SFR are reset and programs run from the address indicated by the reset vector. ____________ The internal RAM is not reset. When the RESET pin becomes "L" while writing data to the internal RAM, the internal RAM is in an indeterminate state. 5.1.2 Power-on Reset The microcomputer resets pins, the CPU and SFR when the supply voltage applied to the VCC pin meets ___________ the recommended performance conditions while an "L" signal is applied to the RESET pin. (See Table 5.1.) ____________ The CPU and SFR are reset when the signal applied to the RESET pin changes low ("L") to high ("H") after the main clock oscillation stabilizes and 20 or more clock cycles are applied to the XIN pin. Programs run from the address indicated by the reset vector. The internal RAM is in a indeterminate state Figure 5.1 shows a reset circuit. Figure 5.2 shows a reset sequence. Figure 5.3 shows CPU register condi____________ tions after reset. Table 5.1 lists pin states while the RESET pin is held "L". Refer to 4. SFR for SFR states after reset. 5V VCC 0V 5V RESET 0.2VCC or below 0V Supply a clock with 20 or more cycles to the XIN pin Recommended Operation Voltage RESET VCC The above applies to VCC = 5V Figure 5.1 Reset Circuit Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 44 of 488 M32C/83 Group (M32C/83, M32C/83T) 5. Reset XIN Microprocessor (2) mode BYTE = “H” RESET 20 or more XIN cycles required 40 to 45 BCLK cycles BCLK Content of reset vector Address FFFFFC16 FFFFFD16 FFFFFE16 RD WR CS0 Microprocessor mode BYTE = “L”(2) Address FFFFFC16 FFFFFE16 Content of reset vector RD WR CS0 Single-chip mode Address(1) FFFFFC16 Content of reset vector FFFFFE16 NOTES: 1. Addresses cannot be output from pins, in single-chip mode. 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode. Figure 5.2 Reset Sequence Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 45 of 488 M32C/83 Group (M32C/83, M32C/83T) ____________ 5. Reset Table 5.1 Pin States while RESET Pin is Held "L" Pin States Pin Name P0 P1 P2, P3, P4 P50 P51 P52 P53 P54 P55 P56 P57 P6 to P15 (1) CNVSS = VCC CNVSS = VSS BYTE = VSS Input port (high-impedance) Data input (high-impedance) Input port (high-impedance) Data input (high-impedance) Input port (high-impedance) Address output (indeterminate) Input port (high-impedance) WR output (output "H") Input port (high-impedance) BHE output (indeterminate) Input port (high-impedance) RD output (output "H") Input port (high-impedance) BCLK output Input port (high-impedance) HLDA output (output value depends on an input to HOLD pin) Input port (high-impedance) HOLD input (high-impedance) Input port (high-impedance) RAS output Input port (high-impedance) RDY input (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) BYTE = VCC NOTES: 1. Ports P11 to P15 are provided in the 144-pin package. 5.2 Software Reset When the PM03 bit in the PM0 register is set to "1" (microcomputer reset), pins, the CPU and SFR are reset. Then the microcomputer executes the program from an address determined by the reset vector. When software reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for details. Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is stable. 5.3 Watchdog Timer Reset The microcomputer resets pins, the CPU and the SFR when the watchdog timer underflows while the CM06 bit in the CM0 register is set to "1" (reset). Then the microcomputer executes the program from an address indicated by the reset vector. When watchdog timer reset is performed, some registers in the SFR are not reset. Refer to 4. SFR for details. Because the PM01 to PM00 bits in the PM0 register are not reset, the processor mode remains unchanged. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 46 of 488 M32C/83 Group (M32C/83, M32C/83T) 5. Reset 5.4 Internal Space Figure 5.3 shows CPU register states after reset. Refer to 4. SFR for SFR states after reset. 0 : "0" after reset X : Indeterminate after reset General Register b15 b0 High-Speed Interrupt Register b15 b0 000016 b15 b8 b7 b0 Flag Register (FLG) b23 XXXX16 XXXXXX16 XXXXXX16 Save Flag Register (SVF) Save PC Register (SVP) Vector Register (VCT) X000XXXX00000000 IPL U I OBSZDC b0 DMAC-Associated Register b7 b0 0016 0016 000016 b23 0016 0016 Data Register (R0H/R0L) Data Register (R1H/R1L) Data Register (R2) Data Register (R3) Address Register (A0) Address Register (A1) Static Base Register (SB) Frame Base Register (FB) User Stack Pointer (USP) Interrupt Stack Pointer (ISP) Interrupt Table Register (INTB) Program Counter (PC) b23 b15 0016 0016 XXXX16 XXXX16 XXXX16 XXXX16 XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 DMA Mode Register (DMD0) DMA Mode Register (DMD1) DMA Transfer Count Register (DCT0) DMA Transfer Count Register (DCT1) DMA Transfer Count Reload Register (DRC0) DMA Transfer Count Reload Register (DRC1) DMA Memory Address Register (DMA0) DMA Memory Address Register (DMA1) DMA Memory Address Reload Register (DRA0) DMA Memory Address Reload Register (DRA1) DMA SFR Address Register (DSA0) DMA SFR Address Register (DSA1) 000016 00000016 00000016 00000016 00000016 00000016 00000016 00000016 Contents of addresses FFFFFE16 to FFFFFC16 Figure 5.3 CPU Register after Reset Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 47 of 488 M32C/83 Group (M32C/83, M32C/83T) 6. Processor Mode 6. Processor Mode NOTE M32C/83T can be used in single-chip mode. M32C/83T cannot be used in memory expansion mode and microprocessor mode. 6.1 Types of Processor Mode Single-chip mode, memory expansion mode, or microprocessor mode can be selected as processor mode. Pin functions, memory map and accessible space vary depending on the selected processor mode. 6.1.1 Single-chip Mode In single-chip mode, internal memory space (the SFR, internal RAM and internal ROM) can be accessed. All I/O ports can be used. 6.1.2 Memory Expansion Mode In memory expansion mode, both external memory space and internal memory space can be accessed . Some pins function as pins for bus control signals. The BYTE pin and register settings determine how many pins are assigned for these pin functions. Refer to 7. Bus for details. 6.1.3 Microprocessor Mode In microprocessor mode, SFR, internal RAM and external memory space can be accessed. Internal ROM cannot be accessed. Some pins function as pins for bus control signals. The BYTE pin and register settings determine how many pins are assigned for these pin functions. (Refer to 7. Bus for details.) 6.2 Setting Processor Mode The processor mode is set by the combination of CNVSS pin and the PM01 to PM00 bit settings in the PM0 register. Do not set the PM01 to PM00 bits to "102". If the PM01 to PM00 bits are rewritten, the mode corresponding to the PM01 to PM00 bits is selected regardless of CNVSS pin level. Do not change the PM01 to PM00 bits when the PM02 to PM07 bits in the PM0 register are being rewritten. Do not enter microprocessor mode while the CPU is executing a program in the internal ROM . Do not enter single-chip mode while the CPU is executing a program in an external memory space. Figures 6.1 and 6.2 show the PM0 register and PM1 register. Figure 6.3 shows a memory map in each processor mode. 6.2.1 Applying VSS to CNVSS Pin The microcomputer enters single-chip mode after reset. Set the PM01 to PM00 bits to "012" (memory expansion mode) to switch to memory expansion mode after the microcomputer starts operating. 6.2.2 Applying VCC to CNVSS Pin The microcomputer enters microprocessor mode after reset. When using the flash memory version, apply VCC to P55 (HOLD) as well as to the CNVSS. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 48 of 488 M32C/83 Group (M32C/83, M32C/83T) 6. Processor Mode Processor Mode Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM0 Address 000416 After Reset 1000 00002 (CNVss = "L") 0000 00112 (CNVss = "H") Bit Symbol PM00 Bit Name b1 b0 Function 0 0: Single-chip mode 0 1: Memory expansion mode(9) 1 0: Do not set to this value 1 1: Microprocessor mode(9) 0: RD / BHE / WR 1: RD / WRH / WRL The microcomputer is reset when this bit is set to "1". When read, its content is "0". b5 b4 RW RW Processor Mode PM01 Bit(2, 3) RW PM02 R/W Mode Select Bit(4) RW PM03 Software Reset Bit RW PM04 Multiplexed Bus Space Select Bit(5) PM05 RW 0 0 : Multiplexed bus is not used 0 1 : Access the CS2 area with the bus 0 1 : Access the CS1 area with the bus RW 1 1 : Access all CS areas with the bus(6) Reserved Bit (b6) Set to "0" RW PM07 BCLK Output Disable Bit(7) 0 : BCLK is output(8) 1 : BCLK is not output RW The CM01 and CM00 bits in the CM0 register determine pin functions. NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. Processor mode is not changed even if the PM03 bit is set to "1" (software reset). 3. Set the PM01 to PM00 bits to "012" or "112" separately. Rewrite other bits before rewriting the PM01 to PM00 bits. 4. When using the 16-bit data bus in the DRAMC, set the PM02 bit to "1". 5. The PM05 to PM04 bits are available in memory expansion mode or microprocessor mode. • Set the PM05 to PM04 bits to "002" in mode 0. • Do not set the PM05 to PM04 bits to "012" in mode 2. 6. The PM05 to PM04 bits cannot be set to "112" in microprocessor mode because the microcomputer starts operation using the separate bus after reset. When the PM05 to PM04 bits are set to "112" in memory expansion mode, the microcomputer can access each 64-Kbyte chip-select-assigned address space. The multiplexed bus is not available in mode 0. The microcomputer accesses CS0 to CS2 in mode 1, CS0 and CS1 in mode 2 and CS0 to CS3 in mode 3. 7. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When a clock output is terminated in microprocessor mode or memory expansion mode, set the PM07 bit to "1" and the CM01 to CM00 bits in the CM0 register to "002" (I/O port P53). P53 outputs "L" . 8. When the PM07 bit is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". 9. M32C/83T cannot be used in memory expansion mode and microprocessor mode. Figure 6.1 PM0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 49 of 488 M32C/83 Group (M32C/83, M32C/83T) 6. Processor Mode Processor Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM1 Address 000516 After Reset 0X00 00002 Bit Symbol PM10 Bit Name b1 b0 Function RW PM11 0 0 : Mode 0 (A20 to A23 for P44 to P47) RW 0 1 : Mode 1 (A20 for P44, CS2 to CS0 for P45 to P47) External Memory Space 1 0 : Mode 2 (A20, A21 for P44, P45, Mode Bit(2, 6) CS1, CS0 for P46, P47) RW 1 1 : Mode 3(3) (CS3 to CS0 for P44 to P47) Internal Memory Wait Bit 0 : No wait state 1 : Wait state 0 : 1 wait state 1 : 2 wait states(4) b5 b4 PM12 RW PM13 SFR Area Wait Bit 0 RW PM14 ALE Pin Select PM15 Bit(2, 6) 0 0 : No ALE 0 1 : P53/BCLK(5) 1 0 : P56/RAS 1 1 : P54/HLDA RW RW (b6) Nothing is assigned. When read, its content is indeterminate. Reserved Bit Set to "0" RW (b7) NOTES: 1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. The PM10 and PM11 bits are available in memory expansion mode or microprocessor mode. 3. The DRAMC is not available when the PM11 and PM10 bits are set to "112" (mode 3). 4. Set the PM13 bit to "1" (2 wait states) to access CAN-associated registers (addresses 01E016 to 024516). 5. Set the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53) when the PM15 and PM14 bits are set to "012" (P53/BCLK select). 6. M32C/83T cannot be used in memory expansion mode and microprocessor mode. Figure 6.2 PM1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 50 of 488 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Memory Expansion Mode Microprocessor Mode Mode 2 Mode 0 Mode 1 Mode 2 SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space Single-Chip Mode Mode 0 Mode 1 SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space Mode 3 Mode 3 SFR Internal RAM Reserved Space Not Used 00000016 00040016 SFR Internal RAM 00080016 Not Used External Space 0 M32C/83 Group (M32C/83, M32C/83T) Figure 6.3 Memory Map in Each Processor Mode CS1 2M bytes (1) External Space 0 CS1 4M bytes (2) External Space 0 External Space 1 Page 51 of 488 CS1 2M bytes (1) External Space 0 CS1, 1M byte External Space 0 CS2, 1M byte External Space 1 Not Used CS2 2M bytes External Space 1 CS2 2M bytes External Space 1 Not Used (Cannot be used as DRAMconnectable space or external space) DRAMConnectable Space 0, 0.5 to 8M bytes ( Remaining space cannot be used if empty space is less than 8M bytes) DRAMConnectable Space 0, 0.5 to 8M bytes( Remaining space cannot be used if empty space is less than 8M bytes) (External Space 2) (External Space 2) (External Space 2) DRAMConnectable Space 0, 0.5 to 8M bytes( Available as external space when DRAM is not used) DRAMConnectable Space 0, 0.5 to 8M bytes( Remaining space cannot be used if empty space is less than 8M bytes) (External Space 2) DRAMConnectable Space 0, 0.5 to 8M bytes (Remaining space cannot be used if empty space is less than 8M bytes) (External Space 2) 10000016 External Space 0 20000016 CS1 4M bytes (2) External Space 0 30000016 External Space 1 CS1, 1M byte External Space 0 CS2, 1M byte External Space 1 Not Used 40000016 Not Used (Cannot be used as DRAMconnectable space or external space) Not Used DRAMConnectable Space 0, 0.5 to 8M byte (Available as external space when DRAM is not used) (External Space 2) C0000016 CS3, 1M byte External Space 2 Not Used External Space 3 E0000016 External Space 3 Not Used Reserved Space Internal ROM Reserved Space Internal ROM CS0 2M bytes External Space 3 CS0 3M bytes External Space 3 Not Used CS0 4M bytes External Space 3 CS3, 1M byte External Space 2 Not Used CS0 2M bytes External Space 3 E0000016 CS0, 1M byte External Space 3 Reserved Space Internal ROM F0000016 FFFFFF16 Internal ROM Reserved Space Internal ROM CS0, 1M byte External Space 3 NOTES: 1. 20000016–00800016=2016K bytes. 32K bytes less than 2M bytes. 2. 40000016–00800016=4064K bytes. 32K bytes less than 4M bytes. The WCR register determines how many wait states are inserted for each space CS0 to CS3. 6. Processor Mode M32C/83 Group (M32C/83, M32C/83T) 7. Bus 7. Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins to input and ______ _______ _______ ________ ______ _________ output data from external devices. A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS3, WRL/WR/CASL, _________ _______ __________ _____ ______ _________ _________ _______ _______ WRH/BHE/CASH, RD/DW, BCLK/ALE, HLDA/ALE, HOLD, ALE/RAS, and RDY are used as bus control pins. NOTE Bus control pins in M32C/83T cannot be used. 7.1 Bus Settings The BYTE pin, the DS register, the PM05 to PM04 bits in the PM0 register and the PM11 to PM10 bits in the PM1 register determine bus settings. Table 7.1 lists how to change a bus setting. Figure 7.1 shows the DS register. Table 7.1 Bus Settings Bus Setting Selecting external address bus width Setting bus width after reset Switching between separate bus or multiplexed bus Number of chip-select Changed By DS register BYTE pin (external space 3 only) PM05 to PM04 bits in PM0 register PM11 to PM10 bits in PM1 register External Data Bus Width Control Register(2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DS Address 000B16 After Reset XXXX 10002 (BYTE pin = "L") XXXX 00002 (BYTE pin = "H") Bit Symbol DS0 Bit Name External Space 0 Data Bus Width Select Bit External Space 1 Data Bus Width Select Bit External Space 2 Data Bus Width Select Bit External Space 3 Data Bus Width Select Bit(1) Function 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide RW RW DS1 RW DS2 RW DS3 RW (b7 - b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. After reset, the DS3 bit is set to "1" when the BYTE pin is held "L". It is set to "0" when the BYTE pin is held "H". 2. The DS register in the M32C/83T cannot be used. Figure 7.1 DS Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 52 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus 7.1.1 Selecting External Address Bus The number of externally-output address bus, chip-select signals and chip-select-assigned address _____ space (CS area) varies depending on each external space mode. The PM11 to PM10 bits in the PM1 register determine the external space mode. When using the DRAMC, row addresses and column addresses are multiplexed to output in the DRAM area. 7.1.2 Selecting External Data Bus The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the external space 3, after reset, becomes 16 bits wide when an "L" signal is applied to the BYTE pin and 8 bits wide when an "H" signal is applied. Do not change the BYTE pin level while the microcomputer is operating. The internal bus is always 16 bits wide. 7.1.3 Selecting Separate/Multiplexed Bus The PM05 to PM04 bits in the PM0 register determine either a separate or multiplexed bus as bus format . 7.1.3.1 Separate Bus The separate bus is a bus format which allows the microcomputer to input and output data and address using separate buses. The DS register selects 8-bit or 16-bit data bus as the external data bus per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0 becomes the data bus and port P1 becomes the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus), ports P0 and P1 become the data bus. When the microcomputer accesses a space while the DSi bit set to "0", port P1 is indeterminate. If the microcomputer accesses a space with the separate bus, the WCR register determines the number of software wait states inserted. 7.1.3.2 Multiplexed Bus The multiplexed bus is a bus format which allows the microcomputer to input and output data and address via bus by timesharing. D0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit data bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. If the microcomputer accesses a space with the multiplexed bus, the WCR register can be set to either two wait states or three wait states. Two-wait-state access is automatically selected if the WCR register is set to no wait state or one wait state. Refer to 7.2.4 Bus Timing for details. The microcomputer starts operation using the separate bus after reset. Therefore, the multiplexed bus _______ _______ _____ can be assigned to access the CS1 area, the CS2 area, or all CS areas. However, the multiplexed bus _____ cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits _____ in the PM0 register are set to "112" (access all CS areas with the bus), only 16 low-order bits, from A0 to A15, of an address are output. See Table 7.2 for details. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 53 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus Table 7.2 Processor Mode and Port Function Processor Mode PM05 to PM04 Bits in PM0 Register SingleChip Mode Memory Expansion Mode/ Microprocessor Mode "012", "102" Access CS1 or CS2 using the Multiplexed Bus Access All Other CS Areas using the Separate Bus Memory Expansion Mode "112"(1) Access all CS Areas using the Multiplexed Bus "002" Access all CS Areas using the Separate Bus Data Bus Width Access all Access one or more Access all Access one or more Access all Access one or more external space with external space with external space with external space with external space with external space with 8-bit data bus 16-bit data bus 8-bit data bus 16-bit data bus 8-bit data bus 16-bit data bus P00 to P07 P10 to P17 I/O port I/O port Data bus D0 to D7 Data bus D0 to D7 Data bus D0 to D7 Data bus D0 to D7 I/O port I/O port Address bus/ Data bus A0/D0 to A7/D7 Address bus A8 to A15 I/O port I/O port Address bus/ Data bus A0/D0 to A7/D7 Address bus/ Data bus A8/D8 to A15/D15 I/O port Address bus/ Data bus(2) A0/D0 to A7/D7 Address bus A8 to A15 Address bus A16 to A19 Data bus D8 to D15 Address bus/ Data bus(2) A0/D0 to A7/D7 Address bus/ Data bus(2) A8/D8 to A15/D15 Address bus A16 to A19 I/O port Address bus A0 to A7 Address bus A8 to A15 Address bus A16 to A19 Data bus D8 to D15 Address bus A0 to A7 Address bus A8 to A15 Address bus A16 to A19 P20 to P27 I/O port P30 to P37 P40 to P43 P44 to P46 P47 P50 to P53 I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port CS (Chip-select signal) or Address bus (A20 to A22) (Refer to 7.2 Bus Control for details)(4) CS (Chip-select signal) or Address bus (A23) (Refer to 7.2 Bus Control for details)(4) Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK (Refer to 7.2 Bus Control for details)(3) HLDA (3) HOLD RAS (3) RDY HLDA (3) HOLD RAS (3) RDY HLDA (3) HOLD RAS (3) RDY HLDA (3) HOLD RAS (3) RDY HLDA (3) HOLD RAS (3) RDY HLDA (3) HOLD RAS (3) RDY P54 P55 P56 P57 NOTES: 1. The PM05 to PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in microprocessor mode because the microcomputer starts operation using the separate bus after reset. When the PM05 to PM04 bits are set to "112" in memory expansion mode, the microcomputer accesses 64K-byte memory space per chip select using the address bus . 2. These ports become address buses when accessing space using the separate bus. 3. The PM15 to PM14 bits in the PM1 register determine which pin outputs the ALE signal. The PM02 bit in the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. P56 provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port. 4. When DRAMC is selected to access DRAM area, CASL, CASH, DW, BCLK become output pins. 5. The PM11 to PM10 bits in the PM1 register determine the CS signal and address bus. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 54 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus 7.2 Bus Control Signals required to access external devices are provided and software wait states are inserted as follows. The signals are available in memory expansion mode and microprocessor mode only. 7.2.1 Address Bus and Data Bus ______ ______ The address bus is a signal accessing 16M-byte space and uses 24 control pins; A0 to A22 and A23. A23 is the inversed output signal of the highest-order address bit. The data bus is a signal which inputs and outputs data. The DS register selects the 8-bit data bus from D0 to D7 or the 16-bit data bus from D0 to D15 for each external space. When applying an "H" signal to the BYTE pin, the data bus accessing the external memory space 3 becomes the 8-bit data bus after reset. When applying an "L" signal to the BYTE pin, the data bus accessing the external memory space 3 becomes the 16-bit data bus. When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate state until the microcomputer accesses an external memory space. When using the DRAMC to access DRAM area, row addresses and column addresses are multiplexed and output via A8 to A20. 7.2.2 Chip-Select Signal _____ The chip-select signal shares ports with A0 to A22 and A23. The PM11 to PM10 bits in the PM1 register _____ determine which CS area is accessed and how many chip-select signals are output. A maximum of four chip-select signals can be output. _____ In microprocessor mode, the chip-select signal is not output after reset. A23, however, can perform as the chip-signal signal. ______ The chip-select signal becomes "L" while the microcomputer accesses the external CSi area (i=0 to 3). It becomes high ("H") when the microcomputer accesses another external memory space or an internal memory space. Figure 7.2 shows an example of the address bus and chip-select signal output. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 55 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in the next cycle after having accessed the external space i, both address bus and chip-select signal change. Example 2: When the microcomputer accesses the SFR or the internal ROM/RAM area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not. Access External Space Access SFR, Internal ROM/RAM Area Access External Space i Access External Space j Data Bus Address Bus Chip-Select Signal CSk Chip-Select Signal CSp Data Data Data Bus Address Bus Chip-Select Signal CSk Data Address Address i = 0 to 3 k = 0 to 3 j = 0 to 3, excluding i p= 0 to 3, excluding k (See Figure 6.3 for i, j and p, k) k = 0 to 3 Example 3: When the microcomputer accesses the space i specified by the same chip-select signal in the next cycle after having accessed the external space i, the address bus changes but the chip-select signal does not. Access External Space i Access External Space i Example 4: When the microcomputer does not access any space in the next cycle after having accessed an external space (no pre-fetch of an instruction is generated), neither address bus nor chip-select signal changes. Access External No Access Space Data Bus Address Bus Chip-Select Signal CSk Data Data Data Bus Address Bus Chip-Select Signal CSk Data Address Address i = 0 to 3 (See Figure 6.3 for i and k) k = 0 to 3 k = 0 to 3 NOTES: 1. The above applies to the address bus and chip-select signal in two consecutive cycles. By combining these examples, a chip-select signal extended by two or more cycles may be output. Figure 7.2 Address Bus and Chip-Select Signal Outputs (Separate bus) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 56 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus 7.2.3 Read and Write Signals _____ ______ When set to the 16-bit data bus, the PM02 bit in the PM0 register selects a combination of the RD, WR ________ _____ ________ _________ and BHE signals or the RD, WRL and WRH signals to determine the read or write signal. When the DS3 _____ ______ ________ to DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). If any of the DS3 to DS0 bits are set to "1" (16-bit data bus) when accessing an 8-bit space, the combination of _____ ______ ________ RD, WR and BHE is automatically selected regardless of the PM02 bit setting. Tables 7.3 and 7.4 list each signal operations. _____ ______ ________ The RD, WR and BHE signals are combined for the read or write signal after reset. _____ ________ _________ When changing the combination to RD, WRL and WRH, set the PM02 bit before writing data to an external memory. _____ ________ When using the DRAMC to access the DRAM with the 16-bit bus, set the PM02 bit to "1" (RD/ WRL/ _________ WRH). _____ ________ _________ Table 7.3 RD, WRL and WRH Signals Data Bus RD WRL WRH L H H H L H 16 Bits H H L H L L L(1) H Not used 8 Bits H(1) L Not used NOTES: ______ ________ 1. The WR signal is used instead of the WRL signal. _____ ______ ________ Status of External Data Bus Read data Write 1-byte data to even address Write 1-byte data to odd address Write data to both even and odd addresses Write 1-byte data Read 1-byte data Table 7.4 RD, WR and BHE Signals Data Bus RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of External Data Bus Write 1-byte data to odd address Read 1-byte data from odd address Write 1-byte data to even address Read 1-byte data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1-byte data Read 1-byte data 16 Bits 8 Bits Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 57 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus 7.2.4 Bus Timing Bus cycle for the internal ROM and internal RAM are basically one BCLK cycle. When the PM12 bit in the PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles. Bus cycles for the SFR are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1" (2 wait states), the bus cycles are three BCLK cycles. To access CAN-associated registers (addresses 01E016 to 024516), set the PM13 bit to "1". Bus cycle for an external space is basically one BCLK cycle for a read operation and two BCLK cycles for a write operation. The WCR register inserts wait states equivalent to one to three BCLK cycles into an external space. Bus cycles are two BCLK cycles if selecting one wait state. Bus cycles are four BCLK cycles if selecting three wait states. If applicable to the followings, bus cycles vary from those selected by the WCR register. Figure 7.5 shows each bit status and bus cycle. • Write cycle with the separate bus and no wait state • Read cycle and write cycle with the multiplexed bus and no wait state. • Read cycle and write cycle with the multiplexed bus and one wait state. Figure 7.3 shows the WCR register. Figures 7.4 and 7.5 show bus timing in an external space. Wait Control Register(1, 2, 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol WCR Address 000816 After Reset 1111 11112 Bit Symbol WCR0 Bit Name b1 b0 Function 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states b3 b2 RW RW External Space 0 Wait Bit WCR1 RW WCR2 External Space 1 Wait Bit WCR3 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states b5 b4 RW RW WCR4 External Space 2 Wait Bit WCR5 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states b7 b6 RW RW WCR6 External Space 3 Wait Bit WCR7 0 0: No wait state 0 1: 1 wait state 1 0: 2 wait states 1 1: 3 wait states RW RW NOTES: 1. When using the multiplexed bus, "2 waits" is selected even if the WCR register is set to "002" (no wait state) or "012" (1 wait state). "102" (2 wait states) and "112" (3 wait states) can be selected. 2. When using the separate bus, the read bus runs one BCLK cycle and the write bus runs two BCLK cycles (1 wait state) if the WCR register is set to "002". 3.The WCR register cannot be used in M32C/83T. Figure 7.3 WCR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 58 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus Table 7.5 Software Wait State and Bus Cycle Space SFR Internal ROM/RAM External Bus Status PM1 Register PM13 Bit 0 1 0 1 002 Separate Bus External Memory Multiplexed Bus 012 102 112 002 012 102 112 PM12 Bit WCR Register WCRj to WCRi Bits Bus Cycle 2 BCLK cycles 3 BCLK cycles 1 BCLK cycle 2 BCLK cycles Read :1 BCLK cycle Write : 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 4 BCLK cycles 3 BCLK cycle 3 BCLK cycles 3 BCLK cycles 4 BCLK cycles i = 0, 2, 4, 6 j = i + 1 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 59 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus (1) Separate Bus with No Wait State Bus cycle(1) Bus cycle(1) BCLK Write Signal Read Signal Data Bus Address Bus(2) Chip-Select Signal(2, 3) Output Address Input Address (2) Separate Bus with 1 Wait State Bus cycle(1) Bus cycle(1) BCLK Write Signal Read Signal Output Address Address Input Data Bus Address Bus(2) Chip-Select Signal(2, 3) (3) Separate Bus with 2 Wait States Bus cycle(1) Bus cycle(1) BCLK Write Signal Read Signal Data Bus Address Bus(2) Chip-Select Signal(2, 3) NOTES: 1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively. 2. The address bus and chip-select signal may be extended depending on CPU state such as an instruction queue buffer. 3. When the microcomputer continuously accesses the same external space (same CS area), the chipselect signal may be output continuously. Data Output Address Address Input Figure 7.4 External Bus Operation with Software Wait State (1) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 60 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus (1) Separate Bus with 3 Wait States Bus cycle(1) BCLK Write Signal Read Signal Data Bus Address Bus(2) Chip-Select Signal(2, 3) (2) Multiplexed Bus with 2 Wait States Bus cycle(1) BCLK Write Signal Read Signal ALE Address Bus Address Bus/Data Bus(2) Chip-Select Signal(2, 3) Address Address Data output Address Data output Address Bus cycle(1) Input Address Bus cycle(1) Address Input (3) Multiplexed Bus with 3 Wait States Bus cycle(1) BCLK Write Signal Read Signal Address Bus Address Bus/ Data Bus(2) ALE Chip-Select Signal(2, 3) Address Address Data output Address Bus cycle(1) Address Input NOTES: 1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively. 2. The address bus and chip-select signal may be extended depending on CPU state such as an instruction queue buffer. 3. When the microcomputer continuously accesses the same external space (same CS area), the chipselect signal may be output continuously. Figure 7.5 External Bus Operation with Software Wait State (2) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 61 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus 7.2.5 ALE Signal The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the ALE signal. The PM15 to PM14 bits in the PM1 register determine the output pin for the ALE signal. The ALE signal is output to an internal space and external space. (1) 8-Bit Data Bus ALE D0/A0 to D7/A7 A8 to A15 Address Data (1) (2) 16-Bit Data Bus ALE D0/A0 to D15/A15 Address Data (1) Address (2) A16 to A19 A20/CS3 A21/CS2 A22/CS1 A23/CS0 Address A16 to A19 A20/CS3 A21/CS2 A22/CS1 A23/CS0 Address (2) Address or CS Address or CS NOTES: 1. D0/A0 to D7/A7 are placed in high-impedance state when read. 2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port. Figure 7.6 ALE Signal and Address/Data Bus _______ 7.2.6 RDY Signal _______ The RDY signal facilitates access to external devices which need longer access time. When an "L" signal ________ is applied to the RDY pin on the falling edge of last BCLK of the bus cycle, wait states are inserted into the ________ bus cycle. When an "H" signal is applied to the RDY pin on the falling edge of the BCLK, the bus cycle starts running again. ________ Table 7.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure _____ ________ 7.7 shows an example of the RD signal extended by the RDY signal. Table 7.6 Microcomputer States in a Wait State(1) Item State Oscillation On _____ _____ _____ ________ RD Signal, WR Signal, Address Bus, CSi (i=0 to 3), Maintains the same state as when RDY signal __________ Data Bus, ALE Signal, HLDA, Programmable I/O Ports was received Internal Peripheral Circuits On NOTES: ________ 1. The RDY signal cannot be accepted immediately before software wait states are inserted. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 62 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus (1) Separate Bus with 2 Wait States 1st cycle 2nd cycle 3rd cycle 4th cycle BCLK RD CSi (1) (i=0 to 3) RDY tsu(RDY - BCLK) Timing to receive RDY (2) Multiplexed Bus with 2 Wait States 1st cycle 2nd cycle 3rd cycle 4th cycle BCLK RD CSi (1) (i=0 to 3) RDY tsu(RDY - BCLK) : Wait states inserted by RDY : Wait states inserted by program Timing to receive RDY tsu(RDY-BCLK): Setup time for RDY input Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3) NOTES: 1. The chip-select signal (CSi) may be extended depending on CPU state such as the instruction queue buffer. _____ ________ Figure 7.7 RD Signal Output Extended by RDY Signal _________ 7.2.7 HOLD Signal __________ The HOLD signal transfers bus privileges from the CPU to external circuits. When an "L" signal is applied __________ __________ to the HOLD pin , the microcomputer enters a hold state after bus access is completed. While the HOLD _________ pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal. Table 7.7 shows the microcomputer status in a hold state. __________ Bus is used in the following order of priority: HOLD, DMAC, CPU. __________ HOLD > DMAC > CPU Figure 7.8 Order of Bus Priority Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 63 of 488 M32C/83 Group (M32C/83, M32C/83T) 7. Bus Table 7.7 Microcomputer Status in a Hold State Item Oscillation _____ _____ _______ RD Signal, WR Signal, Address Bus, Data Bus, BHE, _______ _______ CS0 to CS3 Programmable I/O Ports: P0 to P15 __________ Status On High-impedance __________ HLDA Internal Peripheral Circuits ALE Signal Maintains the same state as when HOLD signal is received Output "L" On (excluding the watchdog timer) Output "L" 7.2.8 External Bus State when Accessing Internal Space Table 7.8 shows external bus states when an internal space is accessed. Table 7.8 External Bus State when Accessing Internal Space Item Address bus Data Bus When Read When Write _____ ______ ________ _________ RD, WR, WRL, WRH ________ BHE _______ _______ CS0 to CS3 ALE State when accessing SFR, internal ROM and internal RAM Holds an address of an external space accessed just before High-impedance High-impedance Output "H" Holds state of external space last accessed Output "H" Output ALE 7.2.9 BCLK Output The CPU clock operates the CPU. When combining the PM07 bit in the PM0 register set to "0" (BCLK output) and the CM01 to CM00 bits in the CM0 register set to "002", the CPU clock signal is output from P53 as BCLK. No BCLK is output in single-chip mode. Refer to 8. Clock Generating Circuit for details. _______ __________ __________ _____ 7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW) The DRAM control signals control the DRAM. The DRAM control signals are output when the DRAM area, determined by the AR0 to AR2 bits in the DRAMCONT register, is output. Table 7.9 lists each signal operation. _______ __________ __________ _____ Table 7.9 RAS, CASL, CASH and DW Signals Data Bus Width RAS L L L L L L L L CASL L L H L L H L L CASH L H L L H L Not used Not used DW H H H L L L H L Data Bus State Read data from both even and odd addresses Read 1-byte data from even address Read 1-byte data from odd address Write data to both even and odd addresses Write 1-byte data to even address Write 1-byte data to odd address Read 1-byte data Write 1-byte data 16 bits 8 bits Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 64 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8. Clock Generation Circuit 8.1 Types of Clock Generation Circuits Four circuits are incorporated to generate the system clock signal : • Main clock oscillation circuit • Sub clock oscillation circuit • On-chip oscillator • PLL frequency synthesizer Table 8.1 lists specifications of the clock generation circuit. Figure 8.1 shows a block diagram of the clock generation circuit. Figures 8.2 to 8.8 show registers controlling the clock. Table 8.1 Clock Generation Circuit Specifications Item Use Clock Frequency Connectable Oscillator or Additional Circuit Pins for Oscillator or for Additional Circuit Oscillation Stop/ Restart Function Oscillator State After Reset Other Main Clock Oscillation Circuit Sub Clock Oscillation Circuit On-chip Oscillator PLL Frequency Synthesizer • CPU clock source • Peripheral function clock source 20 MHz to 32 MHz ( See Table 8.2) • Low pass filter VCOUT (connect to low pass filter) P86 (connect to Vss) Available Stopped The sub clock cannot be used when using the PLL frequency synthesizer • CPU clock source • CPU clock source • CPU clock source • Peripheral function • Timer A and B • Peripheral function clock source clock source clock source Up to 32 MHz 32.768 kHz Approximatly 1 MHz • Ceramic resonator • Crystal oscillator • Crystal oscillator XIN, XOUT Available Oscillating External clock can be input XCIN, XCOUT Available Stopped External clock can be input. The PLL frequency synthesizer cannot be used when using the sub clock oscillation circuit. Available Stopped When the main clock stops oscillating, the on-chip oscillator starts oscillating automatically and becomes the clock source for the CPU and peripheral functions Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 65 of 488 Peripheral Function Clock Main Clock Oscillation Circuit 00 XIN XOUT On-chip Oscillator a b 01 fAD CLKOUT c PLL Frequency Synthesizer e 1 1 0 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 f1 1/2 1/2 1/2 1/2 1/2 CM21 CST 1/2n CM05 0 10 Port P53 fC f8 f32 f8 f32 f2n(1) CM02 CM17 11 CM01 to CM00 Main Clock SQ R 1/m (Note 2) 0 M32C/83 Group (M32C/83, M32C/83T) Figure 8.1 Clock Generation Circuit Page 66 of 488 Sub Clock Oscillation Circuit CM07 1 WAIT Instruction (wait mode) Software Reset fC CPSR=1 Divider Reset XCIN XCOUT CPU Clock BCLK RESET NMI CM04 Sub Clock Output to determine an interrupt request level SQ R 1/32 fC32 CM10 = 1 (stop mode) CM0i : Bit in CM0 register CM1i : Bit in CM1 register CM2i : Bit in CM2 register CST : Bit in TCSPR register CPSR : Bit in CPSRF register NOTES: 1. The CNT3 to CNT0 bits in the TCSRR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. The MCD4 to MCD0 bits in the MCD register select divide-by-m (m=1,2,3,4,6,8,10,12,14,16 ). On-chip Oscillator PLL Frequency Synthesizer a Clock Edge Detect /Charge and Discharge Circuit Control Circuit to Generate Oscillation Stop Detect Interrupt Request Interrupt Request Signal Watchdog Timer Interrupt Request On-chip Oscillator Charge and Discharge Circuit Programmable Counter Phase Comparator Charge Pump 1/2 e 1/3 PLC11 PLL Clock c Reference Frequency Counter Voltage Controlled Oscillator (VCO) PLC12 b On-chip Oscillator Clock CM21 Switch Signal PLC07 : Bit in PLC0 register PLC11, PLC12 : Bits in PLC1 register PLC07 VCONT 8. Clock Generation Circuit M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit System Clock Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 After Reset 0000 X0002 1 Bit Symbol CM00 Bit Name b1 b0 Function 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 RW RW Clock Output Function Select Bit(2) CM01 In Wait Mode, Peripheral Function Clock Stop Bit Reserved Bit RW CM02 0 : Peripheral clock does not stop in wait mode RW 1 : Peripheral clock stops in wait mode(3) Set to "1" RW (b3) CM04 Port XC Switch Bit Main Clock (XIN-XOUT) Stop Bit(5) Watchdog Timer Function Select Bit System Clock Select Bit(8) 0 : I/O port function RW 1 : XCIN-XCOUT oscillation function(4) 0 : Main clock oscillates 1 : Main clock stops(6) 0 : Watchdog timer interrupt 1 : Reset(7) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock RW CM05 CM06 RW CM07 RW NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to "002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00 bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", XOUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT. 7. Once the CM06 bit is set to "1", it cannot be set "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bits simultaneously. Figure 8.2 CM0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 67 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit System Clock Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 010000 Symbol CM1 Bit Symbol Address 000716 After Reset 0010 00002 Bit Name All Clock Stop Control Bit(2) Reserved Bit Function 0 : Clock oscillates 1 : All clocks stop (stop mode)(3) Set to "0" RW RW CM10 (b4 - b1) RW Reserved Bit (b5) Reserved Bit CPU Clock Select Bit 2(4) Set to "1" RW RW (b6) CM17 Set to "0" 0 : Main clock 1 : PLL clock RW NOTES: 1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the CM10 bit is set to "1", XOUT becomes "H" and the internal feedback resistance is disabled. XIN, XCIN and XCOUT are placed in high-impedance states. 3. When the CM10 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1". 4. CM17 bit is enabled only when the CM21 bit in the CM2 register is set to "0". Use the procedure shown in Figure 8.13 to set the CM17 bit to "1". Figure 8.3 CM1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 68 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Main Clock Division Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol MCD Bit Symbol Address 000C16 After Reset XXX010002 Bit Name b4 b3 b2 b1 b0 Function 1 0 0 1 0 : Divide-by-1(no division) mode 0 0 0 1 0 : Divide-by-2 mode 0 0 0 1 1 : Divide-by-3 mode 0 0 1 0 0 : Divide-by-4 mode 0 0 1 1 0 : Divide-by-6 mode 0 1 0 0 0 : Divide-by-8 mode 0 1 0 1 0 : Divide-by-10 mode 0 1 1 0 0 : Divide-by-12 mode 0 1 1 1 0 : Divide-by-14 mode 0 0 0 0 0 : Divide-by-16 mode (Note 3) RW RW MCD0 MCD1 Main Clock Division Select Bit(2, 4) RW MCD2 RW RW MCD3 MCD4 RW (b7 - b5) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. While the microcomputer is in stop mode or low-power consumption mode, the MCD register is set to "0816" (divide-by-8 mode). In on-chip oscillator mode, divide-by-8 mode cannot be entered even if the CM05 bit in the CM0 register is set to "1"(XIN-XOUT stopped). 3. Do not set to bit combinations not listed above. 4. Access CAN-associated register addresses (addresses 01E016 to 024516) after setting the MCD register to "1216" (no division mode). Figure 8.4 MCD Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 69 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Oscillation Stop Detect Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM2 Bit Symbol Address 000D16 0000 After Reset 0016 Bit Name Oscillation Stop Detect Enable Bit CPU Clock Select Bit(2, 3) Oscillation Stop Detect Flag(4) XIN Clock Monitor Flag(5) Function RW CM20 0: Disables oscillation stop detect function RW 1: Enables oscillation stop detect function 0: Clock selected by the CM17 bit 1: On-chip oscillator clock 0: Main clock does not stop 1: Detects main clock stop 0: Main clock oscillates 1: Main clock stops Set to "0" RW CM21 CM22 RW CM23 RO (b7 - b4) Reserved Bit RW NOTES: 1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the main clock oscillation stop is detected while the CM20 bit is set to "1" (oscillation stop detect function enabled), the CM21 bit is set to "1". Although the main clock starts oscillating, the CM21 bit is not set to "0". When the main clock is used as a CPU clock source after the main clock resumes oscillation, set the CM21 bit to "0" by program. 3. When the CM20 bit is set to "1" (oscillation stop detect function enabled) and the CM22 bit is set to "1", do not set the CM21 bit to "0". 4. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0", not "1", by program. If the CM22 bit is set to "0" by program while the main clock is stopped, the CM22 bit cannot be set to "1" until the next main clock stop is detected. 5. Determine the main clock state by reading the CM23 bit several times after the oscillation stop interrupt is generated. Figure 8.5 CM2 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 70 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Count Source Prescaler Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TCSPR Bit Symbol Address 035F16 After Reset(2) 0XXX 00002 Bit Name Function RW RW CNT0 If setting value is n, f2n is divided the main clock, on-chip oscillator clock or PLL clock by 2n. When n is set to "0", no division is selected. CNT1 Division Rate Select Bit(1) RW RW CNT2 CNT3 Nothing is assigned. When write, set to "0". (b6 - b4) When read, its content is indeterminate. CST Operation Enable Bit 0: Divider stops 1: Divider starts RW RW NOTES: 1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "1". 2. Value of the TCSPR register is not reset by software reset or watchdog timer reset. Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit Symbol Address 034116 After Reset 0XXX XXXX2 Bit Name Function RW Nothing is assigned. When write, set to "0". (b6 - b0) When read, its content is indeterminate. CPSR Clock Prescaler Reset Flag When the CPSR bit is set to "1", fC divided by 32 is reset. When read, its content is "0". RW Figure 8.6 TCSPR and CPSRF Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 71 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit PLL Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 001 Symbol PLC0 Bit Symbol Address 037616 After Reset 0011 X1002 Bit Name Function RW RW PLC00 Programmable Counter Select Bit(2) PLC01 See Table 8.2 RW PLC02 Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Reserved Bit(2) Reserved Bit(2) Set to "1" RW (b3) (b4) RW (b5) Set to "0" RW (b6) PLC07 Reserved Bit Operation Enable Bit(3, 4) Set to "0" 0: PLL is Off 1: PLL is On RW RW NOTES: 1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. Set these bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be changed. 3. To use the PLL function, the PD8_7 bit in the PD8 register is set to "0" (input) and the CM04 bit in the CM0 register is set to "0" (I/O port). Set the PD8_6 bit in the PD8 register to "0" (input) before connecting P86 to Vss. 4. Before the microcomputer enters wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), the PLC07 bit to "0" and PLV00 bit to "0" (cut off power to PLL) in this order. VDC Control Register for PLL(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PLV Bit Symbol Address 001716 After Reset XXXX XX012 Bit Name PLL VDC Enable Bit(2) Function 0 : Cut off power to PLL 1 : Power to PLL Set to "0" RW RW PLV00 (b1) Reserved Bit RW Nothing is assigned. When write, set to "0". (b7 - b2) When read, its content is indeterminate. NOTES: 1. Rewrite the PLV register after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. Before the microcomputer enters wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source), the PLC07 bit to "0" (PLL off) and PLV00 bit to "0" (cut off power to PLL) in this order. Figure 8.7 PLC0 and PLV Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 72 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit PLL Control Register 1(1, 2) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PLC1 Bit Symbol Address 037716 After Reset XXXX 00002 Bit Name Reserved Bit PLL Clock Division Enable Bit(3) PLL Clock Division Switch Bit(4) Reserved Bit Set to "0" Function RW RW (b0) PLC11 0 : Disables the PLL clock to be divided RW 1 : Enables the PLL clock to be divided 0 : Divide-by-2 1 : Divide-by-3 Set to "0" RW PLC12 (b3) RW Nothing is assigned. When write, set to "0". (b7 - b4) When read, its content is indeterminate. NOTES: 1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. Rewrite the PLC1 register after the CM17 bit in the CM1 register is set to "0" (main clock) . 3. When the CM21 bit in the CM2 register is set to "0" (clock selected by the CM17 bit), if the PLC11 bit is set to "1" before the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock dividedby-2 or divided-by-3 becomes the clock source of the CPU clock and peripheral function clock. 4. Do not rewrite the PLC12 bit if the PLL clock is the CPU clock source. Figure 8.8 PLC1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 73 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.1.1 Main Clock Main clock oscillation circuit generates the main clock. The main clock becomes a clock source for the CPU clock and peripheral function clock. The main clock oscillation circuit is configured by connecting an oscillator or resonator between the XIN and XOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the oscillation circuit in stop mode to reduce power consumption. The externally generated clock can be input to the XIN pin in the main clock oscillation circuit. Figure 8.9 shows an example of a main clock circuit connection. Circuit constants vary with each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The main clock divided-by-eight becomes the CPU clock after reset. To reduce power consumption, set the CM05 bit in the CM0 register to "1" (main clock stopped) after switching the CPU clock source to the sub clock or on-chip oscillator clock. In this case, XOUT becomes "H". XIN is pulled up by XOUT via the feedback resistor which remains on. When an externally generated clock is input to the XIN pin, the main clock does not stop even if the CM05 bit is set to "1". Terminate main clock operation externally if necessary. All clocks, including the main clock, stop in stop mode. Refer to 8.5 Power Consumption Control for details. Microcomputer (Built-in Feedback Resistor) CIN XIN Microcomputer (Built-in Feedback Resistor) XIN External Clock VCC VSS Oscillator XOUT Rd(1) VSS COUT XOUT Open NOTE: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally. Figure 8.9 Main Clock Circuit Connection Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 74 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.1.2 Sub Clock Sub clock oscillation circuit generates the sub clock. The sub clock becomes a clock source for the CPU clock and a count source for the timers A and B. The same frequency, fc, as the sub clock can be output from the CLKOUT pin. The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and XCOUT pins. The circuit has a built-in feedback resistor. The feedback resistor is separated from the oscillation circuit in stop mode to reduce power consumption. The externally generated clock can be applied to the XCIN pin. Figure 8.10 shows an example of a sub clock circuit connection. Circuit constants vary with each oscillator. Use the circuit constant recommended by each oscillation manufacturer. The sub clock stops after reset. The feedback resistor is separated from the oscillation circuit. When the PD8_6 and PD8_7 bits in the PD8 register are set to "0" (input mode) and the PU25 bit in the PUR2 register is set to "0" (no pull-up), set the CM04 bit in the CM0 register to "1" (XCIN-XCOUT oscillation function). The sub clock oscillation circuit starts oscillating. To apply the external clock to the XCIN pin, set the CM04 bit to "1" when the PD8_6 bit is set to "0" and the PU25 bit to "0". The clock applied to the XCIN pin becomes the clock source for the sub clock. When the CM07 bit in the CM0 register is set to "1" (sub clock) after the sub clock oscillation has stabilized, the sub clock becomes the CPU clock. All clocks, including the sub clock, stop in stop mode. Refer to 8.5 Power Consumption Control for details. XCIN shares pins with VCONT and XCOUT shares pins with P86. The sub clock and PLL frequency synthesizer cannot be used simultaneously. Microcomputer (Built-in Feedback Resistor) CCIN XCIN Microcomputer (Built-in Feedback Resistor) XCIN External Clock VCC VSS Oscillator XCOUT RCd(1) VSS CCOUT XCOUT Open NOTE: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally. Figure 8.10 Sub Clock Connection Circuit Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 75 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.1.3 On-chip Oscillator Clock On-chip oscillator generates the on-chip oscillator clock. The 1MHz on-chip oscillator clock becomes a clock source for the CPU clock and peripheral function clock. The on-chip oscillator clock stops after reset. When the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock), the on-chip oscillator starts oscillating. Instead of the main clock, the on-chip oscillator clock becomes the clock source for the CPU clock and peripheral function clock. 8.1.3.1 Oscillation Stop Detect Function When the main clock is terminated by external factors, the on-chip oscillator automatically starts oscillating to generate another clock. When the CM 20 bit is set to "1" (oscillation stop detect function enabled), the oscillation stop detect interrupt request is generated as soon as the main clock stops. Simultaneously, the on-chip oscillator starts oscillating. The on-chip oscillator clock takes place of the main clock as the clock source for the CPU clock and peripheral function clock. Associated bits are set as follows: • CM21 bit = 1 (on-chip oscillator clock becomes the clock source of the CPU clock.) • CM22 bit = 1 (main clock stop is detected.) • CM23 bit = 1 (main clock stops) (See Figure 8.15) 8.1.3.2 How to Use Oscillation Stop Detect Function • The oscillation stop detect interrupt shares vectors with the watchdog timer interrupt. When both oscillation stop detect interrupt and watchdog timer interrupt are used, read the CM22 bit with an interrupt service routine to determine which interrupt request has been generated. • When the main clock resumes running after an oscillation stop is detected, set the main clock as the clock source for the CPU clock and peripheral function clock. Figure 8.11 shows the procedure to switch the on-chip oscillator clock to the main clock. • In low-speed mode, when the main clock is stopped by setting the CM20 bit to "1", the oscillation stop detect interrupt request is generated. Simultaneously, the on-chip oscillator starts oscillating. The sub clock remains the CPU clock. The on-chip oscillator clock becomes the clock source for the peripheral function clock. • To enter wait mode while the oscillation stop detect interrupt function is in use, set the CM02 bit to "0" (peripheral function clock does not stop in wait mode). • When the oscillation stop detect interrupt request is generated in wait mode, wait mode cannot be exited by the oscillation stop detect interrupt. After the microcomputer exits wait mode, the oscillation stop detect interrupt is acknowledged first, followed by the interrupt used to exit wait mode. • The oscillation stop detect function is provided to handle main clock stop caused by external factors. Set the CM20 bit to "0" (oscillation stop detect function disabled) when the main clock is terminated by program, i.e., entering stop mode or setting the CM05 bit is set to "1" (main clock oscillation stop). • When the main clock frequency is 2MHz or less, the oscillation stop detect function is not available. Set the CM20 bit to "0". Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 76 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Switch to the main clock No Determine several times whether the CM23 bit is set to "0" (main clock oscillates) Yes Set the MCD register to "0816" (divide-by-8) Set the CM22 bit to "0" (main clock does not stop) Set the CM21 bit to "0" (main clock as CPU clock source) End CM21 to CM23 bits : Bits in CM2 register Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock 8.1.4 PLL Clock The PLL frequency synthesizer generates the PLL clock based on the main clock. The PLL clock can be used as a clock source for the CPU clock or peripheral function clock. Connect a resistor and capacitor to the VCONT pin when using the PLL frequency synthesizer. Set the PD8_6 and PD8_7 bits in the PD8 register to "0" (input mode) and the CM04 bit to "0" (the XCIN and XCOUT pins as ports). After that, connect the VCONT pin, the P86 pin, and the VSS pin to the circuit as is shown in Figure 8.12. Set the PLV00 bit in the PLV register to "1" (power to PLL). The PLL frequency synthesizer stops after reset. When the PLC07 bit is set to "1" (PLL on), the PLL frequency synthesizer starts operating. Wait 20 ms (5 V operation) to 50 ms (3.3 V operation) for the PLL clock to stabilize. The PLL clock can either be the clock output from the voltage controlled oscillator (VCO) divided-by-2 or divided-by-3. When the PLL clock is used as a clock source for the CPU clock or peripheral function clock, set each bit as is shown in Table 8.2. Figure 8.13 shows the procedure for using the PLL clock as the CPU clock source. To enter wait or stop mode, set the CM17 bit to "0" (main clock as CPU clock source). Set the PLC07 bit in the PLC0 register to "0" (PLL off) and the PLV00 bit to "0" (no power to PLL) before the microcomputer enters wait or stop mode. The VCONT and P86 pins share pins with XCIN and XCOUT pins. When the PLL frequency synthesizer is being used, the sub clock cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 77 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Microcomputer R1 VCONT C1 P86 VSS NOTES: 1. Connect VSS to GND via C1 and C2 with shortest possible wiring. Ground pattern must be formed around the circuit. C2 2. Optimal values of the low pass filter circuit element, connected to the VCONT pin, varies with environment (e.g.noise). Evaluate not only with these optimal values, but also with other values, to determine the values most appropriate for your system. Use capacitors for temperature compensation. C1=220pF, C2=0.1 µF, R1=1 kΩ(2) Figure 8.12 External Circuit with PLL Frequency Synthesizer Table 8.2 Bit Settings to Use PLL Clock as CPU Clock Source PLC0 Register PLC1 Register f(XIN) PLL Clock PLC02 PLC01 PLC00 PLC12 0 30 MHz 10MHz 0 1 1 1 20 MHz 0 32MHz 8MHz 1 0 0 1 21.3MHz Use PLL clock as CPU clock source Set the PLC11 bit to "1" (PLL clock division enabled) Set the PLC02 to PLC00 bits and the PLC12 bit Set the PLC07 bit to "1" (PLL on) Wait 20 to 50ms Set the CM17 bit to "1" (PLL clock as CPU clock source) PLC11 and PLC12 bits : Bit in PLC1 register PLC00 to PLC02 bits, PLC07 bit : Bits in PLC0 register CM17 bit : Bit in CM1 register End Figure 8.13 Procedure to Use PLL Clock as CPU Clock Source Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 78 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.2 CPU Clock and BCLK The CPU operation clock is referred to as the CPU clock. The CPU clock is also the count source for the watchdog timer. After reset, the CPU clock is the main clock divided-by-8. In memory expansion or microprocessor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Refer to 8.4 Clock Output Function for details. The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the CPU clock. Table 8.3 shows CPU clock source and bit settings. When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock, the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock. The MCD register selects the clock division. When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip oscillator clock is the CPU clock), the MCD register is set to "0816" (divide-by-8 mode). Therefore, when the main clock starts running, the CPU clock enters middle-speed mode (divide-by-8). Table 8.3 CPU Clock Source and Bit Settings CM0 Register CPU Clock Source CM07 Main Clock Sub Clock On-chip Oscillator Clock PLL Clock 0 1 0 0 CM2 Register CM21 0 0 1 0 CM1 Register CM17 0 0 0 1 8.3 Peripheral Function Clock The peripheral function clock becomes the operation clock or count source for peripheral functions excluding the watchdog timer. 8.3.1 f1, f8, f32 and f2n f1, f8, f32 and f2n are the main clock(1) or on-chip oscillator clock divided-by-1, -8, -32 ,or -2n (n=1 to 15. No division when n=0). The CM21 bit determines which clock is selected. When the CM02 bit is set to "1" (peripheral function stops in wait mode) when entering wait mode, f1, f8, f32 and f2n stop running. These clocks also stop in low-power consumption mode. f1, f8 and f2n are used as the operation clock for the serial I/O and the count source for timers A and B. The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. f1 is also used as the operation clock for the intelligent I/O. The CLKOUT pin outputs f8 and f32 . Refer to 8.4 Clock Output Function for details. 8.3.2 fAD fAD is the operation clock for the A/D convertor and has the same frequency as the main clock(1) and onchip oscillator clock. The CM21 bit determines which clock is selected. When the CM02 bit is set to "1" (peripheral function stop in wait mode) when entering wait mode, fAD stops. fAD also stops in low-power consumption mode. NOTES: 1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 79 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.3.3 fC32 fC32 is the sub clock divided by 32. fC32 is used for as a count source for the timers A and B. fC32 is available when the sub clock is running. 8.4 Clock Output Function The CLKOUT pin outputs fC, f8 or f32. In memory expansion and microprocessor modes, a clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Table 8.4 lists CLKOUT pin function in single-chip mode. Table 8.5 lists CLKOUT pin functions in memory expansion and microprocessor modes. Table 8.4 CLKOUT Pin in Single-Chip Mode PM0 Register (1) CM0 Register (2) PM07 1 1 1 CM01 0 0 1 1 CM00 0 1 0 1 CLKOUT Pin Function P53 I/O port Outputs fc Outputs f8 Outputs f32 - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable) 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable) Table 8.5 BLCK/CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode(4) PM1 Register(1) PM15 PM14 PM0 Register(1) PM07 0 1 002, 102, 112, 1 1 1 0 1 CM0 Register(2) CM01 0 (3) 0 0 1 1 0 (3) CM00 0 (3) 0 1 0 1 0 (3) CLKOUT Pin Function Outputs BCLK Outputs "L" (not P53) Outputs fc Outputs f8 Outputs f32 Outputs ALE - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 and PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable) 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable) 3. When the PM07 bit is set to "0" (selected in the CM01 to CM00 bits) or the PM15 to PM14 bits are set to "012" (P53/BCLK), set the CM01 to CM00 bits to "002" (I/O port P53) 4. M32C/83T cannot be used in memory expansion mode and microprocessor mode. 8.5 Power Consumption Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document. Figure 8.14 shows a block diagram of status transition in wait mode and stop mode. Figure 8.15 shows a block diagram of status transition in all modes. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 80 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.5.1 Normal Operation Mode The normal operation mode is further separated into six modes. In normal operation mode, the CPU clock and peripheral function clock are supplied to operate the CPU and peripheral function. The power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillation circuits stop, power consumption is further reduced. 8.5.1.1 High-Speed Mode The main clock(1) becomes the CPU clock and the clock source for the peripheral function clock. When the sub clock runs, fC32 can be used as a count source for the timers A and B. 8.5.1.2 Medium-Speed Mode The main clock divided-by-2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The main clock is the clock source for the peripheral function clock. When the sub clock runs, fC32 can be used as the count source for the timers A and B. 8.5.1.3 Low-Speed Mode The sub clock becomes the CPU clock. The main clock is the count source for the peripheral function clock. fC32 can be used as the count source for the timers A and B. 8.5.1.4 Low-Power Consumption Mode The microcomputer enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock becomes the CPU clock. fC32 can be used as the count source for timers A and B. Only fC32 can be used as the peripheral function clock. In low-power consumption mode, the MCD register is set to "0816" (divide-by-8 mode). Therefore, when the main clock resumes running, the microcomputer is in middle-speed mode (divide-by-8 mode). 8.5.1.5 On-chip Oscillator Mode The on-chip oscillator clock divided-by-1(no division), -2, -3, -4, -6, -8, -10, -12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is the clock source for the peripheral function clock. When the sub clock runs, fC32 can be used as the count source for the timers A and B. 8.5.1.6 On-chip Oscillator Low-Power Consumption Mode The microcomputer enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip oscillator mode. The on-chip oscillator clock divided-by-1(no division), -2, -3, -4, -6, -8, -10, 12, -14, or -16 becomes the CPU clock. The on-chip oscillator clock is the clock source for the peripheral function clock. When the sub clock runs, fC32 can be used as the count source for the timers A and B. Switch the CPU clock after the clock to be switched to stabilizes. Sub clock oscillation will take longer(2) to stabilize. Wait, by program, until the clock stabilizes directly after running the microcomputer on or exiting stop mode. To switch the on-chip oscillator to the main clock, enter medium-speed mode (divide-by-8) after the main clock is divided by eight in on-chip oscillator mode (MCD register=0816). Do not enter on-chip oscillator mode or on-chip oscillator low-power consumption mode from low-speed mode or low-power consumption mode and vice versa. NOTES: 1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock . 2. Contact your oscillator manufacturer for oscillation stabilization time. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 81 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.5.2 Wait Mode In wait mode, the CPU clock stops running. The CPU and watchdog timer, operated by the CPU clock, also stop. Because the main clock, sub clock and on-chip oscillator clock continue running, peripheral functions using these clocks also continue operating. 8.5.2.1 Peripheral Function Clock Stop Function If the CM02 bit is set to "1" (peripheral function clock stops in wait mode), f1, f8, f32, f2n and fAD stop in wait mode. Power consumption can be reduced because the peripheral function that has f1, f8, f32, f2n, or fAD as a count source stops. fC32 does not stop running. 8.5.2.2 Entering Wait Mode Follow the procedure below to enter wait mode. • Initial Setting Set each interrupt priority level after setting the exit priority level required to exit wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7". • Before Entering Wait Mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit wait mode (3) Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0" (4) Set the IPL in the FLG register. Then set the exit priority level to the same level as IPL (Interrupt priority level of the interrupt used to exit wait mode > exit priority level ≥ interrupt priority level of the interrupts not used to exit wait mode) (5) Set the PRC0 bit in the PRCR register to "1" (write enable) (6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock), the PLC07 bit in the PLC0 register to "0" (PLL off), and the PLV00 bit in the PLV register to "0"(cut off power to PLL) (7) Set the I flag to "1" (8) Execute the WAIT instruction • After Exiting Wait Mode Set the interrupt priority level required to exit wait mode to "7" immediately after exiting wait mode. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 82 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit 8.5.2.3 Pin Status in Wait Mode Table 8.6 lists pin states in wait mode. Table 8.6 Pin Status in Wait Mode Pin _______ _______ Memory Expansion Mode Microprocessor Mode Maintains state immediately before entering wait mode Single-Chip Mode Address Bus, Data Bus, CS0 to CS3, ________ BHE _____ ______ ________ _________ ______ _________ ________ RD, WR, WRL, WRH, DW, CASL, CASH ________ "H" (1) "H" (1) "H" "L" Maintains state immediately before entering wait mode RAS __________ HLDA, BCLK ALE Port CLKOUT When fC is selected When f8, f32 are selected Outputs clock The clock is output when the CM02 bit in the CM0 register is set to "0" (peripheral function clock not stop in wait mode). Maintains state immediately before entering wait mode when the CM02 bit is set to "1" (peripheral function clock stopped in wait mode). NOTES: ________ ________ 1. When performing a self-refresh operation using the DRAMC, CAS and RAS become low ("L"). 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode. 8.5.2.4 Exiting Wait Mode _______ Wait mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts. _______ When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupt disabled) before executing the WAIT instruction. The CM02 bit affects the peripheral function interrupts. When the CM02 bit is set to "0" (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait mode), peripheral functions using the peripheral function clock stop. Therefore, the peripheral function interrupts cannot be used to exit wait mode. However, peripheral function interrupts caused by an external signal can be used to exit wait mode. _______ The CPU clock used when exiting wait mode by the peripheral function interrupts or NMI interrupt is the same CPU clock used when WAIT instructions are executed. Table 8.7 shows interrupts to be used to exit wait mode and usage conditions. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 83 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Table 8.7 Interrupts to Exit Wait Mode Interrupt _______ When CM02=0 Available Available when the internal and external clocks are used Available When CM02=1 NMI Interrupt Serial I/O Interrupt Available only when the external clock is used Key Input Interrupt Available Available A/D Conversion Interrupt Available in single or single-sweep mode Do not use Timer A Interrupt Timer B Interrupt ______ Available in all modes Available in event counter mode or when the count source is fC32 INT Interrupt CAN Interrupt Intelligent I/O Interrupt Available Available Available Available Do not use Do not use 8.5.3 Stop Mode In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as the CPU and peripheral functions operated by these clocks, also stop. The least power required to operate the microcomputer is in stop mode. The internal RAM holds its data if the voltage applied to the Vcc pin is 2.5V or more. ______ ______ Interrupts used to exit stop mode are NMI interrupt, key input interrupt, and INT interrupt. 8.5.3.1 Entering Stop Mode Stop mode is entered when setting the CM10 bit in the CM1 register to "1" (all clocks stops). The MCD4 to MCD0 bits in the MCD register become set to "010002" (divide-by-8 mode). Enter stop mode after setting the followings. • Initial Setting Set each interrupt priority level after setting the minimum interrupt priority level required to exit stop or wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7". • Before Entering Stop Mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit stop mode (3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0" (4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL (Interrupt priority level of the interrupt used to exit stop mode > interrupt priority level to exit stop mode ≥ interrupt priority level of the interrupts not used to exit stop mode) (5) Set the PRC0 bit in the PRCR register to "1" (write enabled) (6) Select the main clock as the CPU clock • When the CPU clock source is the sub clock, Set the CM05 bit in the CM0 register to "0" (main clock oscillates) and CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD register setting) • When the CPU clock source is the PLL clock, Set the CM17 bit in the CM1 register to "0" (main clock) and the PLC07 bit in the PLC0 register to "0" (PLL off) • When the CPU clock source is the on-chip oscillator clock, Set the MCD4 to MCD0 bits to "010002" (divide-by-8 mode), the CM05 bit to "0" (main clock oscillates), and the CM21 it in the CM2 register to "0" (clock selected by the CM17 bit) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 84 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit (7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscilla tion stop detect function disabled) (8) Set the I flag to "1" (9) Set the CM10 bit to "1" (all clocks stops) • After Exiting Stop Mode Set the interrupt priority level required to exit stop mode to "7" immediately after exiting stop mode. 8.5.3.2 Exiting Stop Mode _______ Stop mode is exited by the hardware reset, NMI interrupt, or peripheral function interrupts (key input ______ interrupt and INT interrupt). _______ When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to "0002" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops). 8.5.3.3 Pin Status in Stop Mode Table 8.8 lists pin status in stop mode. Table 8.8 Pin Status in Stop Mode Pin _______ _______ _______ Memory Expansion Mode Microprocessor Mode(2) Maintains state immediately before entering stop mode Single-Chip Mode Address Bus, Data Bus, CS0 to CS3, BHE _____ ______ ________ _________ ______ _________ ________ RD, WR, WRL, WRH, DW, CASL, CASH ________ "H" (1) "H" (1) "H" "H" Maintains state immediately before entering stop mode RAS __________ HLDA, BCLK ALE Port CLKOUT When fC selected When f8, f32 selected XIN XOUT XCIN, XCOUT "H" Maintains state immediately before entering stop mode High-impedance "H" High-impedance NOTES: ________ ________ 1. When performing a self-refresh operation using DRAMC, CAS and RAS become low ("L"). 2. M32C/83T cannot be used in memory expansion mode and microprocessor mode. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 85 of 488 M32C/83 Group (M32C/83, M32C/83T) 8. Clock Generation Circuit Reset All oscillation is stopped CM10=1 (Note 2) CPU operation is stopped Stop mode Interrupt Inter rupt Middle-speed mode (divide-by-8 mode) (Note 1) (Note 2) WAIT instruction Interrupt Wait mode (Note 2) Stop mode CM10=1 (Note 2) High-speed / middle-speed mode (Note 1) WAIT instruction Wait mode Interrupt Low-speed/ low-power consumption mode (Note 3) WAIT instruction Wait mode Interrupt On-chip oscillator / On-chip oscillator lowpower consumption Normal operation mode WAIT instruction Interrupt Wait mode NOTES: 1. See Figure 8.15. 2. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source) before the PLC07 bit is set to "0" (PLL off). Set the PLV00 bit to "0" (no power to PLL) before the microcomputer enters wait mode or stop mode. 3. When the PLL frequency synthesizer is used, the microcomputer cannot enter low-speed and low-power consumption mode. Figure 8.14 Status Transition in Wait Mode and Stop Mode Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 86 of 488 After reset, middle-speed mode ( divide-by-8) MCD=XX16 (Note 1) High-speed mode PLC11=0 CM17=0 High-speed mode Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Main clock oscillation Sub clock stop On-chip oscillator clock stop PLL clock stop CPU clock: f(XIN)/8 CM07=0 MCD=0816 CM21=0 CM05=0 CM04=0 PLC07=0 PLC11=0 CM17=0 Main clock oscillation Sub clock oscillation On-chip oscillator clock stop PLL clock oscillation Main clock oscillation Sub clock oscillation On-chip oscillator clock stop PLL clock oscillation CM04=1 (Note 1) CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=1 PLC07=1 PLC11=0 CM17=0 PLC07=0 PLC11=1 CM17=1 (Note 6) CPU clock: f(XPLL) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=1 PLC07=1 PLC11=1 CM17=1 Main clock oscillation Sub clock stop On-chip oscillator clock stop PLL clock stop Main clock oscillation Sub clock oscillation On-chip oscillator clock stop PLL clock stop High-speed mode CM04=0 CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 CM07=0 (Note 1) PLC07=1 High-speed mode PLC07=1 CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=0 PLC07=0 PLC11=0 CM17=0 CM04=1 Middle-speed mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=1 PLC07=1 PLC11=0 CM17=0 Middle-speed mode CPU clock: f(XPLL)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=1 PLC07=1 PLC11=1 CM17=1 Low-speed mode PLC07=0 Middle-speed mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=0 PLC07=0 PLC11=0 CM17=0 Middle-speed mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 CM07=1 (Note 2) Main clock stop is detected when CM20=1 Low-speed mode CM21=1 On-chip oscillator mode (Note 1) CM21=0 CM21=1 (Note 1) CM21=0 On-chip oscillator mode Main clock oscillation Sub clock oscillation On-chip oscillator clock stop PLL clock stop CPU clock: f(XCIN) CM07=1 CM21=0 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 CM21=0 CM21=1 (Note 1) Main clock stop is detected when CM20=1 CM04=1 CM04=0 CM07=0 Main clock oscillation Sub clock stop On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/ n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=1 CM05=0 CM04=0 PLC07=0 PLC11=0 CM17=0 Main clock oscillation Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=1 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 CM05=1 (Note 5) CM05=0 On-chip oscillator low power consumption mode CM05=1 CM07=1 (Note 2) Main clock oscillation Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: f(XCIN) CM07=1 CM21=1 CM05=0 CM04=1 PLC07=0 PLC11=0 CM17=0 CM05=0 Low power consumption mode CM05=1 Low power consumption mode CM05=0 CM05=1 CM05=0 On-chip oscillator low power consumption mode CM04=0 (Note 4, 5) Main clock stop Sub clock stop On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=1 CM05=1 CM04=0 PLC07=0 PLC11=0 CM17=0 CM04=1 Main clock stop Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: On-chip oscillator clock/n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=1 CM05=1 CM04=1 PLC07=0 PLC11=0 CM17=0 Main clock stop Sub clock oscillation On-chip oscillator clock oscillation PLL clock stop CPU clock: f(XCIN) CM07=1 MCD=0816 CM21=1 CM05=1 CM04=1 PLC07=0 PLC11=0 CM17=0 (Note 3) Main clock stop Sub clock oscillation On-chip oscillator clock stop PLL clock stop CPU clock: f(XCIN) CM07=1 MCD=0816 CM21=0 CM05=1 CM04=1 PLC07=0 PLC11=0 CM17=0 (Note 3) 5. The CM05 bit is not set to "1" when the microcomputer detects a main clock oscillation stop through the oscillation stop detect circuit . 6. To select the PLL clock, set the PLC07 bit to "1" (PLL on) after the PLC11 bit is set to "1" (division enabled). To select the main clock, set the PLC11 bit to "0" (division disabled) after the PLC07 bit is set to "0" (PLL off). Switch the PLL clock after a PLL clock oscillation is fully stabilized. Figure 8.15 Status Transition Main clock oscillation Sub clock stop On-chip oscillator clock stop PLL clock oscillation Main clock oscillation Sub clock stop On-chip oscillator clock stop PLL clock oscillation M32C/83 Group (M32C/83, M32C/83T) Page 87 of 488 High-speed mode CPU clock: f(XPLL) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=0 PLC07=1 PLC11=1 CM17=1 PLC11=1 CM17=1 High-speed mode CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=0 PLC07=1 PLC11=0 CM17=0 Middle-speed mode CPU clock: f(XPLL)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=0 PLC07=1 PLC11=1 CM17=1 PLC11=0 CM17=0 (Note 6) Middle-speed mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=0 PLC07=1 PLC11=0 CM17=0 8. Clock Generation Circuit : Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown. MCD=XX16: Desired division must be set in the MCD register. NOTES: 1. Switch clock after main clock oscillation is fully stabilized. 2. Switch clock after sub clock oscillation is fully stabilized. 3. The MCD register is set to "0816" (divide-by-8 mode) automatically. 4. When the CM20 bit is set to "1" (oscillation stop detect function enabled), the microcomputer detects a main clock oscillation stop. If the microcomputer then enters on-chip oscillator low power consumption mode, the CM05 bit is set to "1" (main clock stopped). See Figure 1.8.10 about the follow-up handling. M32C/83 Group (M32C/83, M32C/83T) 9. Protection 9. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 9.1 shows the PRCR register. Each bit in the PRCR register protects the following registers: • The PRC0 bit protects the CM0, CM1, CM2, MCD, PLC0 and PLC1 registers; • The PRC1 bit protects the PM0, PM1, PM2, INVC0 and INVC1 registers; • The PRC2 bit protects the PD9 and PS3 registers; • The PRC3 bit protects the PLV and VDC0 registers. The PRC2 bit is set to "0" (write disable) when data is written to a desired address after setting the PRC2 bit to "1" (write enable). Set the PD9 and PS3 registers immediately after setting the PRC2 bit in the PRCR register to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the following instruction. The PRC0, PRC1 and PRC3 bits are not set to "0" even if data is written to desired addresses. Set the PRC0, PRC1 and PRC3 bits to "0" by program. Protect Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Address 000A16 After Reset XXXX 00002 Bit Symbol Bit Name Function Enables writing to CM0, CM1, CM2, MCD, PLC0, PLC1 registers 0 : Write disable 1 : Write enable Enables writing to PM0, PM1, INVC0, INVC1 registers 0 : Write disable 1 : Write enable Enables writing to PD9, PS3 registers 0 : Write disable 1 : Write enable Enables writing to PLV, VDC0 and VDC1 registers 0 : Write disable 1 : Write enable RW PRC0 Protect Bit 0 RW PRC1 Protect Bit 1 RW PRC2 Protect Bit 2(1) RW RW PRC3 Protect Bit 3 Nothing is assigned. When write, set to "0". (b7 - b4) When read, its content is indeterminate. NOTES: 1. The PRC2 bit can be set to "0" by writing to a desired address after the PRC2 bit is set to "1". The PRC0, PRC1 and PRC3 bits are not automatically set to "0". Set to"0" by program. Figure 9.1 PRCR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 88 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10. Interrupts 10.1 Types of Interrupts Figure 10.1 shows types of interrupts. Software (Non-Maskable Interrupt) Interrupt Special (Non-Maskable Interrupt) Hardware Peripheral Function(1) (Maskable Interrupt) NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. Do not use this interrupt. For development support tools only. Figure 10.1 Interrupts • Maskable Interrupt The I flag enables or disables an interrupt. The interrupt priority order based on interrupt priority level can be changed. • Non-maskable Interrupt The I flag does not enable nor disable an interrupt . The interrupt priority order based on interrupt priority level cannot be changed. 10.2 Software Interrupts Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable interrupts. 10.2.1 Undefined Instruction Interrupt The undefined instruction interrupt occurs when the UND instruction is executed. 10.2.2 Overflow Interrupt The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic operation) and the INTO instruction is executed. Instructions to set the O flag are : ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX 10.2.3 BRK Interrupt The BRK interrupt occurs when the BRK instruction is executed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 89 of 488            Undefined Instruction (UND Instruction) Overflow (INTO Instruction) BRK Instruction BRK2 Instruction(2) INT Instruction _______               NMI Watchdog Timer Oscillation Stop Detect Single-Step(2) Address Match DMACII M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.2.4 BRK2 Interrupt The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this interrupt. For development support tools only. 10.2.5 INT Instruction Interrupt The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 7 to 54, and 57 are assigned to the vector table used for the peripheral function interrupt. Therefore, the microcomputer executes the same service routine when the INT instruction is executed as when a peripheral function interrupt occurs. When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the relocatable vector of the specified software interrupt number. Where the stack is saved varies, depending on the software interrupt number. ISP is selected as the stack for the software interrupt numbers 0 to 31 (the U flag is set to "0"). SP, which is set before the INT instruction is executed, is selected as the stack for the software interrupt numbers 32 to 63 (the U flag is not changed). With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select) when an interrupt request is acknowledged. With software interrupt numbers 32 to 54 and 57, the SP to be used varies, depending on whether the interrupt is generated by the peripheral function interrupt request or by the INT instruction. 10.3 Hardware Interrupts Special interrupts and peripheral function interrupts are available as hardware interrupts. 10.3.1 Special Interrupts Special interrupts are non-maskable interrupts. ______ 10.3.1.1 NMI Interrupt ______ ______ The NMI interrupt occurs when a signal applied to the NMI pin changes from an "H" signal to an "L" ______ signal. Refer to 10.8 NMI Interrupt for details. 10.3.1.2 Watchdog Timer Interrupt The watchdog timer interrupt occurs when the count source of the watchdog timer underflows. Refer to 11. Watchdog Timer for details. 10.3.1.3 Oscillation Stop Detection Interrupt The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscillation stop. Refer to 8. Clock Generating Circuit for details. 10.3.1.4 Single-Step Interrupt Do not use the single-step interrupt. For development support tool only. 10.3.1.5 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 3) when the AIERi bit in the AIER register is set to "1" (address match interrupt enabled). Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur when a table data or addresses of the instruction other than the starting address, if the instruction has multiple addresses, is set. Refer to 10.10 Address Match Interrupt for details. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 90 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.3.2 Peripheral Function Interrupt The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupts and software interrupt numbers 7 to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function interrupt is a maskable interrupt. See Table 10.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details. 10.4 High-Speed Interrupt The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in 3 cycles. When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "1112" (level 7) to use the high-speed interrupt. Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority level 7 available for interrupts). Set the starting address of the high-speed interrupt service routine in the VCT register. When the high-speed interrupt is acknowledged, the FLG register is saved to the SVF register and PC is saved to the SVP registers. The program is executed from an address indicated by the VCT register. Execute the FREIT instruction to return from the high-speed interrupt service routine. The values saved to the SVF and SVP registers are restored to the FLG register and PC by executing the FREIT instruction. The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used. 10.5 Interrupts and Interrupt Vectors There are four bytes in one vector. Set the starting address of interrupt service routine in each vector table. When an interrupt request is acknowledged, the interrupt service routine is executed from the address set in the interrupt vectors. Figure 10.2 shows the interrupt vector. MSB LSB Vector Address + 0 Vector Address + 1 Vector Address + 2 Vector Address + 3 Low-order bits of an address Middle-order bits of an address High-order bits of an address 0 0 16 Figure 10.2 Interrupt Vector Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 91 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses FFFFDC16 to FFFFFF16. Table 10.1 lists the fixed vector tables. Refer to 25.2 Functions to Prevent Flash Memory from Rewriting for fixed vectors of the flash memory. Table 10.1 Fixed Vector Table Interrupt Generated by Undefined Instruction Overflow Vector Addresses Address (L) to Address (H) FFFFDC16 to FFFFDF16 FFFFE016 to FFFFE316 If the content of address FFFFE716 is FF16, the program is executed from the address stored into software interrupt number 0 in the relocatable vector table Reserved space These addresses are used for the watchdog timer interrupt and the oscillation stop detect interrupt Reserved space Clock oscillation circuit, Watchdog timer Remarks Reference M32C/80 series software manual BRK Instruction FFFFE416 to FFFFE716 Address Match - FFFFE816 to FFFFEB16 FFFFEC16 to FFFFEF16 Watchdog Timer FFFFF016 to FFFFF316 NMI Reset FFFFF416 to FFFFF716 FFFFF816 to FFFFFB16 FFFFFC16 to FFFFFF16 Reset 10.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 10.2 lists the relocatable vector tables. Set an even address as the starting address of the vector table set in the INTB register to increase interrupt sequence execution rate. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 92 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Table 10.2 Relocatable Vector Tables Interrupt Generated by BRK Instruction(2) Reserved Space A/D1 DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 Transmission, NACK(3) UART0 Reception, ACK(3) Vector Table Address Address(L) to Address(H)(1) +0 to +3 (000016 to 000316) +4 to +27 (000416 to 001B16) +28 to +31 (001C16 to 001F16) +32 to +35 (002016 to 002316) +36 to +39 (002416 to 002716) +40 to +43 (002816 to 002B16) +44 to +47 (002C16 to 002F16) +48 to +51 (003016 to 003316) +52 to +55 (003416 to 003716) +56 to +59 (003816 to 003B16) +60 to +63 (003C16 to 003F16) +64 to +67 (004016 to 004316) +68 to +71 (004416 to 004716) +72 to +75 (004816 to 004B16) +76 to +79 (004C16 to 004F16) +80 to +83 (005016 to 005316) +84 to +87 (005416 to 005716) +88 to +91 (005816 to 005B16) +92 to +95 (005C16 to 005F16) +96 to +99 (006016 to 006316) +100 to +103 (006416 to 006716) 0 1 to 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Interrupt Timer B Serial I/O Timer A Software Interrupt Number M32C/80 Series Software Manual A/D Converter DMAC Reference UART1 Transmission, NACK(3) UART1 Reception, Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 ________ ACK (3) INT5 ________ +104 to +107 (006816 to 006B16) 26 +108 to +111 (006C16 to 006F16) 27 +112 to +115 (007016 to 007316) +116 to +119 (007416 to 007716) 28 29 INT4 ________ INT3 ________ INT2 ________ INT1 _______ +120 to +123 (007816 to 007B16) 30 +124 to +127 (007C16 to 007F16) 31 +128 to +131 (008016 to 008316) +132 to +135 (008416 to 008716) 32 33 Timer B Serial I/O INT0 Timer B5 UART2 Transmission, NACK(3) UART2 Reception, ACK(3) +136 to +139 (008816 to 008B16) 34 +140 to +143 (008C16 to 008F16) 35 +144 to +147 (009016 to 009316) +148 to +151 (009416 to 009716) 36 37 UART3 Transmission, NACK(3) UART3 Reception, ACK(3) UART4 Transmission, NACK(3) UART4 Reception, ACK(3) +152 to +155 (009816 to 009B16) 38 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 93 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Table 10.2 Relocatable Vector Tables (Continued) Interrupt Generated by Vector Table Address Address(L)to Address(H)(1) Software Interrupt Number Reference Serial I/O Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39 Stop Condition Detect, (UART2)(3), Fault Error(4) Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316) 40 Stop Condition Detect, (UART3/UART0)(5), Fault Error(4) Bus Conflict Detect, Start Condition Select, +164 to +167 (00A416 to 00A716) 41 Stop Condition Detect, (UART4/UART1)(5), Fault Error(4) A/D0 Key Input Intelligent I/O Interrupt 0 Intelligent I/O Interrupt 1 Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Intelligent I/O Interrupt 5 Intelligent I/O Interrupt 6 Intelligent I/O Interrupt 7 Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9, CAN 0 Intelligent I/O Interrupt 10, CAN 1 Reserved Space Intelligent I/O Interrupt 11, CAN 2 +168 to +171 (00A816 to 00AB16) 42 +172 to +175 (00AC16 to 00AF16) 43 +176 to +179 (00B016 to 00B316) 44 +180 to +183 (00B416 to 00B716) 45 +184 to +187 (00B816 to 00BB16) 46 +188 to +191 (00BC16 to 00BF16) 47 +192 to +195 (00C016 to 00C316) 48 +196 to +199 (00C416 to 00C716) 49 +200 to +203(00C816 to 00CB16) 50 +204 to +207(00CC16 to 00CF16) 51 +208 to +211(00D016 to 00D316) 52 A/D Converter Interrupts Intelligent I/O CAN +212 to +215 (00D416 to 00D716) 53 +216 to +219 (00D816 to 00DB16) 54 +220 to +227 (00DC16 to 00E316) 55 to 56 +228 to +231 (00E416 to 00E716) 57 Intelligent I/O CAN Reserved Space INT Instruction(2) +232 to +255 (00E816 to 00FF16) 58 to 62 +0 to +3 (000016 to 000316) to +252 to +255 (00FC16 to 00FF16) 0 to 63 Interrupts NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable interrupts. 3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated. _____ 4. When the SS pin is selected, fault error causes an interrupt to be generated. 5. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in UART3. The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in UART4. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 94 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.6 Interrupt Request Reception Software interrupts and special interrupts occur when conditions to generate an interrupt are met. The peripheral function interrupts are acknowledged when all conditions below are met. • I flag = "1" • IR bit = "1" • ILVL2 to ILVL0 bits > IPL The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register. 10.6.1 I Flag and IPL The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically set to "0" after reset. IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7. If a requested interrupt has higher priority than that indicated by IPL, the interrupt is acknowledged. Table 10.3 lists interrupt priority levels associated with IPL. Table 10.3 Interrupt Priority Levels IPL2 0 0 0 0 1 1 1 1 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Interrupt Priority Levels Level 1 and above Level 2 and above Level 3 and above Level 4 and above Level 5 and above Level 6 and above Level 7 and above All maskable interrupts are disabled 10.6.2 Interrupt Control Register and RLVL Register The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 10.3 and 10.4 show the interrupt control register. Figure 10.5 shows the RLVL register. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 95 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0IC to TA4IC TB0IC to TB5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC, AD1IC KUPIC IIO0IC to IIO5IC Address 006C16, 008C16, 006E16, 008E16, 007016 009416, 007616, 009616, 007816, 009816, 006916 009016, 009216, 008916, 008B16, 008D16 007216, 007416, 006B16, 006D16, 006F16 007116, 009116, 008F16, 007116(1), 009116(2) 006816, 008816, 006A16, 008A16 007316, 008616 009316 007516, 009516, 007716, 009716, 007916, 009916 After Reset XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 IIO6IC to IIO11IC 007B16, 009B16, 007D16, 009D16, 007F16, 008116 XXXX X0002 CAN0IC0 to CAN2IC 009D16, 007F16, 008116(3) XXXX X0002 Bit Symbol ILVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW ILVL1 Interrupt Priority Level Select Bit RW ILVL2 RW IR Interrupt Request Bit 0 : No interrupt requested 1 : Interrupt requested(4) RW (b7 - b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. The BCN0IC register shares an address with the BCN3IC register. 2. The BCN1IC register shares an address with the BCN4IC register. 3. The IIO9IC register shares an address with the CAN0IC register. The IIO10IC register shares an address with the CAN1IC register. The IIO11IC register shares an address with the CAN2IC register. 4. The IR bit can be set to "0" only (do not set to "1"). Figure 10.3 Interrupt Control Register (1) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 96 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol INT0IC to INT2IC INT3IC to INT5IC(1) Address 009E16, 007E16, 009C16 007C16, 009A16, 007A16 After Reset XX00 X0002 XX00 X0002 Bit Symbol ILVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW ILVL1 Interrupt Priority Level Select Bit RW ILVL2 RW IR Interrupt Request Bit Polarity Switch Bit Level Sensitive/Edge Sensitive Switch Bit 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Selects falling edge or "L"(3) 1 : Selects rising edge or "H" 0 : Edge sensitive 1 : Level sensitive(4) RW POL RW LVS RW (b7 - b6) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. When the 16-bit data bus is used in microprocessor or memory expansion mode, each pin for the INT3 to INT5 bits is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers to "0002". 2. The IR bit can be set to "0" only (do not set to "1"). 3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges). 4. When setting the LVS bit to "1", set a bit corresponding to the IFSR register to "0" (one edge). Figure 10.4 Interrupt Control Register (2) 10.6.2.1 ILVL2 to ILVL0 Bits The ILVL2 to ILVL0 bits determines the interrupt priority level. The higher the interrupt priority level, the higher interrupt priority is. When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits are set to "0002" (level 0), this interrupt is ignored. 10.6.2.2 IR Bit The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and the program in the corresponding interrupt vector is executed. The IR bit can be set to "0" by program. Do not set to "1". Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 97 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Exit Priority Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RLVL Address 009F16 After Reset XXXX 00002 Bit Symbol RLVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW RLVL1 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit(1) RW RLVL2 RW FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt RW (b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMAC II transfer(3) DMA II DMAC II Select Bit(4) RW Nothing is assigned. When write, set to "0". (b7 - b6) When read, its content is indeterminate. NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. 2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register after setting the DMA II bit to "0". Figure 10.5 RLVL Register 10.6.2.3 RLVL2 to RLVL0 Bits When using an interrupt to exit stop or wait mode, refer to 8.5.2 Wait Mode and 8.5.3 Stop Mode for details. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 98 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.6.3 Interrupt Sequence The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA instruction, if an interrupt request is generated while executing the instruction, the microcomputer suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as follows: (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 00000016 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to the interrupt information is set to "0" (interrupt requested). (2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU. (3) Each bit in the FLG register is set as follows: • The I flag is set to "0" (interrupt disabled) • The D flag is set to "0" (single-step disabled) • The U flag is set to "0" (ISP selected) (4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed interrupt. (5) PC is saved to the stack; or to the SVP register for the high-speed interrupt. (6) The interrupt priority level of the acknowledged interrupt is set in IPL . (7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC. After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt service routine. NOTES: 1. Temporary register cannot be modified by users. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 99 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.6.4 Interrupt Response Time Figure 10.6 shows an interrupt response time. Interrupt response time is the period between an interrupt generation and the execution of the first instruction in an interrupt service routine. An interrupt response time includes the period between an interrupt request generation and the completed execution of an instruction ((a) in Figure 10.6) and the period required to perform an interrupt sequence ((b) in Figure 10.6). Interrupt request is generated Interrupt request is acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in an interrupt routine Interrupt response time (a) Period between an interrupt request generation and the completed execution of an instruction. (b) Period required to perform an interrupt sequence. Figure 10.6 Interrupt Response Time Time (a) varies depending on the instruction being executed. The DIV instruction requires the longest time (a); 40 cycles when an immediate value or register is set as the divisor . When the divisor is a value in the memory, the following value is added. • Normal addressing :2+X • Index addressing :3+X • Indirect addressing : 5 + X + 2Y • Indirect index addressing : 6 + X + 2Y X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be doubled. Table 10.4 lists time (b). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 100 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Table 10.4 Interrupt Sequence Execution Time Interrupt Peripheral Function Interrupt Vector Address Even address Odd address(1) INT Instruction Even address Odd address(1) _______ 16-Bit Bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 8-Bit Bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles NMI Watchdog Timer Undefined Instruction Address Match Overflow BRK Instruction (relocatable vector table) Even address(2) Even address(2) Even address Odd address(1) 14 cycles 17 cycles 19 cycles 19 cycles 5 cycles 16 cycles 19 cycles 19 cycles 21 cycles BRK Instruction (fixed vector table) High-Speed Interrupt Even address(2) Vector table is internal register NOTES: 1. Allocate interrupt vectors to even addresses. 2. Vectors are fixed to even addresses. 10.6.5 IPL Change when Interrupt Request is Acknowledged When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowledged interrupt. Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has no interrupt priority level is acknowledged, the value shown in Table 10.5 is set in IPL as the interrupt priority level. Table 10.5 Interrupts without Interrupt Priority Levels and IPL Interrupt Sources _______ Level that is Set to IPL 7 0 Not changed Watchdog Timer, NMI, Oscillation Stop Detect Reset Software, Address Match Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 101 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.6.6 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32 bits, are saved to the stack. Figure 10.7 shows the stack state before and after an interrupt request is acknowledged. Other important registers are saved by program at the beginning of an interrupt service routine. The PUSHM instruction can save all registers except SP. Refer to 10.4 High-Speed Interrupt for the high-speed interrupt. Address The Stack MSB LSB Address The Stack MSB LSB m-6 m-5 m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] SP value before interrupt is generated m-6 m-5 m–4 m–3 m–2 m–1 m m+1 PCL PCM PCH 00 16 FLG L FLGH Content of previous stack Content of previous stack [SP] New SP value Stack state before an interrupt request is acknowledged Stack state after an interrupt request is acknowledged Figure 10.7 Stack States 10.6.7 Restoration from Interrupt Routine When the REIT instruction is executed at the end of an interrupt service routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, executed before an interrupt request has been acknowledged, starts running again. Refer to 10.4 High-Speed Interrupt for the highspeed interrupt. Restore registers saved by program in an interrupt service routine by the POPM instruction or others before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt sequence by the REIT or FREIT instruction. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 102 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.6.8 Interrupt Priority If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function interrupt). Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set by hardware. Figure 10.8 shows priority levels of hardware interrupts. The interrupt priority does not affect software interrupts. The microcomputer jumps to the interrupt routine when the instruction is executed. _______ Reset > NMI > Oscillation Stop Detect > Peripheral Function > Address Match Watchdog Figure 10.8 Interrupt Priority 10.6.9 Interrupt Priority Level Select Circuit The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point. Figure 10.9 shows the interrupt priority level select circuit. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 103 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts High Each Interrupt Priority Level Level 0 (initial value) A/D1 Converter DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 Transmission/NACK UART0 Reception/ACK UART1 Transmission/NACK UART1 Reception/ACK Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 INT2 IPL INT1 INT0 Timer B5 UART2 Transmission/NACK UART2 Reception/ACK UART3 Transmission/NACK Reset UART3 Reception/ACK UART4 Transmission/ NACK UART4 Reception/ACK Bus Conflict/Start, Stop Condition(UART2) Bus Conflict/Start, Stop Condition( UART0,3) Bus Conflict/Start, Stop Condition(UART1,4) I Flag Address Match Watchdog Timer, Oscillation Stop Detect NMI DMAC II RLVL2 to RLVL0 Bits Each Interrupt Priority Level A/D0 Converter Key Input Interrupt Intelligent I/O Interrupt 0 Intelligent I/O Interrupt 1 Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Intelligent I/O Interrupt 5 Intelligent I/O Interrupt 6 Intelligent I/O Interrupt 7 Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9 /CAN Interrupt 0 Intelligent I/O Interrupt 10 /CAN Interrupt 1 Intelligent I/O Interrupt 11 /CAN Interrupt 2 Interrupt request is acknowledged. To CLK Interrupt request is acknowledged. To CPU Low Peripheral Function Interrupt Priority (if priority levels are the same) Figure 10.9 Interrupt Priority Level Select Circuit Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 104 of 488 M32C/83 Group (M32C/83, M32C/83T) ______ 10. Interrupts 10.7 INT Interrupt ______ External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an interrupt at an applied signal level. The POL bit in the INTiIC register determines the polarity. With an edge sensitive triggering, when the IFSRi bit in the IFSR register is set to "1" (both edges), an interrupt occurs on both rising and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding register to "0" (falling edge). _______ With a level sensitive triggering, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains set to "1" even _______ _______ if the INTi pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when "0" is written by program. Figure 10.10 shows the IFSR register. External Interrupt Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit Symbol Address 031F16 After Reset 0016 Bit Name INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit(1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity Select Bit(1) INT5 Interrupt Polarity Select Bit(1) Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges RW RW IFSR0 IFSR1 RW IFSR2 RW IFSR3 RW IFSR4 RW IFSR5 RW IFSR6 UART0, UART3 Interrupt Cause Select Bit 0 : UART3 bus conflict, start condition detect, stop condition detect, fault error detect RW 1 : UART0 bus conflict, start condition detect, stop condition detect, fault error detect IFSR7 0 : UART4 bus conflict, start condition detect, stop condition detect, fault UART1, UART4 error detect RW Interrupt Cause Select 1 : UART1 bus conflict, start condition detect, stop condition detect, fault Bit error detect NOTES: 1.Set this bit to "0" to select level sensitive. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). Figure 10.10 IFSR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 105 of 488 M32C/83 Group (M32C/83, M32C/83T) ______ 10. Interrupts 10.8 NMI Interrupt ______ ______ The NMI interrupt occurs when the signal applied to the P85/NMI pin changes from an "H" signal to an "L" ______ ______ ______ signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as the NMI interrupt input pin, the P8_5 bit in the P85 register indicates input level for this pin. NOTES: ______ ______ ______ When the NMI interrupt is not used, connect (pull-up) the NMI pin to Vcc via a resistor. Because the NMI interrupt cannot be ignored, the pin must be connected. 10.9 Key Input Interrupt Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait or stop mode. To use the key input interrupt, do not use P104 to P107 as A/D input ports. Figure 10.11 shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode, signals applied to other pins are not detected as a request signal for an interrupt. When the PSC_7 bit in the PSC register(1) is set to "1" (key input interrupt disabled), no key input interrupt occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a port pin is available even when in input mode. NOTES: 1. Refer to 24. Programmable I/O Ports for details on the PSC register. PU31 bit in PUR3 register Pull-up transistor PD10_7 bit PSC_7 bit P107/KI3 Pull-up transistor P106/KI2 Pull-up transistor P105/KI1 Pull-up transistor P104/KI0 PD10_4 bit PD10_6 bit Interrupt Control Circuit Key Input Interrupt Request PD10_7 bit KUPIC Register PD10_5 bit Figure 10.11 Key Input Interrupt Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 106 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.10 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 3). The address match interrupt can be set in four addresses. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and IPL do not affect the address match interrupt. Figure 10.12 shows registers associated with the address match interrupt. Set the starting address of an instruction in the RMADi register. The address match interrupt does not occur when a table data or addresses other than the starting address of the instruction is set. Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol Address 000916 After Reset XXXX 00002 Bit Name Address Match Interrupt 0 Enable Bit Address Match Interrupt 1 Enable Bit Address Match Interrupt 2 Enable Bit Address Match Interrupt 3 Enable Bit Function 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt RW RW AIER0 AIER1 RW AIER2 RW AIER3 RW Nothing is assigned. When write, set to "0". (b7 - b4) When read, its content is indeterminate. Address Match Interrupt Register i b23 b16 b15 b8 b7 b0 Symbol RMAD0 RMAD1 RMAD2 RMAD3 Address 001216 - 001016 001616 - 001416 001A16 - 001816 001E16 - 001C16 After Reset 00000016 00000016 00000016 00000016 Function Addressing Register for the Address Match Interrupt Setting Range 00000016 to FFFFFF16 RW RW Figure 10.12 AIER Register and RMAD0 to RMAD3 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 107 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts 10.11 Intelligent I/O Interrupt and CAN Interrupt The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 54, and 57. Figure 10.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 10.14 shows the IIOiIR register (i = 0 to 11). Figure 10.15 shows the IIOiIE register. When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register to "1" (interrupt request for interrupt used). Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is generated with intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1" (interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested). After the IR bit setting changes from "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1". Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit to "0" by program. If these bits remain set to "1", all generated interrupt requests are ignored. CAN interrupt uses bit 7 in the IIO9IR to IIO11IR registers and bit 7 in the IIO9IE to IIO11IE registers. IIO9IR to IIO11IR registers share addresses with the CAN0IC to CAN2IC registers. Refer to 22.3 CAN Interrupt for details. IIOiIR Register(2) Bit 1 IRLT Bit in IIOiIE Register 0 1 0 Interrupt Request(1) Bit 2 Intelligent I/O Interrupt i Request Interrupt Request(1) 1 0 Bit 7 Interrupt Request(1) IIOiIE Register(3) Bit 1 1 Bit 2 Bit 7 NOTES: 1. See Figures 10.14 and 10.15 for details on bits 1 to 7 in the IIOiIR register and bits 1 to 7 in the IIOiIE register. 2. Bits 1 to 7 in the IIOiIR register are not set to "0" automatically even if an interrupt request is generated. Set to "0" by program. 3. Do not change the IRLT bit and the interrupt enable bit in the IIOiIE register simultaneously. i= 0 to 11 Figure 10.13 Intelligent I/O Interrupt and CAN Interrupt When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE register to "0" (an interrupt used for DMAC, DMAC II) to enable the interrupt request that the IIOiIE register requires. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 108 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Interrupt Request Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IIO0IR to IIO11IR Bit Symbol Address See below After Reset 0000 000X2 Function Nothing is assigned. When write, set to "0". RW (b0) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) NOTES: When read, its content is indeterminate. 0 : Requests no interrupt 1 : Requests an interrupt RW ( Note 2) RW RW RW RW RW RW 1. See table below for bit symbols. 2. Only "0" can be set (nothing is changed even if "1" is set). Bit Symbols for the Interrupt Request Register Symbol IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Address 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 Bit 7 SRT0R IE0R IE1R CAN0R CAN1R CAN2R Bit 6 SRT1R IE2R Bit 5 SIO0RR SIO0TR SIO1RR SIO1TR Bit 4 G0RIR G0TOR G1RIR G1TOR BT1R SIO2RR SIO2TR BT0R BT2R SIO3RR SIO3TR BT3R Bit 3 PO27R PO32R PO33R PO34R PO35R PO36R PO31R PO30R PO37R Bit 2 PO13R PO14R TM12R/PO12R PO10R Bit 1 TM02R TM00R/PO00R TM03R Bit 0 - TM17R/PO17R TM04R/PO04R PO21R PO20R PO22R PO23R PO24R PO25R PO26R TM05R/PO05R TM06R TM07R TM11R/PO11R PO15R TM16R/PO16R TM01R/PO01R BTiR : Intelligent I/O Group i Base Timer Interrupt Request Bit (i=0 to 3) TMmjR : Intelligent I/O Group m Time Measurement j Interrupt Request Bit (j=0 to 7)(m=0,1) POijR : Intelligent I/O Group i Waveform Generation Function j Interrupt Request Bit SIOiRR/SIOiTR : Intelligent I/O Group i Communication Function Interrupt Request Bit (RR:receive, TR:transmit) GmRIR/GmTOR: Intelligent I/O Group m HDLC Data Processing Function Interrupt Request Bit (RIR:input to receive, TOR:input to transmit) SRTmR : Intelligent I/O Group m Special Communication Function Interrupt Request Bit IEkR : Intelligent I/O Group 2 IEBus Communication Function Interrupt Request Bit (k = 0 to 2) CANkR : CAN Communication Function Interrupt Request Bit : Reserved bit. Set to "0". Figure 10.14 IIO0IR to IIO11IR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 109 of 488 M32C/83 Group (M32C/83, M32C/83T) 10. Interrupts Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IIO0IE to IIO11IE Bit Symbol Address See below After Reset 0016 Bit Name Interrupt Request Select Bit(2) Function 0 : Interrupt request is used for DMAC, DMAC II 1 : Interrupt request is used for interrupt RW RW IRLT (Note 1) 0 : Disables an interrupt by bit 1 in IIOiIR register RW 1 : Enables an interrupt by bit 1 in IIOiIR register 0 : Disables an interrupt by bit 2 in IIOiIR register RW 1 : Enables an interrupt by bit 2 in IIOiIR register 0 : Disables an interrupt by bit 3 in IIOiIR register RW 1 : Enables an interrupt by bit 3 in IIOiIR register 0 : Disables an interrupt by bit 4 in IIOiIR register RW 1 : Enables an interrupt by bit 4 in IIOiIR register 0 : Disables an interrupt by bit 5 in IIOiIR register 1 : Enables an interrupt by bit 5 in IIOiIR register (Note 1) (Note 1) (Note 1) (Note 1) RW (Note 1) 0 : Disables an interrupt by bit 6 in IIOiIR register RW 1 : Enables an interrupt by bit 6 in IIOiIR register 0 : Disables an interrupt by bit 7 in IIOiIR register RW 1 : Enables an interrupt by bit 7 in IIOiIR register (Note 1) NOTES: 1. See table below for bit symbols. 2. If an interrupt request is used for interrupt, set bit 1 to 7 to "1" after the IRLT bit is set to "1". Bit Symbols for the Interrupt Enable Register Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE Address 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 Bit 7 SRT0E Bit 6 SRT1E Bit 5 SIO0RE SIO0TE SIO1RE SIO1TE - Bit 4 G0RIE G0TOE G1RIE G1TOE BT1E SIO2RE SIO2TE BT0E BT2E SIO3RE SIO3TE BT3E Bit 3 PO27E PO32E PO33E PO34E PO35E PO36E PO31E PO30E PO37E Bit 2 PO13E PO14E TM12E/PO12E PO10E Bit 1 TM02E TM00E/PO00E TM03E Bit 0 IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT TM17E/PO17E TM04E/PO04E PO21E PO20E PO22E PO23E PO24E PO25E PO26E TM05E/PO05E TM06E TM07E TM11E/PO11E PO15E TM16E/PO16E TM01E/PO01E IE0E IE1E CAN0E CAN1E CAN2E IE2E - BTiE TMmjE POijE SIOiRE/SIOiTE GmRIE/GmTOE SRTmE : Intelligent I/O Group i Base Timer Interrupt Enable Bit (i=0 to 3) : Intelligent I/O Group m Time Measurement j Interrupt Enable Bit (j=0 to 7)(m=0,1) : Intelligent I/O Group i Waveform Generation Function j Interrupt Enable Bit : Intelligent I/O Group i Communication Function Interrupt Enable Bit (RE:receive, TE:transmit) : Intelligent I/O Group m HDLC Data Processing Function Interrupt Enable Bit (RIE:input to receive, TOE:input to transmit) : Intelligent I/O Group m Special Communication Function Interrupt Enable Bit : Intelligent I/O Group 2 IEBus Communication Function Interrupt Enable Bit (k=0 to 2) : CAN Communication Function Interrupt Enable Bit : Reserved bit. Set to "0". IEkE CANkE - Figure 10.15 IIO0IE to IIO11IE Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 110 of 488 M32C/83 Group (M32C/83, M32C/83T) 11. Watchdog Timer 11. Watchdog Timer The watchdog timer detects a program which is out of control. The watchdog timer contains a 15-bit counter which is decremented by the CPU clock that the prescaler divides. The CM06 bit in the CM0 register determines whether the watchdog timer interrupt request or reset is generated when the watchdog timer underflows. The CM06 bit can be set to "1" (reset) only. Once the CM06 bit is set to "1", it cannot be changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset. When the main clock, on-chip oscillator clock, or the PLL clock runs as the CPU clock, the WDC7 bit in the WDC register determines whether the prescaler divides by 16 or by 128. When the sub clock runs as the CPU clock, the prescaler divides by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle. When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock: Watchdog timer cycle = Divide by 16 or 128 prescaler x counter value of watchdog timer (32768) CPU clock Divided by 2 prescaler x counter value of watchdog timer (32768) CPU clock When the sub clock is selected as the CPU clock, Watchdog timer cycle = For example, if the CPU clock frequency is 30MHz and the prescaler divides by 16, watchdog timer cycle is approximately 17.5 ms. The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler stop after reset. They begin counting when the WDTS register is set. Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the beginning of the watchdog timer interrupt routine. The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting from the value held when the mode or state is exited. Figure 11.1 shows a block diagram of the watchdog timer. Figure 11.2 shows registers associated with the watchdog timer. Prescaler CM07 = 0 WDC7 = 0 0 1/16 CPU Clock HOLD Signal 1/128 CM07 = 0 WDC7 = 1 Watchdog Timer Interrupt Request Reset Watchdog Timer CM06 1 CM07 = 1 1/2 Write to WDTS Register Set to 7FFF16 Internal Reset Signal CM06, CM07 : Bits in CM0 register WDC7 : Bit in WDC register Figure 11.1 Watchdog Timer Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 111 of 488 M32C/83 Group (M32C/83, M32C/83T) 11. Watchdog Timer Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Address 000F16 After Reset 000X XXXX2 Bit Symbol (b4 - b0) Bit Name High-Order Bit of Watchdog Timer Function RW RO (b6 - b5) WDC7 Reserved Bit Set to "0" 0 : Divide-by-16 1 : Divide-by-128 RW Prescaler Select Bit RW Watchdog Timer Start Register b7 b0 Symbol WDTS Address 000E16 After Reset Indeterminate Function The watchdog timer is reset to start counting by a write instruction to the WDTS register. Default value of the watchdog timer is always set to "7FFF16" regardless of the value written. RW WO Figure 11.2 WDC Register and WDTS Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 112 of 488 M32C/83 Group (M32C/83, M32C/83T) 11. Watchdog Timer System Clock Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 1 After Reset 0000 X0002 Bit Symbol CM00 Bit Name b1 b0 Function 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 RW RW Clock Output Function Select Bit(2) CM01 In Wait Mode, Peripheral Function Clock Stop Bit Reserved Bit RW CM02 0 : Peripheral clock does not stop in wait mode RW 1 : Peripheral clock stops in wait (3) mode Set to "1" RW (b3) CM04 Port XC Switch Bit Main Clock (XIN-XOUT) Stop Bit(5) Watchdog Timer Function Select Bit System Clock Select Bit(8) 0 : I/O port function RW 1 : XCIN-XCOUT oscillation function(4) 0 : Main clock oscillates 1 : Main clock stops(6) 0 : Watchdog timer interrupt 1 : Reset(7) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock RW CM05 CM06 RW CM07 RW NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 to CM00 bits to "002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), set the CM01 to CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 to CM00 bits) in microprocessor or memory expansion mode, and the CM01 to CM00 bits are set to "002", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), set the PD8_7 to PD8_6 bits to "002" (with port P87 and P86 input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering the low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", XOUT becomes "H". The built-in feedback resistor remains on. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD register is set to "0816" (divide-by-8 mode). In on-chip oscillation mode, the MCD register is not divided by eight even if the CM05 bit terminates XIN-XOUT. 7. Once the CM06 bit is set to "1", it cannot be set "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bits simultaneously. Figure 11.3 CM0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 113 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC 12. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized when using DMAC. DMAC2 and DMAC3 share registers required for high-speed interrupts. High-speed interrupts cannot be used when using three or more DMAC channels. The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. The cycle-steal method employed by DMAC enables high-speed operation between a transfer request and the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 12.1 shows a mapping of registers to be used for DMAC. Table 12.1 lists specifications of DMAC. Figures 12.2 to 12.5 show registers associated with DMAC. Because the registers shown in Figure 12.1 are allocated to the CPU, use the LDC instruction to write to the registers. To set DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register bank 1) and set R0 to R3, A0, A1 registers with the MOV instruction. To set DSA2 and DSA3 registers, set the B flag to "1" and set the SB, FB, SVP, VCT registers with the LDC instruction. To set the DRA2 and DRA3 registers, set the SVP, VCT registers with the LDC instruction. DMAC-Associated Registers DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMA Mode Register 0 DMA Mode Register 1 DMA 0 Transfer Count Register DMA 1 Transfer Count Register DMA 0 Transfer Count Reload Register(1) DMA 1 Transfer Count Reload Register(1) DMA 0 Memory Address Register DMA 1 Memory Address Register DMA 0 SFR Address Register DMA 1 SFR Address Register DMA 0 Memory Address Reload Register(1) DMA 1 Memory Address Reload Register(1) When Three or More DMAC Channels are Used, the Register Bank 1 is Used as DMAC Registers DCT2 (R0) DCT3 (R1) DRC2 (R2) DRC3 (R3) DMA2 (A0) DMA3 (A1) DSA2 (SB) DSA3 (FB) DMA2 Transfer Count Register DMA3 Transfer Count Register DMA2 Transfer Count Reload Register(1) DMA3 Transfer Count Reload Register(1) DMA2 Memory Address Register DMA3 Memory Address Register DMA2 SFR Address Register DMA3 SFR Address Register When Three or More DMAC Channels are Used, the High-Speed Interrupt Register is Used as DMAC Registers SVF DRA2 (SVP) DRA3 (VCT) Flag Save Register DMA2 Memory Address Reload Register(1) DMA3 Memory Address Reload Register(1) When using DMA2 and DMA3, use the CPU registers shown in parentheses (). NOTES: 1. Registers are used for repeat transter, not for single transfer. Figure 12.1 Register Mapping for DMAC Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 114 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. Therefore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged. Table 12.1 DMAC Specifications Item Channels Transfer Memory Space Specification 4 channels (cycle-steal method) • From a desired address in a 16M-byte space to a fixed address in a 16M-byte space • From a fixed address in a 16M-byte space to a desired address in a 16M-byte space 128K bytes (when a 16-bit data is transferred) or 64K bytes (when an 8bit data is transferred) ________ ________ Falling edge or both edges of input signals to the INT0 to INT3 pins Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 to UART4 transmit and receive interrupt requests A/D conversion interrupt request Intelligent I/O interrupt request CAN interrupt request Maximum Bytes Transferred DMA Request Factors(1) Software trigger Channel Priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority) Transfer Unit 8 bits, 16 bits Destination Address Forward/fixed (forward and fixed directions cannot be specified when specifying source and destination addresses simultaneously) Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "000016" Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register is reloaded into the DCTi register and the DMA transfer is continued DMA Interrupt Request Generation Timing When the DCTi register changes "000116" to "000016" DMA Startup Single Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 to MD0 bits in the DMDj register (j = 0 to 1) are set to "012" (single transfer) Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 to MDi0 bits are set to "112" (repeat transfer) DMA Stop Single Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" (DMA disabled) or when the DCTi register is set to "000016" (0 DMA transfer) by DMA transfer or write Repeat Transfer DMA stops when the MDi1 to MDi0 bits are set to "002" or when the DCTi register is set to "000016" and the DRCi register set to "000016" Reload Timing to the DCTi When the DCTi register is set to "000016" from "000116" in repeat transor DMAi Register fer mode DMA Transfer Cycles Minimum 3 cycles between SFR and internal RAM NOTES: 1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 115 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC DMAi Request Factor Select Register (i=0 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address DM0SL to DM3SL 037816, 037916, 037A16, 037B16 Bit Symbol After Reset 0X00 00002 Bit Name Function RW RW DSEL0 DSEL1 DMA Request Cause Select Bit(1) See Table 12.2 about DMiSL register (i = 0 to 3) function RW DSEL2 RW DSEL3 RW DSEL4 Software DMA Request Bit(2) When a software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, its content is always "0") RW DSR RW (b6) DRQ Nothing is assigned. When write, set "0". When read, its content is indeterminate. DMA Request Bit(2, 3) 0 : Not requested 1 : Requested RW NOTES: 1. Change the DSEL4 to DSEL0 bit settings while the MDi1 to MDi0 bits in the DMA0 or DMD1 register are set to "002" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the DSEL4 to DSEL0 bit settings are changed. e.g., MOV.B #083h, DMiSL ; Set timer A0 2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously. e.g., OR.B #0A0h, DMiSL 3. Do not set the DRQ bit to "0". Figure 12.2 DM0SL to DM3SL Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 116 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC Table 12.2 DMiSL Register (i = 0 to 3) Function Setting Value b4 b3 b2 b1 b0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 DMA0 DMA Request Cause DMA1 DMA2 DMA3 Falling edge of INT3(1) Both edges of INT3(1) (Note 2) (Note 2) Software Trigger Falling edge of INT0 Falling edge of INT1 Falling edge of INT2 Both edges of INT0 Both edges of INT1 Both edges of INT2 Timer A0 Interrupt Request Timer A1 Interrupt Request Timer A2 Interrupt Request Timer A3 Interrupt Request Timer A4 Interrupt Request Timer B0 Interrupt Request Timer B1 Interrupt Request Timer B2 Interrupt Request Timer B3 Interrupt Request Timer B4 Interrupt Request Timer B5 Interrupt Request UART0 Transmit Interrupt Request UART0 Receive or ACK Interrupt Request(3) UART1 Transmit Interrupt Request UART1 Receive or ACK Interrupt Request(3) UART2 Transmit Interrupt Request UART2 Receive or ACK Interrupt Request(3) UART3 Transmit Interrupt Request UART3 Receive or ACK Interrupt Request(3) UART4 Transmit Interrupt Request UART4 Receive or ACK Interrupt Request(3) A/D0 Interrupt Request A/D1 Interrupt Request A/D0 Interrupt request A/D1 Interrupt Request Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request Intelligent I/O Interrupt 5 Request Intelligent I/O Interrupt 6 Request Intelligent I/O Interrupt 7 Request Intelligent I/O Interrupt 8 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) Intelligent I/O Interrupt 11 Request(6) Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request Intelligent I/O Interrupt 5 Request Intelligent I/O Interrupt 6 Request Intelligent I/O Interrupt 7 Request Intelligent I/O Interrupt 8 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) Intelligent I/O Interrupt 11 Request(6) Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request NOTES: 1. If the INT3 pin is used as data bus in the memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be generated by an input signal to the INT3 pin. 2. The falling edge and both edges of input signal into the INTj pin (j = 0 to 3) cause a DMA request. The INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa. 3. The UkSMR register and UkSMR2 register (k = 0 to 4) switch the UARTj receive to ACK or ACK to UARTk receive. 4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request. 5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request. 6. The same setting is used to generate an intelligent I/O interrupt 11 request and a CAN interrupt 2 request. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 117 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC DMA Mode Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMD0 Bit Symbol Address CPU Internal Register After Reset 0016 Bit Name b1 b0 Function 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits RW RW MD00 Channel 0 Transfer Mode Select Bit MD01 Channel 0 Transfer Unit Select Bit Channel 0 Transfer Direction Select Bit RW BW0 RW RW0 0 : Fixed address to memory (forward direction) RW 1 : Memory (forward direction) to fixed address b5 b4 MD10 Channel 1 Transfer Mode Select Bit MD11 Channel 1 Transfer Unit Select Bit Channel 1 Transfer Direction Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits RW RW BW1 RW RW1 0 : Fixed address to memory (forward direction) RW 1 : Memory (forward direction) to fixed address NOTES: 1. Use the LDC instruction to set the DMD0 register. DMA Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMD1 Bit Symbol Address CPU Internal Register After Reset 0016 Bit Name b1 b0 Function 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits RW RW MD20 Channel 2 Transfer Mode Select Bit MD21 Channel 2 Transfer Unit Select Bit Channel 2 Transfer Direction Select Bit RW BW2 RW RW2 0 : Fixed address to memory (forward direction) RW 1 : Memory (forward direction) to fixed address b5 b4 MD30 Channel 3 Transfer Mode Select Bit MD31 Channel 3 Transfer Unit Select Bit Channel 3 Transfer Direction Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits RW RW BW3 RW3 RW 0 : Fixed address to memory (forward direction) RW 1 : Memory (forward direction) to fixed address NOTES: 1. Use the LDC instruction to set the DMD1 register. Figure 12.3 DMD0 Register, DMD1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 118 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC DMAi Transfer Count Register (i=0 to 3) b15 b8 b7 b0 Symbol DCT0(2) DCT1(2) DCT2(bank1;R0)(3) DCT3(bank1;R1)(4) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXX16 XXXX16 000016 000016 Function Set the number of transfers Setting Range 000016 to FFFF16(1) RW RW NOTES: 1. When the DCTi register to "000016", no data transfer occurs regardless of a DMA request. 2. Use the LDC instruction to set the DCT0 and DCT1 registers. 3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set R0 register. Use the MOV instruction to set the R0 register. 4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to set the R1 register. DMAi Transfer Count Reload Register (i=0 to 3) b15 b8 b7 b0 Symbol DRC0(1) DRC1(1) DRC2(bank1;R2)(2) DRC3(bank1;R3)(3) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXX16 XXXX16 000016 000016 Function Set the number of transfers Setting Range 000016 to FFFF16 RW RW NOTES: 1. Use the LDC instruction to set the DRC0 and DRC1 registers. 2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set R2 register. Use the MOV instruction to set the R2 register. 3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the R3 register. Figure 12.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 119 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC DMAi Memory Address Register (i=0 to 3) b23 b16 b15 b8 b7 b0 Symbol DMA0(2) DMA1(2) DMA2(bank1;A0)(3) DMA3(bank1;A1)(4) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXXXX16 XXXXXX16 00000016 00000016 Function Set a source memory address or destination memory address(1) Setting Range 00000016 to FFFFFF16 (16-Mbyte space) RW RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a destination address is selected. When the RWk bit is set to "1" (memory to fixed address), a source address is selected. 2. Use the LDC instruction to set the DMA0 and DMA1 registers. 3. To set the DMA2 register, set the B flag in the FLG register to "1" (register bank 1) and set A0 register. Use the MOV instruction to set the A0 register. 4. To set the DMA3 register, set the B flag to "1" and set A1 register. Use the MOV instruction to set the 1 register. DMAi SFR Address Register (i=0 to 3) b23 b16 b15 b8 b7 b0 Symbol DSA0(2) DSA1(2) DSA2(bank1;SB)(3) DSA3(bank1;FB)(4) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXXXX16 XXXXXX16 00000016 00000016 Function Set a source fixed address or destination fixed address(1) Setting Range 00000016 to FFFFFF16 (16-Mbyte space) RW RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1) is set to "0" (fixed address to memory), a source address is selected. When the RWk bit is set to "1" (memory to fixed address), a destination address is selected. 2. Use the LDC instruction to set the DSA0 and DSA1 registers. 3. To set the DSA2 register, set the B flag in the FLG register to "1" (register bank 1) and the set the SB register. Use the LDC instruction to set the SB register. 4. To set the DSA3 register, set the B flag to "1" and set the FB register. Use the LDC instruction to set the FB register. DMAi Memory Address Reload Register(1) (i=0 to 3) b23 b16 b15 b8 b7 b0 Symbol DRA0 DRA1 DRA2(SVP)(2) DRA3(VCT)(3) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 Function Set a source memory address or destination memory address NOTES: 1. Use the LDC instruction to set the these registers. 2. To set the DRA2 register, set the SVP register. 3. To set the DRA3 register, set the VCT register. Setting Range 00000016 to FFFFFF16 (16-Mbyte space) RW RW Figure 12.5 DMA0 to DMA3 Registers, DSA0 to DSA3 Registers and DRA0 to DRA3 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 120 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC 12.1 Transfer Cycles Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus cycle to write data to a memory space or the SFR area (destination write). The number of read and write bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the DS register. Software wait state ________ insertion and the RDY signal make a bus cycle longer. 12.1.1 Effect of Source and Destination Addresses When a 16-bit data is transferred with a 16-bit data bus, and the source address starts with an odd address, source read cycle has one more bus cycle compared to a source address starting with an even address. When a 16-bit data is transferred with a 16-bit data bus and the destination address starts with an odd address, destination write cycle has one more bus cycle compared to a destination address starting with an even address. 12.1.2 Effect of the DS Register In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on the data bus used at the source and destination addresses. See Figure 7.1 for details about the DS register. (1) When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice. Therefore, two bus cycles are required to read the data and another two bus cycles to write the data. (2) When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for reading and one bus cycle is for writing. (3) When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice. Therefore, one bus cycle is required for reading and two bus cycles is for writing. 12.1.3 Effect of Software Wait State When the SFR area or memory space with software wait states is accessed, the number of cycles is incremented by software wait states. Figure 12.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 12.6, the number of source-read bus cycles is illustrated under different conditions, provided that the destination address is an address of an external space with the destination write bus cycle as two BCLK cycles (=one bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the transfer cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both destinationwrite bus cycle and source-read bus cycle. As shown in example (2) of Figure 12.6, when an 8-bit data bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two bus cycles each are required for the source-read bus cycle and destination-write bus cycle. , ________ 12.1.4 Effect of RDY Signal ________ In memory expansion or microprocessor mode, the RDY signal affects a bus cycle of source address or _______ destination address is allocated address in an external space. Refer to 7.2.6 RDY Signal for details. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 121 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC (1) When 8-bit data is transferred or when 16-bit data is transferred from an even source address by a 16-bit data bus BCLK Address Bus RD Signal WR Signal Data bus CPU Use Source Destination CPU Use CPU Use Source Destination CPU Use (2) When 16-bit data is transferred from an odd source address or when 16-bit data is transferred from source by an 8-bit data bus BCLKClock CPU Address Bus RD Signal WR Signal Data Bus CPU Use Source Source + 1 Destination CPU Use CPU Use Source Source + 1 Destination CPU Use (3) When one wait state is inserted into the source-read bus cycle under the conditions in (1) BCLK Address Bus RD Signal WR Signal Data Bus CPU Use Source Destination CPU Use CPU Use Source Destination CPU Use (4) When one wait state is inserted into the source-read bus cycle under the conditions in (2) BCLK Address Bus RD Signal WR Signal Data Bus CPU Use Source Source + 1 Destination CPU Use CPU Use Source Source + 1 Destination CPU Use NOTES: 1. The above applies when the destination-write bus cycle is 2 BCLK cycles (1 bus cycle). However, if the destination-write bus cycle is placed under these conditions, it will change to the same timing as the source-read bus cycle illustrated above. Figure 12.6 Transfer Cycle Examples with the Source-Read Bus Cycle Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 122 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC 12.2 DMAC Transfer Cycles The number of DMAC transfer cycle can be calculated as follows. Any combination of even or odd transfer read and write addresses are possible. Table 12.3 lists the number of DMAC transfer cycles. Table 12.4 lists coefficient j, k. Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k Table 12.3 DMAC Transfer Cycles Single-Chip Mode Transfer Unit Bus Width Access Address 16-bit 8-bit transfers (BWi bit in the DMDp register = 0) 16-bit transfers (BWi bit = 1) i= 0 to 3, p = 0 to 1 Table 12.4 Coefficient j, k Internal Space Internal ROM or Internal ROM or Internal RAM Internal RAM with with no wait state a wait state j=1 k=1 j=2 k=2 SFR Area j=2 k=2 External Space Separate Separate Separate Separate Multiplexed Multiplexed Bus with no Bus with 1 Bus with 2 Bus with 3 Bus with 2 Bus with 3 wait state wait state wait states wait states wait states wait states j=1 k=2 j=2 k=2 j=3 k=3 j=4 k=4 j=3 k=3 j=4 k=4 8-bit 16-bit 8-bit Even Odd Even Odd Even Odd Even Odd Read Cycle 1 1 — — 1 2 — — Write Cycle 1 1 — — 1 2 — — Memory Expansion Mode Microprocessor Mode Read Write Cycle Cycle 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 12.3 Channel Priority and DMA Transfer Timing When multiple DMA requests are generated in the same sampling period, between the falling edge of the CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested) simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3. Figure 12.7 shows an example of the DMA transfer by external factors. In Figure 12.7, the DMA0 request having the highest priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts. After one DMA1 transfer is completed, the privilege is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when DMA requests, as DMA1 in Figure 12.7, occur more than once before receiving bus privilege, the DRQ bit is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is completed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 123 of 488 M32C/83 Group (M32C/83, M32C/83T) 12. DMAC When DMA transfer request signals are applied to INT0 and INT1 simultaneously and a DMA transfer with minimum cycle occurs. BCLK DMA0 DMA1 CPU INT0 DRQ Bit in DMA0 Register INT1 DRQ Bit in DMA1 Register Bus priviledge acquired Figure 12.7 DMA Transfer by External Factors Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 124 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII 13. DMAC II The DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which transfers the sum of two data added by an interrupt request from any peripheral functions. Table 13.1 lists specifications of the DMAC II. Table 13.1 DMAC II Specifications Specification Interrupt requests generated by all peripheral functions when the ILVL2 to ILVL0 bits are set to "1112" Transfer Data • Data in memory is transferred to memory (memory-to-memory transfer) • Immediate data is transferred to memory (immediate data transfer) • Data in memory (or immediate data) + data in memory are transferred to memory (calculation transfer) Transfer Block 8 bits or 16 bits Transfer Space 64-Kbyte space in addresses 0000016 to 0FFFF16(1, 2) Transfer Direction Fixed or forward address Selected separately for each source address and destination address Transfer Mode Single transfer, burst transfer Chained Transfer Function Parameters (transfer count, transfer address and other information) are switched when transfer counter reaches zero End-of-Transfer Interrupt Interrupt occurs when a transfer counter reaches zero Multiple Transfer Function Multiple data can be transferred by a generated request for one DMA II transfer NOTES: 1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16. 2. The actual space where transfer can occur is limited due to internal RAM capacity. Item DMAC II Request Factor 13.1 DMAC II Settings DMAC II can be made available by setting up the following registers and tables. • RLVL register • DMAC II Index • Interrupt control register of the peripheral function causing a DMAC II request • The relocatable vector table of the peripheral function causing a DMAC II request • IRLT bit in the IIOiIE register (i = 0 to 11) if using the intelligent I/O or CAN interrupt Refer to 10. Interrupts for details on the IIOiIE register 13.1.1 RLVL Register When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), the DMAC II is activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt control register set to "1112" (level 7). Figure 13.1 shows the RLVL register. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 125 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII Exit Priority Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RLVL Address 009F16 After Reset XXXX 00002 Bit Symbol RLVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW RLVL1 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit(1) RW RLVL2 RW FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt RW (b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMAC II transfer(3) DMA II DMAC II Select Bit(4) RW Nothing is assigned. When write, set to "0". (b7 - b6) When read, its content is indeterminate. NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. 2. When the FSIT bit is set to "1", interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to interrupt priority level 7 and the DMA II bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. After reset, the DMA II bit is indeterminate. When using an interrupt, set the interrupt control register after setting the DMA II bit to "0". Figure 13.1 RLVL Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 126 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII 13.1.2 DMAC II Index The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination address, chained transfer address, and end-of-transfer interrupt address. This DMAC II index must be located on the RAM area. Figure 13.2 shows a configuration of the DMAC II index. Table 13.2 lists a configuration of the DMAC II index in transfer mode. Memory-to-Memory Transfer, Immediate Transfer, Calculation Transfer 16 bits DMAC II Index Starting Address (BASE) Transfer Mode BASE + 2 BASE + 4 BASE + 6 BASE + 8 BASE + 10 BASE + 12 BASE + 14 BASE + 16 Transfer Counter Operation Address(1) Transfer Destination Address Chained Transfer Address(2) Chained Transfer Address(2) End-of-Transfer Interrupt Address(3) End-of-Transfer Interrupt Address(3) (MOD) (COUNT) BASE BASE + 2 BASE + 4 BASE + 6 BASE + 8 Multiple Transfer 16 bits Transfer Mode Transfer Counter Transfer Source Address Transfer Destination Address Transfer Source Address (MOD) (COUNT) (SADR1) (DADR1) (SADR2) (DADR2) Transfer Source Address (or immediate data) (SADR) (OADR) (DADR) (CADR0) (CADR1) (IADR0) (IADR1) BASE + 10 Transfer Destination Address BASE + 28 Transfer Source Address BASE + 30 Transfer Destination Address (SADR7) (DADR7) NOTES: 1. This data is not required when not using the calculation transfer function. 2. This data is not required when not using the chained transfer function. 3. This data is not required when not using the end-of-transfer interrupt. The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation transfer function, set destination address to BASE+6. (See Table 13.2) Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request. Figure 13.2 DMAC II Index The followings are details of the DMAC II index. Set these parameters in the specified order listed in Table 13.2, according to DMAC II transfer mode. • Transfer mode (MOD) Two-byte data is required to set transfer mode. Figure 13.3 shows a configuration for transfer mode. • Transfer counter (COUNT) Two-byte data is required to set the number of transfer. • Transfer source address (SADR) Two-byte data is required to set the source memory address or immediate data. • Operation address (OADR) Two-byte data is required to set a memory address to be calculated. Set this data only when using the calculation transfer function. • Transfer destination address (DADR) Two-byte data is required to set the destination memory address. • Chained transfer address (CADR) Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set this data only when using the chained transfer function. • End-of-transfer interrupt address (IADR) Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this data only when using the end-of-transfer interrupt. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 127 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII Table 13.2 DMAC II Index Configuration in Transfer Mode Memory-to-Memory Transfer /Immediate Data Transfer Chained Transfer Not Used Used Not Used MOD COUNT SADR DADR CADR0 CADR1 12 bytes Not Used Used MOD COUNT SADR DADR IADR0 IADR1 12 bytes Used Used MOD COUNT SADR DADR CADR0 CADR1 IADR0 IADR1 16 bytes Not Used Not Used MOD COUNT SADR OADR DADR 10 bytes Calculation Transfer Used Not Used MOD COUNT SADR OADR DADR CADR0 CADR1 14 bytes Not Used Used MOD COUNT SADR OADR DADR IADR0 IADR1 14 bytes Used Used MOD COUNT SADR OADR DADR CADR0 CADR1 IADR0 IADR1 18 bytes SADRi DADRi i=1 to 7 Max 32 bytes (when i=7) Multiple Transfer Not Available Not Available MOD COUNT SADR1 DADR1 End-of-Transfer Not Used Interrupt MOD COUNT SADR DADR DMAC II Index 8 bytes Transfer Mode (MOD)(1) b15 b8 b7 b0 Bit Symbol SIZE Bit Name Transfer Unit Select Bit Transfer Data Select Bit Function (MULT=0) 0: 8 bits 1: 16 bits 0: Immediate data 1: Memory Function (MULT=1) RW RW IMM Set to "1" RW UPDS Transfer Source 0: Fixed address Direction Select Bit 1: Forward address Transfer Destination 0: Fixed address Direction Select Bit 1: Forward address b6 b5 b4 RW UPDD RW OPER/ Calculation Transfer 0: Not used CNT0(2) Function Select Bit 1: Used BRST/ Burst Transfer CNT1(2) Select Bit INTE/ End-of-Transfer CNT2(2) Interrupt Select Bit CHAIN Chained Transfer Select Bit 0: Single transfer 1: Burst transfer 0: Interrupt not used 1: Use interrupt 0 0 0: Do not set to this value 0 0 1: Once 0 1 0: Twice : : 1 1 0: 6 times 1 1 1: 7 times RW RW RW 0: Chained transfer not used Set to "0" 1: Use chained transfer RW Nothing is assigned. When write, set to "0". (b14 - b8) When read, its content is indeterminate. MULT Multiple Transfer Select Bit 0: Multiple transfer not used 1: Use multiple transfer RW NOTES: 1. MOD must be located on the RAM. 2. When the MULT bit is set to "0" (no multiple transfer), bits 4 to 6 becomes the OPER, BRST, INTE bits. When the MULT bit is set to "1" (multiple transfer), bits 4 to 6 becomes the CNT0 to CNT2 bits. Figure 13.3 MOD Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 128 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII 13.1.3 Interrupt Control Register for the Peripheral Function For the peripheral function interrupt activating a DMAC II request, set the ILVL2 to ILVL0 bits to "1112" (level 7). 13.1.4 Relocatable Vector Table for the Peripheral Function Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt activating a DMAC II request. When using the chained transfer, the relocatable vector table must be located in the RAM. 13.1.5 IRLT Bit in the IIOiIE Register (i=0 to 11) When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE register of the interrupt to "0". 13.2 DMAC II Performance The DMAC II function is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II request is activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral function interrupt cannot be used. When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "1112" (level 7), the DMAC II is activated regardless of what state the I flag and IPL is in. 13.3 Transfer Data The DMAC II transfers 8-bit or 16-bit data. • Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space (Addresses 0000016 to 0FFFF16) to another desired memory location in the same space. • Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space. • Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired memory location in a 64K-byte space. When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16 . 13.3.1 Memory-to-Memory Transfer Data transfer between any two memory locations can be: • a transfer from a fixed address to another fixed address • a transfer from a fixed address to a relocatable address • a transfer from a relocatable address to a fixed address • a transfer from a relocatable address to another relocatable address When a relocatable address is selected, the DMAC II increments address, after a transfer, for the next transfer. In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is incremented by two. When a source or destination address exceeds address 0FFFF16 as a result of address incrementation, the source or destination address returns to address 00000016 and continues incrementation. Maintain source and destination address at address 0FFFF16 or below. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 129 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII 13.3.2 Immediate Data Transfer The DMAC II transfers immediate data to a desired memory location. A fixed or relocatable address can be selected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate data, write the data in the low-order byte of SADR (high-order byte is ignored). 13.3.3 Calculation Transfer After two memory data, or an immediate data and memory data are added together, the calculated result is transferred to a desired memory location. SADR must have one memory location address to be calculated or immediate data. OADR must have the other memory location address to be calculated. Fixed or relocatable address can be selected as source and destination addresses when using a memory + memory calculation transfer. If the transfer source address is relocatable, the operation address also becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address when using an immediate data + memory calculation transfer. 13.4 Transfer Modes In DMAC II, single and burst transfers are available. The BRST bit in MOD selects transfer method, either the single transfer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set to "000016". All interrupts are ignored while transfer is in progress. 13.4.1 Single Transfer For every transfer request factor, the DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When the source or destination address is relocatable, the DMAC II increments the address, after a transfer, for the next transfer. COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the interrupt is acknowledged when COUNT reaches "0". 13.4.2 Burst Transfer For every transfer request factor, the DMAC II continuously transfers data the number of times determined by COUNT. The DMAC II decrements COUNT every time a transfer occurs. The burst transfer ends when COUNT reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the end-of-transfer interrupt. All interrupts are ignored while the burst transfer is in progress. 13.4.3 Multiple Transfer The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memoryto-memory transfer. One transfer request factor initiates multiple transfers. The CNT2 to CNT0 bits in MOD selects the number of transfers from "0012" (once) to "1112" (7 times). Do not set the CNT2 to CNT0 bits to "0002". The transfer source and destination addresses for each transfer must be allocated alternately to addresses following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer, end-of-transfer interrupt and chained transfer cannot be used. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 130 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII 13.4.4 Chained Transfer The CHAIN bit in MOD selects the chained transfer. The following process initiates the chained transfer. (1) Transfer, caused by a transfer request factor, occurs according to the content of the DMAC II index. The vectors of the request factor indicates the address where the DMAC II index is allocated. For each request, the BRST bit in MOD selects either single or burst transfer. (2) When COUNT reaches "0", the contents of CADR1 to CADR0 are written to the vector of the request factor. When the INTE bit in the MOD is set to "1," the end-of-transfer interrupt is generated simultaneously. (3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the DMAC II index indicated by the vector rewritten in (2). Figure 13.4 shows the relocatable vector and DMACII index of when the chained transfer is in progress. For the chained transfer, the relocatable vector table must be located in the RAM. RAM INTB Relocatable vector Peripheral I/O interrupt vector causing DMAC II request Default value of DMAC II is BASE(1). BASE(1) DMAC II Index(1) (CADR1 to CADR0) BASE(2) The above vector is rewritten to BASE(2) when a transfer is completed. Starts at BASE(2) when next request conditions are met. Transferred according to the DMAC II Index. BASE(2) DMAC II Index(2) (CADR1 to CADR0) BASE(3) The above vector is rewritten to BASE(3) when a transfer is completed. Figure 13.4 Relocatable Vector and DMAC II Index 13.4.5 End-of-Transfer Interrupt The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer interrupt service routine in the IADR1 to IADR0 bits. The end-of-transfer interrupt is generated when COUNT reaches "0." Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 131 of 488 M32C/83 Group (M32C/83, M32C/83T) 13. DMACII 13.5 Execution Time DMAC II execution cycle is calculated by the following equations: Multiple transfers: t = 21 + (11 + b + c) x k cycles Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles a: If IMM = 0 (source of transfer is immediate data), a = 0; if IMM = 1 (source of transfer is memory), a = –1 b: If UPDS = 1 (source transfer address is a relocatable address), b = 0; if UPDS = 0 (source transfer address is a fixed address), b = 1 c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0; if UPDD = 0 (destination transfer address is a fixed address), c = 1 d: If OPER = 0 (calculation function is not selected), d = 0; if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed address memory), d = 7; if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address memory), d = 8 e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4 m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in COUNT n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1 k: Number of transfers set in the CNT2 to CNT0 bits The equations above are approximations. The number of cycles may change with CPU state, bus wait state, and DMAC II index allocation. The first instruction from the end-of-transfer interrupt service routine is executed in the 8th cycle after the DMAC II transfer is completed. If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address, single transfer and double transfer: a=-1 b=0 c=1 d=0 e=0 m=1 First DMAC II transfer t=6+26x1+4x1=36 cycles Second DMAC II transfer t=6+26x1+4x0=32 cycles DMAC II transfer request DMAC II transfer request Program DMAC II transfer (First time) 36 cycles Program DMAC II transfer (Second time) 32 cycles 7 cycles Processing the end-of-transfer interrupt Transfer counter = 2 Transfer counter = 1 Decrement a transfer counter Transfer counter = 0 Decrement a transfer counter Transfer counter = 1 Figure 13.5 Transfer Cycle When an interrupt request which acts as a DMAC II transfer request factor and another interrupt request _______ with higher priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence has been completed. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 132 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer 14. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each timer operates independently. The count source for each timer is the clock for timer operations including counting and reloading, etc. Figures 14.1 and 14.2 show block diagrams of timer A and timer B configuration. Clock prescaler f1 1/8 1/2n CST f1 f8 f2n fC32 TCK1 to TCK0 00 01 10 11 Main clock, PLL clock or On-chip oscillator clock XCIN Set the CPSR bit in the CPSRF register to "1" 1/32 Reset fC32 f8 f2n (Note 1) 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 01 00 TMOD1 to TMOD0 Timer A0 interrupt Timer A0 TA0IN Noise filter 01: Event counter mode 11 TA0TGH to TA0TGL TCK1 to TCK0 00 01 10 11 00: Timer mode 10: One-shot tiemr mode 11: PWM mode 10 TMOD1 to TMOD0 Timer A1 interrupt Timer A1 TA1IN Noise filter 01 00 01: Event counter mode 11 TA1TGH to TA1TGL TCK1 to TCK0 00 01 10 11 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 TMOD1 to TMOD0 Timer A2 interrupt Timer A2 TA2IN Noise filter 01 00 01: Event counter mode 11 TA2TGH to TA2TGL TCK1 to TCK0 00 01 10 11 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 01 00 TMOD1 to TMOD0 Timer A3 interrupt Timer A3 TA3IN Noise filter 01: Event counter mode 11 TA3TGH to TA3TGL TCK1 to TCK0 00 01 10 11 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 TMOD1 to TMOD0 Timer A4 interrupt Timer A4 TA4IN Noise filter 01 00 01: Event counter mode 11 TA4TGH to TA4TGL Timer B2 overflow or underflow CST: Bit in TCSPR register TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TAiGH to TAiGL: Bits in ONSF register or TRGSR register (i=1 to 4) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.1 Timer A Configuration Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 133 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer Main clock, PLL clock or On-chip clock f1 1/8 1/2n CST f1 f8 f2n fC32 00 01 10 11 f8 f2n XCIN Clock prescaler 1/32 Reset fC32 (Note 1) Timer B2 overflow or underflow (to a count source of the timer A) Set the CPSR bit in the CPSRF register to "1" TCK1 to TCK0 00: Timer mode 10: Pulse width measurement mode TMOD1 to TMOD0 1 0 TCK1 TB0IN Noise filter 00 01 10 11 TCK1 to TCK0 Timer B0 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 to TMOD0 Timer B0 interrupt Timer B1 interrupt Timer B1 TB1IN Noise filter 00 01 10 11 TCK1 to TCK0 0 TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 to TMOD0 Timer B2 interrupt Timer B2 TB2IN Noise filter 0 TCK1 01:Event counter mode 00 01 10 11 TCK1 to TCK0 00: Timer mode 10: Pulse width measurement mode TMOD1 to TMOD0 1 TB3IN 00 01 10 11 Noise filter TCK1 to TCK0 Timer B3 TCK1 Timer B3 interrupt 0 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 to TMOD0 TB4IN 00 01 10 11 Noise filter TCK1 to TCK0 Timer B4 0 TCK1 Timer B4 interrupt 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 to TMOD0 TB5IN Noise filter Timer B5 0 TCK1 Timer B5 interrupt 01:Event counter mode CST : Bit in TCSPR register TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TBiMR register (i=0 to 5) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.2 Timer B Configuration Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 134 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) 14.1 Timer A Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 show registers associated with the timer A. The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the same function. The TMOD1 to TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is used. • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers. • One-shot timer mode: The timer outputs one valid pulse until the counter reaches "000016". • Pulse width modulation mode: The timer continuously outputs desired pulse widths. Table 14.1 lists TAiOUT pin settings when used as an output. Table 14.2 lists TAiIN and TAiOUT pin settings when used as an input. Select clock High-Order Bits of Data Bus Select Count Source f1 f8 f2n(1) fC32 00 01 10 11 TCK1 to TCK0 • Timer :TMOD1 to TMOD0=00, MR2=0 • One-Shot Timer :TMOD1 to TMOD0=10 TMOD1 to TMOD0, • Pulse Width Modulation:TMOD1 to TMOD0=11 MR2 • Timer(gate function):TMOD1 to TMOD0=00, MR2=1 • Event counter:TMOD1 to TMOD0=01 Low-Order Bits of Data Bus 8 loworder bits Reload Register 8 highorder bits TAiIN Polarity Selector TAiS Counter Increment / decrement Always decrement except in event counter mode 00 01 11 01 0 1 TMOD1 to TMOD0 TB2 Overflow(2) 10 TAj Overflow(2) 11 TAk Overflow(2) TAiTGH to TAiTGL 00 01 Decrement TAiUD Pulse Output MR2 TAiOUT Toggle Flip Flop i=0 to 4 j=i-1, except j=4 if i=0 k=i+1, except k=0 if i=4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. Overflow or underflow TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 034716 034616 034916 034816 034B16 034A16 034D16 034C16 034F16 034E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1 : Bits in TAiMR register TAiTGH to TAiTGL: Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4 TAiS: Bits in the TABSR register TAiUD: Bits in the UDF register Figure 14.3 Timer A Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 135 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Timer Ai Register (i=0 to 4)(1) b15 b8 b7 b0 Symbol TA0 to TA2 TA3, TA4 Address 034716-034616, 034916-034816, 034B16-034A16 034D16-034C16, 034F16-034E16 After Reset Indeterminate Indeterminate Mode Timer Mode Function If setting value is n, count source is divided by n+1. If setting value is n, count source is divided by FFFF16 - n+1 when the counter is incremented and by n+1 when the counter is decremented. If setting value is n, count source is divided by n, then stops. Setting Range RW 000016 to FFFF16 RW Event Counter Mode(2) One-Shot Timer Mode(4) 000016 to FFFF16 RW 000016 to FFFF16(3) WO If count source frequency is fj Pulse Width and setting value of the TAi Modulation Mode(5) register is n, PWM cycle: (216-1) / fj (16-Bit PWM) "H" width of PWM pulse: n / fj If count source frequency is fj, setting value of high-order bits in the TAi register is n and setting value of low-order bits in the TAi register is m, PWM cycle: (28-1)x(m+1) / fj "H" width of PWM pulse: (m+1)n / fj 000016 to FFFE16(3) WO Pulse Width Modulation Mode(5) (8-Bit PWM) 0016 to FE16(3) (High-order address bits) 0016 to FF16(3) (Low-order address bits) WO fj : f1, f8, f2n, fC32 NOTES: 1. Use 16-bit data for reading and writing. 2. The TAi register counts how many pulses are input externally or how many times another timer counter overflows and underflows. 3. Use the MOV instruction to set the TAi register. 4. When the TAi register is set to "000016", the counter does not start and the timer Ai interrupt request is not generated. 5. When the TAi register is set to "000016", the pulse width modulator does not operate and the TAiOUT pin is held "L". The TAi interrupt request is also not generated. The same situation occurs in 8-bit pulse width modulator mode if the 8 high-order bits in the TAi register are set to "0016". Figure 14.4 TA0 to TA4 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 136 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR0 to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0000 0X002 Bit Symbol TMOD0 TMOD1 Bit Name b1b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW RW RW Operation Mode Select Bit (b2) MR1 MR2 MR3 TCK0 Nothing is assigned. When write, set to "0". RW Function varies depending on operation mode RW RW RW RW Count Source Select Bit TCK1 Function varies depending on operation mode Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 034016 After Reset 0016 Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit Name Timer A0 Count Start Flag Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag Function 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW RW RW RW RW RW RW RW Figure 14.5 TA0MR to TA4MR Registers and TABSR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 137 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Up/Down Flag(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 034416 After Reset 0016 Bit Symbol TA0UD TA1UD TA2UD TA3UD TA4UD Bit Name Timer A0 Up/Down Flag Timer A1 Up/Down Flag Timer A2 Up/Down Flag Timer A3 Up/Down Flag Timer A4 Up/Down Flag Function 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment (Note 2) RW RW RW RW RW RW (Note 2) (Note 2) (Note 2) (Note 2) TA2P TA3P 0 : Disables two-phase pulse signal Timer A2 Two-Phase processing function Pulse Signal Processing WO 1 : Enables two-phase pulse signal Function Select Bit (Note 3) processing function 0 : Disables two-phase pulse signal Timer A3 Two-Phase processing function Pulse Signal Processing WO 1 : Enables two-phase pulse signal Function Select Bit (Note 3) processing function 0 : Disables two-phase pulse signal Timer A4 Two-Phase processing function Pulse Signal Processing WO 1 : Enables two-phase pulse signal Function Select Bit (Note 3) processing function TA4P NOTES: 1. Use the MOV instruction to set the UDF register. 2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register causes increment/decrement switching) in event counter mode. 3. Set this bit to "0" when not using the two-phase pulse signal processing function. One-Shot Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 034216 After Reset 0016 Bit Symbol TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE Bit Name Timer A0 One-Shot Start Flag Timer A1 One-Shot Start Flag Timer A2 One-Shot Start Flag Timer A3 One-Shot Start Flag Timer A4 One-Shot Start Flag Z-Phase Input Enable Bit Function 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : Disables Z-phase input 1 : Enables Z-phase input b7 b6 RW (Note 1) RW (Note 1) (Note 1) RW RW (Note 1) RW (Note 1) RW RW TA0TGL Timer A0 Event/Trigger Select Bit TA0TGH NOTES: 1. When read, the bit is set to "0". 2. Overflow or underflow. 0 0 : Selects an input to the TA0IN pin RW 0 1 : Selects the TB2 overflows(2) 1 0 : Selects the TA4 overflows(2) RW 1 1 : Selects the TA1 overflows(2) Figure 14.6 UDF Register and ONSF Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 138 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 034316 After Reset 0016 Bit Symbol TA1TGL Bit Name b0 b1 Function RW Timer A1 Event/Trigger Select Bit TA1TGH 0 0 : Selects an input to the TA1IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA0 overflows(1) RW 1 1 : Selects the TA2 overflows(1) b3 b2 TA2TGL Timer A2 Event/Trigger Select Bit TA2TGH TA3TGL Timer A3 Event/Trigger Select Bit TA3TGH 0 0 : Selects an input to the TA2IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA1 overflows(1) RW 1 1 : Selects the TA3 overflows(1) b5 b4 0 0 : Selects an input to the TA3IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA2 overflows(1) RW 1 1 : Selects the TA4 overflows(1) b7 b6 TA4TGL TA4TGH Timer A4 Event/Trigger Select Bit 0 0 : Selects an input to the TA4IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA3 overflows(1) RW 1 1 : Selects the TA0 overflows(1) NOTES: 1. Overflow or underflow. Count Source Prescaler Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TCSPR Address 035F16 After Reset (2) 0XXX 00002 Bit Symbol CNT0 Bit Name Function RW RW CNT1 Divide Ratio Select Bit CNT2 If setting value is n, f2n is the main clock, PLL clock or on-chip oscillator clock divided by 2n. Not divided if n=0.(1) RW RW RW CNT3 Nothing is assigned. When write, set to "0". (b6 - b4) When read, its content is indeterminate. CST Operation Enable Bit 0 : Stops divider 1 : Starts divider RW NOTES: 1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has performed. Figure 14.7 TRGSR Register and TCSPR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 139 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Table 14.1 Pin Settings for Output from TAiOUT Pin (i=0 to 4) Pin PS1, PS2 Registers P70/TA0OUT(1) P72/TA1OUT P74/TA2OUT P76/TA3OUT P80/TA4OUT PS1_0= 1 PS1_2= 1 PS1_4= 1 PS1_6= 1 PS2_0= 1 Setting PSL1, PSL2 Registers PSL1_0=1 PSL1_2=1 PSL1_4=0 PSL1_6=1 PSL2_0=0 PSC Register PSC_0= 0 PSC_2= 0 PSC_4= 0 PSC_6= 0 – NOTES: 1. P70/TA0OUT is a port for the N-channel open drain output. Table 14.2 Pin Settings for Input to TAiIN and TAiOUT Pins (i=0 to 4) Pin Setting PS1, PS2 Registers PD7, PD8 Registers P70/TA0OUT P71/TA0IN P72/TA1OUT P73/TA1IN P74TA2OUT P75/TA2IN P76TA3OUT P77/TA3IN P80/TA4OUT P81/TA4IN PS1_0=0 PS1_1=0 PS1_2=0 PS1_3=0 PS1_4=0 PS1_5=0 PS1_6=0 PS1_7=0 PS2_0=0 PS2_1=0 PD7_0=0 PD7_1=0 PD7_2=0 PD7_3=0 PD7_4=0 PD7_5=0 PD7_6=0 PD7_7=0 PD8_0=0 PD8_1=0 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 140 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) 14.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 14.3). Figure 14.8 shows the TAiMR register (i=0 to 4) in timer mode. Table 14.3 Specifications in Timer Mode Item Count Source Counting Operation f1, f8, f2n(1), fC32 • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio Counter Start Condition Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer 1/(n+1) n: setting value of the TAi register (i=0 to 4) 000016 to FFFF16 The TAiS bit in the TABSR register is set to "1" (starts counting) The TAiS bit is set to "0" (stops counting) Programmable I/O port or gate input Programmable I/O port or pulse output The TAi register indicates counter value • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Gate function Input signal to the TAiIN pin determines whether the timer counter starts or stops counting • Pulse output function The polarity of the TAiOUT pin is inversed whenever the timer counter underflows Specification Interrupt Request Generation Timing The timer counter underflows NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 141 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (Timer Mode) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0000 0X002 Bit Symbol TMOD0 Bit Name Function RW RW Operation Mode Select Bit TMOD1 b1 b0 0 0 : Timer mode RW Nothing is assigned. When write, set to "0". b4 b3 (b2) MR1 Gate Function Select Bit MR2 MR3 TCK0 Count Source Select Bit TCK1 Set to "0" in timer mode 0 X : Gate function disabled(1) RW (TAiIN pin is a programmable I/O pin) 1 0 : Timer counts only while the TAiIN pin is held "L" RW 1 1 : Timer counts only while the TAiIN pin is held "H" RW b7 b6 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 RW RW NOTES: 1. X can be set to either "0" or "1". 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.8 TA0MR to TA4MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 142 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) 14.1.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. The timers A2, A3 and A4 can count externally generated twophase signals. Table 14.4 lists specifications in event counter mode (when not handling a two-phase pulse signal). Table 14.5 lists specifications in event counter mode (when handling a two-phase pulse signal with the timer A2, A3 and A4). Figure 14.9 shows the TAiMR (i=0 to 4) register in event counter mode. Table 14.4 Specifications in Event Counter Mode (when not processing two-phase pulse signal) Item Count Source program) • Timer B2 overflow or underflow signal, timer Aj overflow or underflow signal (j=i-1, except j=4 if i=0) and timer Ak overflow or underflow signal (k=i+1, except k=0 if i=4) Counting Operation • External signal and program can determine whether the timer increments or decrements the counter • When the timer counter underflows or overflows, the content of the reload register is reloaded into the count register and counting resumes. When the free-running count function is selected, the timer counter continues running without reloading. Divide Ratio Counter Start Condition Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer • 1/(FFFF16 - n + 1) for counter increment • 1/(n + 1) for counter decrement n : setting value of the TAi register 0000 16 to FFFF16 The TAiS bit in the TABSR register is set to "1" (starts counting) The TAiS bit is set to "0" (stops counting) Programmable I/O port or count source input Programmable I/O port, pulse output or input selecting a counter increment or decrement The TAi register indicates counter value • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Free-running count function Content of the reload register is not reloaded even if the timer counter overflows or underflows • Pulse output function The polarity of the TAiOUT pin is inversed whenever the timer counter overflows or underflows Specification • External signal applied to the TAiIN pin (i = 0 to 4) (valid edge can be selected by Interrupt Request Generation Timing The timer counter overflows or underflows Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 143 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Table 14.5 Specifications in Event Counter Mode (when processing two-phase pulse signal on timer A2, A3 and A4) Item Count Source Counting Operation Specification Two-phase pulse signal applied to the TAiIN pin, or TAiIN and TAiOUT pin (i = 2 to 4) • Two-phase pulse signal determines whether the timer increments or decrements a counter value • When the timer counter overflows or underflows, content of the reload register is reloaded into the count register and counting resumes. With the free-running count function, the timer counter continues running without reloading. Divide Ratio Counter Start Condition Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer • 1/ (FFFF16 - n + 1) for counter increment • 1/ (n + 1) for counter decrement n : setting value of the TAi register 000016 to FFFF16 The TAiS bit in the TABSR register is set to "1" (starts counting) The TAiS bit is set to "0" (stops counting) Two-phase pulse signal is applied Two-phase pulse signal is applied The TAi register indicates counter value • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function(1) • Normal processing operation (the timer A2 and timer A3) While a high-level ("H") signal is applied to the TAjOUT pin (j = 2 or 3), the timer increments a counter value on the rising edge of the TAjIN pin or decrements a counter value on the falling edge. Interrupt Request Generation Timing The timer counter overflows or underflows TAjOUT TAjIN Increment Increment Increment Decrement Decrement Decrement • Multiply-by-4 processing operation (the timer A3 and timer A4) While an "H" signal is applied to the TAkOUT pin (k = 3 or 4) with the rising edge of the TAkIN pin, the timer counter increments a counter value on the rising and falling edges of the TAkOUT and TAkIN pins. While "H" is applied to the TAkOUT pin on the falling edge of the TAkIN pin, the timer decrements a counter value on the rising and falling edges of the TAkOUT and TAkIN pins. TAkOUT TAkIN Increment on all edges Decrement on all edges NOTES: 1. Only timer A3 operation can be selected. The timer A2 is for the normal processing operation. The timer A4 is for the multiply-by-4 operation. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 144 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (Event Counter Mode) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0000 0X0016 Bit Symbol TMOD0 Function Bit Name Function RW (When not using two-phase (When using two-phase pulse signal processing) pulse signal processing) Operation Mode Select Bit TMOD1 b1 b0 RW 0 1 : Event counter mode(1) RW (b2) Nothing is assigned. When write, set to "0". 0 : Counts falling edges of an external signal Set to "0" 1 : Counts rising edges of an external signal RW MR1 Count Polarity Select Bit(2) RW MR2 Increment/Decrement 0 : Setting of the UDF register Set to "1" Switching Cause 1 : Input signal to Select Bit (3) TAiOUT pin Set to "0" in event counter mode Count Operation Type Select Bit 0 : Reloading 1 : Free running RW MR3 RW TCK0 RW 0 : Normal processing operation RW 1 : Multiplied-by-4 processing operation TCK1 Two-Phase Pulse Set to "0" Signal Processing Operation Select Bit(4,5) NOTES: 1. The TAiTGH to TAiTGL bits in the ONSF or TRGSR register determine the count source in the event counter mode. 2. The MR1 bit is enabled only when counting how many times external signals are applied. 3. The timer decrements a counter value when "L" is applied to the TAiOUT pin and the timer increments a counter value when "H" is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (twophase pulse signal processing function enabled) and the TAiTGH and TAiTGL bits to "002" (input to the TAjIN pin). Figure 14.9 TA0MR to TA4MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 145 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) 14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing The timer counter is reset to "0" by a Z-phase input when processing a two-phase pulse signal. This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free_______ run type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin. When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), the timer counter can be reset by a Z-phase input. To reset the timer counter by a Z-phase input, set the TA3 register to "000016" beforehand. _______ Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer A3 count source cycle or more. Figure 14.10 shows two-phase pulses (A-phase and B-phase) and the Z-phase. Z-phase input resets the counter in the next count source following Z-phase input. Figure 14.11 shows the counter reset timing. Timer A3 interrupt request is generated twice when a timer A3 overflow or underflow, and a counter _______ reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request when this function is used. TA3OUT (A-phase) TA3IN (B-phase) Count source INT2 (1) (Z-phase) Pulse width of one count source cycle or more is required NOTES: 1. When the rising edge of INT2 is selected. Figure 14.10 Two-phase Pulse (A-phase and B-phase) and Z-phase TA3OUT (A-phase) TA3IN (B-phase) Count source INT2 (1) (Z-phase) Counter value m m+1 1 2 3 4 5 Timer counter is reset at this timing NOTES: 1. When the rising edge of INT2 is selected. Figure 14.11 Counter Reset Timing Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 146 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) 14.1.3 One-shot Timer Mode In one-shot timer mode, the timer operates only once for each trigger (see Table 14.6). Once a trigger occurs, the timer starts and continues operating for a desired period. Figure 14.12 shows the TAiMR register (i=0 to 4) in one-shot timer mode. Table 14.6 Specifications in One-shot Timer Mode Item Count Source Counting Operation f1, f8, f2n(1), fC32 The timer decrements a counter value • When the timer counter reaches "000016", it stops counting after reloading. • If a trigger occurs while counting, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio Counter Start Condition 1/n n : setting value of the TAi register (i=0 to 4) 000016 to FFFF16 but the timer counter does not run if n=000016 The TAiS bit in the TABSR register is set to "1" (starts counting) and following triggers occur: • External trigger input • The timer overflow or underflow signal • The TAiOS bit in the ONSF register is set to "1" (timer started) Counter Stop Condition • After the timer counter has reached "000016" and is reloaded • When the TAiS bit is set to "0" (timer stopped) Interrupt Request Generation Timing The timer counter reaches "000016" TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer Programmable I/O port or trigger input Programmable I/O port or pulse output The value in the TAi register is indeterminate when read • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Specification NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 147 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (One-Shot Timer Mode) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 0 10 After Reset 0000 0X002 Bit Symbol TMOD0 Bit Name Function RW RW Operation Mode Select Bit TMOD1 b1b0 1 0 : One-shot timer mode RW (b2) MR1 Nothing is assigned. When write, set to "0". External Trigger Select 0 : Falling edge of input signal to TAiIN pin RW Bit(1) 1 : Rising edge of input signal to TAiIN pin Trigger Select Bit 0 : The TAiOS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits RW MR2 MR3 TCK0 Set to "0" in the one-shot timer mode b7b6 RW RW Count Source Select Bit TCK1 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 RW NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH to TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.12 TA0MR to TA4MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 148 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) 14.1.4 Pulse Width Modulation Mode In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 14.7). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 14.13 shows the TAiMR register (i=0 to 4) in pulse width modulation mode. Figures 14.14 and 14.15 show examples of how a 16-bit pulse width modulator operates and of how an 8-bit pulse width modulator operates. Table 14.7 Specifications in Pulse Width Modulation Mode Item Count Source Counting Operation f1, f8, f2n(1), fC32 The timer decrements the counter (The counter functions as an 8-bit or a 16-bit pulse width modulator) • The timer reloads on the rising edge of PWM pulse and continues counting. • The timer is not affected by the trigger that is generated during counting. 16-Bit PWM • "H" width = n / fj • Cycle = 8-Bit PWM (216-1) / fj fixed 0016 to FE16 0016 to FF16 n : setting value of the TAi register fj : Count source frequency • "H" width = n x (m+1) / fj n : setting value of high-order bit address of the TAi register • Cycles = Counter Start Condition (28-1) x (m+1) / fj m : setting value of low-order bit address of the TAi register • External trigger is input • The timer overflows and underflows • The TAiS bit in the TABSR register is set to "1" (start counting) Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer The TAiS bit is set to "0" (stop counting) Programmable I/O port or trigger input Pulse output The value in the TAi register is indeterminate when read • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Interrupt Request Generation Timing On the falling edge of the PWM pulse 000016 to FFFE16 Specification NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 149 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0000 0X002 Bit Symbol TMOD0 Bit Name Function RW RW Operation Mode Select Bit TMOD1 b1b0 1 1 : Pulse width modulation (PWM) mode RW Nothing is assigned. When write, set to "0". (b2) MR1 External Trigger Select Bit(1) Trigger Select Bit 16/8-Bit PWM Mode Select Bit 0 : Falling edge of input signal to TAiIN pin RW 1 : Rising edge of input signal to TAiIN pin 0 : The TAiS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits RW MR2 MR3 TCK0 0: Functions as a 16-bit pulse width modulator RW 1: Functions as an 8-bit pulse width modulator b7 b6 Count Source Select Bit TCK1 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 RW RW NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH to TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.13 TA0MR to TA4MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 150 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer A) When the reload register is set to "000316" and an external trigger (rising edge of input signal to the TAiIN pin) is selected 1 / fj x (216 – 1) Count source Input signal to TAiIN pin “H” “L” No trigger is generated by this signal 1 / fi x n(1) PWM pulse output from TAiOUT pin “H” “L” “1” IR bit in TAiIC register “0” fj : Count source (f1, f8, f2n(2), fC32) i=0 to 4 Set to "0" by an interrupt request acknowledgement or by program NOTES: 1. n = 000016 to FFFE16. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.14 16-bit Pulse Width Modulator Operation When 8 high-order bits of the reload register are set to "0216", 8 low-order bits of the reload register are set to "0216" and an external trigger (falling edge of input signal to the TAiIN pin) is selected 1 / fj x (m + 1) x (28 – 1) Count source(1) Input signal to TAiIN pin “H” “L” 1 / fj x (m + 1) (3) Underflow signal of 8-bit prescaler(2) “H” “L” 1 / fj x (m + 1) x n (3) PWM pulse output from TAiOUT pin “H” “L” “1” IR bit in TAiIC register “0” fj : Count source frequency (f1, f8, f2n(4), fC32) i=0 to 4 Set to "0" by an interrupt request acknowledgement or by program NOTES: 1. 8-bit prescaler counts a count source. 2. 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler. 3. m = 0016 to FF16, n = 0016 to FE16 4. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n ( n=1 to 15). Figure 14.15 8-bit Pulse Width Modulator Operation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 151 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) 14.2 Timer B Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to 14.19 show registers associated with the timer B. The timer B supports the following three modes. The TMOD1 to TMOD0 bits in the TBiMR register (i=0 to 5) determine which mode is used. • Timer mode : The timer counts an internal count source. • Event counter mode : The timer counts pulses from an external source or overflow and underflow of another timer. • Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an external signal. Table 14.18 lists TBiIN pin settings. High-order Bits of Data Bus Select Clock Source Low-order Bits of Data Bus 8 low-order bits 8 highorder bits f1 00 TCK1 to TCK0 01 f8 (1) 10 f2n fc32 11 TBj Overflow TBiIN (Note 2, 3) 00: Timer 01: Pulse Period and Pulse TMOD1 to TMOD0 Width Measurement Reload Register TCK1 1 0 01: Event Counter TBiS Counter Polarity Switching and Edge Pulse Counter Reset Circuit TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Address 035116 035016 035316 035216 035516 035416 031116 031016 031316 031216 031516 031416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 i=0 to 5 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. The timer counter overflows or underflows. 3. j=i-1, except j=2 when i=0 j=5 when i=3 TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TBiS : Bits in the TABSR and the TBSR register Figure 14.16 Timer B Block Diagram Timer Bi Register(1) (i=0 to 5) b15 b8 b7 b0 Symbol TB0 to TB2 TB3 to TB5 Address 035116 - 035016, 035316 - 035216, 035516 - 035416 031116 - 031016, 031316 - 031216, 031516 - 031416 After Reset Indeterminate Indeterminate Mode Timer Mode Event Counter Mode Function Setting Range RW If setting value is n, a count source 000016 to FFFF16 RW is divided by n+1 If setting value is n, a count source 000016 to FFFF16 RW is divided by n+1(2) RO Pulse Period/Pulse A count source is incremented Width Measurement between one valid edge and Mode another valid edge of TBiIN pulse NOTES: 1. Use 16-bit data for read and write operations. 2. The TBi register counts the number of external input pulses or the number of times another timer counter overflows and underflows. Figure 14.17 TB0 to TB5 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 152 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) Timer Bi Mode Register (i=0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB0MR to TB5MR Address After Reset 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 Bit Name b1b0 Function RW Operation Mode Select Bit TMOD1 MR0 MR1 MR2 MR3 TCK0 Count Source Select Bit TCK1 0 0 : Timer mode RW 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse width measurement mode RW 1 1 : Do not set to this value RW Function varies depending on operation mode (1, 2) RW RW RW RW Function varies depending on operation mode RW NOTES: 1. Only MR2 bits in the TB0MR and TB3MR registers are enabled. 2. Nothing is assigned in the MR2 bit in the TB1MR, TB2MR, TB4MR and TB5MR registers. When write, set to "0". When read, its content is indeterminate. Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 034016 After Reset 0016 Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit Name Timer A0 Count Start Flag Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag Function 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW RW RW RW RW RW RW RW Figure 14.18 TB0MR to TB5MR Registers, TABSR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 153 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) Timer B3, B4,B5 Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 030016 After Reset 000X XXXX2 Bit Symbol Bit Name Function RW Nothing is assigned. When write, set to "0". (b4 - b0) When read, its content is indeterminate. TB3S TB4S TB5S Timer B3 Count Start Flag Timer B4 Count Start Flag Timer B5 Count Start Flag 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW RW Figure 14.19 TBSR Register Table 14.8 Settings for the TBiIN Pins (i=0 to 5) Port Name Function PS1, PS3(1) Registers Setting PD7, PD9(1) Registers P90 P91 P92 P93 P94 P71 TB0IN TB1IN TB2IN TB3IN TB4IN TB5IN PS3_0=0 PS3_1=0 PS3_2=0 PS3_3=0 PS3_4=0 PS1_1=0 PD9_0=0 PD9_1=0 PD9_2=0 PD9_3=0 PD9_4=0 PD7_1=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" ( write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 154 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) 14.2.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 14.9). Figure 14.20 shows the TBiMR register (i=0 to 5) in timer mode. Table 14.9 Specifications in Timer Mode Item Count Source Counting Operation f1, f8, f2n(1), fC32 The timer decrements a counter value • When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes Divide Ratio Counter Start Condition Counter Stop Condition TBiIN Pin Function Read from Timer Write to Timer 1/(n+1) n: setting value of the TBi register (i=0 to 5) 000016 to FFFF16 The TBiS bits in the TABSR or TBSR registers are set to "1" (starts counting) The TBiS bit is set to "0" (stops counting) Programmable I/O port The TBi register indicates counter value • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter • While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing) Specification Interrupt Request Generation Timing The timer counter underflows NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Timer Bi Mode Register (i=0 to 5) (Timer Mode) b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 Bit Name Function RW RW RW Operation Mode Select Bit TMOD1 MR0 MR1 Disabled in timer mode. Can be set to "0" or "1". b1b0 0 0 : Timer mode RW RW RW TB0MR, TB3MR registers: Set to "0" in timer mode MR2 TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Set to "0" in timer mode b7 b6 MR3 TCK0 RW 0 0 : f1 0 1 : f8 1 0 : f2n(1) 1 1 : fC32 RW RW Count Source Select Bit TCK1 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.20 TB0MR to TB5MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 155 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) 14.2.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. (See Table 14.10) Figure 14.21 shows the TBiMR register (i=0 to 5) in event counter mode. Table 14.10 Specifications in Event Counter Mode Item Count Source program) • TBj overflows or underflows (j=i-1, except j=2 when i=0, j=5 when i=3) Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register to continue counting Divide Ratio Counter Start Condition Counter Stop Condition TBiIN Pin Function Read from Timer Write to Timer 1/(n+1) n : setting value of the TBi register 000016 to FFFF16 The TBiS bit in the TABSR or TBSR register is set to "1" (starts counting) The TBiS bit is set to "0" (stops counting) Programmable I/O port or count source input The TBi register indicates the value of the counter • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter • While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing) Specification • External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by Interrupt Request Generation Timing The timer counter underflows Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 156 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) Timer Bi Mode Register (i=0 to 5) (Event Counter Mode) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 TMOD1 MR0 Bit Name Operation Mode Select Bit b1 b0 Function RW RW RW 0 1 : Event counter mode b3 b2 Count Polarity Select Bit(1) MR1 0 0 : Counts falling edges of external signal RW 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges of external signal RW 1 1 : Do not set to this value RW TB0MR and TB3MR registers: Set to "0" in event counter mode MR2 TB1MR, TB2MR, TB4MR and TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. Can be set to "0" or "1". Count Source Select Bit 0 : Input signal from the TBiIN pin 1 : TBj overflows or underflows(2) MR3 TCK0 TCK1 RW RW NOTES: 1. The MR0 and MR1 bits are enabled when the TCK1 bit is set to "0" (input signal from the TBiIN pin). The MR1 bit can be set to either "0" or "1", when the TCK1 bit is set to "1" (timer overflow or underflow). 2. j=i – 1, except j=2 when i=0 and j=5 when i=3. Figure 14.21 TB0MR to TB5MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 157 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) 14.2.3 Pulse Period/Pulse Width Measurement Mode In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. (See Table 14.11) Figure 14.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse width measurement mode. Figure 14.23 shows an example of an operation timing when measuring a pulse period. Figure 14.24 shows an example of the pulse width measurement. Table 14.11 Specifications in Pulse Period/Pulse Width Measurement Mode Item Count Source Counting Operation f1, f8, f2n(3), fC32 • The timer increments a counter value Counter value is transferred to the reload register on the valid edge of a pulse to be measured. It is set to "000016" and the timer continues counting Counter Start Condition Counter Stop Condition The TBiS bit (i=0 to 5) in the TABSR or TBSR register is set to "1" (starts counting) The TBiS bit is set to "0" (stops counting) • The timer counter overflows The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after setting the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to the TBiMR register. TBiIN Pin Function Read from Timer Write to Timer Input for a pulse to be measured The TBi register indicates reload register values (measurement results)(2) Value written to the TBi register can be written to neither reload register nor counter Specification Interrupt Request Generation Timing • On the valid edge of a pulse to be measured(1) NOTES: 1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the timer has started counting. 2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid edge after the timer has started counting. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 158 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) Timer Bi Mode Register (i=0 to 5) (Pulse Period / Pulse Width Measurement Mode) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 TMOD1 MR0 Bit Name Operation Mode Select Bit b1 b0 Function RW RW 1 0 : Pulse period measurement mode, pulse width measurement mode RW b3 b2 Measurement Mode Select Bit MR1 0 0 : Pulse period measurement 1 RW 0 1 : Pulse period measurement 2 1 0 : Pulse width measurement RW 1 1 : Do not set to this value (Note 1) RW TB0MR, TB3MR registers: Set to "0" in pulse period/pulse width measurement mode MR2 TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 : No overflow Timer Bi Overflow Flag(2) 1 : Overflow b7 b6 MR3 RO TCK0 Count Source Select Bit TCK1 0 0 : f1 0 1 : f8 1 0 : f2n(3) 1 1 : fC32 RW RW NOTES: 1. The MR1 to MR0 bits selects the following measurements. Pulse period measurement 1 (MR1 to MR0 bits = 002) : Measures between the falling edge and the next falling edge of a pulse to be measured Pulse period measurement 2 (MR1 to MR0 bits = 012) : Measures between the rising edge and the next rising edge of a pulse to be measured Pulse width measurement (MR1 to MR0 bits = 102) : Measures between a falling edge and the next rising edge of a pulse to be measured and between the rising edge and the next falling edge of a pulse to be measured 2. The MR3 bit is indeterminate when reset. When the timer overflows, the MR3 bit is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after the MR3 bit is set to "1", the MR3 bit is set to "0" (no overflow) by writing again. The MR3 bit cannot be set to "1" by program. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 14.22 TB0MR to TB5MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 159 of 488 M32C/83 Group (M32C/83, M32C/83T) 14. Timer (Timer B) Count source Pulse to be measured “H” “L” Transferred (indeterminate value) Transferred (measured value) Counter to reload register transfer timing Timing that the counter reaches "000016" “1” (Note 1) (Note 1) (Note 2) TBiS bit in TABSR or TBSR register “0” IR bit in TBilC register “1” “0” Set to "0" by an interrupt request acknowledgement or by program MR3 bit in TBiMR register “1” “0” i=0 to 5 NOTES: 1. The counter is reset when a measurement is completed. 2. The timer counter overflows. Figure 14.23 Pulse Period 1 Measurement Count source Pulse to be measured “H” “L” Transferred (indeterminate value) Transferred (measured value) Transferred (measured value) Transferred (measured value) Counter to reload register transfer timing Timing that the counter reaches "000016" “1” “0” “1” “0” (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) TBiS bit in TABSR or TBSR register IR bit in TBilC register Set to "0" by an interrupt request acknowledgement or by program. MR3 bit in TBiMR register “1” “0” i=0 to 5 NOTES: 1. The counter is reset when a measurement is completed. 2. The timer counter overflows. Figure 14.24 Pulse Width Measurement Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 160 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions 15. Three-Phase Motor Control Timer Functions Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 15.1 lists specifications of the three-phase motor control timer functions. Table 15.2 lists pin settings. Figure 15.1 shows a block diagram. Figures 15.2 to 15.7 show registers associated with the three-phase control timer functions. Table 15.1 Three-Phase Motor Control Timer Functions Specification Item ___ ___ ___ _______ Specification Six pins (U, U, V, V, W, W) Apply a low-level signal ("L") to the NMI pin Timer A4, A1, A2 (used in one-shot timer mode) ___ Three-Phase Waveform Output Pin Forced Cutoff(1) Timers to be Used Timer A4: U- and U-phase waveform control ___ Timer A1: V- and V-phase waveform control ___ Timer A2: W- and W-phase waveform control Timer B2 (used in timer mode) Carrier wave cycle control Dead time timer (three 8-bit timers share reload register) Dead time control Output Waveform Triangular wave modulation, Sawtooth wave modification Can output a high-level waveform or a low-level waveform for one cycle Can set positive-phase level and negative-phase level separately Carrier Wave Cycle Triangular wave modulation: count source x (m+1) x 2 Sawtooth wave modulation: count source x (m+1) m: setting value of the TB2 register, 000016 to FFFF16 Count source: f1, f8, f2n(2), fc32 Three-Phase PWM Output Width Triangular wave modulation: count source x n x 2 Sawtooth wave modulation: count source x n n : setting value of the TA4, TA1 and TA2 register (of the TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to "1"), 000116 to FFFF16 Count source: f1, f8, f2n(2), fc32 Dead Time Count source x p, or no dead time p: setting value of the DTT register, 0116 to FF16 Count source: f1, or f1 divided by 2 Active Level Positive and Negative-Phase Concurrent Active Disable Function Interrupt Frequency Selected from a high level ("H") or low level ("L") Positive and negative-phases concurrent active disable function Positive and negative-phases concurrent active detect function For the timer B2 interrupt, one carrier wave cycle-to-cycle basis through 15 time- carrier wave cycle-to-cycle basis can be selected NOTES: _______ 1. Forced cutoff by the signal applied to the NMI pin is available when the INV02 bit is set to "1" (threephase motor control timer functions) and the INV03 bit is set to "1" (three-phase motor control timer output enabled). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 161 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Table 15.2 Pin Settings Pin PS1, PS2 Registers(1) Setting PSL1, PSL2 Registers PSC Register P72/V P73/V P74/W P75/W P80/U P81/U PS1_2 =1 PS1_3 =1 PS1_4 =1 PS1_5 =1 PS2_0 =1 PS2_1 =1 PSL1_2 =0 PSL1_3 =1 PSL1_4 =1 PSL1_5 =0 PSL2_0 =1 PSL2_1 =0 PSC_2 =1 PSC_3 =0 PSC_4 =0 NOTES: 1. Set the PS1_2 to PS1_5 and PS2_0 to PS2_1 bits in the PS1 and PS2 registers to "1" after the INV02 bit is set to "1". Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 162 of 488 INV13 ICTB2 Register n=1 to 15 INV03 DQ T R INV00 to INV07: Bits in INVC0 Register INV10 to INV15: Bits in INVC1 Register DUi, DUBi: Bits in IDBi Register (i=0,1) TA1S to TA4S: Bits in TABSR Register INV00 1 0 ICTB2 Counter n=1 to 15 Timer B2 Interrupt Request Bit RESET NMI INV01 INV11 Circuit to set Interrupt Generation Frequency Value to be written to INV03 bit Write signal to INV03 bit Timer B2 Underflow M32C/83 Group (M32C/83, M32C/83T) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 INV05 INV14 INV04 DQ T Inverse Control Reload Register n = 1 to 255 INV12 Trigger Trigger Dead Time Timer n = 1 to 255 INV02 Write Signal to Timer B2 INV10 INV07 f1 1/2 1 0 Timer B2 (Timer Mode) U Start Trigger Signal for Timers A1, A2, A4 INV06 U-phase Output Control Circuit Transfer Trigger(1) D Q D Q T T Figure 15.1 Three-Phase Motor Control Timer Functions Block Diagram Page 163 of 488 DU1 bit DU0 bit U-Phase Output Signal TA41 Register Timer A4 One-Shot Pulse DUB1 bit DUB0 bit U-Phase Output Signal Three-Phase Output Shift Register (U Phase) INV11 D Q D Q T T Reload Control Signal for Timer A4 TA4 Register Reload Trigger Timer A4 Counter (One-Shot Timer Mode) TQ DQ T Inverse Control U When setting the TA4S bit to "0", signal is set to "0" Trigger Trigger TA11 Register INV06 V-Phase Output Signal V-Phase Output Control Circuit INV11 V-Phase Output Signal Dead Time Timer n = 1 to 255 DQ T Inverse Control V TA1 Register Reload Trigger Timer A1 Counter Inverse Control DQ T V (One-Shot Timer Mode) TQ Trigger Trigger INV06 Inverse Control Dead Time Timer n = 1 to 255 DQ T When setting the TA1S bit to "0", signal is set to "0" W TA2 Register TA21 Register Reload Trigger W-Phase Output Signal W-Phase Output Signal DQ T Inverse Control Timer A2 Counter W-Phase Output Control Circuit W (One-Shot Timer Mode) INV11 TQ 15. Three-Phase Motor Control Timer Functions When setting the TA2S bit to "0", signal is set to "0" Switching to P80, P81 and P72 to P75 is not shown in this diagram. NOTES: 1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows, if the INV06 bit is set to "0" (triangular wave modulation). M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Three-Phase PWM Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC0 Bit Symbol Address 030816 After Reset 0016 Bit Name Function 0: The ICTB2 counter is incremented by one on the rising edge of the timer A1 reload control signal 1: The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 0: ICTB2 counter is incremented by one whenever the timer B2 counter underflows 1: Selected by the INV00 bit 0: No three-phase control timer functions 1: Three-phase control timer function 0: Disables three-phase control timer output 1: Enables three-phase control timer output 0: Enables concurrent active output 1: Disables concurrent active output 0: Not detected 1: Detected 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Transfer trigger is generated when the INV07 bit is set to "1". Trigger to the dead time timer is also generated when setting the INV06 bit to "1". Its value is "0" when read. RW Interrupt Enable Output INV00 Polarity Select Bit(3) Interrupt Enable Output Specification Bit(2, 3) RW INV01 RW INV02 Mode Select Bit(4, 5, 6) (6, 7) INV03 Output Control Bit RW RW Positive and NegativeINV04 Phases Concurrent Active Disable Function Enable Bit Positive and NegativeINV05 Phases Concurrent Active Output Detect Flag(8) INV06 Modulation Mode Select(9, 10) RW RW RW INV07 Software Trigger Select RW NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). Rewrite the INV00 to INV02 and INV06 bits when the timers A1,A2, A4 and B2 stop. 2. Set the INV01 bit to "1" after setting the ICTB2 register . 3. The INV00 and INV01 bits are enabled only when the INV11 bit is set to "1" (three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter underflows, regardless of INV00 and INV01 bit settings, when the INV11 bit is set to "0" (three-phase mode). When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflow. When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. 4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and the ICTB2 counter. 5. Set pins after the INV02 bit is set to "1". See Table 15.2 for pin settings. 6. When the INV02 bit is set to "1" and the INV03 bit to "0", U, U, V, V, W and W pins, including pins shared with other output functions, are placed in high-impedance states. 7. The INV03 bit is set to "0" when the followings occurs : - Reset - A concurrent active state occurs while INV04 bit is set to "1" - The INV03 bit is set to "0" by program - A signal applied to the NMI pin changes "H" to "L" 8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0". 9. The following table describes how the INV06 bit works. INV06 = 0 Triangular wave modulation mode Timing to Transfer from the IDB0 Transferred once by generating a and IDB1 Registers to Three-Phase transfer trigger after setting the IDB0 Output Shift Register and IDB1 registers Mode Timing to Trigger the Dead Time Timer when the INV16 Bit=0 INV13 Bit Item INV06 = 1 Sawtooth wave modulation mode Transferred every time a transfer trigger is generated On the falling edge of a one-shot pulse By a transfer trigger, or the falling edge of a one-shot pulse of the timer A1, A2 or A4 of the timer A1, A2 or A4 Enabled when the INV11 bit=1 and the Disabled INV06 bit=0 Transfer trigger : Timer B2 underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1 10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). Figure 15.2 INVC0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 164 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Three-Phase PWM Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC1 Bit Symbol Address 030916 After Reset 0016 Bit Name Timer A1, A2 and A4 Start Trigger Select Bit Timer A1-1, A2-1, A4-1 Control Bit(2, 3) Function 0: Timer B2 counter underflows 1: Timer B2 counter underflows and write to the TB2 register 0: Three-phase mode 0 1: Three-phase mode 1 RW RW INV10 INV11 RW INV12 Dead Time Timer 0 : f1 Count Source Select Bit 1 : f1 divided-by-2 Carrier Wave Detect Flag(4) RW INV13 0: Timer A1 reload control signal is "0" RO 1: Timer A1 reload control signal is "1" 0 : Active "L" of an output waveform 1 : Active "H" of an output waveform 0: Enables dead time 1: Disables dead time RW INV14 Output Polarity Control Bit INV15 Dead Time Disable Bit RW INV16 0: Falling edge of a one-shot pulse of Dead Time Timer Trigger the timer A1, A2, A4(5) RW 1: Rising edge of the three-phase output Select Bit shift register (U-, V-, W-phase) Reserved Bit Set to "0" RW (b7) NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). The timers A1, A2, A4, and B2 must be stopped during rewrite. 2. The following table lists how the INV11 bit works. Item Mode INV11 = 0 Three-phase mode 0 INV11 = 1 Three-phase mode 1 Used Enabled Enabled when INV11=1 and INV06=0 TA11, TA21 and TA41 Registers Not used INV00 and INV01 Bits in the INVC0 Register INV13 Bit Disabled. The ICTB2 counter is incremented whenever the timer B2 counter underflows Disabled 3. When the INV06 bit is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0" (threephase mode 0). Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). 4. The INV13 bit is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the INV11 bit to "1" (three-phase mode 1). 5. If the following conditions are all met, set the INV16 bit to "1". • The INV15 bit is set to "0" (dead time timer enabled) • The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit is set to "1". (The positive-phase and negative-phase always output opposite level signals.) If above conditions are not met, set the INV16 bit to "0". Figure 15.3 INVC1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 165 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Three-Phase Output Buffer Register i(1) (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset IDB0, IDB1 Bit Symbol DUi DUBi DVi DVBi DWi DWBi 030A16, 030B16 XX11 11112 Bit Name Function RW RW RW RW RW RW RW RO U-Phase Output Buffer i Write output level U-Phase Output Buffer i 0: Active level 1: Inactive level V-Phase Output Buffer i V-Phase Output Buffer i When read, the value of the threeW-Phase Output Buffer i phase shift register is read. W-Phase Output Buffer i Nothing is assigned. When write, set to "0". (b7 - b6) When read, its content is "0." NOTES: 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger. After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal first. Then the value written in the IDB1 register on the falling edge of timers A1, A2 and A4 oneshot pulse determines each phase output signal. Dead Time Timer(1, 2) b7 b0 Symbol DTT Address 030C16 After Reset Indeterminate Function If setting value is n, the timer stops when counting n times a count source selected by the INV12 bit after start trigger occurs. Positive or negative phase, which changes from inactive level to active level, shifts when the dead time timer stops. Setting Range RW 1 to 255 WO NOTES: 1. Use the MOV instruction to set the DTT register. 2. The DTT register is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06 bit in the INVC0 register determines start trigger of the DTT register. Figure 15.4 IDB0, IDB1 and DTT Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 166 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Timer B2 Interrupt Generation Frequency Set Counter(1, 2, 3) b7 b0 Symbol Address After Reset ICTB2 030D16 Function Indeterminate Setting Range RW When the INV01 bit is set to "0" (the ICTB2 counter increments whenever the timer B2 counter underflows) and the setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow occurs. When the INV01 bit is set to "1" (selected by the INV00 bit) and setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow meeting the condition selected in the INV00 bit occurs. Nothing is assigned. When write, set to "0". 1 to 15 WO NOTES: 1. Use the MOV instruction to set the ICTB2 register. 2. If the INV01 bit in the INVC0 register is set to "1", set the ICTB2 register when the TB2S bit is set to "0" (timer B2 counter stopped). If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2 register when the timer B2 counter underflows. 3. If the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, n being the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. Timer Ai, Ai-1 Register (i=1, 2, 4)(1, 2, 3, 4, 5, 6, 7) b15 b8 b7 b0 Symbol TA1, TA2, TA4 TA11, TA21, TA41 Address After Reset 034916 - 034816, 034B16 - 034A16, 034F16 - 034E16 Indeterminate 030316 - 030216, 030516 - 030416, 030716 - 030616 Indeterminate Function If setting value is n, the timer stops when the n th count source is counted after a start trigger is generated. Positive phase changes to negative phase, and vice versa, when the timers A1, A2 and A4 stop. Setting Range RW 000016 to FFFF16 WO NOTES: 1. Use a 16-bit data for read and write.. 2. If the TAi or TAi1 register is set to "000016", no counters start and no timer Ai interrupt is generated. 3. Use the MOV instruction to set the TAi and TAi1 registers. 4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an inactive level to an active level when the dead time timer stops. 5. When the INV11 bit is set to "0" (three-phase mode 0), the value of the TAi register is transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first transferred to the reload register by a timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to the reload register with every timer Ai start trigger. 6. Do not write to these registers when the timer B2 counter underflows. 7. Follow the procedure below to set the TAi1 register. (1) Write value to the TAi1 register. (2) Wait one timer Ai count source cycle. (3) Write the same value as (1) to the TAi1 register. Timer B2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TB2SC Bit Symbol PWCON 035E16 XXXX XXX02 Bit Name Timer B2 Reload Timing Switching Bit(1) Function 0 : Timer B2 underflow 1 : Timer A output in odd-number times RW RW Nothing is assigned. When write, set to "0". When read, its content is "0." NOTES: 1. When setting the INV11 bit to "0" (three-phase mode 0) or the INV06 bit to "1" (sawtooth wave modulation mode), set the PWCON bit to "0". Figure 15.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers and TB2SC Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 167 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Timer B2 Register(1) b15 b8 b7 b0 Symbol TB2 Address 035516 - 035416 After Reset Indeterminate Function If setting value is n, count source is divided by n+1. The timers A1, A2 and A4 start every time an underflow occurs. NOTES: 1. Use a 16-bit data for read and write. Setting Range 000016 to FFFF16 RW RW Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TRGSR Bit Symbol TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL 034316 0016 Bit Name Timer A1 Event/Trigger Select Bit Timer A2 Event/Trigger Select Bit Function Set to "012" (TB2 underflow) before using a V-phase output control circuit Set to "012" (TB2 underflow) before using a W-phase output control circuit b5 b4 RW RW RW RW RW RW RW RW RW Timer A3 Event/Trigger Select Bit TA3TGH TA4TGL TA4TGH Timer A4 Event/Trigger Select Bit 0 0 1 1 0 : Selects an input to the TA3IN pin 1 : Selects TB2 overflow(1) 0 : Selects TA2 overflow(1) 1 : Selects TA4 overflow(1) Set to "012" (TB2 underflow) before using a U-phase output control circuit NOTES: 1. Overflow or underflow Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TABSR Bit Symbol TA0S 034016 0016 Bit Name Timer A0 Count Start Flag Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag Function 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW TA1S RW TA2S RW TA3S RW TA4S RW TB0S TB1S RW RW TB2S RW Figure 15.6 TB2, TRGSR and TABSR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 168 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Timer Ai Mode Register (i=1, 2, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0 1 1 0 TA1MR, TA2MR, TA4MR Bit Symbol 035716, 035816, 035A16 0000 0X002 Bit Name Function Set to "102" (one-shot timer mode) with the three-phase motor control timer function RW RW TMOD0 Operation Mode TMOD1 Select Bit (b2) MR1 Nothing is assigned. When write, set to "0". Set to "0" with the three-phase motor RW control timer function Set to "1"(selected by the TRGSR register) with the threephase motor control timer function RW External Trigger Select Bit MR2 Trigger Select Bit MR3 Set to "0" with the three-phase motor control timer function b7 b6 RW TCK0 Count Source Select Bit TCK1 0 0 1 1 0 : f1 1 : f8 0 : f2n(1) 1 : fC32 RW RW NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Timer B2 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0 0 0 TB2MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 035D16 00XX 00002 Bit Name Function RW Set to "002" (timer mode) when using Operation Mode the three-phase motor control timer RW Select Bit function Disabled when using the three-phase motor control timer function. When write, set to "0". When read, its content is indeterminate. Set to "0" when using three-phase motor control timer function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 RW RW TCK0 Count Source Select Bit TCK1 0 0 1 1 0 : f1 1 : f8 0 : f2n(1) 1 : fC32 RW RW NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.7 TA1MR, TA2MR, TA4MR Registers and TB2MR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 169 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions The three-phase control timer function is available by setting the INV02 bit in the INVC0 register to "1". __ The timer B2 is used for carrier wave control and timers A4, A1, A2 for three-phase PWM output (U, U, V, __ ___ V, W, W) control. An exclusive dead time timer controls dead time. Figure 15.8 shows an example of the triangular modulation waveform. Figure 15.9 shows an example of the sawtooth modulation waveform. Triangular waveform as a Carrier Wave Triangular Wave Signal Wave TB2S Bit in TABSR Register Timer B2 Timer A1 Reload Control Signal(1) Timer A4 Start Trigger Signal(1) TA4 Register(2) TA41 Register(2) Reload Register(2) Timer A4 (1) One-Shot Pulse U-Phase Output Signal(1) U-Phase Output (1) Signal INV14 = 0 ("L" active) U-Phase U -Phase Dead time INV14 = 1 ("H" active) U-Phase Dead time U-Phase INV00, INV01: Bits in the INVC0 register INV11, INV14: Bits in the INVC1 register NOTES: 1. Internal signals. See Figure 15.1. 2. Applies only when the INV11 bit is set to "1" (three-phase mode). The above applies to INVC0 = 00XX11XX2 and INVC1 = 010XXXX02 (X varies depending on each system.) Examples of PWM output change are (b) When INV11=0 (three-phase mode 0) (a) When INV11=1 (three-phase mode 1) - INV01=0, ICTB2=116 (The timer B2 interrupt is generated - INV01=0 and ICTB2=216 (The timer B2 interrupt is whenever the timer B2 underflows) generated with every second timer B2 underflow) or - Default value of the timer: TA4=m INV01=1, INV00=1and ICTB2=116 (The timer B2 interrupt is The TA4 register is changed whenever the timer B2 generated on the falling edge of the timer A1 reload control interrupt is generated. signal) First time: TA4=m. Second time: TA4=n. - Default value of the timer: TA41=m, TA4=m Third time: TA4=n. Fourth time: TA=p. The TA4 and TA41 registers are changed whenever the Fifth time: TA4=p. timer B2 interrupt is generated. - Default value of the IDB0 and IDB1 registers: First time: TA41=n, TA4:=n. DU0=1, DUB0=0, DU1=0, DUB1=1 Second time: TA41=p, TA4=p. They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by - Default value of the IDB0 and IDB1 registers the sixth timer B2 interrupt. DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the third timer B2 interrupt. m m m m m m n n n n n n n p p p p p p q q q q q q r r r Rewrite the IDB0 and IDB1 registers Transfer a counter value to the three-phase shift register Figure 15.8 Triangular Wave Modulation Operation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 170 of 488 M32C/83 Group (M32C/83, M32C/83T) 15. Three-Phase Motor Control Timer Functions Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start Trigger Signal(1) Timer A4 One-Shot Pulse(1) Rewrite the IDB0 and IDB1 registers U-Phase Output (1) Signal U-Phase Output Signal(1) U-Phase INV14 = 0 ("L" active) Dead time U-Phase Transfer the counter to the three-phase shift register U-Phase INV14 = 1 ("H" active) U-Phase INV14: Bits in the INVC1 register NOTES: 1. Internal signals. See Figure 15.1. The above applies to INVC0 = 01XX110X2 and INVC1 = 010XXX002 (X varies depending on each system.) The examples of PWM output change are - Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt. Dead time Figure 15.9 Sawtooth Wave Modulation Operation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 171 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O 16. Serial I/O Serial I/O consists of five channels (UART0 to UART4). Each UARTi (i=0 to 4) has an exclusive timer to generate the transfer clock and operates independently. Figure 16.1 shows a UARTi block diagram. UARTi supports the following modes : - Clock synchronous serial I/O mode - Clock asynchronous serial I/O mode (UART mode) - Special mode 1 (I2C mode) - Special mode 2 - Special mode 3 (Clock-divided synchronous function, GCI mode) - Special mode 4 (Bus conflict detect function, IE mode) - Special mode 5 (SIM mode) Figures 16.2 to 16.9 show registers associated with UARTi. Refer to the tables listing each mode for register and pin settings. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 172 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O RxDi RxD Polarity Switching Circuit Selecting Clock Source 00 CKDIR f1 Inside 01 0 f8 10 f2n(2) CLK1 to CLK0 1 Outside UiBRG Register 1 / (m+1) Clock Asynchronous Receive SMD2 to SMD0 010, 100, 101, 110 1/16 Receive 001 Control Circuit Clock Synchronous Type Clock Asynchronous Transmit 1/16 Receive Clock TxD Polarity Switching Circuit Transmit/ Receive Unit (Note 1) TxDi CKPOL CLK Polarity Switching Circuit Transmit 010, 100, 101, 110 Control Circuit Clock Synchronous Type 001 Clock Synchronous Type (when internal clock is selected) 1/2 0 1 Clock Synchronous CKDIR Clock Synchronous Type (when internal clock is selected) Type (when external clock is selected) CTS/RTS disabled CRD RTSi Transmit Clock CLKi CTSi / RTSi CTS/RTS selected 1 CRS 0 CTS/RTS disabled 0 CRD 1 Vss CTSi m : setting value of UiBRG register NOTES: 1. P70 and P71 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 0 RxDi RxD Data Inverse Circuit 1 IOPOL No inverse Inverse Clock Synchronous Type Clock Asynchronous Type (7 bits) Clock Clock Asynchronous Asynchronous Type (7 bits) Type (8 bits) STPS 1SP 0 PRYE Clock PAR disabled Synchronous Type 0 UARTi Receive Register 0 0 SP 1 2SP SP PAR Clock 1 Asynchronous PAR enabled Type SMD2 to SMD0 1 Clock Asynchronous Type (9 bits) Clock 1 Synchronous Type Clock Asynchronous Type (8 bits) Clock Asynchronous Type (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB Register Logic Inverse Circuit + MSB/LSB Conversion Circuit High-order bits of data bus Low-order bits of data bus Logic Inverse Circuit + MSB/LSB Conversion Circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB Register Clock Asynchronous Type (8 bits) Clock Asynchronous Type (9 bits) Clock Synchronous Type PRYE STPS SMD2 to SMD0 2SP 1 Clock PAR enabled Asynchronous Type 1 1 Clock Asynchronous Type (9 bits) 1 1 SP SP 0 1SP PAR 0 Clock PAR Synchronous disabled Type 0 0 Clock Asynchronous Type (7 bits) Clock Asynchronous Type (8 bits) Clock Synchronous Type 0 Clock Asynchronous Type (7 bits) UARTi Transmit Register Error Signal Output disable 0 Error Signal Output Circuit 1 Error Signal Output enable IOPOL 0 No inverse TxD Data Inverse Circuit TxDi SP: Stop bit PAR: Parity bit i=0 to 4 SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register UiERE: Bit in UiC1 register UiERE 1 Inverse Figure 16.1 UARTi Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 173 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Transmit Buffer Register (i=0 to 4)(1) b15 b8 b7 b0 Symbol Address U0TB to U2TB 036B16-036A16, 02EB16-02EA16, 033B16-033A16 U3TB, U4TB 032B16-032A16, 02FB16-02FA16 Bit Symbol After Reset Indeterminate Indeterminate Function RW WO WO (b7 - b0) Transmit data (D7 to D0) Transmit data (D8) (b8) Nothing is assigned. When write, set to "0". (b15 - b9) When read, its content is indeterminate. NOTES: 1. Use the MOV instruction to set the UiTB register. UARTi Receive Buffer Register (i=0 to 4) b15 b8 b7 b0 Symbol Address U0RB to U2RB 036F16 - 036E16, 02EF16 - 02EE16, 033F16 - 033E16 U3RB, U4RB 032F16 - 032E16, 02FF16 - 02FE16 Bit Symbol After Reset Indeterminate Indeterminate Bit Name Function Received data (D7 to D0) RW RO RO (b7 - b0) (b8) Received data (D8) Nothing is assigned. When write, set to "0". (b10 - b9) When read, its content is indeterminate. ABT Arbitration Lost Detect Flag(1) 0: Not detected (win) 1: Detected (lose) RW RO RO RO RO OER FER 0: No overrun error occurs Overrun Error Flag(2) 1: Overrun error occurs Framing Error Flag(2, 3) Parity Error Flag(2, 3) Error Sum Flag(2, 3) 0: No framing error occurs 1: Framing error occurs 0: No parity error occurs 1: Parity error occurs 0: No error occurs 1: Error occurs PER SUM NOTES: 1. The ABT bit can be set to "0" only. 2. When the SMD2 to SMD0 bits in the UiMR register is set to "0002" (serial I/O disable) or the RE bit in the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0" (no error occurs). When all OER, FER and PER bits are set to "0" (no error), the SUM bit is set to "0" (no error). Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register. 3. These error flags are disabled when the SMD2 to SMD0 bits in the UiMR register are set to "0012" (clock synchronous serial I/O mode, special mode 2, or special mode 3) or to "0102" (I2C mode). When read, the contents are indeterminate. Figure 16.2 U0TB to U4TB Registers and U0RB to U4RB Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 174 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Baud Rate Register (i=0 to 4)(1, 2, 3) b7 b0 Symbol Address After Reset Indeterminate U0BRG to U4BRG 036916, 02E916, 033916, 032916, 02F916 Function If the setting value is m, the UiBRG register divides a count source by m+1 Setting Range 0016 to FF16 RW WO NOTES: 1. Use the MOV instruction to set the UiBRG register. 2. Set the UiBRG register data transmit and receive is stopped. 3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 register. UARTi Transmit/Receive Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0MR to U4MR Bit Symbol Address 036816, 02E816, 033816, 032816, 02F816 After Reset 0016 Bit Name b2 b1 b0 Function RW SMD0 SMD1 SMD2 0 0 0: Serial I/O disabled RW 0 0 1: Clock synchronous serial I/O mode 2 Serial I/O Mode Select 0 1 0: I C mode RW 1 0 0: UART mode, 7-bit transfer data Bit 1 0 1: UART mode, 8-bit transfer data 1 1 0: UART mode, 9-bit transfer data RW Do not set value other than the above Internal/External Clock 0 : Internal clock Select Bit 1 : External clock Stop Bit Length Select 0 : 1 stop bit Bit 1 : 2 stop bits Odd/Even Parity Select Enables when PRYE = 1 0 : Odd parity Bit 1 : Even parity Parity Enable Bit 0 : Disables a parity 1 : Enables a parity RW RW CKDIR STPS PRY RW PRYE RW IOPOL TxD,RxD Input/Output 0: Not inversed Polarity Switch Bit 1: Inverse RW Figure 16.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 175 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Transmit/Receive Control Register 0 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C0 to U4C0 Bit Symbol Address 036C16, 02EC16, 033C16, 032C16, 02FC16 After Reset 0000 10002 Bit Name b0 b1 Function RW RW CLK0 CLK1 0 0: Selects f1 UiBRG Count 0 1: Selects f8 (4) Source Select Bit 1 0: Selects f2n(2) 1 1: Do not set to this value CST/RTS Function Enabled when CRD=0 0 : Selects CTS function Select Bit 1 : Selects RTS function Transmit Register Empty Flag CTS/RTS Disable Bit 0 : Data in the transmit register (during transmission) 1 : No data in the transmit register (transmission is completed) 0 : Enables CTS/RTS function 1 : Disables CTS/RTS function RW CRS RW TXEPT RO CRD RW NCH 0 : TxDi/SDAi and SCLi are ports for the Data Output Select CMOS output 1 : TxDi/SDAi and SCLi are ports for the Bit(1) N-channel open drain output RW CKPOL CLK Polarity Select Bit 0 : Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge RW 1 : Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge 0 : LSB first 1 : MSB first RW UFORM Transfer Format Select Bit(3) NOTES: 1. P70/TxD2 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 3. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "0012" (clock synchronous serial I/O mode), or "1012" (UART mode, 8-bit transfer data). Set this bit to "1" when the SMD2 to SMD0 bits are set to "0102" (I2C mode), and to "0" when the SMD2 to SMD0 bits are set to "1002"(UART mode, 7-bit transfer data) or "1102"(UART mode, 9-bit transfer data). 4. If the CLK1 and CLK0 bits are changed, set the UiBRG register. Figure 16.4 U0C0 to U4C0 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 176 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Transmit/Receive Control Register 1 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C1 to U4C1 Bit Symbol Address 036D16, 02ED16, 033D16, 032D16, 02FD16 After Reset 0000 00102 Bit Name Transmit Enable Bit Function 0: Transmit disable 1: Transmit enable RW RW RO RW TE TI RE Transmit Buffer 0: Data in the UiTB register 1: No data in the UiTB register Empty Flag Receive Enable Bit Receive Complete Flag 0: Receive disable 1: Receive enable 0: No data in the UiRB register 1: Data in the UiRB register RI RO UiIRS UARTi Transmit 0: No data in the UiTB register (TI = 1) Interrupt Cause 1: Transmission is completed (TXEPT = 1) Select Bit UARTi Continuous Receive Mode Enable Bit Data Logic Select Bit RW UiRRM 0: Disables continuous receive mode to be entered RW 1: Enables continuous receive mode to be entered 0: Not inversed 1: Inverse RW UiLCH Clock-Divided Synchronous SCLKSTPB Stop Bit / /UiERE Error Signal Output Enable Bit(1) Clock-divided synchronous stop bit (special mode 3) 0: Stops synchronizing 1: Starts synchronizing RW Error signal output enable bit (special mode 5) 0: Not output 1: Output NOTES: 1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register. 2. The UiLCH bit is enabled when the SMD2 to SMD0 bits are set to "0012" (clock synchronous serial I/O mode), "1002"(UART mode, 7-bit transfer data), or "1012" (UART mode, 8-bit transfer data). Set this bit to "0" when the SMD2 to SMD0 bits are set to "0102" (I2C mode) or "1102"(UART mode, 9-bit transfer data) UARTi Special Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR to U4SMR Bit Symbol Address 036716, 02E716, 033716, 032716, 02F716 After Reset 0016 Bit Name I2C Mode Select Bit Function 0: Except I2C mode 1: I2C mode RW RW RW RW(1) RW RW IICM ABC BBS LSYN ABSCS Arbitration Lost Detect 0: Update per bit Flag Control Bit 1: Update per byte Bus Busy Flag SCLL Sync Output Enable Bit 0: Stop condition detected 1: Start condition detected (Busy) 0: Disabled 1: Enabled Bus Conflict Detect 0: Rising edge of transfer clock Sampling Clock Select Bit 1: Timer Aj underflow(2) Auto Clear Function Select 0: No auto clear function Bit for Transmit Enable Bit 1: Auto clear at bus conflict Transmit Start Condition Select Bit Clock Divide Synchronous Bit 0: Not related to RxDi 1: Synchronized with RxDi (Note 3) ACSE SSS SCLKDIV RW RW RW NOTES: 1. The BBS bit is set to "0" by program. It is unchanged if set to "1". 2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal, UART3: timer A3 underflow signal, UART4: timer A4 underflow signal. 3. Refer to notes for the SU1HIM bit in the UiSMR2 register. Figure 16.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 177 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Special Mode Register 2 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR2 to U4SMR2 Bit Symbol Address 036616, 02E616, 033616, 032616, 02F616 After Reset 0000 00002 Bit Name I2C Mode Select Bit 2 (Note 1) Function RW RW RW IICM2 CSC Clock Synchronous Bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Output 1: No output 0: Disabled 1: Enabled 0: Transfer clock 1: 0 output 0: Output 1: No output (high-impedance) (Note 2) SWC SCL Wait Output Bit RW ALS SDA Output Stop Bit RW STC UARTi Initialize Bit RW SWC2 SCL Wait Output Bit 2 RW SDHI SDA Output Inhibit Bit External Clock Synchronous Enable Bit RW SU1HIM RW NOTES: 1. Refer to 16.3 Special mode 1 (I2C Mode). 2. The external clock synchronous function can be selected by combining the SU1HIM bit and the SCLKDIV bit in the UiSMR register. SCLKDIV bit in the UiSMR Register 0 0 1 SU1HIM bit in the UiSMR2 Register 0 1 0 or 1 External Clock Synchronous Function Selection No synchronization Same division as the external clock External clock divided by 2 Figure 16.6 U0SMR2 to U4SMR2 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 178 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Special Mode Register 3 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR3 to U4SMR3 Bit Symbol Address 036516, 02E516, 033516, 032516, 02F516 After Reset 0016 Bit Name Function RW RW RW SSE CKPH SS Pin Function Enable Bit(1) Clock-Phase Set Bit Serial Input Port Set Bit Clock Output Select Bit Fault Error Flag(2) 0: Disables SS pin function 1: Enables SS pin function 0: No clock delay 1: Clock delay 0: Selects the TxDi and RxDi pins (master mode) 1: Selects the STxDi and SRxDi pins (slave mode) 0: CMOS output 1: N-channel open drain output 0: No error 1: Error b7 b6 b5 DINC RW NODC ERR RW RW DL0 SDAi Digital Delay Time Set Bit(3, 4) DL1 DL2 000 : No delay 001 : 1-to-2 cycles of BRG count source 010 : 2-to-3 cycles of BRG count source 011 : 3-to-4 cycles of BRG count source 100 : 4-to-5 cycles of BRG count source 101 : 5-to-6 cycles of BRG count source 110 : 6-to-7 cycles of BRG count source 111 : 7-to-8 cycles of BRG count source RW RW RW NOTES: 1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled). 2. The ERR bit is set to "0" by program. It is unchanged if set to "1". 3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I2C mode. Set these bits to "0002" (no delay) except in the I2C mode. 4. When the external clock is selected, approximately 100ns delay is added. Figure 16.7 U0SMR3 to U4SMR3 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 179 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O UARTi Special Mode Register 4 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR4 to U4SMR4 Bit Symbol Address 036416, 02E416, 033416, 032416, 02F416 After Reset 0016 Bit Name Start Condition Generate Bit(1) Restart Condition Generate Bit(1) Stop Condition Generate Bit(1) SCL, SDA Output Select Bit ACK Data Bit ACK Data Output Enable Bit SCL Output Stop Enable Bit SCL Wait Output Bit 3 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start Function RW RW STAREQ RSTAREQ RW STPREQ RW STSPSEL 0: Selects the serial I/O circuit 1: Selects the start/stop condition generation circuit 0: ACK 1: NACK 0: Serial I/O data output 1: ACK data output 0: Disabled 1: Enabled 0: SCL "L" hold disabled 1: SCL "L" hold enabled RW ACKD RW ACKC RW SCLHI RW SWC9 RW NOTES: 1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to "0". When a condition generation is incomplete, the bit remains unchanged as "1". Figure 16.8 U0SMR4 to U4SMR4 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 180 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O External Interrupt Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit Symbol Address 031F16 After Reset 0016 Bit Name INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit(1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity Select Bit(1) INT5 Interrupt Polarity Select Bit(1) Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges RW RW IFSR0 IFSR1 RW IFSR2 RW IFSR3 RW IFSR4 RW IFSR5 RW IFSR6 UART0, UART3 Interrupt Cause Select Bit 0 : UART3 bus conflict, start condition detect, stop condition detect, fault error detect RW 1 : UART0 bus conflict, start condition detect, stop condition detect, fault error detect IFSR7 0 : UART4 bus conflict, start condition detect, stop condition detect, fault UART1, UART4 error detect RW Interrupt Cause Select 1 : UART1 bus conflict, start condition detect, stop condition detect, fault Bit error detect NOTES: 1.Set this bit to "0" to select level sensitive. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). Figure 16.9 IFSR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 181 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Clock Synchronous Serial I/O) 16.1 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 16.1 lists specifications of clock synchronous serial I/O mode. Table 16.2 lists registers to be used and settings. Tables 16.3 to 16.5 list pin settings. When UARTi (i=0 to 4) operation mode is selected, the TxDi pin outputs an "H" signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 16.10 shows transmit and receive timings in clock synchronous serial I/O mode. Table 16.1 Clock Synchronous Serial I/O Mode Specifications Item Transfer Data Format Transfer Clock Specification • Transfer data : 8 bits long • The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected): fj 2(m+1) fj=f1, f8, f2n(1) m :setting value of the UiBRG register 0016 to FF16. Transmit/Receive Control Transmit Start Condition • The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin _______ _______ _______ _______ • Selected from the CTS function, RTS function or CTS/RTS function disabled • To start transmitting, the following requirements must be met(2): - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) ________ _______ - Apply an "L" signal to the CTSi pin when the CTS function is selected Receive Start Condition • To start receiving, the following requirements must be met(2): - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit to "1" (transmit enable) - Set the TI bit to "0" (data in the UiTB register) Interrupt Request Generation Timing • Transmit interrupt timing can be selected from the followings: - The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed) : when a data transfer from the UARTi transmit register is completed • Receive interrupt timing Error Detect When data is transferred from the UARTi receive register to the UiRB register (reception completed) • Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register Selectable Function • CLK polarity Transferred data is output and input on either the rising edge or falling edge of the transfer clock • LSB first / MSB first Data is transmitted or received in either bit 0 or in bit 7 • Continuous receive mode Data can be received simultaneously by reading the UiRB register • Serial data logic inverse This function inverses transmitted or received data logically NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L"). 3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 182 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Clock Synchronous Serial I/O) Table 16.2 Registers to be Used and Setting Value in Clock Synchronous Serial I/O Mode Register UiTB UiRB UiBRG UiMR Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiLCH SCLKSTPB UiSMR UiSMR2 UiSMR3 0 to 7 0 to 7 0 to 2 NODC 4 to 7 UiSMR4 i=0 to 4 0 to 7 Set transmit data Received data can be read Overrun error flag Set bit rate Set to "0012" Select the internal clock or external clock Set to "0" Select count source for the UiBRG register _______ _______ Function Select CTS or RTS when using either Transmit register empty flag _______ _______ Enables or disables the CTS or RTS function Select output format of the TxDi pin Select transmit clock polarity Select either LSB first or MSB first Set to "1" to enable data transmission and reception Transmit buffer empty flag Set to "1" to enable data reception Reception complete flag Select how the UARTi transmit interrupt is generated Set to "1" when using continuous receive mode Set to "1" when using data logic inverse Set to "0" Set to "0016" Set to "0016" Set to "0002" Select clock output format Set to "00002" Set to "0016" Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 183 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Clock Synchronous Serial I/O) Table 16.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) Port P60 P61 P62 P63 P64 P65 P66 P67 Function PS0 Register __________ Setting PSL0 Register PSL0_4=0 PD6 Register PD6_0=0 PD6_1=0 PD6_2=0 PD6_4=0 PD6_5=0 PD6_6=0 PS0_0=0 PS0_0=1 PS0_1=0 PS0_1=1 PS0_2=0 PS0_3=1 PS0_4=0 PS0_4=1 PS0_5=0 PS0_5=1 PS0_6=0 PS0_7=1 CTS0 input __________ RTS0 output CLK0 input CLK0 output RxD0 input TxD0 output __________ CTS1 input _________ RTS1 output CLK1 input CLK1 output RxD1 input TxD1 output Table 16.4 Pin Settings (2) Port P70(1) P71(1) P72 P73 Function PS1 Register TxD2 output RxD2 input CLK2 input CLK2 output __________ Setting PSL1 Register PSL1_0=0 PSL1_2=0 PSL1_3=0 PSC Register PSC_0=0 PSC_2=0 PSC_3=0 PD7 Register PD7_1=0 PD7_2=0 PD7_3=0 PS1_0=1 PS1_1=0 PS1_2=0 PS1_2=1 PS1_3=0 PS1_3=1 CTS2 input __________ RTS2 output NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.5 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 Function PS3 Register(1) CLK3 input CLK3 output RxD3 input TxD3 output __________ Setting PSL3 Register PSL3_2=0 PSL3_3=0 PSL3_4=0 PSL3_5=0 PD9 Register(1) PD9_0=0 PD9_1=0 PD9_3=0 PD9_4=0 PD9_5=0 PD9_7=0 PS3_0=0 PS3_0=1 PS3_1=0 PS3_2=1 PS3_3=0 PS3_3=1 PS3_4=0 PS3_4=1 PS3_5=0 PS3_5=1 PS3_6=1 PS3_7=0 CTS3 input __________ RTS3 output __________ CTS4 input __________ RTS4 output CLK4 input CLK4 output TxD4 output RxD4 input NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 184 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Clock Synchronous Serial I/O) (1) Transmit Timing (Internal clock selected) Tc Transfer Clock "1" "0" "1" "0" Data is transferred from the UiTB register to the UARTi transmit register "H" Data is set in the UiTB register TE bit in UiC1 register TI bit in UiC1 register CTSi "L" TCLK Pulse stops because CTSi = H Pulse stops because TE bit = 0 CLKi TxDi TXEPT bit in UiC0 register IR bit in SiTIC register "1" "0" "1" "0" D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 Set to "0" by an interrupt request acknowledgement or by program The above applies to the following settings: TC=2(m+1)/fj • The CKDIR bit in the UiMR register is set to "0" (internal clock selected) fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1)) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) m : Setting value of the UiBRG register The CRS bit is set to "0" (CTS function selected) i = 0 to 4 • The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the NOTES: falling edge of the transfer clock) 1. The CNT3 to CNT0 bits in the TCSPR register select no division ( • The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register) n=0) or divide-by-2n (n=1 to 15). (2) Receive Timing (External clock selected) RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register RTSi "1" "0" "1" "0" "1" "0" Dummy data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register "H" "L" 1 / fEXT Becomes "L" when the UiRB register is read CLKi Received data is taken in RxDi RI bit in UiC1 register IR bit in SiRIC register "1" "0" "1" "0" D0 D1 D2 D3 D4 D 5 D6 D7 D 0 D1 D2 D3 D 4 D 5 D6 Read by the UiRB register D7 D0 D1 D2 D 3 D4 D 5 D6 Data transferred from UARTi register to UiRB register Set to "0" by an interrupt request acknowledgement or by program OER bit in UiRB register "1" "0" The above applies to the following settings: • The CKDIR bit in the UiMR register is set to "1" (external clock selected) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "1" (RTS function selected) • The CKPOL bit in the UiC0 register is set to "0" (Data is received on the rising edge of the transfer clock) fEXT: External clock frequency i=0 to 4 Meet the following conditions while "H" is applied to the CLKi pin before receiving data: • Set the TE bit in the UiC1 register to "1" (transmit enable) • Set the RE bit in the UiC1 register to "1" (receive enable) • Write dummy data to the UiTB register Figure 16.10 Transmit and Receive Operation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 185 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Clock Synchronous Serial I/O) 16.1.1 Selecting CLK Polarity As shown in Figure 16.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the transfer clock. (1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0" (Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 NOTES: 1. The CLKi pin is held high ("H") when no data is transferred. 2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). (2) When the CKPOL bit in the UiC0 register is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 NOTES: 3. The CLKi pin is held low ("L") when no data is transferred. 4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). Figure 16.11 Transfer Clock Polarity 16.1.2 Selecting LSB First or MSB First As shown in Figure 16.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format. (1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0" (LSB first) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). (2) When the UFORM bit in the UiC0 register is set to "1" (MSB first) CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 NOTES: 2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). Figure 16.12 Transfer Format Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 186 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Clock Synchronous Serial I/O) 16.1.3 Continuous Receive Mode When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set dummy data in the UiTB register by program. 16.1.4 Serial Data Logic Inverse When the UiLCH bit in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 16.13 shows a switching example of the serial data logic. (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed) Transfer clock TxDi "H" "L" "H" (no inverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) Transfer clock TxDi "H" "L" "H" (inverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge) and the UFORM bit in the UiC register is set to "0" (LSB first). Figure 16.13 Serial Data Logic Inverse Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 187 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) 16.2 Clock Asynchronous Serial I/O (UART) Mode In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format. Table 16.6 lists specifications of UART mode. Table 16.6 UART Mode Specifications Item Transfer Data Format Specification • Character bit (transfer data ) : selected from 7 bits, 8 bits, or 9 bits long • Start bit: 1 bit long • Parity bit: selected from odd, even, or none Transfer Clock • Stop bit: selected from 1 bit or 2 bits long • The CKDIR bit in the UiMR register is set to "0" (internal clock selected) : fj/16(m+1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register 0016 to FF16 • The CKDIR bit is set to "1" (external clock selected) : fEXT/16(m+1) fEXT: clock applied to the CLKi pin _______ _______ _______ _______ Transmit/Receive Control • Select from CTS function, RTS function or CTS/RTS function disabled Transmit Start Condition • To start transmitting, the following requirements must be met: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) _______ _______ - Apply an "L" signal to the CTSi pin when the CTS function is selected Receive Start Condition • To start receiving, the following requirements must be met: - Set the RE bit in the UiC1 register to "1" (receive enable) - The start bit is detected • Transmit interrupt timing can be selected from the followings: - The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed) : when data transmission from the UARTi transfer register is completed • Receive interrupt timing Error Detect when data is transferred from the UARTi receive register to the UiRB register (reception completed) • Overrun error(2) This error occurs when the bit before the last stop bit of the next received data is read prior to reading the UiRB register (the first stop bit when selecting 2 stop bits) • Framing error This error occurs when the number of stop bits set is not detected • Parity error When parity is enabled, this error occurs when the number of "1" in parity and character bits does not match the number of "1" set • Error sum flag Selectable Function This flag is set to "1" when any of an overrun, framing or parity errors occur • LSB first / MSB first Data is transmitted or received in either bit 0 or in bit 7 •Serial data logic inverse Logic values of data to be transmitted or received data are inversed. The start bit and stop bit are not inversed •TxD, RxD I/O polarity switching TxD pin output and RxD pin input are inversed NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged as "1" (interrupt requested). Interrupt Request Generation Timing Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 188 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) Table 16.7 lists registers to be used and settings. Tables 16.8 to 16.10 list pin settings. When UARTi (i=0 to 4) operation mode is selected, the TxDi pin outputs an "H" signal before transfer is started (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 16.14 shows an example of a transmit operation in UART mode. Figure 16.15 shows an example of a receive operation in UART mode. Table 16.7 Registers to be Used and Settings in UART Register UiTB UiRB 0 to 8 0 to 8 OER, FER, PER, SUM UiBRG UiMR 0 to 7 SMD2 to SMD0 Set bit rate Set to "1002" when transfer data is 7 bits long Set to "1012" when transfer data is 8 bits long Set to "1102" when transfer data is 9 bits long CKDIR STPS PRY, PRYE IOPOL UiC0 CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiLCH UiERE UiSMR UiSMR2 UiSMR3 UiSMR4 NOTES: 1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long. 0 to 7 0 to 7 0 to 7 0 to 7 Select the internal clock or external clock Select stop bit length Select parity enable or disable, odd or even Select TxD / RxD I/O polarity Select count source for the UiBRG register _______ _______ Bit Set transmit data(1) Received data can be read(1) Error flags Function Select either CTS or RTS when using either Transfer register empty flag ________ _______ Enables or disables the CTS or RTS function Select output format of the TxDi pin Set to "0" Select the LSB first or MSB first when a transfer data is 8 bits long Set to "0" when transfer data is 7 bits or 9 bits long Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select how the UARTi transmit interrupt is generated Set to "0" Select whether or not data logic is inversed when transfer data length is 7 or 8 bits. Set to "0" when transfer data length is 9 bits. Set to either "0" or "1" Set to "0016" Set to "0016" Set to "0016" Set to "0016" Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 189 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) Table 16.8 Pin Settings in UART (1) Port P60 P61 P62 P63 P64 P65 P66 P67 Function PS0 Register __________ Setting PSL0 Register – – – – – – PSL0_4=0 – – – PD6 Register PD6_0=0 – PD6_1=0 PD6_2=0 – PD6_4=0 – PD6_5=0 PD6_6=0 – PS0_0=0 PS0_0=1 PS0_1=0 PS0_2=0 PS0_3=1 PS0_4=0 PS0_4=1 PS0_5=0 PS0_6=0 PS0_7=1 CTS0 input __________ RTS0 output CLK0 input RxD0 input TxD0 output __________ CTS1 input __________ RTS1 output CLK1 input RxD1 input TxD1 output Table 16.9 Pin Settings (2) Port P70(1) P71(1) P72 P73 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Function PS1 Register TxD2 output RxD2 input CLK2 input __________ Setting PSL1 Register PSL1_0=0 – – – PSL1_3=0 PSC Register PSC_0=0 – – – PSC_3=0 PD7 Register – PD7_1=0 PD7_2=0 PD7_3=0 – PS1_0=1 PS1_1=0 PS1_2=0 PS1_3=0 PS1_3=1 CTS2 input __________ RTS2 output Table 16.10 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 NOTES: 1. Set the PD9 and PS3 registers set immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Function PS3 CLK3 input RxD3 input TxD3 output __________ Setting Register(1) PSL3 Register – – PSL3_2=0 PSL3_3=0 – PSL3_4=0 – PSL3_5=0 – – PD9 Register(1) PD9_0=0 PD9_1=0 – PD9_3=0 – PD9_4=0 – PD9_5=0 – PD9_7=0 PS3_0=0 PS3_1=0 PS3_2=1 PS3_3=0 PS3_3=1 PS3_4=0 PS3_4=1 PS3_5=0 PS3_6=1 PS3_7=0 CTS3 input __________ RTS3 output __________ CTS4 input __________ RTS4 output CLK4 input TxD4 output RxD4 input Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 190 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) (1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin, when the stop bit state is verified. The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin Tc Transfer Clock TE bit in UiC1 register TI bit in UiC1 register "1" "0" "1" "0" Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register "H" CTSi "L" Start bit TxDi TXEPT bit in UiC0 "1" register "0" "1" "0" Parity bit P SP Stop bit Pulse stops because the TE bit is set to "0" P SP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 IR bit in SiTIC register Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above timing applies under the following conditions: • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) • The CRD bit in the UiC0 register is set to "0" and the CRS bit is set to "0" (CTS function selected) • The UilRS bit in the UiC1 register is set to "1" (transmission completed) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj: count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT: count source frequency set in the UiBRG register (external clock) m: setting value of the UiBRG register NOTE: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (2) 9-bit Data Transmit Timing (with no parity and 2 stop bits) Tc Transfer Clock TE bit in UiC1 register TI bit in UiC1 register "1" "0" "1" "0" Data is set in the UiTB register Start bit TxDi TXEPT bit in UiC0 register "0" IR bit in SiTIC register "1" "0" "1" Data is transferred from the UiTB register to the UARTi transmit register Stop Stop bit bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above timing applies under the following conditions: • The PRYE bit in the UiMR register is set to "0" (parity disabled) • The STPS bit in the UiMR register is set to "1" (2 stop bits) • The CRD bit in the UiC0 register is set to "1" (CTS function disabled) • The UilRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj: count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT: count source frequency set in the UiBRG register (external clock) m: setting value of the UiBRG register NOTE: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 16.14 Transmit Operation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 191 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) 8-bit Data Reception Timing (with no parity and 1 stop bit) Count Source set in UiBRG register RE bit in UiC1 register RxDi "1" "0" Start bit Determine if it is "L" Transfer Clock RI bit in UiC1 register RTSi IR bit in SiRIC register Data is transferred from the URTi receive Start receiving when the transfer clock is "1" generated on the falling edge of the start bit register to the UiRB register "0" "H" "L" "1" "0" Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 NOTES: 1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled), the SRPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set to "1" (RTS function selected). Stop bit D0 D1 D7 Capture a received data Change to "L" by reading the UiRB register Figure 16.15 Receive Operation 16.2.1 Bit Rate In UART mode, bit rate is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4) register and again divided by 16. Table 16.11 lists an example of bit rate setting. Table 16.11 Bit Rate Count Source of UiBRG f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Function Clock: 16MHz Setting Value of UiBRG: n 103 (67h) 51 (33h) 25 (19h) 103 (67h) 68 (44h) 51 (33h) 34 (22h) 31 (1Fh) 25 (19h) 19 (13h) Actual Bit Rate (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000 Peripheral Function Clock: 24MHz Setting Value of UiBRG: n 155 (96h) 77 (46h) 38 (26h) 155 (96h) 103 (67h) 77 (46h) 51 (33h) 47 (2Fh) 38 (26h) 28 (1Ch) Actual Bit Rate (bps) 1202 2404 4808 9615 14423 19231 28846 31250 38462 51724 Peripheral Function Clock: 32MHz Setting Value of UiBRG: n 207 (CFh) 103 (67h) 51 (33h) 207 (CFh) 138 (8Ah) 103 (67h) 68 (44h) 63 (3Fh) 51 (33h) 38 (26h) Actual Bit Rate (bps) 1202 2404 4808 9615 14388 19231 28986 31250 38462 51282 Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 192 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) 16.2.2 Selecting LSB First or MSB First As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format. This function is available for 8-bit transfer data. (1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first) CLKi TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first) CLKi TxDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP RxDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP ST : Start bit P : Parity bit SP : Stop bit NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (no inverse). Figure 16.16 Transfer Format 16.2.3 Serial Data Logic Inverse After the UiLCH bit in the UiC1 register is set to "1", data logic is inversed when writing to the UiTB register (i=0 to 4) and reading from the UiRB register. Figure 16.17 shows a switching example of the serial data logic. (1) When the UiLCH bit in the UiC1 register (i=0 to 4) = 0 (no inverse) Transfer Clock TxDi (no inverse) “H” “L” “H” “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) When the UiLCH bit in the UiC1 register = 1 (inverse) Transfer Clock TxDi “H” “L” “H” (inverse) “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP NOTES: 1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). Figure 16.17 Serial Data Logic Inverse Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 193 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (UART) 16.2.4 TxD and RxD I/O Polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity bit, are inversed. Figure 16.18 shows TxD and RxD I/O polarity inverse. (1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse) Transfer Clock “H” “L” TxDi “H” (no inverse) “L” RxDi “H” ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (no inverse) “L” (2) When the IOPOL bit in the UiMR register is set to "1" ( inverse) Transfer Clock TxDi RxDi “H” “L” “H” (inverse) “L” “H” ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP ST : Start bit P : Even parity SP : Stop bit (inverse) “L” NOTES: 1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). Figure 16.18 TxD, RxD I/O Polarity Inverse Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 194 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.3 Special Mode 1 (I2C Mode) I2C mode is a mode to communicate with external devices with a simplified I2C . Table 16.12 lists specifications of I2C mode. Table 16.13 lists registers to be used and settings, Table 16.14 lists each function. Figure 16.19 shows a block diagram of I2C mode. Figure 16.20 shows timings for transfer to the UiRB register and interrupts. Tables 16.14 to 16.16 list pin settings. As shown in Table 16.14, I2C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to "0102" and the IICM bit in the UiMR register is set to "1". SDAi output changes after SCLi becomes low ("L") and stabilizes due to a SDAi output via the delay circuit. Table 16.12 I2C Mode Specifications Item Interrupt Specifications Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment detect Selectable Function • Arbitration lost The update timing of the ABT bit in the UiRB register can be selected. Refer to 16.3.3 Arbitration. • SDAi digital delay Selected from no digital delay or 2 to 8 cycle delay of the count source of BRG. Refer to 16.3.5 SDA Output. • Clock phase setting Selected from clock delay or no clock delay. Refer to 16.3.4 Transfer Clock. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 195 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) SDAi (Note1) Timer I/O UARTi IICM 1 Delay Circuit 0 SDHI D Q T To DMAi IICM=0 or IICM2=1 Transmit Register UARTi IICM=1 and IICM2=0 UARTi Transmission NACK Interrupt Request ALS Arbitration 1 0 IICM Receive Register UARTi IICM=0 or IICM2=1 To DMAi Noise Filter Detects Start Condition S R Q IICM=1 and IICM2=0 UARTi Reception ACK Interrupt Request DMAi Request Bus busy NACK DQ T DQ T Detects Stop Condition Falling edge detect LSYN bit SCLi (Note 1) ACK I/O UARTi IICM=1 1 IICM 0 R Data Register Internal Clock 9th Pulse 1 0 IICM Bus Conflict Start Condition Detect Stop Condition Detect Interrupt Request Noise Filter Noise Filter Bus Conflict SWC2 CLK Detect Control UARTi External Clock R S Falling Edge of 9th Pulse SWC Port reading (Note 1) UARTi IICM=0 I/0 Timer * When the IICM bit is set to "1", port pin can be read regardless of the direction register being set to "1". CLKi i=0 to 4 NOTES: 1. Set the PSj (j=0,1,3), PSLj or PSC register to determine. IICM : Bit in the UiSMR register IICM2 : Bit in the UiSMR2 register Figure 16.19 I2C Mode Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 196 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.13 Registers To Be Used and Settings (I2C Mode) Register UiTB UiRB Bit Master 0 to 7 0 to 7 8 ABT OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1 to CLK0 CRS TXEPT CRD, NCH CKPOL UFORM TE TI RE RI UiRRM, UiLCH, UiERE IICM ABC BBS 3 to 7 IICM2 CSC SWC Set transmit data Received data can be read ACK or NACK bit can be read Arbitration lost detect flag Overrun error flag Set bit rate Set to "0102" Set to "0" Set to "0" Select count source of the UiBRG register Disabled because CRD = 1 Transfer register empty flag Set to "1" Set to "0" Set to "1" Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Set to "0" Function Slave Disabled Disabled Set to "1" Disabled UiBRG UiMR UiC0 UiC1 UiSMR UiSMR2 UiSMR3 UiSMR4 Set to "1" Select an arbitration lost detect timing Disabled Bus busy flag Set to "000002" See Table 16.14 Set to "1" to enable clock synchronization Set to "0" Set to "1" to output fixed "L" from the SDAi on the falling edge of the ninth bit of the transfer clock ALS Set to "1" to terminate SDA output when Not used. Set to "0" detecting the arbitration lost STC Not used. Set to "0" Set to "1" to reset UARTi by detecting a start condition SWC2 Set to "1" to forcibly output an "L" signal from SCL SDHI Set to "1" to disable SDA output SU1HIM Set to "0" SSE Set to "0" CKPH See Table 16.14. DINC, NODC, ERR Set to "0" DL2 to DL0 Set digital delay value STAREQ Set to "1" when generating start condition Not used. Set to "0" RSTAREQ Set to "1" when generating restart condition STPREQ Set to "1" when generating stop condition STSPSEL ACKD ACKC SCLHI SWC9 Set to "1" when using a condition generating function Select ACK or NACK Set to "1" to output ACK data Set to "1" to enable SCL output stop when Not used. Set to "0" detecting stop condition Not used. Set to "0" Set to "1" to output fixed "L" from SCLi on the falling edge of the ninth bit of the transfer clock IFSR i=0 to 4 IFSR6, IFSR7 Set to "1" Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 197 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.14 I2C Mode Functions I2C Mode (SMD2 to SMD0=0102, IICM=1) Function Clock Synchronous Serial I/O Mode (SMD2 to SMD0=0012, IICM=0) IICM2=0 (NACK/ACK interrupt) CKPH=0 (No clock delay) CKPH=1 (Clock delay) IICM2=1 (UART transmit / UART receive interrupt) CKPH=0 (No clock delay) CKPH=1 (Clock delay) Interrupt Numbers 39 to 41 Generated(1) (See Figure 16.20) Interrupt Number 17, 19, 33, 35 and 37 Generated(1) (See Figure 16.20) Interrupt Numbers 18, 20, 34, 36 and 38 Generated(1) (See Figure 16.20) Data Transfer Timing from the UART Receive Shift Register to the UiRB Register UARTi Transmit Output Delay P63, P67, P70, P92, P96 Pin Functions P62, P66, P71, P91, P97 Pin Functions P61, P65, P72, P90, P95 Pin Functions Noise Filter Width Reading RxDi and SCLi Pin Levels Default Value of TxDi, SDAi Output SCLi Default and End Value DMA Generated (See Figure 16.20) UARTi Transmission Transmission started or completed (selected by the UiIRS register) UARTi Reception Receiving at 8th bit CKPOL=0(rising edge) CKPOL=1(falling edge) CKPOL=0(rising edge) CKPOL=1(falling edge) No delay TxDi output RxDi input Select CLKi input or output 15ns Can be read if port direction bit is set to "0" CKPOL=0 (H) CKPOL=1 (L) – UARTi reception Start condition or stop condition detect (See Table 16.17) UARTi Transmission Rising edge of 9th bit of SCLi No Acknowlegement Detect (NACK) Rising edge of 9th bit of SCLi UARTi Transmission Next falling edge after the 9th bit of SCLi Acknowlegement Detect (ACK) - UARTi Reception Rising edge of 9th bit of SCLi Falling edge of 9th bit of SCLi Rising edge of 9th bit of SCLi Falling edge of 9th bit of SCLi Falling edge and rising edge of 9th bit of SCLi Delay SDAi input and output SCLi input and output – (Not used in I2C mode) 200ns Can be read regardless of the port direction bit Values set in the port register before entering I2C mode(2) H L H L Acknowlegement detect (ACK) UARTi Reception Falling edge of 9 bit of SCLi 1st to 7th bits of the received data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register. 1st to 8th bits are stored into bits 7 to 0 in the UiRB register(3) Bits 6 to 0 in the UiRB registerts(4) are read as bit 7 to 1. Bit 8 in the UiRB register is read as bit 0 Store Received Data 1st to 8th bits of the received data are stored into bits 0 to 7 in the UiRB register 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register Reading Received Data The UiRB register status is read i=0 to 4 NOTES: 1. Follow the procedures below to change how an interrupt is generated. (a) Disable interrupt of corresponding interrupt number. (b) Change how an interrupt is generated. (c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested). (d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number. 2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled). 3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi). 4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 198 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) ACK interrupt (DMA request) or NACK interrupt b15 b9 ••• b8 b7 b0 Data is transferred to the UiRB register D8 D7 D 6 D 5 D4 D3 D2 D1 D 0 Contents of the UiRB register (2) When IICM2 is set to "0" and CKPH is set to "1" (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) ACK interrupt (DMA request) or NACK interrupt b15 b9 ••• b8 b7 b0 Data is transferred to the UiRB register D8 D7 D6 D 5 D 4 D3 D2 D1 D0 Contents of the UiRB register (3) When IICM2 is set to "1" (UART transmit or receive interrupt) and CKPH is set to "0" 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) Transmit interrupt b15 b9 ••• b8 b7 b0 Receive interrupt (DMA request) Data is transferred to the UiRB register D0 D 7 D6 D5 D4 D 3 D 2 D 1 (4) When IICM2 is set to "1" and CKPH is set to "1" 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Contents of the UiRB register SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) Transmit interrupt Receive interrupt (DMA request) Data is transferred to the UiRB register. b15 ••• b9 b8 b7 b0 Data is transferred to the UiRB register. b15 ••• b9 b8 b7 b0 D0 D7 D 6 D 5 D 4 D 3 D 2 D 1 D 8 D7 D6 D5 D 4 D 3 D2 D 1 D0 i=0 to 4 IICM2 : Bit in the UiSMR2 register CKPH : Bit in the UiSMR3 regiser The above timing applies to the following setting : • CKDIR bit in the UiMR register = 1 (select slave) Contents of the UiRB register Contents of the UiRB register Figure 16.20 UiRB Register Transfer and Interrupt Timings Table 16.15 Pin Settings in I2C Mode (1) Port P62 P63 P66 P67 Function PS0 Register SCL0 output SCL0 input SDA0 output SDA0 input SCL1 output SCL1 input SDA1 output SDA1 input PS0_2=1 PS0_2=0 PS0_3=1 PS0_3=0 PS0_6=1 PS0_6=0 PS0_7=1 PS0_7=0 PSL0_6=0 Setting PSL0 Register PSL0_2=0 PD6_2=0 PD6_3=0 PD6_6=0 PD6_7=0 PD6 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 199 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.16 Pin Settings (2) Port P70(1) P71(1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Function PS1 Register SDA2 output SDA2 input SCL2 output SCL2 input PS1_0=1 PS1_0=0 PS1_1=1 PS1_1=0 PSL1_1=0 Setting PSL1 Register PSC Register PSL1_0=0 PSC_0=0 PSC_1=0 PD7_1=0 PD7_0=0 PD7 Register Table 16.17 Pin Settings (3) Port P91 P92 P96 P97 Function PS3 Register(1) SCL3 output SCL3 input SDA3 output SDA3 input SDA4 output SDA4 input SCL4 output SCL4 input PS3_1=1 PS3_1=0 PS3_2=1 PS3_2=0 PS3_6=1 PS3_6=0 PS3_7=1 PS3_7=0 PSL3_2=0 PSL3_7=0 Setting PSL3 Register PSL3_1=0 PD9_1=0 PD9_2=0 PD9_6=0 PD9_7=0 PD9 Register(1) NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. 16.3.1 Detecting Start Condition and Stop Condition The microcomputer detects either a start condition or stop condition. The start condition detect interrupt is generated when the SCLi (i=0 to 4) pin is held high ("H") and the SDAi pin changes high ("H") to low ("L"). The stop condition detect interrupt is generated when the SCLi pin is held high ("H") and the SDAi pin changes low ("L") to high ("H"). The start condition detect interrupt shares interrupt control registers and vectors with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is requested. 3 to 6 cycles < setup time(1) 3 to 6 cycles < hold time(1) Setup time SCLi SDAi (Start condition) Hold time SDAi (Stop condition) i=0 to 4 NOTES: 1. These cycles are main clock generation frequency cycles (XIN). Figure 16.21 Start Condition or Stop Condition Detect Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 200 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.3.2 Start Condition or Stop Condition Output The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1" (start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1" (start). The stop condition is generated when the STPREQ bit in the UiSMR4 is set to "1" (start). The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4 register is set to "1" (start or stop condition generation circuit selected). The restart condition is output when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition is output when the STPREQ bit and the STSPSEL bit are set to "1". When the start condition, stop condition or restart condition is output, do not generate an interrupt between the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the STSPSEL bit is set to "1". Table 16.18 lists function of the STSPSEL bit. Figure 16.22 shows functions of the STSPSEL bit. Table 16.18 STSPSEL Bit Function Function Start condition and stop condition output STSPSEL = 0 Program with a port determines how the start condition or stop condition is output Timing to generate a start condition and stop condition interrupt request The start condition and stop condition are detected STSPSEL = 1 The STAREQ bit, RSTAREQ bit and STPREQ bit determine how the start condition or stop condition is output Start condition and stop condition generation are completed (1) In slave mode, CKDIR is set to "1" (external clock) STSPSEL is set to "0" (no start condition and stop condition output) SCLi SDAi Start condition detect interrupt Stop condition detect interrupt (1) In master mode, CKDIR is set to "0" (internal clock) STSPSEL is set to "1" (start condition and stop condition output) Setting value of the STSPEL bit SCLi SDAi STAREQ=1 (start) Start condition detect interrupt i=0 to 4 0 1 0 1 0 STPREQ=1 (start) Stop condition detect interrupt Figure 16.22 STSPSEL Bit Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 201 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.3.3 Arbitration The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB register. On the rising edge of SCLi, the microcomputer determines whether a transmit data matches data input to the SDAi pin. When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" as soon as a data discrepancy is detected. The ABT bit is set to "0" if not detected. When the ABC bit is set to "1", the ABT bit is set to "1" (detected-arbitration is lost) on the falling edge of the ninth bit of the transfer clock if any discrepancy is detected. When the ABT bit is updated per byte, set the ABT bit to "0" (not detected-arbitration is won) between an ACK detection in the first byte data and the next byte data to be transferred. When the ALS bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost occurs. As soon as the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state. 16.3.4 Transfer Clock The transfer clock transmits and receives data as is shown in Figure 16.22 The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi) with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous enabled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal input to the SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals from the internal SCLi and the SCLi pin. The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit is set to "1". The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to output an "L" signal on the falling edge of the ninth cycle of the transfer clock or not. When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop condition is detected (high-impedance). When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin forcibly outputs an "L" signal while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC2 bit to "0" (transfer clock) and the transfer clock is input to and output from the SCLi pin. When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to "1" (SCL "L" hold enabled), the SCLi pin is fixed to output an "L" signal on the next falling edge after the ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to "0" (SCL "L" hold disabled). 16.3.5 SDA Output Values in bits 7 to 0 (D7 to D0) in the UiTB register (i=0 to 4) are output in descending order from D7. The ninth bit (D8) is ACK or NACK. Set the default value of SDAi transmit output when the IICM bit is set to "1" (I2C mode) and the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled). The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8 UiBRG register count source cycles. When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly placed in a high-impedance state. Do not set in the SDHI bit on the rising edge of the URTi transfer clock. The ABT bit in the UiRB register may be set to "1" (detected). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 202 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.3.6 SDA Input When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK. When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register. If the IICM bit in the UiSMR register is set to "1" and the CKPH bit is set to "1", the same data as that of when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising edge of the ninth bit of the transfer clock. 16.3.7 ACK, NACK When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin outputs the value set in the ACKD bit. If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H") on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock. When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection. 16.3.8 Transmit and Receive Reset When the STC bit in the UiSMR2 register is set to "1" (UARTi initialization enabled) and a start condition is detected, - the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift register. The first bit starts transmitting when the next clock is input. UARTi output value remains unchanged between when clock is input and when data of the first bit is output. The value remains the same value as when start condition was detected. - the receive shift register is reset and the first bit starts receiving when the next clock is input. - the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes low ("L") on the falling edge of the ninth bit of the transfer clock. If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains unchanged. Select the external clock as the transfer clock when using this function. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 203 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.4 Special Mode 2 In special mode 2, serial communication between one or multiple masters and multiple slaves is available. _____ The SSi input pin (i=0 to 4) controls the serial bus communication. Table 16.19 lists specifications of special mode 2. Table 16.20 lists registers to be used and settings. Tables 16.20 to 16.22 list pin settings. Table 16.19. Special Mode 2 Specifications Transfer data : 8 bits long The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected) : fj/2(m+1) fj = f1, f8, f2n(1) m : setting value of the UiBRG register 0016 to FF16 The CKDIR bit to "1" (external clock selected) : input clock from the CLKi pin ______ Transmit/Receive Control SSi input pin function Transmit Start Condition •To start transmitting, the following requirements must be met(2) : - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Receive Start Condition • To start receiving, the following requirement must be met(2) : - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit to "1" (receive enable) - Set the TI bit to "0" (data in the UiTB register) Interrupt Request • Transmit interrupt timing can be selected from the followings: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transmission started) - The UiIRS register is set to "1" (transmission completed): when data transmission from UARTi transfer register is completed • Receive interrupt timing When data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection •Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register •Fault error ______ In master mode, the fault error occurs an "L" signal is applied to the SSi pin Selectable Function • CLK polarity Select from the rising edge or falling edge of the transfer clock when transferred data is output and input • LSB first / MSB first Data is transmitted or received in either bit 0 or in bit 7 • Continuous receive mode Reception is enabled simultaneously by reading the UiRB register • Serial data logic inverse This function inverses transmitted or received data logically • TxD, RxD I/O polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed • Clock phase Select from one of 4 combinations of transfer data polarity and phases _____ • SSi input pin function Output pin is placed in a high-impedance state to avoid data conflict between master and other masters or slaves NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L"). 3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 204 of 488 Item Transfer Data Format Transfer Clock Specification M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.20. Registers To Be Used and Settings in Special Mode 2 Register UiTB UiRB UiBRG UiMR 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL UiC0 CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiSMR UiSMR2 UiSMR3 0 to 7 0 to 7 SSE CKPH DINC NODC ERR 5 to 7 UiSMR4 IFSR i=0 to 4 0 to 7 IFSR6, IFSR7 Bit Set transmit data Received data can be read Overrun error flag Set bit rate Set to "0012" Set to "0" in master mode or "1" in slave mode Set to "0" Select count source for the UiBRG register Disabled since CRD = 1 Transfer register empty flag Set to "1" Select the output format of the TxDi pin Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in the UiSMR3 register Select either LSB first or MSB first Set to "1" to enable data transmission and reception Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select how the UARTi transmit interrupt is generated Set to "1" to enable continuous receive mode Set to "0016" Set to "0016" Set to "1" Clock phase can be set by the combination of the CKPH bit and the CKPOL bit in the UiC0 register Set to "0" in master mode or "1" in slave mode Set to "0" Fault error flag Set to "0002" Set to "0016" Select how fault error occurs Function UiLCH, SCLKSTPB Set to "0" Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 205 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.21 Pin Settings in Special Mode 2 (1) Port ______ Function SS0 input CLK0 input (slave) CLK0 output (master) RxD0 input (master) STxD0 output (slave) TxD0 output (master) SRxD0 input (slave) ______ SS1 input CLK1 input (slave) CLK1 output (master) RxD1 input (master) STxD1 output (slave) TxD1 output (master) SRxD1 input (slave) PS0 Register PS0_0=0 PS0_1=0 PS0_1=1 PS0_2=0 PS0_2=1 PS0_3=1 PS0_3=0 PS0_4=0 PS0_5=0 PS0_5=1 PS0_6=0 PS0_6=1 PS0_7=1 PS0_7=0 Setting PSL0 Register – – – – PSL0_2=1 – – – – – – PSL0_6=1 – – P60 P61 P62 P63 P64 P65 P66 P67 PD6 Register PD6_0=0 PD6_1=0 – PD6_2=0 – – PD6_3=0 PD6_4=0 PD6_5=0 – PD6_6=0 – – PD6_7=0 Table 16.21 Pin Settings (2) Port P70(1) P71(1) P72 Function TxD2 output (master) SRxD2 input (slave) RxD2 input (master) STxD2 output (slave) CLK2 input (slave) CLK2 output (master) ______ SS2 input PS1 Register PS1_0=1 PS1_0=0 PS1_1=0 PS1_1=1 PS1_2=0 PS1_2=1 PS1_3=0 Setting PSL1 Register PSC Register PSL1_0=0 PSC_0=0 – – – – PSL1_1=1 PSC_1=0 – – PSL1_2=0 PSC_2=0 – – PD7 Register – PD7_0=0 PD7_1=0 – PD7_2=0 – PD7_3=0 P73 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.23 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 Function CLK3 input (slave) CLK3 output (master) RxD3 input (master) STxD3 output (slave) TxD3 output (master) SRxD3 input (slave) ______ SS3 input _______ SS4 input CLK4 input (slave) CLK4 output (master) TxD4 output (master) SRxD4 input (slave) RxD4 input (master) STxD4 output (slave) PS3 Register(1) PS3_0=0 PS3_0=1 PS3_1=0 PS3_1=1 PS3_2=1 PS3_2=0 PS3_3=0 PS3_4=0 PS3_5=0 PS3_5=1 PS3_6=1 PS3_6=0 PS3_7=0 PS3_7=1 Setting PSL3 Register – – – PSL3_1=1 PSL3_2=0 – PSL3_3=0 PSL3_4=0 PSL3_5=0 – – PSL3_6=0 – PSL3_7=1 PD9 Register(1) PD9_0=0 – PD9_1=0 – – PD9_2=0 PD9_3=0 PD9_4=0 PD9_5=0 – – PD9_6=0 PD9_7=0 – NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 206 of 488 M32C/83 Group (M32C/83, M32C/83T) ______ 16. Serial I/O (Special Function) 16.4.1 SSi Input Pin Function (i=0 to 4) ____ ______ When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the SSi input pin function is selected, activating the pin function. The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave. ______ When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting determines which master microcomputer is active and when. 16.4.1.1 When Setting the DINC Bit to "1" (Slave Mode) _____ When an "H" signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high-impedance state and the transfer clock input to the CLKi pin is ignored. When a low-level signal ("L") is _____ applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled. 16.4.1.2 When Setting the DINC Bit to "0" (Master Mode) _____ When an "H" signal is applied to the SSi pin, serial communication is available due to transmission _____ privilege. The master outputs the transfer clock. When an "L" signal is applied to the SSi pin, it indicates that another master is active and TxDi, RxDi and CLKi pins are placed in a high-impedance state. Moreover, a fault error occurs and the IR bit in the BCNiIC register is set to "1" (interrupt requested). The ERR bit in the UiSMR3 register indicates whether a fault error occurs. In master mode, software interrupt numbers 39, 40 and 41 are used for the fault error interrupt. The fault error interrupt is generated when the ERR bit changes "0" to "1". The fault error interrupt of UART0 and of UART3 share an interrupt vector. The fault error interrupt of UART1 and of UART4 share an interrupt vector. The IFSR6 and IFSR7 bits in the IFSR register determine which fault error interrupt is used. Communication is not terminated even if a fault error is generated while communicating. To stop communication, the SMD 2 to SMD0 bit in the UiMR register is set to "0002" (serial I/O disabled). Microcomputer P13 P12 P93(SS3) P90(CLK3) P91(RxD3) P92(TxD3) Master Microcomputer P93(SS3) P90(CLK3) P91(STxD3) P92(SRxD3) Slave Microcomputer P93(SS3) P90(CLK3) P91(STxD3) P92(SRxD3) Slave ___ Figure 16.23 Serial Bus Communication Control with SS Pin Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 207 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.4.2 Clock Phase Setting Function The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four combinations of transfer clock polarity and phases. The transfer clock phase and polarity must be the same between the master and the slave involved in the transfer. 16.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock)) Figure 16.24 shows transmit and receive timing. 16.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock)) _____ When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin _____ is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the transfer clock. Figure 16.25 shows the transmit and receive timing. _____ When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high ("H"), the STxDi pin is _____ placed in a high-impedance state. When the SSi pin becomes low ("L"), the first data is output. The serial transmission is synchronized with the transfer clock. Figure 16.26 shows the transmit and receive timing. Input Signal to the SS Pin in the Master "H" "L" Clock Output "H" (CKPOL=0, CKPH=0) "L" Clock Output "H" (CKPOL=1, CKPH=0) "L" Clock Output "H" (CKPOL=0, CKPH=1) "L" Clock Output "H" (CKPOL=1, CKPH=1) "L" "H" "L" Data Output Timing D0 D1 D2 D3 D4 D5 D6 D7 Data Input Timing Figure 16.24 Transmit and Receive Timing in Master Mode (Internal Clock) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 208 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Input Signal to the SS Pin "H" "L" "H" Clock Input (CKPOL=0, CKPH=0) "L" "H" Clock Input (CKPOL=1, CKPH=0) "L" Data Output Timing(1) "H" "L" Highimpedance D0 D1 D2 D3 D4 D5 D6 D7 Highimpedance Data Input Timing Indeterminate NOTES: 1. P70 is a port for the N-channel open drain output and must be pulled up externally for data output. Figure 16.25 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=0) "H" Input Signal to the SS Pin "L" "H" Clock Input (CKPOL=0, CKPH=1) "L" "H" Clock Input (CKPOL=1, CKPH=1) "L" Data Output Timing(1) "H" "L" Highimpedance D0 D1 D2 D3 D4 D5 D6 D7 Highimpedance Data Input Timing NOTES: 1. P70 is a port for the N-channel open drain output and must be pulled up externally for data output. Figure 16.26 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=1) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 209 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.5 Special Mode 3 (GCI Mode) In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial I/O mode. Table 16.24 lists specifications of GCI mode. Table 16.25 lists registers to be used and settings. Tables 16.25 to 16.27 list pin settings. Table16.24 GCI Mode Specifications Item Transfer Data Format Transfer Clock Transfer data : 8 bits long The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected): an input from the CLKi pin ________ Specification Clock Synchronization Function The CTSi pin inputs a trigger Transmit/Receive Start Conditions When a trigger signal is applied to the CTSi pin under the following conditions: • Set the TE bit in the UiC1 register to "1" (transmit enable) • Set the RE bit in the UiC1 register to "1" (receive enable) • Set the TI bit in the UiC1 register to "0" (data in UiTB register) Interrupt Request Generation Timing Transmit interrupt timing can be selected from the followings: • The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty) : when data is transferred from the UiTB register to the UARTi transmit register (transmission started) • The UiIRS bit is set to "1" (transmit completed): when a data transmission from the UARTi transfer register is completed Receive interrupt timing when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection Overrun error(1) This error occurs when the seventh bit of the next received data is read before reading the UiRB register. NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 210 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.25 Registers To Be Used and Settings in GCI Mode Register UiTB UiRB UiBRG UiMR 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM, UiLCH SCLKSTPB UiSMR UiSMR2 UiSMR3 0 to 6 SCLKDIV 0 to 6 SU1HIM 0 to 2 NODC 4 to 7 UiSMR4 i=0 to 4 0 to 7 Bit Set transmit data Received data Overrun error flag Set to "0016" Set to "0012" Set to "1" Set to "0" Set to "002" Disabled because CRD = 1 Transfer register empty flag Set to "1" Select the output format of the TxDi pin Set to "0" Set to "0" Set to "1" to enable data transmission and reception Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select how the UARTi transmit interrupt is generated Set to "0" Set to "0" Set to "00000002" See Table 16.29 Set to "00000002" See Table 16.29 Set to "0002" Set to "0" Set to "00002" Set to "0016" Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 211 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.26 Pin Settings in CGI Mode (1) Port __________ Function PS0 Register CTS0 input(1) CLK0 input RxD0 input TxD0 output __________ Setting PSL0 Register – – – – – – – – PD6 Register PD6_0=0 PD6_1=0 PD6_2=0 – PD6_4=0 PD6_5=0 PD6_6=0 – PS0_0=0 PS0_1=0 PS0_2=0 PS0_3=1 PS0_4=0 PS0_5=0 PS0_6=0 PS0_7=1 P60 P61 P62 P63 P64 P65 P66 P67 NOTES: _______ CTS1 input(1) CLK1 input RxD1 input TxD1 output 1. CTS input is used to input a trigger. Table 16.27 Pin Settings (2) Port P70(1) P71(1) P72 P73 Function PS1 Register TxD2 output RxD2 input CLK2 input __________ Setting PSL1 Register PSL1_0=0 – – – – – – PSC Register PSC_0=0 – PD7_1=0 PD7_2=0 PD7_3=0 PD7 Register PS1_0=1 PS1_1=0 PS1_2=0 PS1_3=0 CTS2 input(2) NOTES: 1. P70 and P71 are ports for the N-channel open drain output. _______ 2. CTS input is used to input a trigger. Table 16.28 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. _______ 2. CTS input is used to input a trigger. Function PS3 Register(1) CLK3 input RxD3 input TxD3 output __________ __________ Setting PSL3 Register – – PSL3_2=0 PSL3_3=0 PSL3_4=0 PSL3_5=0 – – PD9 Register(1) PD9_0=0 PD9_1=0 – PD9_3=0 PD9_4=0 PD9_5=0 – PD9_7=0 PS3_0=0 PS3_1=0 PS3_2=1 PS3_3=0 PS3_4=0 PS3_5=0 PS3_6=1 PS3_7=0 CTS3 input(2) CTS4 input(2) CLK4 input TxD4 output RxD4 input Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 212 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) To generate the internal clock synchronized with the external clock, first set the SU1HIM bit in the UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 16.29. Then apply a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock operation. Figure 16.27 shows an example of the clock-divided synchronous function. Table 16.29 Clock-Divided Synchronous Function Select SCLKDIV Bit in UiSMR Register 0 0 1 SU1HIM Bit in UiSMR2 Register 0 1 0 or 1 Not synchronized Same division as the external clock Same division as the external clock divided by 2 i=0 to 4 A in Figure 16.27 B in Figure 16.27 Clock-Divided Synchronous Function Example of Waveform External Clock from the CLKi Pin Trigger Signal from the CTSi Pin 1 2 3 4 5 6 7 8 Transfer Clock A TxDi Transfer Clock 1 2 3 4 5 6 7 8 The SCLKSTPB bit in the UiC1 register stops the clock B TxDi i=0 to 4 A, B : See Table 16.29. 1 2 3 4 5 6 7 8 Figure 16.27 Clock-Divided Synchronous Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 213 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.6 Special Mode 4 (IE Mode) In IE mode, devices connected with the IEBus can communicate in UART mode. Table 16.30 lists registers to be used and settings. Tables 16.30 to 16.32 list pin settings. Table 16.30. Registers To Be Used and Settings in IE Mode Register UiTB UiRB 0 to 8 0 to 8 OER, FER, PER, SUM UiBRG UiMR 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL UiC0 CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM, UiLCH, SCLKSTPB UiSMR 0 to 3 ABSCS ACSE SSS SCLKDIV UiSMR2 UiSMR3 UiSMR4 IFSR i=0 to 4 0 to 7 0 to 7 0 to 7 IFSR6, IFSR7 Set to "00002" Select bus conflict detect sampling timing Set to "1" to automatically clear the transmit enable bit Select transmit start condition Set to "0" Set to "0016" Set to "0016" Set to "0016" Select how the bus conflict interrupt occurs Set bit rate Set to "1102" Select the internal clock or external clock Set to "0" Disabled because PRYE=0 Set to "0" Select TxD and RxD I/O polarity Select the count source for the UiBRG register Disabled because CRD=1 Transfer register empty flag Set to "1" Select output format of the TxDi pin Set to "0" Set to "0" Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select how the UARTi transmit interrupt is generated Set to "0" Bit Set transmit data Received data can be read Error flags Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 214 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.31 Pin Settings in IE Mode (1) Port P61 P62 P63 P65 P66 P67 Function PS0 Register CLK0 input CLK0 output RxD0 input TxD0 output CLK1 input CLK1 output RxD1 input TxD1 output PS0_1=0 PS0_1=1 PS0_2=0 PS0_3=1 PS0_5=0 PS0_5=1 PS0_6=0 PS0_7=1 – – – – – – – – Setting PSL0 Register – PD6_2=0 – PD6_5=0 – PD6_6=0 – PD6 Register PD6_1=0 Table 16.32 Pin Settings (2) Port P70(1) P71(1) P72 Function PS1 Register TxD2 output RxD2 input CLK2 input CLK2 output PS1_0=1 PS1_1=0 PS1_2=0 PS1_2=1 – – PSL1_2=0 PSL1_0=0 Setting PSL1 Register – – PSC_2=0 PSC Register PSC_0=0 PD7 Register – PD7_1=0 PD7_2=0 – NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 16.33 Pin Settings (3) Port P90 P91 P92 P95 P96 P97 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Function PS3 Register(1) CLK3 input CLK3 output RxD3 input TxD3 output CLK4 input CLK4 output TxD4 output RxD4 input PS3_0=0 PS3_0=1 PS3_1=0 PS3_2=1 PS3_5=0 PS3_5=1 PS3_6=1 PS3_7=0 – – – PSL3_2=0 PSL3_5=0 – – – Setting PSL3 Register – PD9_1=0 – PD9_5=0 – – PD9_7=0 PD9 Register(1) PD9_0=0 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 215 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) If the output level of the TxDi pin (i=0 to 4) differs from the input level of the RxDi pin, an interrupt request is generated. UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number 41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6 bit and the IFSR7 bit in the IFSR register accordingly. When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined, on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3 in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) overflows. Use the timer Aj in one-shot timer mode. When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the BCNiIC register to "1" (discrepancy detected), the TE bit is set to "0" (transmit disable). When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), the TxDi pin starts transmitting data on the falling edge of the RxDi pin. Figure 16.28 shows bits associated with the bus conflict detect function. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 216 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) (1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected) (i=0 to 4) Bus conflict is detected on the rising edge of the transfer clock when ABSCS is set to "0" Transfer Clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi Trigger signal is applied to the TAjIN pin Timer Aj When ABSCS is set to "1", bus conflict is detected when the timer Aj underflows (in the one-shot mode). An interrupt request is generated. Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2 (2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared) Transfer Clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi IR bit in BCNilC register TE bit in UiC1 register (3) The SSS bit in the UiSMR Register (Transmit start condition selected) When SSS is set to "0", data is transmitted after one transfer clock cycle if data transmission is enabled. Transfer Clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi transmit enable conditons are met When SSS is set to "1", data is transmitted on the rising edge of RxDi(1) CLKi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi (Note 2) NOTES: 1. Data is transmitted on the falling edge of RxDi when IOPOL is set to "0". Data is transmitted on the rising edge of RxDi when IOPOL is set to "1". 2. Data transmission condition must be met before the falling edge of RxD. Figure 16.28 Bit Function Related Bus Conflict Detection Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 217 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.7 Special Mode 5 (SIM Mode) In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are available and the TxDi pin (i=0 to 4) can output an "L" signal when a parity error is detected. Table 16.34 lists specifications of SIM mode. Table 16.35 lists registers to be used and register settings in SIM mode. Tables 16.36 to 16.38 list the pin settings. Table16.34 SIM Mode Specifications Item Transfer Data Format • Transfer data: 8-bit UART mode • One stop bit • In direct format Parity: Data logic: Even Direct Specification Transfer format: LSB first • In inverse format Parity: Data logic: Odd Inverse Transfer format: MSB first Transfer Clock The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected): fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register 0016 to FF16 Do not set the CKDIR bit to "1" (external clock selected) Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled) Other Setting Items The UiIRS bit in the UiC1 register is set to "1" (transmission completed) Transmit Start Condition To start transmitting, the following requirements must be met: • Set the TE bit in the UiC1 register to "1" (transmit enable) • Set the TI bit in the UiC1 register to "0" (data being in the UiTB register) Receive Start Condition To start receiving, the following requirements must be met: • Set the RE bit in the UiC1 register to "1" (receive enable) • Detect the start bit Interrupt Request Generation Timing Transmit interrupt timing • The UiIRS bit is set to "1" (transmission is completed): when data transmission from the UARTi transfer register is completed Receive interrupt timing when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection • Overrun error(1) This error occurs when the eighth bit of the next data is received before reading the UiRB register • Framing error This error occurs when the number of the stop bit set is not detected • Parity error This error occurs when the number of "1" in parity bit and character bits differ from the number set. • Error sum flag The SUM bit is set to "1" when an overrun error, framing error or parity error occurs. NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 218 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.35 Registers To Be Used and Settings Register UiTB UiRB 0 to 7 0 to 7 OER, FER, PER, SUM UiBRG UiMR 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL UiC0 CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiLCH UiERE UiSMR UiSMR2 UiSMR3 UiSMR4 i=0 to 4 0 to 3 0 to 7 0 to 7 0 to 7 Set bit rate Set to "1012" Set to "0" Set to "0" Set to "1" for direct format or "0" for inverse format Set to "1" Set to "0" Select count source for the UiBRG register Disabled because CRD=1 Transfer register empty flag Set to "1" Set to "1" Set to "0" Set to "0" for direct format or "1" for inverse format Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Set to "1" Set to "0" Set to "0" for direct format or "1" for inverse format Set to "1" Set to "0016" Set to "0016" Set to "0016" Set to "0016" Bit Set transmit data Received data can be read Error flags Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 219 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Table 16.36 Pin Settings in SIM Mode (1) Port P62 P63 P66 P67 Function PS0 Register RxD0 input TxD0 output RxD1 input TxD1 output PS0_2=0 PS0_3=1 PS0_6=0 PS0_7=1 – – – – Setting PSL0 Register – PD6_6=0 – PD6 Register PD6_2=0 Table 16.37 Pin Settings (2) Port P70(1) P71(1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Function PS1 Register TxD2 output RxD2 input PS1_0=1 PS1_1=0 – PSL1_0=0 Setting PSL1 Register – PSC Register PSC_0=0 PD7 Register – PD7_1=0 Table 16.38 Pin Settings (3) Port P91 P92 P96 P97 Function PS3 RxD3 input TxD3 output TxD4 output RxD4 input Register(1) – PSL3_2=0 – – PS3_1=0 PS3_2=1 PS3_6=1 PS3_7=0 Setting PSL3 Register – – PD9_7=0 PD9 Register(1) PD9_1=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Figure 16.29 shows an example of a SIM interface operation. Figure 16.30 shows an example of a SIM interface connection. Connect TxDi to RxDi for a pull-up. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 220 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) (1) Transmit Timing Tc Transfer Clock TE bit in the UiC1 register TI bit in the UiC1 register "1" "0" "1" "0" Data is written to the UiTB register (Note 1) Start bit Parity Stop bit bit D2 D3 D4 D5 D6 D7 P SP Data is transferred from the UiTB register to the UARTi transmit register TxDi Parity Error Signal returned from Receiving End Signal Line Level(2) TXEPT bit in the UiC0 register IR bit in the SiTIC register ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 An "L" signal is applied from the SIM card due to a parity error P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 An interrupt routine detects "H" or "L" P SP "1" "0" "1" "0" An interrupt routine detects "H" or "L" Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above applies under the following conditions: • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) • The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated when transmission completed) Tc = 16(m+1) / fj fj: count source frequency of the UiBRG register (f1, f8, f2n(4)) m: setting value of the UiBRG register (2) Receive Timing Transfer Clock RE bit in the UiC1 register Transmit Waveform from the Transmitting End TxDi "1" "0" Start bit ST D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxDi outputs "L" due to a parity error ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Signal Line Level(3) RI bit in the UiC1 register IR bit in the SiRIC register "1" "0" "1" "0" Read the UiRB register Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above applies under the following conditions: • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) Tc = 16(m+1) / fj fj: count source frequency of the UiBRG register (f1, f8, f2n(4)) m: setting value of the UiBRG register NOTES: 1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit. 2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi pin and parity error signal from the receiving end, is generated. 3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxDi pin, is generated. 4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15). Figure 16.29 SIM Interface Operation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 221 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) Microcomputer SIM card TxDi RxDi i=0 to 4 Figure 16.30 SIM Interface Connection 16.7.1 Parity Error Signal 16.7.1.1 Parity Error Signal Output Function When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1", the parity error signal can be output. The parity error signal is output when a parity error is detected upon receiving data. TxDi outputs an "L" signal in the timing shown in Figure 16.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB register is set to "0" and TxDi again outputs an "H" signal simultaneously. 16.7.1.2 Parity Error Signal To determine whether the parity error signal is output, the port that shares a pin with RxDi is read by using a transmit complete interrupt routine. RxDi "H" "L" "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxDi Recieve Complete Flag Hi-Z "1" "0" NOTES: 1. The above applies to direct format conditions (PRY=1, UFORM=0, UiLCH=0). ST : Start bit P : Even parity SP : Stop bit i=0 to 4 Figure 16.31 Parity Error Signal Output Timing (LSB First) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 222 of 488 M32C/83 Group (M32C/83, M32C/83T) 16. Serial I/O (Special Function) 16.7.2 Format 16.7.2.1 Direct Format Set the PRYE bit in the UiMR register (i=0 to 4) to "1", the PRY bit to "1", the UFORM bit in the UiC0 register to "0" and the UiLCH bit in the UiC1 register to "0". When data are transmitted, data set in UiTB register are transmitted with the even-numbered parity, starting from D0. When data are received, received data are stored in the UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs. 16.7.2.2 Inverse Format Set the PRYE bit to "1", the PRY bit to "0", the UFORM bit to "1" and the UiLCH bit to "1". When data are transmitted, values set in the UiTB register are logically inversed and are transmitted with the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be stored in the UiRB register, starting from D7. The odd-numbered parity determines whether a parity error occurs. (1) Direct Format Transfer Clock "H" "L" TxDi "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 P P : Even parity (2) Inverse Format Transfer Clock TxDi "H" "L" "H" "L" D7 D6 D5 D4 D3 D2 D1 D0 P P : Odd parity i=0 to 4 Figure 16.32 SIM Interface Format Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 223 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 17. A/D Converter The A/D converter consists of two 10-bit successive approximation A/D converters, each with a capacitive coupling amplifier. The result of an A/D conversion is stored into the A/D register corresponding to selected pins. Table 17.1 lists specifications of the A/D converter. Figure 17.1 shows a block diagram of the A/D converter. Table 17.2 lists the differences between A/D0 and A/D1 conversions, which share the same conversion method. A/D0 and A/D1 can perform conversions simultaneously. Table 17.3 lists settings of the following pins; AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0, ANEX1 and __________ ADTRG. Figures 17.2 to 17.7 show registers associated with the A/D converter. NOTE In this section, the 144-pin package is given as the example. The AN150 to AN157 pins are not included in the 100-pin package. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 224 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter Table 17.1 A/D Converter Specifications Item A/D Conversion Method Analog Input Resolution Operating Mode Analog Input Pins(3) Voltage(1) Operating Clock, ØAD(2) 0V to AVCC (VCC) fAD, fAD/2, fAD/3, fAD/4 Select from 8 bits or 10 bits One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1 34 pins 8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27), AN15 (AN150 to AN157) 2 extended input pins (ANEX0 and ANEX1) A/D Conversion Start Condition Software trigger • The ADST bit in the ADiCON0 (i=0, 1) register is set to "1" (A/D conversion started) by program • The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a conversion simultaneously) by program External trigger (re-trigger is enabled) __________ Specification Successive approximation (with a capacitive coupling amplifier) When a falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by program Hardware trigger (re-trigger is enabled) One of the following interrupt requests is generated after the ADST bit is set to "1" by program: • The timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting) • The intelligent I/O interrupt request Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1) Conversion Rate Per Pin • Without the sample and hold function 8-bit resolution : 49 ØAD cycles 10-bit resolution : 59 ØAD cycles • With the sample and hold function 8-bit resolution : 28 ØAD cycles 10-bit resolution : 33 ØAD cycles NOTES: 1. Analog input voltage is not affected by the sample and hold function status. 2. ØAD frequency must be under 16 MHz when VCC=5V. ØAD frequency must be under 10 MHz when VCC=3.3V. Without the sample and hold function, the ØAD frequency must be 250 kHz or more. With the sample and hold function, the ØAD frequency must be 1 MHz or more. 3. AVCC = VREF = VCC, A/D input voltage (for AN0 to AN7, AN00 to AN07, AN20 to AN27, AN150 to AN157, ANEX0 and ANEX1) ≤ VCC. Table 19.2 Difference between A/D0 and A/D1 Item Analog Input Pins(1) A/D0 AN (AN0 to AN7) ANEX0, ANEX1 Enabled Channel 1 in group 2 A/D1 Select from AN0 (AN00 to AN07), AN2 (AN20 to AN27) or AN15 (AN150 to AN157) Extended Analog Input Pins External Op-Amp(1) Intelligent I/O used as a Trigger NOTES: 1. When the ADS bit in the AD0CON2 register is set to "0" (channel replacement disabled) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 225 of 488 Not provided Disabled Channel 1 in group 3 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 000 001 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 (Note 1) Software trigger 0 010 011 01 10 1 ADTRG TB2 interrupt request •Intelligent I/O group2 channel 1 interrupt request (A/D0) •Intelligent I/O group3 channel 1 interrupt request (A/D1) 00 TRG1 to TRG0 bits in ADiCON2 register A/Di trigger TRG bit in ADiCON0 register 100 101 110 111 000 001 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN150 AN151 AN152 AN153 AN154 AN155 AN156 AN157 (Note 2) (Note 1) OPA1 to OPA0 bits in AD0CON1 register 010 011 100 ANEX1 ANEX0 1X X1 01 101 110 11 111 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 000 001 010 011 100 101 110 111 CH2 to CH0 bits in AD0CON0 register 0 1 0 1 00 APS1 to APS0 bits in AD1CON2 register 11 10 000 001 00 010 011 ADS bit in AD0CON2 register 100 101 110 CH2 to CH0 bits in AD1CON0 register 111 Comparator 0 AD00 register AD01 register AD02 register Comparator 1 AD10 register AD11 register AD12 register Decoder Decoder AD03 register AD04 register AD05 register AD06 register AD07 register Successive conversion register AD13 register AD14 register AD15 register AD16 register AD17 register Successive conversion register AD0CON0 register AD1CON0 register Resistor ladder AD0CON1 register ØAD0 1 Resistor ladder AD1CON1 register ØAD1 1 1/3 0 1/3 1 0 0 1 0 1 1 fAD 1/2 1/2 0 fAD 1/2 1/2 0 CSK0 bit in AD0CON0 register CSK1 bit in AD0CON1 register CSK0 bit in AD1CON0 register CSK1 bit in AD1CON1 register i=0,1 NOTES: 1. These pins are available in single-chip mode. 2. These pins are provided in the 144-pin package. Figure 17.1 A/D Converter Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 226 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter Table 17.3 Pin Settings Port Name P100 P101 P102 P103 P104 P105 P106 P107 P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 P150 P151 P152 P153 P154 P155 P156 P157 P95 P96 P97 NOTES: 1. This pin is available in single-chip mode. 2. This pin is provided in the 144-pin package. 3. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN00(1) AN01(1) AN02(1) AN03(1) AN04(1) AN05(1) AN06(1) AN07(1) AN20(1) AN21(1) AN22(1) AN23(1) AN24(1) AN25(1) AN26(1) AN27(1) AN150(2) AN151(2) AN152(2) AN15 3(2) AN154(2) AN155(2) AN156(2) AN157(2) ANEX0 ANEX1 ___________ Function PD10, PD0, PD2, PD15, PD9(3) Registers PD10_0 = 0 PD10_1 = 0 PD10_2 = 0 PD10_3 = 0 PD10_4 = 0 PD10_5 = 0 PD10_6 = 0 PD10_7 = 0 PD0_0 = 0 PD0_1 = 0 PD0_2 = 0 PD0_3 = 0 PD0_4 = 0 PD0_5 = 0 PD0_6 = 0 PD0_7 = 0 PD2_0 = 0 PD2_1 = 0 PD2_2 = 0 PD2_3 = 0 PD2_4 = 0 PD2_5 = 0 PD2_6 = 0 PD2_7 = 0 PD15_0 = 0 PD15_1 = 0 PD15_2 = 0 PD15_3 = 0 PD15_4 = 0 PD15_5 = 0 PD15_6 = 0 PD15_7 = 0 PD9_5 = 0 PD9_6 = 0 PD9_7 = 0 - Bit and Setting PS3(3), PS9 PSL3, IPS Registers PUR0, PUR3, PUR4 Registers PU30 = 0 Registers PU31 = 0 - PU00 = 0 PU01 = 0 - PU04 = 0 - PU05 = 0 PS9_0 = 0 PS9_1 = 0 PS9_4 = 0 PS9_5 = 0 PS3_5 = 0 PS3_6 = 0 PS3_7 = 0 IPS2 = 1 PU42 = 0 PU43 = 0 PSL3_5 = 1 PSL3_6 = 1 - PU27 = 0 - ADTRG Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 227 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter A/D0 Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD0CON0 Address 039616 After Reset 0016 Bit Symbol CH0 Bit Name b2 b1 b0 Function 0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 0 1 1 : AN3 1 0 0 : AN4 1 0 1 : AN5 1 1 0 : AN6 1 1 1 : AN7 b4 b3 RW RW CH1 Analog Input Pin Select Bit(2, 3, 4) RW CH2 RW MD0 MD1 0 0 : One-shot mode A/D Operation 0 1 : Repeat mode Mode Select Bit 0(2) 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 Trigger Select Bit A/D Conversion Start Flag Frequency Select Bit(6) 0 : Software trigger 1 : External trigger, hardware trigger(5) 0 : A/D conversion stops 1 : A/D conversion starts(5) 0 : Select from fAD/3 or fAD/4 1 : Select from fAD/1 or fAD/2 RW RW TRG RW ADST RW CKS0 RW NOTES: 1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Analog input pins must be set again after changing A/D operation mode. 3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. 4. Set the PSC_7 bit in the PSC register to "1" (AN4 to AN7) to use the P10 pin as a analog input pin. 5. To set the TRG bit to "1", select the cause of trigger by setting the TRG1 and TRG0 bits in the AD0CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". 6. AD frequency must be under 16 MHz when VCC=5V. AD frequency must be under 10 MHz when VCC=3.3V. Combination of the CKS0 and CKS1 bits selects AD. CKS0 0 0 1 1 CKS1 0 1 0 1 AD fAD divided by 4 fAD divided by 3 fAD divided by 2 fAD Figure 17.2 AD0CON0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 228 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter A/D0 Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD0CON1 Address 039716 After Reset 0016 Bit Symbol SCAN0 Bit Name b0 b1 Function 0 0 : AN0, AN1 (AN0) 0 1 : AN0 to AN3 (AN0, AN1) 1 0 : AN0 to AN5 (AN0 to AN2) 1 1 : AN0 to AN7 (AN0 to AN3) 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : Select from fAD/2 or fAD/4 1 : Select from fAD/1 or fAD/3 0 : No VREF connection(4) 1 : VREF connection b6 b7 RW RW A/D Sweep Pin Select Bit(2) SCAN1 A/D Operation Mode Select Bit 1 8/10-bit Mode Select Bit Frequency Select Bit(3) VREF Connection Bit External Op-Amp Connection Mode Bit(5) RW MD2 RW BITS RW CKS1 RW VCUT RW OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used(6) 0 1 : Signal into ANEX0 is A/D converted 1 0 : Signal into ANEX1 is A/D converted 1 1 : External op-amp connection mode RW RW NOTES: 1. When the AD0CON1 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. This bit is disabled in one-shot mode and repeat mode. Pins in parentheses are those most commonly used in the A/D conversions when the MD2 bit is set to "1". 3. AD frequency must be under 16 MHz when VCC=5V. AD frequency must be under 10 MHz when VCC=3.3V. Combination of the CKS0 and CKS1 bits selects AD (see the AD0CON0 register). 4. Do not set the VCUT bit to "0" during the A/D conversion. This is a reference voltage for the A/D0. It does not affect D/A conversion. 5. In single sweep mode and repeat sweep mode 0 or 1, the OPA1 and OPA0 bits cannot be set to "012"or "102". 6. When the OPA1 to OPA0 bits is set to "002", set the PSL3_5 bit in PSL3 register to "0" (other than ANEX0) and the PSL3_6 bit to "0" (other than ANEX1). Figure 17.3 AD0CON1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 229 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter A/D0 Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD0CON2 Bit Symbol Address 039416 000 After Reset X000 00002 Bit Name A/D Conversion Method Select Bit Reserved Bit Function RW SMP 0 : Without the sample and hold function RW 1 : With the sample and hold function Set to "0" RW (b3 - b1) ADS A/D Channel Replace 0 : Disables channel replacement 1 : Enables channel replacement(5) Select Bit(2) b6 b5 RW TRG0 External Trigger Request Cause Select Bit TRG1 0 0 : Selects ADTRG 0 1 : Selects a timer B2 interrupt request of the three-phase motor control timer functions (after ICTB2 counter completes counting) 1 0 : Selects the intelligent I/O group 2 channel 1 interrupt 1 1 : Do not set to this value RW RW PST Simultaneous Start Bit(2, 3, 4) When this bit is set to "1", A/D0 and A/D1 start conversions simultaneously. WO When read, its content is indeterminate. NOTES: 1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Do not set the APS1 and APS0 bits to "1" while either A/D0 or A/D1 is operating. 3. The PST bit is enabled when the TRG bit in the AD0CON0 register is set to "0" (software trigger). Do not set the PST bit to "1" when the TRG bit is set to "1" (external trigger). 4. Set both A/D0 and A/D1 to the same setting. 5. If the ADS bit is set to "1", do not select single sweep mode or repeat sweep mode as the A/D operation mode. A/D0 Register i (i =0 to 7) b15 b8 b7 b0 Symbol AD00 to AD02 AD03 to AD05 AD06 to AD07 Address 038116 - 038016, 038316 - 038216, 038516 - 038416 038716 - 038616, 038916 - 038816, 038B16 - 038A16 038D16 - 038C16, 038F16 - 038E16 After Reset Indeterminate Indeterminate Indeterminate Function 8 low-order bits in an A/D conversion result In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its contents is indeterminate. RW RO RO Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Figure 17.4 AD0CON2 Register, AD00 to AD07 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 230 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter A/D1 Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD1CON0 Address 01D616 After Reset 0016 Bit Symbol CH0 Bit Name b2 b1 b0 Function 0 0 0 : ANi0 0 0 1 : ANi1 0 1 0 : ANi2 0 1 1 : ANi3 1 0 0 : ANi4 1 0 1 : ANi5 1 1 0 : ANi6 1 1 1 : ANi7 b4 b3 RW RW CH1 Analog Input Pin Select Bit(2, 3, 4, 5, 6) RW CH2 (i=0, 2, 15) RW MD0 A/D Operation Mode Select Bit 0(2) MD1 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 0 : Software trigger 1 : External trigger, hardware trigger(7) 0 : A/D conversion stops 1 : A/D conversion starts(7) 0 : Select from fAD/3 or fAD/4 1 : Select from fAD/1 or fAD/2 RW RW TRG Trigger Select Bit A/D Conversion Start Flag Frequency Select Bit(8) RW ADST RW CKS0 RW NOTES: 1. When the AD1CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Set analog input pins again after changing A/D operation mode. 3. This bit is disabled in single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. 4. The APS1 to APS0 bit in the AD1CON2 register select i=0, 2 or 15. 5. i=0 or 2 is available in single-chip mode only. 6. i=15 is available in the 144-pin package. 7. To set the TRG bit to "1", select the cause of trigger by setting the the TRG1 and TRG0 bits in the AD1CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". 8. AD frequency must be under 16 MHz when VCC=5V. AD frequency must be under 10 MHz when VCC=3.3V. Combination of the CKS0 and CKS1 bits selects AD. CKS0 0 0 1 1 CKS1 0 1 0 1 AD fAD divided by 4 fAD divided by 3 fAD divided by 2 fAD Figure 17.5 AD1CON0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 231 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter A/D1 Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD1CON1 Address 01D716 After Reset XX00 00002 Bit Symbol SCAN0 Bit Name b1 b0 Function RW A/D Sweep Pin Select Bit(2, 3, 4) SCAN1 A/D Operation Mode Select Bit 1 8/10-bit Mode Select Bit Frequency Select Bit(5) VREF Connection Bit RW 0 0 : ANi0,ANi1 (ANi0) 0 1 : ANi0 to ANi3 (ANi0,ANi1) 1 0 : ANi0 to ANi5 (ANi0 to ANi2) RW 1 1 : ANi0 to ANi7 (ANi0 to ANi3) (i=0, 2, 15) 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : Select from fAD/2 or fAD/4 1 : Select from fAD/1 or fAD/3 0 : VREF not connected(6) 1 : VREF connected RW MD2 BITS RW CKS1 RW VCUT RW (b7 - b6) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. When the AD1CON1 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. This bit is disabled in one-shot mode and repeat mode. Pins in parentheses are those most commonly used for A/D conversions when the MD2 bit is set to "1" (repeat sweep mode 1). 3. The APS1 to APS0 bits in the AD1CON2 register select i=0, 2 or 15. 4. i=15 is available in the 144-pin package. 5. AD frequency must be under 16 MHz when VCC=5V. AD frequency must be under 10 MHz when VCC=3.3V. Combination of the CKS0 and CKS1 bits selects AD (see the AD1CON0 register). 6. Do not set the VCUT bit to "0" during the A/D conversion. This is a reference voltage for the A/D1. It does not affect the D/A conversion. Figure 17.6 AD1CON1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 232 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter A/D1 Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD1CON2 Bit Symbol Address 01D416 After Reset X00X X0002 Bit Name A/D Conversion Method Select Bit Bit name RW SMP 0 : Without the sample and hold function RW 1 : With the sample and hold function b2 b1 APS0 Analog Input Port Select Bit APS1 0 0 : AN150 to AN157(2) 0 1 : Do not set to this value 1 0 : AN00 to AN07(3) 1 1 : AN20 to AN27(3) RW RW (b4 - b3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b6 b5 TRG0 External Trigger Request Cause Select Bit TRG1 0 0 : Selects ADTRG 0 1 : Selects a timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting) 1 0 : Selects the Intelligent I/O group 3 channel 1 interrupt 1 1 : Do not set to this value RW RW (b7) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. When the AD1CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. AN150 to AN157 are provided in the 144-pin package. 3. AN00 to AN07, AN20 to AN27 are available in single-chip mode only. A/D1 Register j (j=0 to 7) b15 b8 b7 b0 Symbol AD10 to AD12 AD13 to AD15 AD16 to AD17 Address 01C116 - 01C016, 01C316 - 01C216, 01C516 - 01C416 01CD16 - 01CC16, 01CF16 - 01CE16 After Reset Indeterminate Indeterminate 01C716 - 01C616, 01C916 - 01C816, 01CB16 - 01CA16 Indeterminate Function 8 low-order bits in an A/D conversion result In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its content is indeterminate. RW RO RO Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Figure 17.7 AD1CON2 Register, AD10 to AD17 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 233 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 17.1 Mode Description 17.1.1 One-shot Mode In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 17.4 lists specifications of one-shot mode. Table 17.4 One-shot Mode Specifications Item Function Start Condition Specification Analog voltage, applied to a pin selected by the CH2 to CH0 bits in the ADiCON0 register (i=0, 1), is converted to a digital code once. When the TRG bit in the ADiCON0 register is set to "0" (software trigger), • The ADST bit in the ADiCON0 register is set to "1" (A/D conversion starts) by program • The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a conversion simultaneously) by program When the TRG bit is set to "1" (external trigger, hardware trigger), __________ • A falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by program • One of the following interrupt requests is generated after the ADST bit is set to "1" by program: - The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 counter completes counting) is generated - The intelligent I/O interrupt request is generated Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1) Stop Condition • A/D conversion is completed (the ADST bit is set to "0" when the internal trigger is selected) • The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing A/D conversion is completed Analog Voltage Input Pins Reading of A/D Conversion Result Select one from AN0 to AN7, ANEX0, or ANEX1 Select one from ANj0 to ANj7 (j=0, 2, 15) The ADik register (k=0 to 7) corresponding to selected pin 17.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 17.5 lists specifications of repeat mode. Table 17.5 Repeat Mode Specifications Item Function Start Condition Stop Condition Specification Analog voltage, applied to a pin selected by the CH2 to CH0 bits in the ADiCON0 register (i=0, 1), is converted to a digital code once. Same as one-shot mode The ADST bit in the ADiCON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing Not generated Analog Voltage Input Pins Select one from AN0 to AN7, ANEX0, or ANEX1 Select from ANj0 to ANj7 (j=0, 2, 15) Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 234 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 17.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 17.6 lists specifications of single sweep mode. Table 17.6 Single Sweep Mode Specifications Item Function Start Condition Stop Condition Specification Analog voltage, applied to pins selected by the SCAN1 to SCAN0 bits in the ADiCON0 register (i=0, 1), are converted one-by-one to a digital code Same as one-shot mode • A/D conversion is completed (the ADST bit in the ADiCON0 register is set to "0" when the internal trigger is selected) • The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing Sweep operation is completed Analog Voltage Input Pins Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pins) Select from ANj0 (j=0, 2, 15) to ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to ANj7 (8 pins) Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins 17.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 17.7 lists specifications of repeat sweep mode 0. Table 17.7 Repeat Sweep Mode 0 Specifications Item Function Start Condition Stop Condition Analog Voltage Input Pins Specification Analog voltage, applied to pins selected by the SCAN1 to SCAN0 bits in the ADiCON0 register (i=0, 1), are repeatedly converted to a digital code Same as one-shot mode The ADST bit in the ADiCON0 register is set to "0" (A/D conversion stopped) by program Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pins) Select from ANj0 (j=0, 2, 15) to ANj1 (2 pins), ANj0 to ANj3 (4 pins), ANj0 to ANj5 (6 pins), or ANj0 to ANj7 (8 pins) Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins Interrupt Request Generation Timing Not generated Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 235 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 17.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a digital code. Table 17.8 lists specifications of repeat sweep mode 1. Table 17.8 Repeat Sweep Mode 1 Specifications Item Function Specification Analog voltage selectively applied to 8 pins selected by the SCAN1 to SCAN0 bits in the ADiCON1 register (i=0,1) is repeatedly converted to a digital code. e.g., When ANj0 is selected (j =none, 0, 2, 15), analog voltage is converted to a digital code in the following order: Start Condition Stop Condition ANj0 ANj1 ANj0 Same as one-shot mode ANij2 ANj0 ANj3 ....... etc. The ADST bit in the ADiCON1 register is set to "0" (A/D conversion stopped) by program ANj0 to ANj7 (8 pins) Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), or AN0 to AN3 (4 pins) Select from ANj0 (j=0, 2, 15) (1 pin), ANj0 to ANj1 (2 pins), AN0 to AN2 (3 pins), ANj0 to ANj3 (4 pins) Interrupt Request Generation Timing Not generated Analog Voltage Input Pins Prioritized Pins Reading of A/D Conversion Result The ADik register (k=0 to 7) corresponding to selected pins 17.2 Function 17.2.1 Resolution Select Function The BITS bit in the ADiCON1 (i=0, 1) register determines the resolution. When the BITS bit is set to "1" (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADij register (j = 0 to 7). When the BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADij register. 17.2.2 Sample and Hold When the SMP bit in the ADiCON2 register is set to "1" (with the sample and hold function), A/D conversion rate per pin increases to 28 ØAD cycles for 8-bit resolution and 33 ØAD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold function is to be used or not. 17.2.3 Trigger Select Function The TRG bit in the ADiCON0 register and the TRG1 to TRG0 bits in the ADiCON2 register determine the trigger to start the A/D conversion. Table 17.9 lists settings of the trigger select function. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 236 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter Table 17.9 Trigger Select Function Settings Bit and Setting ADiCON0 Register TRG = 0 ADiCON2 Register Software trigger The A/Di starts the A/D conversion when the ADST bit in the ADiCON0 register is set to "1" Two-circuit simultaneous start A/D0 and A/D1 start the A/D conversion simultaneously when the PST bit in the AD0CON2 register is set to "1" by program (Refer to 17.2.4 Two-Circuit Simultaneous Start) TRG = 1(1) TRG1 to TRG0 = 002 External trigger(2) __________ Trigger Falling edge of a signal applied to ADTRG TRG1 to TRG0 = 012 Hardware trigger(2) The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 counter completes counting) TRG1 to TRG0 = 102 Hardware trigger(2) The intelligent I/O interrupt request is generated Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1) i= 0,1 NOTES: 1. The A/Di starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is generated. 2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion. (The A/D conversion in process is aborted.) 17.2.4 Two-Circuit Simultaneous Start (Software Trigger) A/D0 and A/D1 start simultaneously when the PST bit in the AD0CON2 register is set to "1" (two-circuit simultaneous start). Do not set the PST bit to "1" while either A/D0 or A/D1 is performing an A/D conversion, or if the TRG bit is set "1" (external trigger). Do not set the ADST bit to "1" (A/D conversion started) when using the PST bit. 17.2.5 Pin Input Replacement Function When the ADS bit in the AD0CON2 register is set to "1" (channel replacement enabled), channels of the A/D0 can be replaced with channels of the A/D1 and vice versa. Voltage applied to the ANj (j = 0 to 7) pin is converted to digital code in the A/D1 and the conversion result is stored into the AD1j register. Voltage applied to the AN0j, AN2j or AN15j pin is converted to digital code in the A/D0 and the conversion results are stored into the AD0j register. To set the ADS bit to "1", set the MD1 to MD0 bits in the AD0CON0 register to "002" (one-shot mode) or "012" (repeat mode). Single sweep, repeat sweep 0, and repeat sweep 1 modes cannot be used. Set the OPA1 to OPA0 bits in the AD0CON1 register to "002" (no ANEX0 and ANEX1 used). Set the same value to both AD0CON0 register and AD1CON0 register, and to both AD0CON1 register and AD1CON1 register. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 237 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 17.2.6 Extended Analog Input Pins In one-shot mode and repeat mode, the ANEX0 and ANEX1 pins can be used as analog input pins. The OPA1 to OPA0 bits in the AD0CON1 register select which pins to use as analog input pins. An A/D conversion result for the ANEX0 pin is stored into the AD00 register. The result for the ANEX1 pin is stored into the AD01 register. 17.2.7 External Operation Amplifier (Op-Amp) Connection Mode In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using extended analog input pins ANEX0 and ANEX1. When the OPA1 to OPA0 bits in the AD0CON1 register are set to "112" (external op-amp connection), voltage applied to the AN0 to AN7 pins are output from ANEX0. Amplify this output signal by an external op-amp and apply it to ANEX1. Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the corresponding ADij register (i=0, 1; j=0 to 7). A/D conversion rate varies depending on the response of the external op-amp. Do not connect the ANEX0 pin to the ANEX1 pin directly. Figure 17.8 shows an example of an external op-amp connection. Table 17.10 Extended Analog Input Pin Settings AD0CON1 Register OPA1 0 0 1 1 OPA0 0 1 0 1 Not used P95 as an analog input Not used Output to an external op-amp Not used Not used P96 as an analog input Input from an external op-amp ANEX0 Function ANEX1 Function Microcomputer Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 Resistor ladder Successive conversion register ANEX1 External op-amp Comparator Figure 17.8 External Op-Amp Connection Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 238 of 488 M32C/83 Group (M32C/83, M32C/83T) 17. A/D Converter 17.2.8 Power Consumption Reducing Function When the A/D converter is not used, the VCUT bit in the ADiCON1 register (i=0, 1) isolates the resistor ladder of the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to "1" (VREF connection) before setting the ADST bit in the ADiCON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1" simultaneously, nor set the VCUT bit to "0" (no VREF connection) during the A/D conversion. The VCUT bit does not affect the VREF performance of the D/A converter. 17.2.9 Analog Input Pin and External Sensor Equivalent Circuit Figure 17.9 shows an example of the analog input pin and external sensor equivalent circuit. Microcomputer Sensor equivalent circuit R0 VIN C (2.0pF) VC R (7.8k ) Sampling time (the time needed until the capacitor is fully charged after closing switch) 3 Sample and hold function is enabled : φAD 2 Sample and hold function is disabled : φAD Figure 17.9 Analog Input Pin and External Sensor Equivalent Circuit Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 239 of 488 M32C/83 Group (M32C/83, M32C/83T) 18. D/A Converter 18. D/A Converter The D/A converter consists of two separate 8-bit R-2R ladder D/A converters. Digital code is converted to an analog voltage when a value is written to the corresponding DAi registers (i=0,1). The DAiE bit in the DACON register determines whether the D/A conversion result is output or not. Set the DAiE bit to "1" (output enabled) to disable a pull-up of a corresponding port. Output analog voltage (V) is calculated from value n (n=decimal) set in the DAi register. V = VREF x n (n = 0 to 255) 256 VREF : reference voltage (not related to VCUT bit setting in the ADiCON1 register) Table 18.1 lists specifications of the D/A converter. Table 18.2 lists pin settings of the DA0 and DA1 pins. Figure 18.1 shows a block diagram of the D/A converter. Figure 18.2 shows the D/A control register. Figure 18.3 shows a D/A converter equivalent circuit. When the D/A converter is not used, set the DAi register to "0016" and the DAiE bit to "0" (output disabled). Table 18.1 D/A Converter Specifications Item D/A Conversion Method Resolution Analog Output Pin Table 18.2 Pin Settings Port P93 P94 Function PD9 DA0 output DA1 output Register(1) PD9_3=0 PD9_4=0 Bit and Setting PS3 Register(1) PS3_3=0 PS3_4=0 PSL3 Register PSL3_3=1 PSL3_4=1 Specification R-2R 8 bits 2 channels NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.31 Jan.31, 2006 Page 240 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 18. D/A Converter Low-Order Bits of Data Bus DA0 Register DA0E 0 R-2R Resistor Ladder 1 DA0 DA1 Register DA1E 0 R-2R Resistor Ladder 1 DA0E, DA1E: Bits in the DACON register Figure 18.1 D/A Converter DA1 Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 241 of 488 M32C/83 Group (M32C/83, M32C/83T) 18. D/A Converter D/A Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit Symbol Address 039C16 After Reset XXXX XX002 Bit Name D/A0 Output Enable Bit Function 0 : Disables an output 1 : Enables an output 0 : Disables an output 1 : Enables an output RW RW DA0E DA1E D/A1 Output Enable Bit RW Nothing is assigned. When write, set to "0". (b7 - b2) When read, its content is indeterminate. D/A Register i (i=0, 1) b7 b0 Symbol DA0, DA1 Address 039816, 039A16 After Reset Indeterminate Function Output value of D/A conversion Setting Range 0016 to FF16 RW RW Figure 18.2 DACON Register, DA0 and DA1 Registers DA0E r DA0 "1" 2R MSB D/A register 0 AVSS VREF(4) NOTES: 1. The above applies when the DA0 register is set to "2A16". 2. This circuitry is the same for D/A1. 3. To reduce power consumption when the D/A converter is not used, set the DAiE bit (i=0, 1) to "0" (output disabled) and the DAi register to "0016" to stop current from flowing into the R-2R resistor. 4. This VREF is not related to VCUT bit setting in the AD0CON1 and AD1CON1 registers. 0 1 2R 2R 2R 2R 2R 2R 2R LSB "0" R R R R R R R 2R Figure 18.3 D/A Converter Equivalent Circuit Rev. 1.31 Jan.31, 2006 Page 242 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 19. CRC Calculation 19. CRC Calculation The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) generates CRC code. The CRC code is a 16-bit code generated for a block of data of desired length. This block of data is in 8-bit units. The CRC code is set in the CRCD register every time one-byte data is transferred to the CRCIN register after a default value is written to the CRCD register. CRC code generation for one-byte data is completed in two cycles. Figure 19.1 shows a block diagram of a CRC circuit. Figure 19.2 shows registers related to CRC. Figure 19.3 shows an example of the CRC calculation. High-order bits of data bus Low-order bits of data bus 8 low-order bits 8 highorder bits CRCD register CRC code generation circuit x16 + x12 + x5 + 1 CRCIN register Figure 19.1 CRC Calculation Block Diagram CRC Data Register b15 b8 b7 b0 Symbol CRCD Address 037D16- 037C16 After Reset Indeterminate Function After default value is written to the CRCD register, the CRC code can be read from the CRCD register by writing data to the CRCIN register. Bit position of the default value is inversed. The inversed value is read as the CRC code. Setting Range RW 000016 to FFFF16 RW CRC Input Register b7 b0 Symbol CRCIN Address 037E16 After Reset Indeterminate Function Data input. Inverse bit position of data. Setting Range 0016 to FF16 RW RW Figure 19.2 CRCD Register and CRCIN Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 243 of 488 M32C/83 Group (M32C/83, M32C/83T) 19. CRC Calculation CRC Calculation and Setup Procedure to Generate CRC Code for "80C416" CRC Calculation for M32C CRC Code : a remainder of a division, Generator Polynomial : X 16 value of the CRCIN register with inversed bit position generator polynomial +X 12 + X + 1 (1 0001 0000 0010 00012) 5 Setting Steps (1) Inverse a bit position of "80C416" per byte by program "8016" "0116", "C416" "2316" b15 b0 (2) Set "000016" (default value) b7 b0 CRCD register CRCIN register Bit position of the CRC code for "8016" (918816) is inversed to "118916", which is stored into the CRCD register in 3rd cycle. b15 b0 (3) Set "0116" 118916 b7 b0 CRCD register (4) Set "2316" CRCIN register Bit position of the CRC code for "80C416" (825016) is inversed to "0A4116", which is stored into the CRCD register in 3rd cycle. b15 b0 0A4116 CRCD register Details of CRC Calculation As shown in (3) above, bit position of "0116" (000000012) written to the CRCIN register is inversed and becomes "100000002". Add "1000 0000 0000 0000 0000 00002", as "100000002" plus 16 digits, to "000016" as the default value of the CRCD register to perform the modulo-2 division. 1000 1000 Modulo-2 Arithmetic is data 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 calculated on the law below. 1000 1000 0001 0000 1 0+0=0 1000 0001 0000 1000 0 0+1=1 Generator Polynomial 1000 1000 0001 0000 1 1+0=1 1001 0001 1000 1000 1+1=0 -1=1 CRC Code "0001 0001 1000 10012 (118916)", the remainder "1001 0001 1000 10002 (918816)" with inversed bit position, can be read from the CRCD register. When going on to (4) above, "2316 (001000112)" written in the CRCIN register is inversed and becomes "110001002". Add "1100 0100 0000 0000 0000 00002", as "110001002" plus 16 digits, to "1001 0001 1000 10002" as a remainder of (3) left in the CRCD register to perform the modulo-2 division. "0000 1010 0100 00012 (0A4116)", the remainder with inversed bit position, can be read from CRCD register. Figure 19.3 CRC Calculation Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 244 of 488 M32C/83 Group (M32C/83, M32C/83T) 20. XY Conversion 20. X/Y Conversion The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and inverses high-order bits and low-order bits of a 16-bit data. Figure 20.1 shows the XYC register. The 16-bit XiR register (i=0 to 15) and 16-bit YjR register (j=0 to 15) are allocated to the same address. The XiR register is a write-only register, while the YjR register is a read-only register. Access the XiR and YjR registers from an even address in 16-bit units. Performance cannot be guaranteed if the XiR and YiR registers are accessed in 8-bit units. X/Y Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol XYC Bit Symbol XYC0 Address 02E016 After Reset XXXX XX002 Bit Name Read-Mode Set Bit Function 0 : Data conversion 1 : No data conversion 0 : No bit alignment conversion 1 : Bit alignment conversion RW RW XYC1 Write-Mode Set Bit RW (b7 - b2) Noting is assigned. When write, set to "0". When read, its content is indeterminate. Figure 20.1 XYC Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 245 of 488 M32C/83 Group (M32C/83, M32C/83T) 20. XY Conversion The XYC0 bit in the XYC register determines how to read the YjR register. By reading the YjR register when the XYC0 bit is set to "0" (data conversion), bit j in the X0R to X15R registers can be read simultaneously. For example, bit 0 in the X0R register can be read if reading bit 0 in the Y0R register, bit 0 in the X1R register if reading bit 1 in the Y0R register..., bit 0 in the X14R register if reading bit 14 in the Y0R register and bit 0 in the X15R register if reading bit 15 in the Y0R register. Figure 20.2 shows the conversion table when the XYC0 bit is set to "0". Figure 20.3 shows an example of the X/Y conversion. Address to be read Y15R register Y14R register Y13R register Y12R register Y11R register Y10R register Y9R register Y8R register Y7R register Y6R register Y5R register Y4R register Y3R register Y2R register Y1R register Y0R register Address to be written b15 Bits in the XiR register b0 Figure 20.2 Conversion Table when Setting the XYC0 Bit to "0" b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register Y0R register Y1R register Y2R register Y3R register Y4R register Y5R register Y6R register Y7R register Y8R register Y9R register Y10R register Y11R register Y12R register Y13R register Y14R register Y15R register Figure 20.3 X/Y Conversion Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 246 of 488 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register b0 Bits in the YjR register M32C/83 Group (M32C/83, M32C/83T) 20. XY Conversion By reading the YjR register when the XYC0 bit in the XYC register is set to "1" (no data conversion), the value written to the XiR register can be read directly. Figure 20.4 shows the conversion table when the XYC0 bit is set to "1." Address to be written Address to be read X0R register, Y0R register X1R register, Y1R register X2R register, Y2R register X3R register, Y3R register X4R register, Y4R register X5R register, Y5R register X6R register, Y6R register X7R register, Y7R register X8R register, Y8R register X9R register, Y9R register X10R register, Y10R register X11R register, Y11R register X12R register, Y12R register X13R register, Y13R register X14R register, Y14R register X15R register, Y15R register b15 Bits in the XiR register Bits in the YjR register b0 i=0 to 15 j=0 to 15 Figure 20.4 Conversion Table when Setting the XYC0 Bit to "1" The XYC1 bit in the XYC register selects bit alignment of the value in the XiR register. By writing to the XiR register while the XYC1 bit is set to "0" (no bit alignment conversion), bit alignment is written as is. By writing to the XiR register while the XYC1 bit is set to "1" (bit sequence replaced), bit alignment is written inversed. Figure 20.5 shows the conversion table when the XYC1 bit is set to "1". b15 b0 Data to be written b15 b0 Bits in XiR register (i=0 to 15) Figure 20.5 Conversion Table when Setting the XYC1 Bit to "1" Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 247 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O 21. Intelligent I/O The intelligent I/O is a multifunctional I/O port for time measurement, waveform generation, clock synchronous serial I/O, clock asynchronous serial I/O (UART), IEBus(1) communications, HDLC data processing and more. The intelligent I/O consists of four groups. Each group has one 16-bit base timer for free-running operation, eight 16-bit registers for time measurement and waveform generation and two 8-bit shift registers (or one 16-bit shift register) for communications. Table 21.1 lists functions and channels of the intelligent I/O. NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. Table 21.1 Intelligent I/O Functions and Channels Function Time Measurement(1) Digital Filter Trigger Input Prescaler Trigger Input Gate Waveform Generation Single-phase Waveform Output Phase-delayed Waveform Output SR Waveform Output Bit Modulation PWM Mode RTP Mode Parallel RTP Mode Communication Clock Synchronous Serial I/O Mode UART Mode HDLC Data Processing Mode IEBus Mode Not Available Available 8 bits fixed Variable Available Not Available Available 8 or 16 bits Available Not Available Not Available Not Available Not Available Not Available Available Available Available Available Not Available Available Group 0 Group 1 Group 2 Group 3 Group 0, 1 cascaded 8 channels (3 channels) Not Available 8 channels (3 channels) 2 channels 2 channels 8 channels 8 channels 8 channels (3 channels) (2 channels) (3 channels) 8 channels 4 channels (3 channels)(2) (2 channels) 8 channels (3 channels) 2 channels 2 channels 4 channels (2 channels) 4 channels Not (2 channels) Available 2 channels 2 channels 8 channels (3 channels) NOTES: 1. Time measurement function and waveform generation function share pins 2. The number of channels available in the 100-pin package are indicated in parentethese ( ). The time measurement function and waveform generation function can be selected for each channel. The communication function is available by a combination of multiple channels. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 248 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Figures 21.1 to 21.4 show block diagram of the intelligent I/O groups 0 to 3. Request from the group1 Request from the INT pin Request by matching the base timer with the G0PO0 register Group0 base timer reset BT0S BTS f1 Two-phase pulse signal is applied 11 10 Reset BCK1 to BCK0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 10 : fBT0 00 11 : f1 Digital filter DF1 to DF0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 00 10 : fBT0 Digital 11 : f1 filter DF1 to DF0 Divider by 2(n+1) DIV4 to DIV0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 0 fBT0 Base timer Base timer interrupt request(3) Overflow of base timer bit 15 INPC00 G0TM0, G0PO0 register PWM output G0TM1, G0PO1 register G0TM2, G0PO2 register PWM output G0TM3, G0PO3 register G0TM4, G0PO4 register PWM output G0TM5, G0PO5 register 0 000 to 010 MOD2 to MOD0 OUTC00/ISTxD0 111 INPC01 / ISCLK0 INPC02 / ISRxD0 000 to 010 111 MOD2 to MOD0 OUTC01/ISCLK0 INPC03 INPC04 OUTC04 (Note 1) OUTC05 (Note 1) INPC05 INPC06 Edge Gate select function 1 GT CTS1 to CTS0 0 Prescaler function 1 PR 0 G0TM6, G0PO6 register INPC07 Gate Edge function 1 select GT CTS1 to CTS0 Prescaler function 1 PR G0TM7, G0PO7 register Ch0 to ch7 interrupt request signal Waveform generation match signal for group1 (For cascaded connection) Time measurement trigger for the group1 (For cascaded connection) Transmit interrupt request SOF generation circuit G0TB register (Transmit buffer register) Transmit buffer Transmit register Transmit data generation circuit Transmission (SIO0TR)(3) Bit insert circuit G0TCRC register Transmit latch Data selector 1 TXSL 0 Polarity inverse OPOL ch0 Transmit ch3 Clock operation clock External clock selector Clock wait control circuit Start bit generation circuit Stop bit generation circuit G0TO register Transmit register Transmit buffer HDLC data transmit interrupt request (G0TOR)(3) ch1 ch2 Clock ch3 selector External clock Receive operation clock Arbitration Reception G0RI register Receive buffer Receive register 1 G0RCRC register Receive data generation circuit Data selector G0RB register Receive buffer Receive register 0 Polarity inverse RXSL IPOL G0DR register (Receive data register) Shift register Buffer register Bit insert check Start bit check Stop bit check (SIO0RR)(3) Receive interrupt request Special interrupt check Special communication interrupt request (SRT0R)(3) G0CMP3 register G0CMP3 register G0CMP3 register G0CMP3 register Comparator Comparator Comparator Comparator HDLC data receive interrupt request NOTES: 1. These pins are not connected to external pins in the 100-pin package. 2. Each register enters a reset state after the G0BCR0 register supplies the clock. 3. See Figure 10.14. (G0RIR) DIV4 to DIV0 bits, BCK1 to BCK0 bits : Bits in the G0BCR0 register BTS : Bit in the G0BCR1 register BT0S : Bit in BTSR register CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G0TMCRj register (j = 0 to 7) MOD2 to MOD0 : Bits in the G0POCRj register TXSL, RXSL : Bits in the G0EMR register OPOL, IPOL : Bits in the G0CR register (3) Figure 21.1 Intelligent I/O Group 0 Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 249 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Request from the group0 Request by matching the base timer with the G1PO0 register Group1 base timer reset overflow of bit 15 in the group0 base timer BT1S BTS BCK1 to BCK0 f1 Two-phase pulse signal is applied 11 10 Request from the INT pin Divider by 2(n+1) DIV4 to DIV0 fBT1 1 0 Base timer Base timer interrupt request (BT1R) Overflow of bit 15 in the base timer (4) Waveform generation match signal from the group 0 (For cascaded connection) Time measurement trigger from the group 0 (For cascaded connection) 1 0 1 G1TM0, G1PO0 (Note 1) register PWM output G1TM1, G1PO1 register G1TM2, G1PO2 register PWM output G1TM3, G1PO3 register G1TM4, G1PO4 register PWM output G1TM5, G1PO5 register 000 to 010 MOD2 to MOD0 OUTC10/ISTxD1/ BE1OUT 111 INPC11 / ISCLK1 INPC12 / ISRxD1 00 10 : fBT1 Digital 11 : f1 filter DF1 to DF0 00 10 : fBT1 Digital 11 : f1 filter DF1 to DF0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 0 1 0 1 0 1 0 000 to 010 111 OUTC11/ISCLK1 MOD2 to MOD0 OUTC12 OUTC13 OUTC14 1 0 OUTC15 (Note 2) INPC16 10 : fBT1 Digital 11 : f1 filter DF1 to DF0 10 : fBT1 Digital 11 : f1 filter DF1 to DF0 00 00 0 0 (Note 2) INPC17 Gate Edge function select CTS1 to CTS0 1 GT 0 Prescaler function 1 0 PR 0 1 1 G1TM6, G1PO6 register PWM output OUTC16 Edge select Gate 1 function GT Prescaler function 0 PR 1 G1TM7, G1PO7 register OUTC17 CTS1 to CTS0 CAS Ch0 to ch7 interrupt request signal Transmit interrupt request (SIO1TR)(4) SOF G1TB register (Transmit buffer register) Transmit buffer Transmit register generation circuit Bit insert circuit Transmit data generation circuit Transmission G1TCRC register Transmit latch Start bit generation circuit Stop bit generation circuit Data selector TXSL 0 Polarity inverse OPOL ch0 ch3 External clock Transmit Clock operation clock selector Clock wait control circuit 1 G1TO register Transmit register Transmit buffer ch1 ch2 ch3 External clock HDLC data transmit interrupt request (G1TOR)(4) Clock selector Receive operation clock Arbitration G1RCRC register Reception G1RI register Receive buffer 0 Receive data generation circuit Data selector G1RB register Receive buffer Receive register Receive register 1 Polarity inverse RXSL IPOL G1DR register (Receive data register) Shift register buffer register Bit insert check Start bit check Stop bit check (SIO1RR)(4) Receive interrupt request Special interrupt check Special communication interrupt request (SRT1R)(4) G1CMP3 register G1CMP3 register G1CMP3 register G1CMP3 register Comparator Comparator Comparator Comparator HDLC data receive interrupt request NOTES: 1. The G1TM0 register can be used in a 32-bit cascaded connection only. 2. These pins are not connected to external pins in the 100-pin package. 3. Each register is in a reset state after the G1BCR0 register supplies the clock. 4. See Figure 10.14. DIV4 to DIV0, BCK1 to BCK0 : Bits in the G1BCR0 register CAS, BTS : Bits in the G1BCR1 register BT1S : Bit in the BTSR register CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj register (j = 0 to 7) MOD2 to MOD0 : Bits in the G1POCRj register TXSL, RXSL : Bits in the G1EMR register (G1RIR)(4) Figure 21.2 Intelligent I/O Group 1 Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 250 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Request from the group1 Request from the communication function BT2S BTS BCK1 to BCK0 Request by matching the base timer with the G2PO0 register Group2 base timer reset f1 11 Divider fBT2 by 2(n+1) DIV4 to DIV0 Base timer Base timer interrupt request BT2R(3) Overflow of bit 15 in the base timer Real time port output value 000 to 010, MOD2 to MOD0 100 OUTC20 ISCLK2 0 G2PO0 register Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM IEIN /ISRxD2 Digital filter 1 DF PWM output control /ISTxD2/IEOUT 111 000 to 010, MOD2 to MOD0 100 111 G2PO1 register OUTC21 /ISCLK2 G2PO2 register OUTC22 PWM output control OUTC23 G2PO3 register G2PO4 register OUTC24 PWM output control OUTC25 (Note 1) G2PO5 register Bit modulation PWM G2PO6 register Bit modulation PWM OUTC26 PWM output control OUTC27 G2PO7 register Bit modulation PWM Waveform generation interrupt request PO2jR(3) G2TB register Clock selector Bit counter Transmit register Output control function OPOL Transmit parity calculation Byte counter Transmit latch Polarity inverse ACK calculation Start bit detection IPOL Polarity inverse Arbitration lost detection IE start bit interrupt request (IE0R to IE2R)(3) Receive parity calculation IE, serial I/O interrupt control IE transmit interrupt request (IE0R to IE2R)(3) IE receive interrupt request (IE0R to IE2R)(3) Clock synchronous serial I/O mode transmit interrupt request (SIO2TR)(3) Clock synchronous serial I/O mode receive interrupt request (SIO2RR)(3) Receive register G2RB register ID detection ALL "F" detection Address detect function Statement length detect function NOTES: 1. In the 100-pin package, these pins are not connected to external pins. 2. Each register enters a reset state after the G2BCR0 register supplies the clock. 3. See Figure 10.14. DIV4 to DIV0, BCK1 to BCK0 : Bits in the G2BCR0 register BTS : Bit in the G2BCR1 register BT2S : Bit in the BTSR register OPOL, IPOL : Bits in the G2CR register DF : Bit in the IECR register MOD2 to MOD0 : Bits in the G2POCRj register (j = 0 to 7) Figure 21.3 Intelligent I/O Group 2 Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 251 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Request from group2 Request from communication function BT3S BTS Request by matching the base timer with the G3PO0 register Group3 base timer reset Reset BCK1 to BCK0 f1 11 Divider fBT3 by 2(n+1) DIV4 to DIV0 Base timer Base timer interrupt request (BT3R)(3) Overflow of the bit 15 in the base timer Real time port output value 000 to 010, 100 MOD2 to MOD0 G3PO0 register Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM Bit modulation PWM OUTC30/ISTxD3 111 MOD2 to MOD0 PWM output control 000 to 010, 100 ISCLK3(1) G3PO1 register OUTC31/ISCLK3(1) 111 ISRxD3 G3PO2 register OUTC32 PWM output control OUTC33 G3PO3 register G3PO4 register G3MK4 register G3PO5 register G3MK5 register OUTC34 PWM output control OUTC35 (Note 1) Bit modulation PWM G3PO6 register G3MK6 register G3PO7 register G3MK7 register Bit modulation PWM OUTC36 PWM output control OUTC37 Waveform generation interrupt request (PO3jR)(3) OPOL Bit modulation PWM Transmission Clock selector G3TB register Transmit Shift register Shift counter Polarity inverse Transmit interrupt request (SIO3TR)(3) Transmit operation clock Mode controller Reception Receive operation clock Mode controller Receive interrupt request (SIO3RR)(3) Shift counter IPOL Polarity inverse Receive shift register G3RB register NOTES: 1. In the 100-pin package, these pins are not connected to external pins. 2. Each register enters a reset state after the G3BCR0 register supplies the clock. DIV4 to DIV0, BCK1 to BCK0 : Bits in the G3BCR0 register BTS : Bit in the G3BCR1 register BT3S : Bit in the BTSR register MOD2 to MOD0 : Bits in the G3POCRj register (j = 0 to 7) OPOL, IPOL : Bits in the G3CR register Figure 21.4 Intelligent I/O Group 3 Block Diagram Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 252 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Figures 21.5 to 21.15 show registers associated with the intelligent I/O base timer, the time measurement function and waveform generation function. (For registers associated with the communication function, see Figures 21.32 to 21.38, Figures 21.42 to 21.45, Figures 21.47 to 21.49.) Group i Base Timer Register (i=0 to 3)(2) b15 b8 b7 b0 Symbol G0BT,G1BT G2BT,G3BT Address 00E116 - 00E016, 012116 - 012016 016116 - 016016, 01A116 - 01A016 After Reset Indeterminate Indeterminate Function When the base timer is counting: When read, the value of the counter can be read. When write, the counter starts counting from the value written. When the base timer is reset, the GiBT register is set to "000016"(1). When the base timer is reset: The GiBT register is set to "000016" but the value is indeterminate. No value is written(1). Setting Range RW 000016 to FFFF16 RW NOTES: 1. Each base timer stops only when the BCK1 to BCK0 bits in the GiBCR0 register are set to "002" (clock stopped). The base timer counts when the BCK1 to BCK0 bits are set to a value other than "002". When the BTiS bit in the BTSR register and the BTS bit in the GiBCR1 register are set to "0", the base timer is reset continually, remaining set to "000016". This, in effect, places the base timer in a "no counting" state. When either BTiS bit or BTS bit is set to "1", this state is cleared and counting starts. 2. The GiBT register reflects the value of the base timer with a delay of one half fBTi cycle. Group i Base Timer Control Register 0 (i=0 to 3)(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G0BCR0 to G3BCR0 Address 00E216, 012216, 016216, 01A216 After Reset 0016 Bit Symbol BCK0 Bit Name b1 b0 Function 0 0 1 1 RW Count Source Select Bit BCK1 RW 0 : Clock stops 1 : Do not set to this value 0 : Two-phase pulse signal is applied(2) RW 1 : f1 RW DIV0 If setting value is n (n = 0 to 31), count source is divided by 2(n + 1). No division if n=31. b6 b5 b4 b3 b2 DIV1 Count Source Divide Ratio Select Bit (n=0) 0 0 0 0 0 : Divide-by-2 (n=1) 0 0 0 0 1 : Divide-by-4 (n=2) 0 0 0 1 0 : Divide-by-6 : (n=30) 1 1 1 1 0 : Divide-by-62 (n=31) 1 1 1 1 1 : No division RW DIV2 RW DIV3 RW DIV4 Base Timer Interrupt Select Bit 0 : Bit 15 overflows 1 : Bit 14 overflows RW IT RW NOTES: 1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement, waveform generation function), set the G0BCR0 register and G1BCR0 register to the same value. 2. This setting can be used only when the UD1 to UD0 bits in the GjBCR1 register (j=0, 1) of group 0 or 1 are set to "102" (two-phase signal processing mode). Do not set the BCK1 to BCK0 bits to "102" in other modes or in group 2 or 3. Figure 21.5 G0BT to G3BT Register and G0BCR0 to G3BCR0 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 253 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group i Base Timer Control Register 1 (i=0,1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol 0 G0BCR1, G1BCR1 Bit Symbol RST0 Address 00E316, 012316 After Reset 0016 Bit Name Base Timer Reset Cause Select Bit 0 Function RW 0: The base timer is not reset by synchronizing with the base timer reset RW 1: The base timer is reset by synchronizing with the base timer reset(1) 0: The base timer is not reset by matching with the GiPO0 register 1: The base timer is reset by matching with the GiPO0 register(2) 0: The base timer is not reset by applying "L" to the INTi pin 1: The base timer is reset by applying "L" to the INTi pin(3) Set to "0" 0: Base timer is reset 1: Base timer starts counting b6 b5 RST1 Base Timer Reset Cause Select Bit 1 RW RST2 Base Timer Reset Cause Select Bit 2 RW (b3) BTS Reserved Bit Base Timer Start Bit(5, 6) RW RW UD0 UD1 RW 0 0 : Counter increment mode 0 1 : Counter increment/decrement mode Counter Increment/ : Two-phase pulse signal processing Decrement Control Bit 1 0 mode(7) RW : Do not set to this value 11 0: 16-bit time measurement or Groups 0 and 1 waveform generation function Cascaded Connection 1: 32-bit time measurement or Function Select Bit waveform generation function(4) CAS RW NOTES: 1. In group 0, the base timer is reset by synchronizing with the group 1 base timer reset. In group 1, the base timer is reset by synchronizing with the group 0 base timer reset. 2. The base timer is reset two fBTi clock cycles after the base timer matches the value set in the GiPO0 register. (See Figure 21.13 for details on the GiPO0 register.) When the RST1 bit is set to "1", the value of the GiPOj register (j=1 to7) for the waveform generation function and communication function must be set to a smaller value than that of the GiPO0 register. 3. In group 0, the base timer is reset when "L" is applied to the INT0 pin. In group 1, the base timer is reset when "L" is applied to the INT1 pin. 4. When the CAS bit is set to "1" (32-bit time measurement, waveform generation function), set the G0BCR1 register to "8116" and the G1BCR1 register to "1000 0XX02". 5. When starting the group 0 or 1 base timer separately, set the BTS bit to "1" after the BTkS bit (k=0 to 1) in the BTSR register is set to "0". 6. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS bit to "0". 7. In two-phase pulse signal processing mode, the base timer is not reset, even when the RST1 bit is set to "1", if the counter is decremented two clock cycles after the base timer matches the value set in the GiPO0 register Figure 21.6 G0BCR1 and G1BCR1 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 254 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group 2 Base Timer Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol 00 0 G2BCR1 Bit Symbol Address 016316 After Reset 0016 Bit Name Base Timer Reset Cause Select Bit 0 Base Timer Reset Cause Select Bit 1 Base Timer Reset Cause Select Bit 2 Reserved Bit Base Timer Start Bit(3, 4) Reserved Bit Function RW RST0 0 : The base timer is not reset by synchronizing with the group 1 base timer reset RW 1 : The base timer is reset by synchronizing with the group 1 base timer reset 0 : The base timer is not reset by matching with the G2PO0 register 1 : The base timer is reset by matching with the G2PO0 register(1) 0 : The base timer is not reset by a reset request from the communication function 1 : The base timer is reset by a reset request from the communication function Set to "0" 0 : Base timer is reset 1 : Base timer starts counting Set to "0" RST1 RW RST2 RW (b3) BTS RW RW (b6 - b5) PRP RW Parallel Real-Time 0 : RTP output mode Port Function 1 : Parallel RTP output mode (2) Select Bit RW NOTES: 1. The base timer is reset two fBT2 clock cycles after the base timer matches the value set in the G2PO0 register. (See Figure 21.13 for details on the G2PO0 register.) When the RST1 bit is set to "1", the value of the G2POi register (i=1 to7), for the waveform generation function and communication function, must be set to a smaller value than that of the G2PO0 register. 2. The PRP bit is valid when the RTP bit in the G2POCRi register is set to "1" (not used) 3. When starting the group 2 base timer, set the BTS bit to "1" after the BT2S bit in the BTSR register is set to "0". 4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS bit to "0". Figure 21.7 G2BCR1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 255 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group 3 Base Timer Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol 00 0 G3BCR1 Bit Symbol Address 01A316 After Reset 0016 Bit Name Base Timer Reset Cause Select Bit 0 Base Timer Reset Cause Select Bit 1 Base Timer Reset Cause Select Bit 2 Reserved Bit Function RW RST0 0 : The base timer is not reset by synchronizing with the group 2 base timer reset RW 1 : The base timer is reset by synchronizing with the group 2 base timer reset 0 : The base timer is not reset by matching with the G3PO0 register 1 : The base timer is reset by matching with the G3PO0 register(1) 0 : The base timer is not reset by a reset request from the communication function 1 : The base timer is reset by a reset request from the communication function Set to "0" 0 : Base timer is reset 1 : Base timer starts counting Set to "0" RW RST1 RST2 RW RW (b3) BTS Base Timer Start Bit(3, 4) Reserved Bit RW (b6 - b5) PRP RW RW Parallel Real-Time 0 : RTP output mode Port Function 1 : Parallel RTP output mode (2) Select Bit NOTES: 1. The base timer is reset after two fBT3 clock cycles after the base timer matches the value set in the G3PO0 register. (See Figure 21.13 for details on the G3PO0 register.) When the RST1 bit is set to "1", the value of the G3POi register (i=1 to7), for the waveform generation function and communication function, must be set to a smaller value than that of the G2PO0 register. 2. The PRP bit is valid when the RTP bit in the G3POCRi register is set to "1" (not used) 3. When starting the group 3 base timer, set the BTS bit to "1" after the BT3S bit in the BTSR register is set to "0". 4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the BTS bit to "0". Figure 21.8 G3BCR1 Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 256 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Base Timer Start Register(1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol BTSR Bit Symbol BT0S Address 016416 After Reset XXXX 00002 Bit Name Group 0 Base Timer Start Bit Group 1 Base Timer Start Bit Group 2 Base Timer Start Bit Group 3 Base Timer Start Bit Function 0 : Base timer reset 1 : Base timer starts counting 0 : Base timer reset 1 : Base timer starts counting 0 : Base timer reset 1 : Base timer starts counting 0 : Base timer reset 1 : Base timer starts counting RW RW BT1S RW BT2S RW BT3S RW (b7 - b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. Set registers as follows before using the intelligent I/O: (1) Set the G2BCR0 register to supply the clock to the group 2 base timer (2) Set all BT0S to BT3S bits in the BTSR register to "0" (base timer reset) (3) Set other registers associated with the intelligent I/O The BTiS bit (i=0 to 3) allows the base timers in multiple groups to start counting simultaneously. When starting the base timers separately, set the BTiS bit to "0" before setting the BTS bit in the GiBCR1 register. 2. Use the following procedure to start base timers in multiple groups simultaneously (including groups 1 and 2 cascaded connections). This procedure is not required when starting the base timers individually. • Set the BCK1 to BCK0 bits and DIV4 to DIV0 bits in the GiBCR0 register (i=0 to 3) of the groups to be started simultaneously, to the same value. • After the BCK1 to BCK0 bits or DIV4 to DIV0 bits are changed, use the following procedure to start the base timer twice. (1) Set the BTiS bit in the BTSR register to "1" (base timer starts counting). (2) Set the BTiS bit to "0" (base timer stops counting) after one fBTi clock cycle. (3) After waiting at least one additional fBTi clock cycle, set the BTiS bit to "1" (base timer starts counting). Figure 21.9 BTSR Register Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 257 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group i Time Measurement Control Register j (i=0,1; j=0 to 7)(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G0TMCR0 to G0TMCR3 G0TMCR4 to G0TMCR7 G1TMCR0 to G1TMCR3 G1TMCR4 to G1TMCR7 Address 00D816, 00D916, 00DA16, 00DB16 00DC16, 00DD16, 00DE16, 00DF16 011816, 011916, 011A16, 011B16 011C16, 011D16, 011E16, 011F16 After Reset 0016 0016 0016 0016 Bit Symbol CTS0 Bit Name b1 b0 Function 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : No time measurement : Rising edge : Falling edge : Both edges : No digital filter : Do not set to this value : fBTi : f1 RW RW Time Measurement Trigger Select Bit CTS1 RW b3 b2 DF0 Digital Filter Function Select Bit DF1 Gate Function Select Bit(2, 4) Gate Function Clear Select Bit(2, 3, 5) Gate Function Clear Bit(2, 3) Prescaler Function Select Bit(2) RW RW GT 0 : Gate function is not used 1 : Gate function is used RW GOC 0 : Not cleared 1 : The gate is cleared when the base RW timer matches the GiPOk register The gate is cleared by setting the GSC bit to "1" 0 : Not used 1 : Used RW GSC PR RW NOTES: 1. If the CAS bit in the GiBCR1 register is set to "0" (16-bit time measurement function), the G1TMCR0 and G1TMCR3 to G1TMCR5 registers cannot be used. When write, set these registers to "0016". If the CAS bit is set to "1" (32-bit time measurement function), set the same values in the G0TMCRj and G1TMCRj registers. 2. These bits are in the GiTMCR6 and GiTMCR7 registers. Set all bits 4 to 7 in the GiTMCR0 to GiTMCR5 registers to "0". 3. These bits are enabled only when the GT bit is set to "1" 4. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), set the GT bit to "0". The gate function cannot be used. 5. The GOC bit is set to "0" after the gate function is cleared. See Figure 18.13 for details on the GiPOk register (k=4 when j=6; k=5 when j=7). Group i Time Measurement Prescale Register j (i=0,1; j=6,7) b7 b0 Symbol G0TPR6 to G0TPR7 G1TPR6 to G1TPR7 Address 00E416, 00E516 012416, 012516 After Reset 0016 0016 Function If the setting value is n, the value of the base timer is stored into GiTMj register whenever a trigger input is counted by n+1(1) Setting Range 0016 to FF16 RW RW NOTES: 1. The first prescaler, after the PR bit in the GiTMCRj register is changed from "0" (prescaler function used) to "1" (prescaler function not used), may be divided by n rather than n+1. The subsequent prescaler is divided by n+1. Figure 21.10 G0TMCR0 to G0TMCR7, G1TMCR0 to G1TMCR7, G0TPR6, G0TPR7, G1TPR6, and G1TPR7 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 258 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group i Time Measurement Register j (i=0,1; j=0 to 7) b15 b8 b7 b0 Symbol G0TM0 to G0TM2 G0TM3 to G0TM5 G0TM6 to G0TM7 G1TM0 to G1TM2 G1TM3 to G1TM5 G1TM6 to G1TM7 Address 00C116 - 00C016, 00C316 - 00C216, 00C516 - 00C416 00C716 - 00C616, 00C916 - 00C816, 00CB16 - 00CA16 00CD16 - 00CC16, 00CF16 - 00CE16 010116 - 010016, 010316 - 010216, 010516 - 010416 010716 - 010616, 010916 - 010816, 010B16 - 010A16 010D16 - 010C16, 010F16 - 010E16 After Reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function The value of the base timer is stored every trigger input. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), 16 low-order bits are stored into the G0TMj register and 16 high-order bits are into stored the G1TMj register. Setting Range RW RO Group i Waveform Generation Control Register j (i=0 to 1; j=0 to 7)(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G0POCR0 to G0POCR3 G0POCR4 to G0POCR7 G1POCR0 to G1POCR3 G1POCR4 to G1POCR7 Address 00D016, 00D116, 00D216, 00D316 00D416, 00D516, 00D616, 00D716 011016, 011116, 011216, 011316 011416, 011516, 011616, 011716 After reset 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 Bit Symbol MOD0 Bit Name b2 b1b0 Function 0 0 0 : Single waveform output mode 0 0 1 : SR waveform output mode(2) 0 1 0 : Phase-delayed waveform output mode 0 1 1 : Do not set to this value 1 0 0 : Do not set to this value 1 0 1 : Do not set to this value 1 1 0 : Do not set to this value(3) 1 1 1 : Use a communication function output(4) RW RW MOD1 Operation Mode Select Bit RW MOD2 RW (b3) IVL Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Output Initial Value Select Bit 0: Outputs "L" as default value 1: Outputs "H" as default value RW RLD 0: Reloads the GiPOj register when GiPOj Register Value value is written Reload Timing Select Bit 1: Reloads the GiPOj register when the base timer is reset Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Inverse Output Function 0: Output is not inversed Select Bit(5) 1: Output is inversed RW (b6) INV RW NOTES: 1. Groups 0 and 1 have 16-bit and 32-bit waveform generation functions. If the CAS bit in the GiBCR1 register is set to "0" (16-bit waveform generation function), the G0POCR2 to G0POCR3 and G0POCR 6 to G0POCR7 registers cannot be used. When write, set these registers to "0016". If the CAS bit is set to "1" (32-bit waveform generation function), set the same values in the G0POCRj and G1POCRj registers. 2. This setting is valid only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels output waveforms. Odd channels output no waveform. 3. To receive data in UART mode of group 0 and 1, set the GiPOCR2 register to "0000 01102". 4. This setting is valid only for channels 0 and 1. To use ISTxDi, set the MOD2 to MOD0 bits in the GiPOCR0 register to "1112". To use ISCLKi for an output, set the MOD2 to MOD0 bits in the GiPOCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0 and 1 and for the communication function. 5. The inverse output function is the final step in the waveform generation process. If the INV bit is set to "1", the output signal is "H" when the IVL bit is set to "0" and "L" when the IVL bit is set to "1". Figure 21.11 G0TM0 to G0TM7, G1TM0 to G1TM7, Registers and G0POCR0 to G0POCR7, G1POCR0 to G1POCR7 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 259 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group i Waveform Generation Control Register j (i=2 to 3; j=0 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G2POCR0 to G2POCR3 G2POCR4 to G2POCR7 G3POCR0 to G3POCR3 G3POCR4 to G2POCR7 Address 015016, 015116, 015216, 015316 015416, 015516, 015616, 015716 019016, 019116, 019216, 019316 019416, 019516, 019616, 019716 After Reset 0016 0016 0016 0016 Bit Symbol MOD0 Bit Name b2 b1b0 Function RW MOD1 Operation Mode Select Bit(5) MOD2 Parallel Real-time Port Output Trigger Select Bit(4) Output Initial Value Select Bit GiPOj Register Value Reload Timing Select Bit Real-time Port Function Select Bit 0 0 0 : Single waveform output mode RW 0 0 1 : SR waveform output mode(1) 0 1 0 : Inverse waveform output mode 0 1 1 : Do not set to this value RW 1 0 0 : Bit-modulation PWM mode 1 0 1 : Do not set to this value 1 1 0 : Do not set to this value 1 1 1 : Use a communication function RW output(2) 0: Not triggered by matching the base timer with the GiPO0 to GiPO7 registers 1: Triggered by matching the base timer RW with the GiPO0 to GiPO7 registers 0: Outputs "L" as default value 1: Outputs "H" as default value 0: Reloads the GiPOj register when counter is written to 1: Reloads the GiPOj register when the base timer is reset RW PRT IVL RLD RW RTP INV 0: Not used 1: Used (RTP output mode or parallel RW RTP output mode) RW Inverse Output Function 0: Output is not inversed Select Bit(3) 1: Output is inversed NOTES: 1. This setting is valid only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels output waveforms. Odd channels output no waveforms. 2. This setting is valid only for channels 0 and 1 in the groups 2 and 3. To use ISTxD2 or IEOUT, set the MOD2 to MOD0 bits in the G2POCR0 register to "1112". To use ISCLK2 for an output, set the MOD2 to MOD0 bits in the G2POCR1 register to "1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0 and 1. To use ISTxD3, set the MOD2 to MOD0 bits in the G3POCR0 register to "1112". To use ISCLK3 for an output, set the MOD2 to MOD0 bits in the G3POCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in the channels 0 and 1. 3. The inverse output function is the final step in the waveform generation process. If the INV bit is set to "1" (output inversed), the output signal is "H" when the IVL bit is set to "0" (outputs "L" as an initial value) and "L" when the IVL bit is set to "1" (outputs "H" as an initial value). 4. The PRT bit is valid when the RTP bit is set to "1" (real-time port function used) and the PRP bit in the GiBCR1 register is set to "1" (parallel RTP output mode). 5. When the RTP bit is set to "1", the value written to the MOD2 to MOD0 bits is ignored. Figure 21.12 G2POCR0 to G2POCR7 and G3POCR0 to G3POCR7 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 260 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group i Waveform Generation Register j (i=0 to 3; j=0 to 7) b15 b8 b7 b0 Symbol G0PO0 to G0PO2 G0PO3 to G0PO5 G0PO6 to G0PO7 G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6 to G1PO7 G2PO0 to G2PO2 G2PO3 to G2PO5 G2PO6 to G2PO7 G3PO0 to G3PO2 G3PO3 to G3PO5 G3PO6 to G3PO7 Address 00C116-00C016, 00C316-00C216, 00C516-00C416 00C716-00C616, 00C916-00C816, 00CB16-00CA16 00CD16-00CC16, 00CF16-00CE16 010116-010016, 010316-010216, 010516-010416 010716-010616, 010916-010816, 010B16-010A16 010D16-010C16, 010F16-010E16 014116-014016, 014316-014216, 014516-014416 014716-014616, 014916-014816, 014B16-014A16 014D16-014C16, 014F16-014E16 018116-018016, 018316-018216, 018516-018416 018716-018616, 018916-018816, 018B16-018A16 018D16-018C16, 018F16-018E16 After Reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function • When the RLD bit in the GiPOCRj register is set to "0", value written is immediately reloaded into the GiPOj register to output, for example, a waveform reflecting the value • When the RLD bit is set to "1", the value is reloaded when the base timer is reset. The value written can be read until reload. Setting Range RW 000016 to FFFF16 RW Group 3 Waveform Generation Mask Register j (j=4 to 7) b15 b8 b7 b0 Symbol Address G3MK4, G3MK5 019916-019816, 019B16-019A16 G3MK6, G3MK7 019D16-019C16, 019F16-019E16 Function When one or more bit k (k=0 to 15) in this register is set to "1", the bit k in the group 3 base timer is masked. The masked value is compared to the G3POj register(1). After Reset Indeterminate Indeterminate Setting Range RW 000016 to FFFF16 RW NOTES: 1. This function is enabled in single-phase waveform output mode or phase-delayed waveform output mode. Set the G3MKi register to "000016" in other modes. Figure 21.13 G0PO0 to G0PO7, G1PO0 to G1PO7, G2PO0 to G2PO7, G3PO0 to G3PO7 Registers and G3MK4 to G3MK7 Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 261 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O Group i Function Select Register (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 00E716, 012716 After Reset 0016 G0FS, G1FS Bit Symbol FSC0 Bit Name Function RW FSC1 Channel 0 Time Measurement/ 0 : Selects the waveform generation Waveform Generation RW function Function Select Bit 1 : Selects the time measurement function Channel 1 Time Measurement/ Waveform Generation RW Function Select Bit Channel 2 Time Measurement/ Waveform Generation Function Select Bit Channel 3 Time Measurement/ Waveform Generation Function Select Bit Channel 4 Time Measurement/ Waveform Generation Function Select Bit Channel 5 Time Measurement/ Waveform Generation Function Select Bit Channel 6 Time Measurement/ Waveform Generation Function Select Bit Channel 7 Time Measurement/ Waveform Generation Function Select Bit RW FSC2 FSC3 RW FSC4 RW FSC5 RW FSC6 RW FSC7 RW NOTES: 1. No 16-bit waveform generation function is provided for channels 2, 3, 6 and 7 of the group 0. No 16-bit time measurement function is provided for channels 0, 3, 4 and 5 of the group 1. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement or waveform generation function), set the same values in the G0FS and G1FS registers. Group i Function Enable Register (i=0 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 00E616, 012616, 016616, 01A616 After Reset 0016 G0FE to G3FE Bit Symbol IFE0 IFE1 IFE2 IFE3 IFE4 IFE5 IFE6 IFE7 Bit Name Channel 0 Function Enable Bit Channel 1 Function Enable Bit Channel 2 Function Enable Bit Channel 3 Function Enable Bit Channel 4 Function Enable Bit Channel 5 Function Enable Bit Channel 6 Function Enable Bit Channel 7 Function Enable Bit Function RW 0 : Disables functions for channel j RW 1 : Enables functions for channel j (j=0 to 7) RW RW RW RW RW RW RW Figure 21.14 G0FS and G1FS Registers and G0FE to G3FE Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 262 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Base Timer) Group i RTP Output Buffer Register (i=2, 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0016 G2RTP, G3RTP 016716, 01A716 Bit Symbol RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7 Bit Name Function RW RW RW RW RW RW RW RW RW Channel 0 RTP Output Buffer 0 : Outputs "L" Channel 1 RTP Output Buffer 1 : Outputs "H" Channel 2 RTP Output Buffer Channel 3 RTP Output Buffer Channel 4 RTP Output Buffer Channel 5 RTP Output Buffer Channel 6 RTP Output Buffer Channel 7 RTP Output Buffer Figure 21.15 G2RTP AND G3RTP Registers Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 263 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Base Timer) 21.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 21.2 lists specifications of the base timer. Figures 21.5 to 21.9 show registers associated with the base timer. Figure 21.16 shows a block diagram of the base timer. Figure 21.17 shows an example of a cascaded connection. Figure 21.18 shows an example of the base timer in counter increment mode. Figure 21.19 shows an example of the base timer in counter increment/decrement mode. Figure 21.20 shows an example of two-phase pulse signal processing mode. Table 21.2 Base Timer Specifications Item Count Source (fBTi) (i=0 to 3) Specification f1 divided by 2(n+1) (Group 0 to 3), two-phase pulse input divided by 2(n+1) (Group 0 and 1) n: determined by the DIV4 to DIV0 bits in the GiBCR0 register n=0 to 31; however no division when n=31 The base timer increments the counter The base timer increments/decrements the counter Two-phase pulse signal processing • When starting the base timer of each group separately, set the BTS bit in the GiBCR1 register to "1" (base timer starts counting) • When starting the base timer of multiple groups simultaneously, set the BTiS bit in the BTSR register to "1" (base timer starts counting) Counter Stop Condition Base Timer Reset Condition Set the BTiS bit in the BTSR register to "0" (base timer reset) and the BTS bit in the GiBCR1 register to "0" (base timer reset) • Synchronized with the base timer reset in different groups: Group0 : synchronized with group 1 base timer reset Group1 : synchronized with group 0 base timer reset Group2 : synchronized with group 1 base timer reset Group3 : synchronized with group 2 base timer reset • Matching values in the base timer and GiPO0 register • "L" signal applied to the external interrupt pin ________ Group 0 : ________ pin INT0 Group 1 : INT1 pin • Reset request from communication function (Group 2 and 3) Value when the Base Timer is Reset Interrupt Request Read from Base Timer "000016" The BTiR bit in the interrupt request register is set to "1" (interrupt requested) when bit 14 or bit 15 in the base timer overflows (See Figure 10.14.) • The GiBT register indicates counter value while the base timer is running • The GiBT register is indeterminate when the base timer is reset Write to Base Timer When a value is written while the base timer is running, the counter immediately starts counting from this value. No value can be written while the base timer is reset. Selectable Function • Cascaded connection (Group 0 and 1) Group 1 base timer is incremented every time bit 15 in the group 0 base timer overflows (See Figure 21.17) • Counter increment/decrement mode (Group 0 and 1) The base timer starts when the BTS bit or the BTiS bit is set to "1". After incrementing to "FFFF 16", the counter is then decremented back to "000016". If the RST1 bit in the GiBCR1 register is set to "1" (the base timer is reset by matching with the GiPO0 register), the counter decrements after the base timer matches the GiPO0 register. The base timer increments the counter again when the counter becomes "0000 16." (See Figure 21.19.) Rev. 1.31 Jan.31, 2006 Page 264 of 488 REJ09B0034-0131 Counting Operation Counter Start Condition M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Base Timer) Table 21.2 Base Timer Specifications (Continued) Item Selectable Function Specification • Two-phase pulse processing mode (Group 0 and 1) Two-phase pulse signals from P76 and P77 pins in group 0, and P80 and P81 pins in group 1 are counted (See Figure 21.20) P76, P80 P77, P81 The timer increments counter on all edge The timer decrements counter on all deges fBTi BCK1 to BCK0 f1 Apply two-phase pulse signal ( Group0,1) BTiS bit in BTSR register BTS bit in GiBCR1 register 11 Base timer Divider (1) by 2(n+1) b0 to b13 b14 b15 10 Overflow signal 0 1 RST0 Other base timer reset RST1 Matching with the GiPO0 register RST2 Apply "L" to the INTi pin (Group0,1) Request from communication function (Group2,3) Base timer reset IT Base timer interrupt request (See the BTiR bit in Figure 10.14) NOTES: 1. Divider is reset when both BTiS bit and BTS bit are set to "0". i = 0 to 3 BCK1 to BCK0, IT : Bits in the GiBCR0 register RST2 to RST0 : Bits in the GiBCR1 register Figure 21.16 Base Timer Block Diagram Table 21.3 Base Timer Associated Register Settings (for Time Measurement Function, Waveform Generation Function, and Communication Function) Register Bit Function G2BCR0 Supplies operation clock to the BTSR register. Set to "0111 11112". BTSR Set to "0000 00002" GiBCR0 BCK1 to BCK0 Select count source DIV4 to DIV0 Select divide ratio of count source IT Selects the base timer interrupt GiBCR1 RST2 to RST1 Select factors for a base timer reset BTS Used to start the base timer independently UD1 to UD0 Select how to count (Group 0 and 1) CAS Selects cascaded connection (Group 0 and 1) GiBT Read or write base timer value Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register). GiPOCR0 MOD2 to MOD0 Set to "0002" (single-phase waveform output mode) GiPO0 Set reset cycle GiFS FSC0 Set to "0" (waveform generation function) GiFE IFE0 Set to "1" (channel operation start) i : Bit configurations and functions vary with each group Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 265 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Base Timer) Request from group1 Request by matching the base timer with the G0PO0 register Request from the INT pin BT0S BTS f1 Two-phase pulse signal is applied 11 10 Request from group0 Request by matching the base timer with the G1PO0 register Request from the INT pin BT1S BTS fBT1 0 1 Divider by 2(n+1) Group0 base timer Group1 base timer BCK1 to BCK0 Bit 15 overflow in CAS the group0 base timer 0 INPC1k triggered by the time measurement 1 G1TMj register INPC0j triggered by the time measurement CAS G0TMj register G1POj register G0POj register 0 1 Waveform generation match signal CAS j=0 to 7, k=1,2,6,7 BT0S, BT1S : Bits in the BTSR register BTS, CAS : Bits in the GiBCR1 register (i=0,1) BCK1 to BCK0 : Bits in the GiBCR0 register (i = 0,1) Figure 21.17 Cascaded Connection (1) The IT in the GiBCR0 register (i=0,1) is set to "0" (bit 15 in the base timer overflows) FFFF16 Base Timer i 800016 000016 b15 overflow signal "1" "0" "0" Write "0" by program if setting to "0" BTkR bit in IIOjIR register "1" j=4,7,8,11 k=0 to 3 The above applies under the following conditions: • The RST1 bit in the GiBCR1 register is set to "0" (the base timer is not reset by matching the base timer with the GiPO0 register) • The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode) (2) The IT in the GiBCR0 register (i=0,1) is set to "1" (bit 14 in the base timer overflows) FFFF16 C00016 Base Timer i 800016 400016 000016 b14 overflow signal BTkR bit in IIOjIR register "1" "0" "1" "0" Write "0" by program if setting to "0" j=4,7,8,11 k=0 to 3 The above applies under the following conditions: • The RST1 bit in the GiBCR1 register is set to "0" (the base timer is not reset by matching the base timer with the GiPO0 register) • The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode) Figure 21.18 Counter Increment Mode (Group 0 and 1) Rev. 1.31 Jan.31, 2006 Page 266 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Base Timer) (1) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "0" (bit 15 in the base timer overflows) FFFF16 Base Timer i 800016 b15 overflow signal BTkR bit in IIOjIR register "1" "0" "1" "0" Write "0" by program if setting to "0" j=4, 7, 8, 11; k=0 to 3 The above applies under the following conditions: • The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register). • The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode). (2) When the IT bit in the GiBCR0 register (i= 0 to 1) is set to "1" (bit 14 in the base timer overflows) FFFF16 C00016 Base Timer i 800016 400016 000016 b14 overflow signal BTkR bit in IIOjIR register "1" "0" "1" "0" Write "0" by program if setting to "0" j=4, 7, 8, 11; k=0 to 3 The above applies under the following conditions: • The RST1 in the GiBCR1 register is set to "0" (the base timer is not reset by matching the GiPO0 register). • The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode). (3) When the RST1 bit in the GiBCR1 register (i= 0 to 1) is set to "1" (the base timer is reset by matching with the GiPO0 register) 800216 800016 Base Timer i 000016 j=4, 7, 8, 11; k=0 to 3 The above applies under the following conditions: • Value of GiPO0 register: "800016" • The UD1 to UD0 bits in the GiBCR1 register are set to "012" (counter increment/decrement mode). Figure 21.19 Counter Increment/ Decrement Mode (Group 0 and 1) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 267 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Base Timer) (1) When the base timer is reset while the base timer increments the counter Group0 : P76 Group1 : P80 (A-phase) Input waveform Group0 : P77 Group1 : P81 (B-phase) fBTi "H" "L" "H" "L" min 1 µs min 1 µs "H" ( When selects no division with the divider by 2(n+1) ) "L" Group0 : INT0 Group1 : INT1 (Z-phase) "H" "L" (Note 1) The base timer starts counting Base Timer i m m+1 0 1 2 Set to "0" in this timing Set to "1" in this timing (2) When the base timer is reset while the base timer decrements the counter Group0 : P76 Group1 : P80 (A-phase) Input waveform Group0 : P77 Group1 : P81 (B-phase) fBTi "H" "L" "H" "H" "L" min 1 µs min 1 µs ( When selects no division with the divider by 2(n+1) ) "L" Group0 : INT0 Group1 : INT1 (Z-phase) "H" "L" (Note 1) The base timer starts counting Base Timer i m m-1 0 FFFF16 FFFE16 Set to "0" in this timing i=0, 1 NOTES: 1. 1.5 fBTi clock cycles or more are required. Set to "FFFF16" in this timing Figure 21.20 Base Timer Operation in Two-phase Pulse Signal Proccessing Mode (Group 0 and 1) Rev. 1.31 Jan.31, 2006 Page 268 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Time Measurement Function) 21.2 Time Measurement Function (Group 0 and 1) When external trigger is applied, the value of the base timer is stored into the GiTMj register (i=0 to 1; j=0 to 7). Table 21.4 shows specifications of the time measurement function. Table 21.5 lists pin settings of the time measurement function. Table 21.6 lists settings of time measurement function associated registers. Figures 21.21 and 21.22 show operating examples of the time measurement function. Figure 21.23 shows an operating example of the prescaler function and gate function. Table 21.4 Time Measurement Function Specifications Item Measurement Channel Specification Group 0: Channels 0 to 7 Group 1: Channels 1, 2, 6, 7 Trigger Input Polarity Measurement Start Condition Rising edge, falling edge or both edges of the INPCij pin(1) The IFEj bit in the GiFE register is set to "1" (channel j function enabled) when the FSCj bit (i=0 to1; j=0 to 7) in the GiFS register is set to "1" (time measurement function selected) Measurement Stop Condition Time Measurement Timing The IFEj bit is set to "0" (channel j function disabled) • No prescaler : every time a trigger signal is applied • Prescaler (for channel 6 and channel 7): every GiTPRk register (k=6, 7) +1 times a trigger signal is applied Interrupt Request Generation Timing INPCij Pin Function(1) The TMijR bit in the interrupt request register (See Figure 10.14) is set to "1" (interrupt requested) at time measurement timing Trigger input pin • Digital filter function The digital filter samples a trigger input signal level every f1 or fBTi cycles and passes pulse signals, matching trigger input signal level, three times • Cascaded connection function Group 0 and group 1 are connected to operate as a 32-bit base timer • Prescaler function (for channel 6 and channel 7) Time measurement is executed every GiTPRk register value +1 times a trigger signal is applied • Gate function (for channel 6 and channel 7) After time measurement by the first trigger input, trigger input cannot be received. However, trigger input can be received again by matching the base timer with the GiPOp register, or by setting the GSC bit in the GiTMCRK register to "1", when the GOC bit in the GiTMCRk register is set to "1" (gate cleared by matching the base timer with the GiPOp register (p=4 when k=6, p=5 when k=7)) NOTES: 1. INPC00 to INPC07, INPC11 to INPC12, INPC16 to INPC17 pins (INPC00 to INPC07 pins during cascaded connection) Selectable Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 269 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Time Measurement Function) Table 21.5 Pin Settings for Time Measurement Function Pin(2) PS1, PS2, PS5, PS8, PS9 Registers P74/INPC11 P75/INPC12 P76/INPC00 P77/INPC01 P80/INPC02 P111/INPC11(1) P112/INPC12(1) P142/INPC16(1) P143/INPC17(1) P150/INPC00(1) P151/INPC01(1) P152/INPC02(1) P153/INPC03(1) P154/INPC04(1) P155/INPC05(1) P156/INPC06(1) P157/INPC07(1) NOTES: 1. This port is provided in the 144-pin package only. 2. Apply trigger to INPC0j pin (j=0 to 7) when the CAS bit in the GiBCR register is set to "1" (32-bit time measurement function). Trigger input to INPC1k pin (k=1, 2, 6, 7) is invalid. PS9_4 = 0 PS9_5 = 0 PS1_4 = 0 PS1_5 = 0 PS1_6 = 0 PS1_7 = 0 PS2_0 = 0 PS5_1 = 0 PS5_2 = 0 PS8_2 = 0 PS8_3 = 0 PS9_0 = 0 PS9_1 = 0 Bit and Setting PD7, PD8, PD11, PD14, PD15 Registers PD7_4 = 0 PD7_5 = 0 PD7_6 = 0 PD7_7 = 0 PD8_0 = 0 PD11_1 = 0 PD11_2 = 0 PD14_2 = 0 PD14_3 = 0 PD15_0 = 0 PD15_1 = 0 PD15_2 = 0 PD15_3 = 0 PD15_4 = 0 PD15_5 = 0 PD15_6 = 0 PD15_7 = 0 IPS2 = 0 IPS0 = 1, IPS2 = 0 IPS1 =1 IPS0 = 0 IPS1 = 0 IPS Register Table 21.6 Time Measurement Function Associated Register Settings Register GiTMCRj Bit CTS1 to CTS0 DF1 to DF0 GT, GOC, GSC PR GiTPRk GiFS GiFE i = 0 to 1; FSCj IFEj j = 0 to 7; k = 6, 7 Function Select a time measurement trigger Select the digital filter function Select the gate function Select the prescaler function Setting value of the prescaler Set to "1" (time measurement function) Set to "1" (channel j function enabled) Bit configurations and functions vary with channels and groups used. Registers associated with the time measurement function must be set after setting registers associated with the base timer. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 270 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Time Measurement Function) Input to the INPCij pin "H" "L" FFFF16 n Base timer i p m 000016 n p GiTMj register TMijR bit "1" "0" m Write "0" by program if setting to "0" i=0,1 j=0 to 7 (except j=1, 2, 6, 7 when i=1) TMijR bit : Bits in the IIO0IIR to IIO8IR and IIO10IR to IIO11IR registers The above applies under the following conditions: The CTS1 to CTS0 bits in the GiTMCRj register are set to "012" (rising edge). The PR bit is set to "0" (no prescaler used) and the GT bit is set to"0" (no gate function used). The RTS2 to RTS0 bits in the GiBCR1 register are set to "0002" (no base timer reset). The UD1 to UD0 bits are set to "002" (counter increment mode) and the CAS bit is set to "0" (16-bit time measurement or waveform generation function). To set the base timer to "000016" (setting the RST1 bit to "1" and the RST0 and RST2 bits to "0") when the base timer matches the GiPO0 register, the base timer is set to "000016" after it reaches the value set in the GiPO0 register + 2. Figure 21.21 Time Measurement Function (1) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 271 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Time Measurement Function) (1) When selecting the rising edge as a time measurement trigger (The CTS1 to CTS0 bits in the GiTMCR register (i=0,1, j=0 to 7)=012) fBTi(1) Base timer i n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 (Note 3) "H" INPCij pin input "L" "1" TMijR bit(2) "0" Delayed by max. 1 clock Write "0" by program if setting to "0" n+5 n+8 GiTMj register n NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments counter every time the group 0 base timer overflows. 2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR bit if the CAS bit is set to "1". 3. Input pulses applied to the INPCij pin require 1.5 fBTi clock cycles or more. (2) When selecting both edges as a time measurement trigger (The CTS1 to CTS0 bits=112) fBTi(1) Base timer i "H" "L" n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 INPCij pin input (Note 3) "1" TMijR bit(2) "0" Write "0" by program if setting to "0" GiTMj register n n+2 n+5 n+6 n+8 n+12 NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments the counter whenever the group 0 base timer overflows. 2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR register if the CAS bit is set to "1". 3. No interrupt is generated if the microcomputer receives a trigger signal when the TMijR bit is set to "1". Howver, the value of the GiTMj register changes. (3) Trigger signal when using the digital filter (The DF1 to DF0 bits in the GiTMCR register =102 or 112) fi or fBTi(1) "H" INPCij pin Trigger signal after passing the digital filter "L" "H" "L" Signal, which does not match three times, is stripped off Maximum 3.5 fi or fBTi(1) clock cycles The trigger signal is delayed by the digital filter NOTES: 1. fBTi when the DF1 to DF0 bits are set to "102", and f1 when to "112". Figure 21.22 Time Measurement Function (2) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 272 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Time Measurement Function) (1) With the prescaler function (When the GiTPRj register (i=0, 1, j=6, 7) =0216, the PR bit in the GiTMCR register=1) fBTi(1) Base timer i n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 "H" INPCij pin input Internal time measurement trigger Prescaler(2) "L" "H" "L" 2 Write "0" by program if setting to "0" 1 0 2 TMijR bit(3) "1" "0" GiTMj register n n+12 NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments the counter every time the group 0 base timer overflows. 2. This applies to the second or later prescaler cycles after the PR bit in the GiTMCRj register is set to "1". 3. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11IR registers. The TM0jR register if the CAS bit is set to "1". (2) With the gate function (The gate function is cleared by matching the base timer with the GiPOk register. the GT bit in the GiTMCRj register=1, the GOC bit=1) fBTi(1) FFFF16 Base timer i 000016 Value of the GiPOk register IFEj bit in GiFE register "1" "0" "H" INPCij pin input "L" Internal time measurement trigger GiPOk register match signal Gate control signal(2) TMijR bit(3) "H" "L" "H" "L" This trigger input is disabled due to the gate function. "H" "L" Gate "1" "0" Gate cleared Gate Write "0" by program if setting to "0" GiTMj register NOTES: 1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments the counter every time the group 0 base timer overflows. 2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11IR registers. The TM0jR register if the CAS bit is set to "1". Figure 21.23 Prescaler Function and Gate Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 273 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) 21.3 Waveform Generation Function Waveforms are generated when the value of the base timer matches the GiPOj register (i=0 to 3; j=0 to 7). The waveform generation function has the following six modes : • Single-phase waveform output mode (group 0 to 3) • Phase-delayed waveform output mode (group 0 to 3) • Set/Reset waveform output (SR waveform output) mode (group 0 to 3) • Bit modulation PWM output mode (group 2 and 3) • Real-time port output (RTP output) mode (group 2 and 3) • Parallel real-time port output (parallel RTP output) mode (group 2 and 3) Table 21.7 lists pin settings of the waveform generation function. Table 21.8 lists registers associated with the waveform generation function. Table 21.7 Pin Settings for Waveform Generation Function (1/2) Pin PS0 to PS2, PS5 to PS9 Registers P64/OUTC21 P70/OUTC20 P71/OUTC22 P73/OUTC10(2) P74/OUTC11(2) P75/OUTC12(2) P76/OUTC00(2) P77/OUTC01(2) P81/OUTC30 P82/OUTC32 P92/OUTC20 P110/OUTC10(1,2) P111/OUTC11(1,2) P112/OUTC12(1,2) P113/OUTC13(1,2) P120/OUTC30(1) P121/OUTC31(1) P122/OUTC32(1) P123/OUTC33(1) P124/OUTC34(1) P125/OUTC35(1) P126/OUTC36(1) P127/OUTC37(1) P130/OUTC24(1) P131/OUTC25(1) PS0_4 = 1 PS1_0 = 1 PS1_1 = 1 PS1_3 = 1 PS1_4 = 1 PS1_5 = 1 PS1_6 = 1 PS1_7 = 1 PS2_1 = 1 PS2_2 = 1 PS3_2 = 1 PS5_0 = 1 PS5_1 = 1 PS5_2 = 1 PS5_3 = 1 PS6_0 = 1 PS6_1 = 1 PS6_2 = 1 PS6_3 = 1 PS6_4 = 1 PS6_5 = 1 PS6_6 = 1 PS6_7 = 1 PS7_0 = 1 PS7_1 = 1 Bit and Setting PSL0, PSL1, PSL2, PSL3 Registers PSL0_4 = 1 PSL1_0 = 0 PSL1_1 = 0 PSL1_3 = 0 PSL1_4 = 0 PSL1_5 = 1 PSL1_6 = 0 PSL2_1 = 1 PSL2_2 = 0 PSL3_2 = 1 PSC Register PSC_0 = 1 PSC_1 = 1 PSC_3 = 1 PSC_4 = 1 PSC_6 = 0 - NOTES: 1. This port is provided in the 144-pin package only. 2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7) outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 274 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) Table 21.7 Pin Settings for Waveform Generation Function (2/2) Pin PS0 to PS2, PS5 to PS9 Registers P132/OUTC26(1) P133/OUTC23(1) P134/OUTC20(1) P135/OUTC22(1) P136/OUTC21(1) P137/OUTC27(1) P140/OUTC14(1,2) P141/OUTC15(1,2) P142/OUTC16(1,2) P143/OUTC17(1,2) P150/OUTC00(1,2) P151/OUTC01(1,2) P154/OUTC04(1,2) P155/OUTC05(1,2) PS7_2 = 1 PS7_3 = 1 PS7_4 = 1 PS7_5 = 1 PS7_6 = 1 PS7_7 = 1 PS8_0 = 1 PS8_1 = 1 PS8_2 = 1 PS8_3 = 1 PS9_0 = 1 PS9_1 = 1 PS9_4 = 1 PS9_5= 1 Bit and Setting PSL0, PSL1, PSL2, PSL3 Registers PSC Register - NOTES: 1. This port is provided in the 144-pin package only. 2. When the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement function), the OUTC1j pin (j=0 to 7) outputs a waveform and the OUTC0k pin (k=0, 1, 4, 5), set as above, outputs a 16-bit low-order waveform. Table 21.8 Waveform Generation Function Associated Register Settings Register GiPOCRj Bit MOD2 to MOD0 PRT(1) IVL RLD RTP(1) INV PRP FSCj IFEj RTP0 to RTP7 Function Select waveform output mode Set to "1" when using the parallel RTP output mode Select default value Select reload timing of GiPOj register value Set to "1" when using the RTP output or the parallel RTP output mode MOD2 to MOD0 bits are invalid when the RTP bit is set to "1" Select inversed output Set to "1" when using the parallel RTP output mode Select output waveform inverse timing Set masked values of the base timer and G3PO4 to G3PO7 registers (group 3 only) Set to "0" (waveform generation function) (group 0 and 1 only) Set to "1" (enables channel j function) Set RTP output value in RTP output or parallel RTP output mode G2BCR1 G3BCR1 GiPOj G3MK4 to G3MK7 GiFS GiFE G2RTP G3RTP i = 0 to 3; j = 0 to 7 Bit configurations and functions vary with channels and groups used. Set registers associated with the waveform generation function after setting registers associated with the base timer. NOTES: 1. This bit is in the G2POCRj and G3POCRj registers only. Rev. 1.31 Jan.31, 2006 Page 275 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) 21.3.1 Single-Phase Waveform Output Mode (Group 0 to 3) Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) becomes high ("H") when the value of the base timer matches that of the GiPOj register . The "H" signal switches to an "L" signal when the base timer reaches "000016". If the IVL bit in the GiPOCRj register is set to "1" (outputs "H" as default value), an "H" signal is output when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the waveform being output is inversed. See Figure 21.24 for details on single-phase waveform mode operation. Table 21.9 lists specifications of single-phase waveform mode. Table 21.9 Single-phase Waveform Output Mode Specifications Item Output Waveform(3) • Free-running operation (the RST2 to RST0 bits in the GiBCR1 (i=0 to 3) register are set to "0002") Cycle "L" width "H" width : : : 65536 fBTi m fBTi 65536-m fBTi Specification m : setting value of the GiPOj register (j=0 to 7), 000016 to FFFF16 • The base timer is reset by matching the base timer with the GiPO0 register (the RST1 bit is set to "1", and the RST0 and the RST2 bit are set to "0") n+2 Cycle : fBTi m "L" width : fBTi "H" width n+2-m fBTi m : setting value of the GiPOj register (j=1 to 7), 000016 to FFFF16 : n : setting value of the GiPO0 register, 000116 to FFFD16 If m ≥ n+2, the output level is fixed to "L" Waveform Output Start Condition(1) The IFEj bit in the GiFE register is set to "1" (channel j function enabled) The IFEj bit is set to "0" (channel j function disabled) The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. (See Figure 10.14) OUTCij Pin(2) Pulse signal output pin • Default value set function : Set starting waveform output level • Inversed output function : Waveform output level is inversed and output from the OUTCij pin • Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins (OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection) 3. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed Waveform Output Stop Condition Interrupt Request Selectable Function Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 276 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) (1) Free-Running Operation (The RST2 to RST0 bits in the GiBCR1 register are set to "0002") FFFF16 Base Timer i m 000016 m fBTi 65536-m fBTi OUTCij pin(1) "H" "L" "H" "L" "1" "0" Write "0" by program if setting to "0" 65536 fBTi OUTCij pin(2) POijR bit in the IIOiIR register NOTES: 1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" (output "H" as default value). The above applies applies under the following conditions: • The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset), the UD1 to UD0 bits to "002" (counter increment mode), and CAS bit to "0" (16-bit waveform generation function) i=0 to 3; j=0 to 7 (however, i=0 when j=0, 1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) POijR bit: Bits in the IIO0IR to IIO11IR register (2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register (The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") n+2 Base Timer i m 000016 m fBTi "H" n+2-m fBTi OUTCij pin "L" n+2 fBTi Write "0" by program if setting to "0" POijR bit in the IIOiIR register "1" "0" i=0 to 3; j=1 to 7 (however, i=0 when j=1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) n : Setting value of the GiPO0 register (000116 to FFFD16) POijR bit: Bits in the IIO0IR to IIO11IR register The above diagram applies under the following conditions: • The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as default value). The INV bit is set to "0" (not inverse). • The UD1 to UD0 bits in the GiBCR1 register are set to "002" (counter increment mode), and the CAS bit to "0" (16-bit waveform generation function) • m < n+2 Figure 21.24 Single-Phase Waveform Output Mode Rev. 1.31 Jan.31, 2006 Page 277 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) 21.3.2 Phase-Delayed Waveform Output Mode (Group 0 to 3) Output signal level of the OUTCij pin (i=0 to 3; j=0 to 7) is inversed every time the value of the base timer matches that of the GiPOj register. Table 21.10 lists specifications of phase-delayed waveform mode. Figure 21.25 shows an example of phase-delayed waveform mode operation. Table 21.10 Phase-delayed Waveform Output Mode Specifications Item Output Waveform • Free-running operation (the RST2 to RST0 bits in the GiBCR1 register (i=0 to 3) are set to "0002") Cycle "H" and "L" width : : 65536 x 2 fBTi 65536 fBTi Specification Setting value of the GiPOj (j=0 to 7) register is 000016 to FFFF16 • The base timer is reset by matching the base timer with the GiPO0 register (the RST1 bit is set to "1", and the RST0 and RST2 bit are set to "0") 2(n+2) Cycle : fBTi n+2 "H" and "L" width : fBTi n : setting value of the GiPO0 register, 000116 to FFFD16 Setting value of the GiPOj (j=1 to 7) register is 000016 to FFFF16 If GiPOj register ≥ n+2, the output level is not inversed Waveform Output Start Condition(1) The IFEj bit (j=0 to 7) in the GiFE register is set to "1" (channel j function enabled) Waveform Output Stop Condition Interrupt Request The IFEj bit is set to "0" (channel j function disabled) The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. (See Figure 10.14) OUTC1j Pin Selectable Function Pulse signal output pin • Default value set function : Set starting waveform output level • Inversed output function : Waveform output level is inversed and output from the OUTCij pin • Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 1. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 2. OUTC00, OUTC01, OUTC04, OUTC05, OUTC10 to OUTC17, OUTC20 to OUTC27, and OUTC30 to OUTC37 pins (OUTC10 to OUTC17 pins when using group 0 and group 1 cascaded connection) Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 278 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) (1) Free-Running Operation (The RST2 to RST0 bits in the GiBCR1 register are set to "0002") FFFF16 Base Timer i m 000016 65536 fBTi "H" 65536 fBTi Inverse 65536X2 fBTi Inverse Write "0" by program if setting to "0" OUTCij pin(1) "L" "H" "L" "1" Inverse OUTCij pin(2) Inverse POijR bit "0 " i=0 to 3; j=0 to 7 (however, i=0 when j= 0, 1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) POijR bit: Bits in the IIO0IR to IIO11IR registers NOTES: 1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as initial value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" (output "H" as initial value). The above diagram applies under the following condition: • The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset), the UD1 to UD0 bits to "002" (counter increment mode), and the CAS bit to "0" (16-bit waveform generation function). (2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register (The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") n+2 Base Timer i m 000016 m fBTi n+2 fBTi Inverse Write "0" by program if setting to "0" n+2 fBTi Inverse Inverse OUTCij pin "H" "L" 2(n+2) fBTi PO1jR bit "1" "0" i=0 to 3; j=0 to 7 (however, i=0 when j=1, 4, 5) m : Setting value of the GiPOj register (000016 to FFFF16) n : Setting value of the GiPO0 register (000116 to FFFD16) POijR bit: Bits in the IIO0IR to IIO11IR registers The above diagram applies under the following conditions: • The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as initial value). The INV bit is set to "0" (not inversed). • The UD1 to UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) and the CAS bit to "0" (16-bit waveform generation function). • m < n+2 Figure 21.25 Phase-delayed Waveform Output Mode Rev. 1.31 Jan.31, 2006 Page 279 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) 21.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode (Group 0 to 3) Output signal level of the OUTCij pin (i=0 to 3; j=0, 2, 4, 6) becomes "H" when the value of the base timer matches that of the GiPOj register. The "H" signal switches to an "L" signal when the value of the base timer matches that of the GiPOk register (k=j+1) or when the base timer is set to "000016". If the IVL bit in the GiPOCRj register (j=0 to 7) is set to "1" (outputs "H" as initial value), an "H" signal is output when waveform output starts. If the INV bit is set to "1" (output is inversed), the level of the waveform being output is inversed. Table 21.11 lists specifications of SR waveform mode. Figure 21.26 shows an example of a SR waveform mode operation. Table 21.11 SR Waveform Output Mode Specifications (1/2) Item Output Waveform(2) • Free-running operation (the RST2 to RST0 bits in the GiBCR1 register are set to "0002") (1) m < n "H" width "L" width (2) m ≥ n "H" width "L" width : 65536 - m fBTi m : fBTi : : n-m fBTi m (3) fBTi + 65536 - n(4) fBTi Specification m : setting value of the GiPOj register (j=0, 2, 4, 6) n : setting value of the GiPOk register (k=j+1) m, n=000016 to FFFF16 • The base timer is reset by matching the base timer with the GiPO0 register (1) (the RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0") (1) m < n < p+2 "H" width "L" width : : n-m fBTi m (3) fBTi p+2-n fBTi m fBTi + p + 2 - n(4) fBTi (2) m < p+2 ≤ n "H" width "L" width : : (3) If m ≥ p+2, the output level is fixed to "L" m : setting value of the GiPOj register (j=2, 4, 6) n : setting value of the GiPOk register (k=j+1) p : setting value of the GiPO0 register m, n=000016 to FFFF16 p=000116 to FFFD16 NOTES: 1. When the GiPO0 register resets the base timer, the channel 0 and 1 SR waveform generation functions are not available. 2. When the INV bit in the GiPOCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. 3. Waveform from base timer reset until when output level becomes "H". 4. Waveform from when output level becomes "L" until base timer reset. Rev. 1.31 Jan.31, 2006 REJ09B0034-0131 Page 280 of 488 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) Table 21.11 SR Waveform Output Mode Specifications (2/2) Item Specification Waveform Output Start Condition(5) The IFEq bit (q=0 to 7) in the GiFE register is set to "1" (channel q function enabled) Waveform Output Stop Condition Interrupt Request The IFEq bit is set to "0" (channel q function disabled) The POijR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOj register. The POikR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the GiPOk register. (See Figure 10.14) OUTCij Pin(6) Pulse signal output pin • Default value set function : Set starting waveform output level • Inversed output function : Waveform output level is inversed and output from the OUTCij pin • Cascaded connection function: Connect group 0 and group 1 to operate as a 32-bit base timer NOTES: 5. Set the FSCj bit in the GiFS register to "0" (waveform generation function selected) when using channels shared by both time measurement function and waveform generation function 6. OUTC00, OUTC04, OUTC10, OUTC12, OUTC14, OUTC16, OUTC20, OUTC22, OUTC24, OUTC26, OUTC30, OUTC32, OUTC34, and OUTC36 pins (OUTC10, OUTC12, OUTC14, and OUTC16 pins when using group 0 and group 1 cascaded connection) Selectable Function Rev. 1.31 Jan.31, 2006 Page 281 of 488 REJ09B0034-0131 M32C/83 Group (M32C/83, M32C/83T) 21. Intelligent I/O (Waveform Generation Function) (1) Free-Running Operation (The RST2 to RST0 bits in the GiBCR1 register are set to "0002") FFFF16 n Base Timer i m 000016 n-m fBTi 65536-n+m fBTi OUTCij pin(1) "H" "L" "H" "L" "1" 65536 fBTi OUTCij pin(2) POijR bit POikR bit "0" "1" "0" Write "0" by program if setting to "0" Write "0" by program if setting to "0" i=0, 3; j=0, 2, 4, 6 (however, i=0 when j=0, 4); k=j+1 m : Setting value of the GiPOj register (000016 to FFFF16) n : Setting value of the GiPOk register (000016 to FFFF16) POijR, POikR bits: Bits in the IIO0IR to IIO11IR registers NOTES: 1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" (output "H" as default value). The diagram above applies under the following condition: • The RST2 to RST0 bits in the GiBCR1 register are set to "0002" (no base timer reset), the UD1 to UD0 bits to "002" (counter increment mode), and the CAS bit to "0" (16-bit waveform generation function). • m