M37733EHBXXXFP

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP qSingle power supply ...................................................... 5 V ± 10% qLow power dissipation (at 25 MHz frequency) ............................................47.5 mW (Typ.) qInterrupts ............................................................ 19 types, 7 levels qMultiple-function 16-bit timer ................................................. 5 + 3 qSerial I/O (UART or clock synchronous) ..................................... 3 q10-bit A-D converter ............................................ 8-channel inputs qWatchdog timer qProgrammable input/output (ports P0, P1, P2, P3, P4, P5, P6, P7, P8) ............................... 68 qClock generating circuit ........................................ 2 circuits built-in DESCRIPTION The M37733EHBXXXFP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the PROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on. The M37733EHBXXXFP has the same function as the M37733MHBXXXFP except that the built-in ROM is PROM. (Refer to the basic function blocks description.) For program development, the M37733EHBFS with erasable ROM that is housed in a windowed ceramic LCC is also provided. APPLICATION Control devices for general commercial equipment such as office automation, office equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on. Note. Do not use the windowed EPROM version for mass production, because it is a tool for program development (for evaluation). FEATURES qNumber of basic instructions .................................................. 103 qMemory size PROM ............................................. 124 Kbytes RAM ................................................ 3968 bytes qInstruction execution time The fastest instruction at 25 MHz frequency ...................... 160 ns PIN CONFIGURATION (TOP VIEW) P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3 64 62 59 53 60 57 61 58 49 48 47 46 56 50 54 63 52 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XcIN P76/AN6/XcOUT P75/AN5/ADTRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 55 51 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 M37733EHBXXXFP 33 32 31 30 29 28 27 26 25 P24/A20/D4 P25/A21/D5 P26/A22/D6 P27/A23/D7 P30/R/W P31/BHE P32/ALE P33/HLDA Vss E XOUT XIN RESET CNVSS BYTE P40/HOLD 21 10 11 12 15 16 14 17 18 20 13 P70/AN0 P67/TB2IN/φSUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/φ1 P41/RDY 19 5 22 1 2 6 7 8 23 3 24 4 9 Outline 80P6N-A 1 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Reference External data bus width voltage input selection input VREF BYTE Data Bus(Even) Data Bus(Odd) Data Buffer DBH(8) P0(8) Data Buffer DBL(8) Instruction Register(8) Instruction Queue Buffer Q0(8) Instruction Queue Buffer Q1(8) Address Bus Incrementer(24) (0V) AVSS Input/Output port P2 Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P3 Program Address Register PA(24) Data Address Register DA(24) P2(8) CNVss Incrementer/Decrementer(24) (0V) VSS Program Bank Register PG(8) Data Bank Register DT(8) UART1(9) UART2(9) UART0(9) VCC Input Butter Register IB(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Processor Status Register PS(11) Reset input RESET Direct Page Register DPR(16) Stack Pointer S(16) Timer TA4(16) M37733EHBXXXFP BLOCK DIAGRAM Timer TA3(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Index Register Y(16) XCOUT XCIN Index Register X(16) Accumulatcr B(16) Enable output E Accumulator A(16) Clock Generating Circuit 3968 bytes P7(8) Clock input Clock output XIN XOUT RAM Arithmetic Logic Unit(16) XCOUT XCIN 124 Kbytes 2 PROM P8(8) P6(8) P5(8) P4(8) P3(4) Program Counter PC(16) A-D Converter(10) Input/Output port P1 Instruction Queue Buffer Q2(8) P1(8) AVCC Input/Output port P0 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP FUNCTIONS OF M37733EHBXXXFP Parameter Number of basic instructions Instruction execution time Memory size Input/Output ports Multi-function timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package M37733EHBXXXFP M37733EHBFS Input/Output voltage Output current PROM RAM P0 – P2, P4 – P8 P3 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 Functions 103 160 ns (the fastest instruction at external clock 25 MHz frequency) 124 Kbytes 3968 bytes 8-bit ! 8 4-bit ! 1 16-bit ! 5 16-bit ! 3 (UART or clock synchronous serial I/O) ! 3 10-bit ! 1 (8 channels) 12-bit ! 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) 5 V ± 10% 47.5 mW (at external clock 25 MHz frequency) 5V 5 mA Maximum 16 Mbytes –20 to 85 °C CMOS high-performance silicon gate process 80-pin plastic molded QFP (80P6N-A) 80-pin ceramic LCC (with a window) (80D0) 3 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP PIN DESCRIPTION Pin Vcc, Vss CNVss _____ Name Input/Output Power source Apply 5 V ± 10% to Vcc and 0 V to Vss. CNVss input Reset input Clock input Clock output Enable output External data bus width selection input Analog power source input Reference voltage input I/O port P0 Input Input Input Output Output Input Functions RESET XIN XOUT _ E BYTE AVcc, AVss VREF P00 – P07 This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode. When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between XIN and XOUT. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin functions as the enable signal output pin which indicates the access status in the internal _ bus. When output level of E signal is “L”, data/instruction read or data write is performed. In the memory expansion mode or the microprocessor mode, this pin determines whether the external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal is input. Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. This is reference voltage input pin for the A-D converter. In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output address (A0 – A7). In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address (A0 – A7) is output . In the single-chip mode, these pins have ____same function as port P0. In the memory expansion __ the _____ mode or the microprocessor mode, R/W, BHE, ALE, and HLDA signals are output. In the single-chip mode, these pins have the same functions as_____P0. In the memory expansion port ____ mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a clock φ1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. In addition to having the same functions as port P0 in the single-chip mode, these pins also __ __ function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3 ). In addition to having the same functions as port P0 in the single-chip mode, these pins also ____ ____ function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock φSUB output pin. In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1. Input I/O P10 – P17 I/O port P1 I/O P20 – P27 I/O port P2 I/O P30 – P33 I/O port P3 P40 – P47 I/O port P4 I/O I/O P50 – P57 I/O port P5 P60 – P67 I/O port P6 I/O I/O P70 – P77 I/O port P7 I/O P80 – P87 I/O port P8 I/O 4 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP PIN DESCRIPTION (EPROM MODE) Pin VCC, VSS CNVSS _____ BYTE XIN Name Power supply VPP input VPP input Reset input Clock input Clock output Enable output Analog supply input Reference voltage input Address input (A0 – A7) Address input (A8 – A15) Data I/O (D0 – D7) Address input (A16) Input port P3 Input port P4 Control signal input Input port P6 Input port P7 Input port P8 Input/Output Input Input Input Input Output Output Input Input Input I/O Input Input Input Input Input Input Input Functions Supply 5V±10% to VCC and 0V to VSS. Connect to VPP when programming or verifing. Connect to VPP when programming or verifing. Connect to VSS. Connect a ceramic resonator between XIN and XOUT. Keep open. Connect AVCC to VCC and AVSS to VSS. Connect to VSS. Port P0 functions as the lower 8 bits address input (A0 – A7). Port P1 functions as the higher 8 bits address input (A8 – A15). Port P2 functions as the 8 bits data input/output (D0 – D7). P30 functions as the most significant bit address input (A16). Connect to VSS. Connect to VSS. _____ ___ ___ P50, P51, and P52 function as PGM, OE, and CE input pins respectively. Connect P53, P54, P55, and P56 to VCC. Connect P57 to VSS. Connect to VSS. Connect to VSS. Connect to VSS. RESET _ XOUT E AVCC, AVSS VREF P00 – P07 P10 – P17 P20 – P27 P30 P31 – P33 P40 – P47 P50 – P57 P60 – P67 P70 – P77 P80 – P87 5 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP BASIC FUNCTION BLOCKS The M37733EHBXXXFP has the same functions as the M37733MHBXXXFP except for the following: (1) The built-in ROM is PROM. (2) The status of bit 3 of the oscillation circuit control register 1 (address 6F16) at a reset is different. (3) The usage condition of bit 3 of the oscillation circuit control register 1 is different. Accordingly, refer to the basic function blocks description in the M37733MHBXXXFP except for Figure 1 (bit configuration of the oscillation circuit control register 1) and Figure 3 (microcomputer internal status during reset). In the M37733EHBXXXFP, bit 3 of the oscillation circuit control register 1 must be “1”. (Refer to Figure 1.) The status of this bit at a reset is “1”. 7 6 5 4 0 3 1 2 1 0 Oscillation circuit control register 1 Main clock division selection bit 0 : Main clock is divided by 2. 1 : Main clock is not divided by 2. CC2 CC1 CC0 Address 6F16 Note. Write to the oscillation circuit control register 1 as the flow shown in Figure 2. Main clock external input selection bit 0 : Main-clock oscillation circuit is operating by itself. Watchdog timer is used at returning from STP state. 1 : Main-clock is input externally. Watchdog timer is not used at returning from STP state. Sub clock external input selection bit 0 : Sub-clock oscillation circuit is operating by itself. Port P76 functions as XCOUT pin. Watchdog timer is used at returning from STP state. 1 : Sub-clock is input externally. Port P76 functions as I/O port. Watchdog timer is not used at returning from STP state. 1 : Always “1” (“1” at reset) 0 : Always “0” (However, writing data “5516” shown in Figure 2 is possible.) Clock prescaler reset bit Fig. 1 Bit configuration of oscillation circuit control register 1 (corresponding to Figure 63 in data sheet “M37733MHBXXXFP”) Writing data “5516” (LDM instruction) Next instruction Writing data “8016” (LDM instruction) Writing data “0Y16” (LDM instruction) Reset clock prescaler CC2 to CC0 selection bits • How to reset clock prescaler • How to write in CC2 to CC0 selection bits Note. “Y” is the sum of bits to be set. For example, when setting bits 2 and 1 to “1”, “Y” becomes “6”. Fig. 2 How to write data in oscillation circuit control register 1 (identical with Figure 64 in data sheet “M37733MHBXXXFP”) 6 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register A-D control register 0 A-D control register 1 UART 0 transmit/receive mode register UART 1 transmit/receive mode register UART 0 transmit/receive control register 0 UART 1 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 1 transmit/receive control register 1 Count start flag One- shot start flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Address (0416)••• (0516)••• (0816)••• (0916)••• (0C16)••• (0D16)••• (1016)••• (1116)••• (1416)••• (1E16)••• (1F16)••• (3016)••• (3816)••• 0016 0016 0016 00 00 0016 0016 0016 0016 0016 00000? ?? 000 0016 0016 11 Watchdog timer frequency selection flag Memory allocation control register UART2 transmit/receive mode register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register (6116)••• 0 0 (6316)••• 0 0 0 0 0 0 0 1 (6416)••• (6816)••• 0000000 1000 (6916)••• 0 0 0 0 0 0 1 0 (6C16)••• 0 0 0 0 0 0 0 1 (6D16)••• 0 (6E16)••• (6F16)••• 0 (7016)••• 0016 00 01000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 UART 0 transmission interrupt control register (7116)••• UART 0 receive interrupt control register (7216)••• UART 1 transmission interrupt control register (7316)••• UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register (3416)••• 0 0 0 0 1 0 0 0 (3C16)••• 0 0 0 0 1 0 0 0 (3516)••• 0 0 0 0 0 0 1 0 (3D16)••• 0 0 0 0 0 0 1 0 (4016)••• (4216)••• (4416)••• (5616)••• (5716)••• (5816)••• (5916)••• (5A16)••• 0016 00000 0016 0016 0016 0016 0016 0016 (7416)••• (7516)••• (7616)••• (7716)••• (7816)••• (7916)••• (7A16)••• (7B16)••• (7C16)••• (7D16)••• (7E16)••• (7F16)••• (5B16)••• 0 0 1 0 0 0 0 0 (5C16)••• 001 0000 0000 0016 0 FFF16 Processor status register (PS) Program bank register (PG) Program counter (PCH) Program counter (PCL) Direct page register (DPR) Data bank register (DT) 000??0001?? 0016 Content of FFFF16 Content of FFFE16 000016 0016 (5D16)••• 0 0 1 (5E16)••• (5F16)••• (6016)••• Contents of other registers and RAM are undefined during reset. Initialize them by software. Fig. 3 Microcomputer internal status during reset 7 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP EPROM MODE The M37733EHBXXXFP features an EPROM mode in addition to its _____ normal modes. When the R ESET s ignal level is “L”, the chip automatically enters the EPROM mode. Table 1 list the correspondence between pins and Figure 4 shows the pin connections in the EPROM mode. The EPROM mode is the 1M mode for the EPROM that is equivalent to the M5M27C101K. When in the EPROM mode, ports P0, P1, P2, P30, P50, P51, P52, CNV SS, and BYTE are used for the EPROM (equivalent to the Table 1 Pin function in EPROM mode VCC VPP VSS Address input Data I/O ___ M5M27C101K). When in this mode, the built-in PROM can be programmed or read from using these pins in the same way as with the M5M27C101K. This chip does not have Device Identifier Mode, so that set the corresponding program algorithm. The program area should specify address 0100016 – 1FFFF16. Connect the clock which is either ceramic resonator or external clock to XIN pin and XOUT pin. M37733EHBXXXFP VCC CNVSS, BYTE VSS Ports P0, P1, P30 Port P2 P52 P51 P50 M5M27C101K VCC VPP VSS A0 – A16 D0 – D7 ___ CE ___ CE ___ OE _____ OE _____ PGM PGM 8 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP 62 53 45 61 58 52 57 56 51 49 44 59 54 48 63 64 55 47 VCC P83/TXD0 ↔ P82 /RXD 0/CLKS0 ↔ P81/CLK0 ↔ P80 /CTS 0/RTS 0/CLKS1 ↔ VCC AVCC VREF → AVSS VSS P77/AN7/XCIN ↔ P76/AN6/XCOUT ↔ P75 /AN5/AD TRG /TXD2 ↔ P74/AN4/RXD2 ↔ P73/AN3/CLK2 ↔ P72/AN2 /CTS 2 ↔ P71/AN1 ↔ 60 50 46 43 42 41 ↔ P84/CTS 1/RTS 1 ↔ P85 /CLK1 ↔ P86/RXD1 ↔ P87/TXD1 ↔ P00/A0 ↔ P01/A1 ↔ P02/A2 ↔ P03/A3 ↔ P04/A4 ↔ P05/A5 ↔ P06/A6 ↔ P07/A7 ↔ P10/A8/D8 ↔ P11/A9/D9 ↔ P12 /A10 /D10 ↔ P13/A11 /D11 ↔ P14/A12 /D12 ↔ P15/A13 /D13 ↔ P16/A14 /D14 ↔ P17/A15 /D15 ↔ P20/A16 /D0 ↔ P21/A17 /D1 ↔ P22/A18 /D2 ↔ P23/A19 /D3 ↔ P24/A20 /D4 ↔ P25/A21 /D5 ↔ P26/A22 /D6 ↔ P27/A23 /D7 ↔ P30/R/W ↔ P31/BHE ↔ P32/ALE ↔ P33/HLDA VSS →E → XOUT ← XIN ← RESET CNVSS ← BYTE ↔ P40/HOLD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 D4 D5 D6 D7 A16 M37733EHBXXXFP 33 32 31 30 29 28 27 26 25 VSS      ∗ VPP PGM OE CE P70/AN0 ↔ 1 P67/TB2IN/φSUB ↔ 2 P66/TB1IN ↔ 3 P65/TB0IN ↔ 4 P64/INT 2 ↔ 5 P63/INT 1 ↔ 6 P62 /INT 0 ↔ 7 P61/TA4IN ↔ 8 P60/TA4OUT ↔ 9 P57/TA3IN /KI3 ↔ 10 P56 /TA3OUT /KI 2 ↔ 11 P55/TA2IN /KI 1 ↔ 12 P54/TA2OUT /KI0 ↔ 13 P53/TA1IN ↔ 14 P52/TA1OUT ↔ 15 P51/TA0IN ↔ 16 P50/TA0OUT ↔ 17 P47 ↔ 18 P46 ↔ 19 P45 ↔ 20 P44 ↔ 21 P43 ↔ 22 P42/ φ1 ↔ 23 P41/RDY ↔ 24 V : Connect to ceramic oscillation circuit. Outline 80P6N-A Fig. 4 Pin connection in EPROM mode : It is used in the EPROM mode. 9 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP FUNCTION IN EPROM MODE 1M mode (equivalent to the M5M27C101K) Reading ___ ___ Programming operation To program the M37733EHBXXXFP, first set VCC = 6 V, VPP = 12.5 V, and set the address to 0100016. Apply a 0.2 ms programming pulse, check that the data can be read, and if it cannot be read OK, repeat the procedure, applying a 0.2 ms programming pulse and checking that the data can be read until it can be read OK. Record the accumulated number of pulse applied (X) before the data can be read OK, and then write the data again, applying a further once this number of pulses (0.2 ! X ms). When this series of programming operations is complete, increment the address, and continue to repeat the procedure above until the last address has been reached. Finally, when all addresses have been programmed, read with VCC = VPP = 5 V (or VCC = VPP = 5.5 V). Table 2. I/O signal in each mode Pin Mode Read-out Output Disable Programming Programming Verify Program Disable ___ ___ _____ To read the EPROM, set the CE and OE pins to a “L” level. Input the address of the data (A0 – A16) to be read, and the data will be output to the I/O pins D0 – D7. The data I/O pins will be floating when either __ __ the CE or OE pins are in the “H” state. Programming Programming must be performed in 8 bits by a byte program. To ___ ___ program to the EPROM, set the CE pin to a “L” level and the OE pin to a “H” level. The CPU will enter the programming mode when 12.5 V is applied to the VPP pin. The address to be programmed to is selected with pins A0 –_____ and the data to be programmed is input to pins D0 A16, – D7. Set the PGM pin to a “L” level to being programming. Erasing To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The minimum radiation power necessary for erasing is 15 J/cm2. CE OE PGM VPP 5V 5V VCC 5V 5V Data I/O Output Floating Floating Input Output Floating VIL VIL VIH VIL VIL VIH VIL VIH X VIH VIL VIH X X X 5V 5V VIL 12.5 V 6 V VIH 12.5 V 6 V VIH 12.5 V 6 V Note 1 : An X indicates either VIL or VIH. Programming operation (equivalent to the M5M27C101K) AC ELECTRICAL CHARACTERISTICS (Ta = 25 ± 5 °C, VCC = 6 V ± 0.25 V, VPP = 12.5 ± 0.3 V, unless otherwise noted) Symbol tAS tOES tDS tAH tDH tDFP tVCS tVPS tPW tOPW tCES tOE Address setup time ___ Parameter Test conditions Limits Min. 2 2 2 0 2 0 2 2 0.19 0.19 2 0.2 0.21 5.25 150 130 Typ. Max. Unit µs µs µs µs µs ns µs µs ms ms µs ns OE setup time Data setup time Address hold time Data hold time Output enable to output float delay VCC setup time VPP setup time _____ PGM pulse width _____ PGM over program pulse width ___ CE setup time __ Data valid from OE 10 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP AC waveforms PROGRAM VIH ADDRESS VIL tAS VIH/VOH DATA VIL/VOL VPP VPP VCC VCC +1 VCC VCC VIH CE VERIFY tAH DATA SET DATA OUTPUT VALID tDS tDH tDFP tVPS tVCS VIL VIH PGM tCES VIL VIH OE tOES tPW tOPW tOE VIL Programming algorithm flow chart Test conditions for A.C. characteristics Input voltage : VIL = 0.45 V, VIH = 2.4 V Input rise and fall times (10 % – 90 %) : ≤ 20 ns Reference voltage at timing measurement : Input, Output “L” = 0.8 V, “H” = 2 V START ADDR=FIRST LOCATION VCC=6.0 V VPP=12.5 V X=0 PROGRAM ONE PULSE OF 0.2 ms X=X+1 YES X=25? NO FAIL VERIFY BYTE VERIFY BYTE PASS FAIL DEVICE FAILED PASS PROGRAM PULSE OF 0.2X ms DURATION NO INCREMENT ADDR LAST ADDR? YES VCC=VPP=*5.0 V VERIFY ALL BYTE PASS DEVICE PASSED FAIL DEVICE FAILED *4.5 V ≤ VCC = VPP ≤ 5.5 V 11 MITSUBISHI MICROCOMPUTERS . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som P IM REL IN ARY M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP SAFETY INSTRUCTIONS (1) Sunlight and fluorescent lamp contain light that can erase written information. When using in read mode, be sure to cover the transparent glass portion with a seal or other materials (ceramic package product). (2) Mitsubishi Electric corp. provides the seal for covering the transparent glass. Take care that the seal does not touch the read pins (ceramic package product). (3) Clean the transparent glass before erasing. Fingers’ fat and paste disturb the passage of ultraviolet rays and may affect badly the erasure capability (ceramic package product). (4) A high voltage is used for programming. Take care that overvoltage is not applied. Take care especially at power on. (5) The programmable M37733EHBFP that is shipped in blank is also provided. For the M37733EHBFP, Mitsubishi Electric corp. does not perform PROM programming test and screening following the assembly processes. To improve reliability after programming, performing programming and test according to the flow below before use is recommended. ADDRESSING MODES The M37733EHBXXXFP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37733EHBXXXFP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR PROM ORDERING Please send the following data for writing to PROM. (1) M37733EHBXXXFP writing to PROM order confirmation form (2) 80P6N mark specification form (3) ROM data (EPROM 3 sets) Programming with PROM programmer Screening (Caution) (Leave at 150 °C for 40 hours) Verify test with PROM programmer Function check in target device Caution : Never expose to 150 °C exceeding 100 hours. 12 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP ABSOLUTE MAXIMUM RATINGS Symbol Vcc AVcc VI VI Parameter Conditions Power source voltage Analog power source voltage _____ Input voltage RESET, CNVss, BYTE Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, VREF, XIN Output voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, _ XOUT, E Power dissipation Ta = 25 °C Operating temperature Storage temperature Ratings –0.3 to +7 –0.3 to +7 –0.3 to +12 (Note) –0.3 to Vcc + 0.3 Unit V V V V VO Pd Topr Tstg –0.3 to Vcc + 0.3 300 –20 to +85 –40 to +150 V mW °C °C Note. When the EPROM is programmed, input voltage of pins CNVss and BYTE is 13 V respectively. RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted) Symbol Vcc AVcc Vss AVss VIH VIH VIH VIL VIL VIL IOH(peak) Parameter f(XIN) : Operating Power source voltage f(XIN) : Stopped, f(XCIN) = 32.768 kHz Analog power source voltage Power source voltage Analog power source voltage 33, P4 High-level input voltage P00 – P07, P30 – P_______0 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) High-level input voltage P10 – P17, P20 – P27 (in single-chip mode) High-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67, _______ P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P44 – P47, P50 – P53 Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level average output current P44 – P47, P50 – P53 Main-clock oscillation frequency (Note 4) Sub-clock oscillation frequency Min. 4.5 2.7 Limits Typ. 5.0 Vcc 0 0 0.8 Vcc 0.8 Vcc 0.5 Vcc 0 0 0 Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc –10 Max. 5.5 5.5 Unit V V V V V V V V V V mA IOH(avg) –5 mA IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(XCIN) 10 20 5 15 25 50 mA mA mA mA MHz kHz 32.768 Notes 1. Average output current is the average value of a 100 ms interval. 2. The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4. The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”. 13 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) Symbol VOH VOH VOH VOH Parameter Test conditions Min. 3 4.7 3.1 4.8 3.4 4.8 2 2 0.45 1.9 0.43 1.6 0.4 0.4 0.2 0.1 0.1 1 0.5 0.4 0.4 5 Limits Typ. Max. Unit V V V V V V V V V V V V V µA High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P47, P50 – P57, IOH = –10 mA P60 – P67, P70 – P77, P80 – P87 High-level output voltage P00 – P07, P10 – P17, P20 – P27, IOH = –400 mA P33 IOH = –10 mA High-level output voltage P30 – P32 ICH = –400 µA _ IOH = –10 mA High-level output voltage E IOH = –400 µA Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P43, P54 – P57, IOL = 10 mA P60 – P67, P70 – P75, P80 – P87 Low-level output voltage P44 – P47, P50 – P53 IOL = 20 mA Low-level output voltage P00 – P07, P10 – P17, P20 – P27, IOL = 2 mA P33 IOL = 10 mA Low-level output voltage P30 – P32 IOL = 2 mA _ IOL = 10 mA Low-level output voltage E IOL = 2 mA ______ ____ Hysteresis ___ , ___ , ____ – TA4IN, TB0IN – TB2IN, HOLD RDY TA0IN ___ ___ ___ INT0 – INT2, A__ ,__ 0, CTS1, CTS2, CLK0, DTRG CTS CLK1, CLK2, KI0 – KI3 _____ Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, VI = 5 V – P57, P40 – P47, P50 _____P60 – P67, P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, VI = 0 V P61, P6 P40 – P47, P50 – P53, P60,_____ 5 – P67, P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE VI = 0 V, Low-level input current P54 – P57, P62 – P64 RAM hold voltage without a pull-up transistor VOL VOL VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– VT+ – VT– IIH IIL –5 µA –5 –0.25 2 –0.5 –1.0 µA mA V IIL VRAM VI = 0 V, with a pull-up transistor When clock is stopped. 14 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter Test conditions VCC = 5 V, f(XIN) = 25 MHz (square waveform), (f(f2) = 12.5 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 5 V, f(XIN) = 25 MHz (square waveform), (f(f2) = 1.5625 MHz), f(XCIN) = Stopped, in operating (Note 1) Power source current In single-chip mode, output pins are open, and other pins are VSS. VCC = 5V, f(XIN) = 25 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) VCC = 5 V, f(XIN) : Stopped, f(XCIN) : 32.768 kHz, in operating (Note 3) Min. Limits Typ. Max. Unit 9.5 19 mA 1.3 2.6 mA ICC 10 20 µA 50 100 µA Notes 1. 2. 3. 4. VCC = 5 V, f(XIN) : Stopped, 5 10 µA f(XCIN) : 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, 1 µA when clock is stopped Ta = 85 °C, 20 µA when clock is stopped This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”. A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) Symbol — — Parameter Test conditions Min. Limits Typ. Max. 10 ±3 25 VCC VREF Unit Bits LSB kΩ µs V V Resolution VREF = VCC Absolute accuracy VREF = VCC RLADDER Ladder resistance VREF = VCC tCONV Conversion time VREF Reference voltage Analog input voltage VIA Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 10 9.44 2 0 15 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note)) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input Unit Max. tc External clock input cycle time (Note 1) ns tw(H) External clock input high-level pulse width (Note 2) ns tw(L) External clock input low-level pulse width (Note 2) ns tr External clock rise time 8 ns External clock fall time 8 ns tf Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns. 2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. Min. 40 15 15 Symbol Parameter Limits Single-chip mode Symbol tsu(P0D–E) tsu(P1D–E) tsu(P2D-E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time Parameter Limits Min. 60 60 60 60 60 60 60 60 60 0 0 0 0 0 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Memory expansion mode and microprocessor mode Symbol tsu(D–E) tsu(RDY–φ1) tsu(HOLD–φ1) th(E–D) th(φ1–RDY) th(φ1–HOLD) Data input setup time RDY input setup time HOLD input setup time Data input hold time ___ RDY input hold time ____ HOLD input hold time ___ ____ Parameter Limits Min. 32 55 55 0 0 0 Max. Unit ns ns ns ns ns ns 16 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Timer A input Symbol tc(TA) tw(TAH) tw(TAL) (Count input in event counter mode) parameter Limits Min. 80 40 40 Max. Unit ns ns ns TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width (Note) TAiIN input low-level pulse width (Note) parameter Limits Min. 320 160 160 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19. Timer A input (External trigger input in one-shot pulse mode) Symbol t c(TA) tw(TAH) tw(TAL) TAiIN input cycle time (Note) TAiIN input high-level pulse width TAiIN input low-level pulse width parameter Limits Min. 320 80 80 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19. Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width parameter Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP–TIN) th(TIN–UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns Timer A input (Two-phase pulse input in event counter mode) Symbol t c(TA) TAjIN input cycle time tsu(TAjIN–TAjOUT) TAjIN input setup time tsu(TAjOUT–TAjIN) TAjOUT input setup time parameter Limits Min. 800 200 200 Max. Unit ns ns ns 17 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 320 160 160 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19. Timer B input (Pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time (Note) TBiIN input high-level pulse width (Note) TBiIN input low-level pulse width (Note) Parameter Limits Min. 320 160 160 Max. Unit ns ns ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19. A-D trigger input Symbol ____ Parameter ADTRG input cycle time (minimum allowable trigger) ____ ADTRG input low-level pulse width Limits Min. 1000 125 Max. Unit ns ns tc(AD) tw(ADL) Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time ____ ___ Limits Min. 250 250 250 Max. Parameter Limits Min. 200 100 100 0 30 90 Max. Unit ns ns ns ns ns ns ns 80 External interrupt INTi input, key input interrupt KIi input Symbol ___ Parameter ___ __ Unit ns ns ns tw(INH) tw(INL) tw(KIL) INTi input high-level pulse width INTi input low-level pulse width KIi input low-level pulse width 18 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP DATA FORMULAS Timer A input (Gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 · f(f2) 4 ! 109 2 · f(f2) 4 ! 109 2 · f(f2) Max. Unit ns ns ns Timer A input (External trigger input in one-shot pulse mode) Symbol tc(TA) TAiIN input cycle time Parameter Limits Min. 8 ! 109 2 · f(f2) Max. Unit ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width Parameter Limits Min. 8 ! 109 2 · f(f2) 4 ! 109 2 · f(f2) 4 ! 109 2 · f(f2) Max. Unit ns ns ns Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”. 19 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85°C, f(XIN) = 25 MHz (Note), unless otherwise noted) Single-chip mode Symbol Parameter Test conditions Limits Min. Max. 80 80 80 80 80 80 80 80 80 Unit ns ns ns ns ns ns ns ns ns td(E–P0Q) Port P0 data output delay time td(E–P1Q) Port P1 data output delay time td(E–P2Q) Port P2 data output delay time td(E–P3Q) Port P3 data output delay time Fig. 5 td(E–P4Q) Port P4 data output delay time td(E–P5Q) Port P5 data output delay time td(E–P6Q) Port P6 data output delay time td(E–P7Q) Port P7 data output delay time Port P8 data output delay time td(E–P8Q) Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. P0 P1 P2 P3 P4 P5 P6 P7 P8 φ1 E 50 pF Fig. 5 Measuring circuit for ports P0 – P8 and φ1 20 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Memory expansion mode and microprocessor mode (VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) Symbol td(An–E) Address output delay time Parameter Test (Note 2) Wait mode conditions No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Limits Min. 12 87 12 75 18 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 22 57 5 45 9 15 Fig. 5 4 10 45 No wait Wait 1 Wait 0 18 50 130 5 20 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 12 87 12 87 18 18 0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns td(A–E) Address output delay time Address hold time ALE pulse width th(E–An) tw(ALE) tsu(A–ALE) Address output setup time th(ALE–A) Address hold time td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) ALE output delay time Data output delay time Data hold time _ E pulse width Floating start delay time Floating release delay time ___ BHE output delay time _ td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ1) td(φ1–HLDA) R/ W output delay time ___ ____ φ1 output delay time HLDA output delay time BHE hold time _ R/ W hold time 18 50 Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. 21 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, Symbol Parameter f(XIN) = 25 MHz (Max., Note 1), unless otherwise noted) Limits Min. 1 ! 109 – 28 2 · f(f2) 3 ! 109 – 33 2 · f(f2) 1 ! 109 – 28 2 · f(f2) 3 ! 109 – 45 2 · f(f2) 9 1 ! 10 – 22 2 · f(f2) 9 1 ! 10 – 18 2 · f(f2) 9 2 ! 10 – 23 2 · f(f2) 9 1 ! 10 – 35 2 · f(f2) 9 2 ! 10 – 35 2 · f(f2) 9 1 ! 109 2 · f(f2) 4 1 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 2 ! 109 2 · f(f2) 4 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 3 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 3 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 1 ! 109 2 · f(f2) 0 – 30 45 – 22 – 30 – 30 5 – 20 – 28 – 33 – 28 – 33 – 22 – 22 18 – 25 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns td(An–E) Address output delay time Wait mode No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 td(A–E) Address output delay time th(E–An) Address hold time No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 tw(ALE) ALE pulse width tsu(A–ALE) Address output setup time th(ALE–A) Address hold time td(ALE–E) td(E–DQ) th(E–DQ) ALE output delay time Data output delay time Data hold time _ No wait Wait 1 Wait 0 tw(EL) tpxz(E–DZ) tpzx(E–DZ) E pulse width Floating start delay time Floating release delay time ___ td(BHE–E) BHE output delay time No wait Wait 1 Wait 0 _ td(R/W–E) R/W output delay time ___ No wait Wait 1 Wait 0 th(E–BHE) th(E–R/W) td(E–φ1) BHE hold time _ R/W hold time φ1 output delay time Notes 1. This applies when the main-clock division selection bit = “0”. 2. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”. 22 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP TIMING DIAGRAM XIN tr tf tc tw(H) tw(L) E td(E–P0Q) Port P0 output tsu(P0D–E) Port P0 input th(E–P0D) td(E–P1Q) Port P1 output tsu(P1D–E) Port P1 input th(E–P1D) td(E–P2Q) Port P2 output tsu(P2D–E) Port P2 input th(E–P2D) td(E–P3Q) Port P3 output tsu(P3D–E) Port P3 input th(E–P3D) td(E–P4Q) Port P4 output tsu(P4D–E) Port P4 input th(E–P4D) td(E–P5Q) Port P5 output tsu(P5D–E) Port P5 input th(E–P5D) td(E–P6Q) Port P6 output tsu(P6D–E) Port P6 input th(E–P6D) td(E–P7Q) Port P7 output tsu(P7D–E) Port P7 input th(E–P7D) td(E–P8Q) Port P8 output tsu(P8D–E) Port P8 input th(E–P8D) 23 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) In event counter mode TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) th(TIN–UP) tsu(UP–TIN) In event counter mode (When two-phase pulse input is selected) TAjIN input tsu(TAjIN–TAjOUT) tc(TA) tsu(TAjIN–TAjOUT) tsu(TAjOUT–TAjIN) TAjOUT input tsu(TAjOUT–TAjIN) tc(TB) tw(TBH) TBiIN input tw(TBL) 24 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) RxDi tsu(D–C) th(C–D) tw(INL) INTi input Kli input tw(INH) tw(KNL) 25 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Memory expansion mode and microprocessor mode (When wait bit = “1”) φ1 E RDY input tsu(RDY–φ1) th(φ1–RDY) ( When wait bit = “0”) φ1 E RDY input tsu(RDY–φ1) th(φ1–RDY) (When wait bit = “1” or “0” in common) φ1 tsu(HOLD–φ1) HOLD input th(φ1–HOLD) td(φ1–HLDA) HLDA output td(φ1–HLDA) Test conditions • VCC = 5 V ± 10% • Input timing voltage : V IL = 1.0 V, VIH = 4.0 V • Output timing voltage : V OL = 0.8 V, VOH = 2.0 V 26 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) tw(L) tw(H) tf tr tc XIN φ1 td(E-φ1) tw(EL) E td(E-φ1) td(An-E) th(E-An) Address Address Address An tw(ALE) td(ALE-E) ALE th(ALE-A) tsu(A-ALE) th(E-DQ) tpxz(E-DZ) tpzx(E-DZ) Am/Dm Address Data Address th(E-D) tsu(D-E) Data Address td(E-DQ) td(A-E) DmIN th(E-BHE) td(BHE-E) BHE td(R/W-E) th(E-R/W) R/W Test conditions • VCC = 5 V ± 10% • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V • Data input DmIN : VIL = 0.8 V, VIH = 2.5 V 27 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Memory expansion mode and microprocessor mode (Wait 1 : The external memory area is accessed when wait bit = “0” and wait selection bit = “1”.) tw(L) XIN tw(H) tf tr tc φ1 td(E–φ1) tw(EL) E td(E–φ1) td(An–E) An th(E–An) Address Address tw(ALE) ALE td(ALE–E) th(ALE–A) tsu(A–ALE) Am/Dm Address Data th(E–DQ) tpxz(E–DZ) Address tpzx(E–DZ) Address td(A–E) td(E–DQ) tsu(D–E) th(E–D) DmIN Data td(BHE–E) th(E–BHE) BHE td(R/W–E) R/W th(E–R/W) Test conditions • Vcc = 5 V ± 10% • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V 28 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) tw(L) XIN tw(H) tf tr tc φ1 td(E–φ1) E td(E–φ1) tw(EL) td(An–E) An Address th(E–An) Address Address tw(ALE) ALE td(ALE–E) tsu(A–ALE) th(ALE–A) th(E–DQ) tpxz(E–DZ) Address tpzx(E–DZ) Address Am/Dm Address td(A–E) Data td(E–DQ) tsu(D–E) DmIN th(E–BHE) Data th(E–D) td(BHE–E) BHE td(R/W–E) R/W th(E–R/W) Test conditions • Vcc = 5 V ± 10% • Output timing voltage : V OL = 0.8 V, V OH = 2.0 V • Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V 29 P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP PACKAGE OUTLINE 30 GZZ–SH00–80B ROM number Note : Please fill in all items marked Issuance signatures Company name Date issued 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain the identical data, we will produce writing to PROM based on this data. We shall assume the responsibility for errors only if the written PROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : 27C201 00000 00010 20000 (1) Set “FF 16” in the shaded area. (2) Address 0 16 to 0F16 are the area for storing the data on model designation.This area must be written with the data shown below. Address and data are written in hexadecimal notation. 4D 33 37 37 33 33 45 48 Address 0 1 2 3 4 5 6 7 42 FF FF FF FF FF FF FF Address 8 9 A B C D E F (hexadecimal notation) Date: TEL ( Responsible officer Supervisor Customer ) DATA 128K 3FFFF Note : Make sure that address 01FFFF16 of the microcomputer’s internal ROM corresponds to address 3FFFF16 of EPROM. 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 80P6N Mark Specification Form (for M37733EHBXXXFP) and attach to the Writing to PROM Order Confirmation Form. 3. Comments Receipt 7700 FAMILY WRITING TO PROM ORDER CONFIRMATION FORM SINGLE-CHIP 16-BIT MICROCOMPUTER M37733EHBXXXFP MITSUBISHI ELECTRIC Date: Section head Supervisor signature signature 80P6N (80-PIN QFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 64 41 40 65 Mitsubishi IC catalog name Mitsubishi product number (6-digit, or 7-digit) 80 1 24 25 B. Customer ’s Parts Number + Mitsubishi IC Catalog Name 64 41 40 65 80 1 24 25 Customer ’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas, periods and so on. C. Special Mark Required 64 41 40 65 80 1 24 25 Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. T he layout will be duplicated technically as close as possible. Mitsubishi product number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked for sorting the products. 2 : If special character fonts (e,g., customer ’s trade mark logo) must be used in Special Mark, check the box below. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special character fonts required P . ion. hange icat ecif ct to c l sp je fina re sub ot a its a is n his etric lim e: T otic param N e Som IM REL I Y NAR MITSUBISHI MICROCOMPUTERS M37733EHBXXXFP M37733EHBFS PROM VERSION OF M37733MHBXXXFP Keep safety first in your circuit designs! ¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials ¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. ¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. ¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. ¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 1996 MITSUBISHI ELECTRIC CORP. H-LF449-A KI-9610 Printed in Japan (ROD) 2 New publication, effective Oct. 1996. 32 Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.00 1.01 First Edition The following are added: • PROM ORDER CONFIRMATION FORM • MARK SPECIFICATION FORM 2.00 The following are revised: Page P12 Right Column Line 2 Previous Version M37733EHBXXXFP, M37733EHBFS Datasheet Revision Description Rev. date 970604 980526 980731 Revised Version The M37733EHBXXXFP has 28 powerful addressing modes. R efer to the “7700 Family Software Manual” for the details. The M37733EHBXXXFP has 28 powerful addressing modes. R efer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for the details of each addressing mode. MACHINE INSTRUCTION LIST The M37733EHBXXXFP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37733EHBXXXFP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for details. (1)