• 型  号
  • 产品描述
M38035FE-XXXSP图片

暂无图片

M38035FE-XXXSP

型  号:
M38035FE-XXXSP
大  小:
2052.34KB 共119页
厂  商:
RENESAS[RenesasTechnologyCorp]
主  页:
http://www.renesas.com
功能介绍:
M38035FE-XXXSP - SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER - Renesas Technology Corp
推荐单价:

无报价

立即购买
3803 Group (Spec.L) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0212-0101 Rev.1.01 Jan 25, 2008 • Power source voltage (Flash memory version) [In high-speed mode] At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V At 12.5 MHz oscillation frequency .................... 4.0 to 5.5 V At 8.4 MHz oscillation frequency ...................... 2.7 to 5.5 V [In middle-speed mode] At 16.8 MHz oscillation frequency .................... 4.5 to 5.5 V At 12.5 MHz oscillation frequency .................... 2.7 to 5.5 V [In low-speed mode] At 32 kHz oscillation frequency......................... 2.7 to 5.5 V • Power dissipation (Mask ROM version) In high-speed mode ........................................... 40 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................ 45 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) • Power dissipation (Flash memory version) In high-speed mode ........................................ 27.5 mW (typ.) (at 16.8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ........................................ 1200 µW (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) • Operating temperature range ............................. −20 to 85 °C • Packages SP...............PRDP0064BA-A (64P4B) (64-pin 750 mil SDIP) HP ......PLQP0064KB-A (64P6Q-A) (64-pin 10 × 10 mm LQFP) KP ......PLQP0064GA-A (64P6U-A) (64-pin 14 × 14 mm LQFP) WG ........PTLG0064JA-A (64F0G) (64-pin 6 × 6 mm FLGA) • Power source voltage ................................ VCC = 2.7 to 5.5 V • Program/Erase voltage ............................. VCC = 2.7 to 5.5 V • Programming method ............... Programming in unit of byte • Erasing method ................................................. Block erasing • Program/Erase control by software command • Number of times for programming/erasing ...................... 100 The flash memory version cannot be used for application embedded in the MCU card. DESCRIPTION The 3803 group (Spec.L) is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec.L) is designed for household products, office automation equipment, and controlling systems that require analog signal processing, including the A/D converter and D/A converters. FEATURES • Basic machine-language instructions ................................. 71 • Minimum instruction execution time .......................... 0.24 µs (at 16.8 MHz oscillation frequency) • Memory size Mask ROM/Flash memory .................................... 60 K bytes RAM ...................................................................... 2048 bytes • Programmable input/output ports ....................................... 56 • Software pull-up resistors ............................................ Built-in • Interrupts 21 sources, 16 vectors............................................................... (external 8, internal 12, software 1) • Timers ...................................................................... 16-bit × 1 8-bit × 4 (with 8-bit prescaler) • Serial interface ......... 8-bit × 2 (UART or Clock-synchronized) 8-bit × 1 (Clock-synchronized) • PWM ....................................... 8-bit × 1 (with 8-bit prescaler) • A/D converter ........................................ 10-bit × 16 channels (8-bit reading enabled) • D/A converter ............................................ 8-bit × 2 channels • Watchdog timer ....................................................... 16-bit × 1 • LED direct drive port..............................................................8 • Clock generating circuit ............................. Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) • Power source voltage (Mask ROM version) [In high-speed mode] At 16.8 MHz oscillation frequency ....................4.5 to 5.5 V At 12.5 MHz oscillation frequency ....................4.0 to 5.5 V At 8.4 MHz oscillation frequency ......................2.7 to 5.5 V At 4.2 MHz oscillation frequency ......................2.2 to 5.5 V At 2.1 MHz oscillation frequency ......................2.0 to 5.5 V [In middle-speed mode] At 16.8 MHz oscillation frequency ....................4.5 to 5.5 V At 12.5 MHz oscillation frequency ....................2.7 to 5.5 V At 8.4 MHz oscillation frequency ......................2.2 to 5.5 V At 6.3 MHz oscillation frequency ......................1.8 to 5.5 V [In low-speed mode] At 32 kHz oscillation frequency.........................1.8 to 5.5 V Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 1 of 117 3803 Group (Spec.L) P1 0/INT 41 P1 1/INT 01 P0 2/AN 10 P0 3/AN 11 P0 4/AN 12 P0 5/AN 13 P0 6/AN 14 P0 7/AN 15 P0 0/AN 8 P0 1/AN 9 P1 2 P1 3 P1 4 P1 5 P1 6 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33 P32 P31/DA2 P30/DA1 VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 33 P1 7 32 31 30 29 28 27 26 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 M38039MFL-XXXHP/KP M38039FFLHP/KP 25 24 23 22 21 20 19 18 17 P5 5 /CNTR 1 P5 4 /CNTR 0 P5 1/S OUT2 P6 2 /AN 2 P6 1 /AN 1 P6 0 /AN 0 P5 7/INT 3 P4 7 /S RDY1 /CNTR 2 P4 5 /T XD 1 P4 4/R XD 1 P5 2 /S CLK2 Package code : PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A) Fig 1. Pin configuration (Top view) PLQP0064KB-A (64P6Q-A)/PLQP0064GA-A (64P6U-A) VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN XOUT VSS P5 3/S RDY2 P4 6 /S CLK1 P56 /PWM P4 3/INT 2 P5 0/S IN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) Package code : PRDP0064BA-A (64P4B) Fig 2. Pin configuration (Top view) (PRDP0064BA-A (64P4B)) M38039MFL-XXXSP M38039FFLSP Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 2 of 117 3803 Group (Spec.L) PIN CONFIGURATION (TOP VIEW) A B C D E F G H 8 50 P36/SCLK3 46 P02/AN10 44 P04/AN12 41 P07/AN15 40 P10/INT41 32 P20(LED0) 31 P21(LED1) 30 P22(LED2) 8 7 51 P35/TXD3 47 P01/AN9 45 P03/AN11 42 P06/AN14 39 P11/INT01 27 P25(LED5) 29 P23(LED3) 28 P24(LED4) 7 6 53 P33 52 P34/RXD3 48 P00/AN8 43 P05/AN13 38 P12 37 P13 26 P26(LED6) 25 P27(LED7) 6 5 56 P30/DA1 55 P31/DA2 54 P32 49 P37/SRDY3 33 P17 36 P14 35 P15 34 P16 5 4 1 P62/AN2 64 P63/AN3 58 VREF 59 AVSS 57 VCC 24 VSS 22 XIN 23 XOUT 4 3 60 P67/AN7 61 P66/AN6 4 P57/INT3 7 P54/CNTR0 12 P47/SRDY1/CNTR2 14 P45/TXD1 21 P40/INT40/XCOUT 20 P41/INT00/XCIN 3 2 62 P65/AN5 63 P64/AN4 5 P56/PWM 8 P53/SRDY2 10 P51/SOUT2 13 P46/SCLK1 17 P42/INT1 19 RESET 2 1 2 P61/AN1 3 P60/AN0 6 P55/CNTR1 9 P52/SCLK2 11 P50/SIN2 15 P44/RXD1 16 P43/INT2 18 CNVSS 1 A B C D E F G H Package code : PTLG0064JA-A (64F0G) Note : The numbers in circles corresponds with the number on the packages HP/KP. M38039MFL -XXXWG M38039 FFLWG Package (TOP VIEW) Fig 3. Pin configuration (Top view) (PTLG0064JA-A (64F0G)) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 3 of 117 3803 Group (Spec.L) Table 1 Performance overview Parameter Function 71 0.24 µs (Oscillation frequency 16.8 MHz) Oscillation frequency 16.8 MHz(Maximum) ROM RAM Flash memory version ROM RAM 60 Kbytes 2048 bytes 60 Kbytes 2048 bytes 56 pins Built-in 21 sources, 16 vectors (8 external, 12 internal, 1 software) 8-bit × 4 (with 8-bit prescaler), 16-bit × 1 8-bit × 2 (UART or Clock-synchronized) 8-bit × 1 (Clock-synchronized) 8-bit × 1 (with 8-bit prescaler) 10-bit × 16 channels (8-bit reading enabled) 8-bit × 2 channels 16-bit × 1 8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA) Built-in 2 circuits (connect to external ceramic rasonator or quartz-crystal oscillator) At 16.8 MHz At 12.5 MHz At 8.4 MHz At 4.2 MHz At 2.1 MHz In middlespeed mode At 16.8 MHz At 12.5 MHz At 8.4 MHz At 6.3 MHz In low-speed mode At 32 MHz Mask ROM version Flash memory version Mask ROM version Flash memory version Mask ROM version Flash memory version Mask ROM version Mask ROM version Mask ROM version Flash memory version Mask ROM version Flash memory version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version 4.5 to 5.5 V 4.0 to 5.5 V 2.7 to 5.5 V 2.2 to 5.5 V 2.0 to 5.5 V 4.5 to 5.5 V 2.7 to 5.5 V 2.2 to 5.5 V 1.8 to 5.5 V 1.8 to 5.5 V 40 mW 45 µW VCC 10 mA -20 to 85 °C CMOS sillicon gate 64-pin plastic molded SDIP/LQFP/FLGA Number of basic instructions Minimum instruction execution time Oscillation frequency Memory sizes Mask ROM version I/O port Interrupt Timer P0-P6 Software pull-up resistors Serial interface PWM A/D converter D/A converter Watchdog timer LED direct drive port Clock generating circuits Power source voltage In high-speed mode Flash memory version 2.7 to 5.5 V Flash memory version 27.5 mW Power dissipation In high-speed mode In low-speed mode Flash memory version 1200 µW Input/Output Input/Output withstand voltage characteris- Output current tics Operating temperature range Device structure Package Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 4 of 117 3803 Group (Spec.L) Fig 4. Reset input V SS V CC 1 26 27 32 FUNCTIONAL BLOCK DIAGRAM (Package: PRDP0064BA-A (64P4B)) RESET CNV SS Main clock input X IN Main clock output X OUT Sub-clock Sub-clock input output X CIN X COUT 30 31 28 29 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Data bus CPU Functional block diagram ROM X Prescaler 12 (8) Clock generating circuit RAM A Timer 1 (8) Timer 2 (8) Timer X (8) Timer Y (8) Prescaler Y (8) CNTR 1 Y Prescaler X (8) Page 5 of 117 S CNTR 0 PC H PS CNTR 2 PC L Timer Z (16) 0 A/D converter (10) SI/O2 (8) SI/O1 (8) PWM (8) D/A converter 2 (8) D/A converter 1 (8) SI/O3 (8) INT 3 INT 01 INT 41 P6 (8) P5 (8) P4 (8) INT 00 INT 1 INT 2 INT 40 P3 (8) P2 (8) P1 (8) P0 (8) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 V REF AV SS I/O port P6 I/O port P5 I/O port P4 I/O port P3 I/O port P2 (LED drive) I/O port P1 I/O port P0 3803 Group (Spec.L) PIN DESCRIPTION Table 2 Pin description Pin VCC, VSS CNVSS VREF AVSS RESET XIN XOUT P00/AN8− P07/AN15 P10/INT41 P11/INT01 P12−P17 P20(LED0)P27(LED7) P30/DA1 P31/DA2 P32, P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCOUT P41/INT00/XCIN P42/INT1 P43/INT2 P44/RXD1 P45/TXD1 P46/SCLK1 P47/SRDY1/CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0− P67/AN7 I/O port P6 I/O port P5 I/O port P4 I/O port P2 I/O port P3 Name Power source CNVSS input Reference voltage Analog power source Reset input Functions Function except a port function • Apply voltage of 1.8 V − 5.5 V to VCC, and 0 V to VSS. In the flash memory version, apply voltage of 2.7 V − 5.5 V to VCC. • This pin controls the operation mode of the chip. • Normally connected to VSS. • Reference voltage input pin for A/D and D/A converters. • Analog power source input pin for A/D and D/A converters. • Connect to VSS. • Reset input pin for active “L”. Main clock input • Input and output pins for the clock generating circuit. • Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. Main clock • When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin output open. I/O port P0 I/O port P1 • 8-bit CMOS I/O port. • I/O direction register allows each pin to be individually programmed as either input or output. • CMOS compatible input level. • CMOS 3-state output structure. • Pull-up control is enabled in a bit unit. • P20 − P27 (8 bits) are enabled to output large current for LED drive. • A/D converter input pin • Interrupt input pin • D/A converter input pin • 8-bit CMOS I/O port. • I/O direction register allows each pin to be individually programmed as either input or output. • CMOS compatible input level. • Serial I/O3 function pin • P30, P31, P34 − P37 are CMOS 3-state output structure. • P32, P33 are N-channel open-drain output structure. • Pull-up control of P30, P31, P34 − P37 is enabled in a bit unit. • 8-bit CMOS I/O port. • I/O direction register allows each pin to be individually programmed as either input or output. • CMOS compatible input level. • CMOS 3-state output structure. • Pull-up control is enabled in a bit unit. • Interrupt input pin • Sub-clock generating I/O pin (resonator connected) • Interrupt input pin • Serial I/O1 function pin • Serial I/O1, timer Z function pin • Serial I/O2 function pin • Timer X function pin • Timer Y function pin • PWM output pin • Interrupt input pin • A/D converter input pin Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 6 of 117 3803 Group (Spec.L) PART NUMBERING Product name M3803 9 M F L− XXX SP Package code SP : PRDP0064BA-A (64P4B) HP : PLQP0064KB-A (64P6Q-A) KP : PLQP0064GA-A (64P6U-A) WG : PTLG0064JA-A (64F0G) ROM number Omitted in the flash memory version. −: standard Omitted in the flash memory version. L−: Minner spec. change product ROM/Flash memory size 9: 36864 bytes 1: 4096 bytes A: 40960 bytes 2: 8192 bytes B: 45056 bytes 3: 12288 bytes C: 49152 bytes 4: 16384 bytes D: 53248 bytes 5: 20480 bytes E: 57344 bytes 6: 24576 bytes F: 61440 bytes 7: 28672 bytes 8: 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M: Mask ROM version F: Flash memory version RAM size 0: 1: 2: 3: 4: 192 256 384 512 640 bytes bytes bytes bytes bytes 5: 6: 7: 8: 9: 768 bytes 896 bytes 1024 bytes 1536 bytes 2048 bytes Fig 5. Part numbering Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 7 of 117 3803 Group (Spec.L) GROUP EXPANSION Renesas plans to expand the 3803 group (Spec.L) as follows. Memory Size • Flash memory size .....................................................60 Kbytes • Mask ROM size .........................................................60 Kbytes • RAM size ................................................................. 2048 bytes Packages • PRDP0064BA-A (64P4B) ..............................................64-pin shrink plastic-molded DIP • PLQP0064KB-A (64P6Q-A) ...........................................0.5 mm-pitch plastic molded LQFP • PLQP0064GA-A (64P6U-A) ...........................................0.8 mm-pitch plastic molded LQFP • PTLG0064JA-A (64F0G) ........................................0.65 mm-pitch plastic molded FLGA Memory Expansion Plan ROM size (bytes) M38039FFL M38039MFL 60 K 48 K 32 K 28 K 24 K 20 K 16 K 12 K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (bytes) Fig 6. Memory expansion plan Table 3 Support products Part No. ROM size (bytes) ROM size for User in ( ) 61440 (61310) RAM size (bytes) Package PRDP0064BA-A (64P4B) 2048 PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) PTLG0064JA-A (64F0G) PRDP0064BA-A (64P4B) 57344+4096 (NOTE) 2048 PLQP0064KB-A (64P6Q-A) Flash memory version PLQP0064GA-A (64P6U-A) VCC = 2.7 to 5.5 V PTLG0064JA-A (64F0G) Mask ROM version Remarks M38039MFL-XXXSP M38039MFL-XXXHP M38039MFL-XXXKP M38039MFL-XXXWG M38039FFLSP M38039FFLHP M38039FFLKP M38039FFLWG NOTE: 1. ROM size includes the ID code area. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 8 of 117 3803 Group (Spec.L) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803 group (Spec.L) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc. are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0”, the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 8. Store registers other than those described in Figure 7 with program when the user needs them during interrupts or subroutine calls (see Table 4). [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 A b7 X b7 Y b7 S b15 PCH b7 PCL b0 Accumulator b0 Index Register X b0 Index Register Y b0 Stack Pointer b0 Program Counter b7 b0 N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig 7. 740 Family CPU register structure Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 9 of 117 3803 Group (Spec.L) On-going Routine Interrupt request(1) M(S)←(PCH) (S)←(S) − 1 Execute JSR M(S)←(PCL) Push Return Address on Stack M(S)←(PCH) (S)←(S) − 1 M(S)←(PCL) (S)←(S) − 1 Push Return Address on Stack (S)←(S) − 1 M(S)←(PS) (S)←(S) − 1 Interrupt Service Routine ..... Push Contents of Processor Status Register on Stack Subroutine ..... Execute RTI (S)←(S) + 1 (PS)←M(S) (S)←(S) + 1 (PCL)←M(S) (S)←(S) + 1 (PCH)←M(S) I Flag is Set from “0” to “1” Fetch the Jump Vector Execute RTS (S)←(S) + 1 (PCL)←M(S) (S)←(S) + 1 (PCH)←M(S) POP Return Address from Stack POP Contents of Processor Status Register from Stack POP Return Address from Stack Note 1 : Condition for acceptance of an interrupt → Interrupt enable flag is “1” Interrupt disable flag is “0” Fig 8. Table 4 Register push and pop at interrupt generation and subroutine call Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 10 of 117 3803 Group (Spec.L) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can execute decimal arithmetic. Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to − 128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag − − I flag SEI CLI D flag SED CLD B flag − − T flag SET CLT V flag − CLV N flag − − Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 11 of 117 3803 Group (Spec.L) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B16. b7 b0 1 CPU mode register (CPUM: address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0: Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to “1”. Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(XIN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig 9. Structure of CPU mode register Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 12 of 117 3803 Group (Spec.L) MISRG (1) Bit 0 of address 001016: Oscillation stabilizing time set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by an external interrupt source, usually, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = 01 1 6 , Prescaler 12 = FF 1 6 ) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by setting “1” to bit 0 of MISRG (address 001016). However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Figure 10 shows the structure of MISRG. (2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Automatic Switch Function In order to switch the clock mode of an MCU which has a subclock, the following procedure is necessary: set CPU mode register (003B16) --> start main clock oscillation --> wait for oscillation stabilization --> switch to middle-speed mode (or high-speed mode). However, the 3803 group (Spec.L) has the built-in function which automatically switches from low to middle-speed mode by program. • Middle-speed mode automatic switch by program The middle-speed mode can also be automatically switched by program while operating in low-speed mode. By setting the middle-speed automatic switch start bit (bit 3) of MISRG (address 001016) to “1” in the condition that the middle-speed mode automatic switch set bit is “1” while operating in lowspeed mode, the MCU will automatically switch to middle-speed mode. In this case, the oscillation stabilizing time of the main clock can be selected by the middle-speed automatic switch wait time set bit (bit 2) of MISRG (address 001016). b7 b0 MISRG (MISRG: address 001016) Oscillation stabilizing time set after STP instruction released bit 0 : Automatically set “0116” to Timer 1, “FF16” to Prescaler 12 1 : Automatically set disabled Middle-speed mode automatic switch set bit 0 : Not set automatically 1 : Automatic switching enabled (1) Middle-speed mode automatic switch wait time set bit 0 : 4.5 to 5.5 machine cycles 1 : 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0 : Invalid 1 : Automatic switch start(1) Not used (return “0” when read) (Do not write “1” to this bit) Note 1 : When automatic switch to middle-speed mode from low-speed mode occurs, the values of CPU mode register (3B 16) change. Fig 10. Structure of MISRG Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 13 of 117 3803 Group (Spec.L) MEMORY • Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. • RAM The RAM is used for data storage and for stack area of subroutine calls and interrupts. • ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. The reserved ROM area can program/erase in the flash memory version. • Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. • Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. • Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Since the contents of RAM are undefined at reset, be sure to set an initial value before use. RAM area RAM size (bytes) 192 256 384 512 640 768 896 1024 1536 2048 ROM area ROM size (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 0000 16 0040 16 0100 16 SFR area Zero page RAM XXXX16 0FE0 16 0FEF16 0FF0 16 0FFF 16 YYYY16 Reserved ROM area (128 bytes) ZZZZ16 Not used SFR area (Note 1) SFR area Not used Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 ROM FF00 16 FFDC16 Interrupt vector area FFFE16 FFFF 16 Reserved ROM area Special page Notes 1: Only flash memory version has this SFR area. 2: The reserved ROM area can program/erase in the flash memory version. Note the difference of the mask version. Fig 11. Memory map diagram Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 14 of 117 3803 Group (Spec.L) 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Port P4 (P4) 000916 Port P4 direction register (P4D) 000A16 Port P5 (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 (P6) 000D16 Port P6 direction register (P6D) 000E16 Timer 12, X count source selection register (T12XCSS) 000F16 Timer Y, Z count source selection register (TYZCSS) 001016 MISRG 001116 Reserved (Note 1) 001216 Reserved (Note 1) 001316 Reserved (Note 1) 001416 Reserved (Note 1) 001516 Reserved (Note 1) 001616 Reserved (Note 1) 001716 Reserved (Note 1) 001816 Transmit/Receive buffer register 1 (TB1/RB1) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 001B16 UART1 control register (UART1CON) 001C16 Baud rate generator (BRG1) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Watchdog timer control register (WDTCON) 001F16 Serial I/O2 register (SIO2) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer Z low-order (TZL) Timer Z high-order (TZH) Timer Z mode register (TZM) PWM control register (PWMCON) 002C16 PWM prescaler (PREPWM) 002D16 PWM register (PWM) 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 Baud rate generator 3 (BRG3) Transmit/Receive buffer register 3 (TB3/RB3) Serial I/O3 status register (SIO3STS) Serial I/O3 control register (SIO3CON) UART3 control register (UART3CON) AD/DA control register (ADCON) AD conversion register 1 (AD1) DA1 conversion register (DA1) DA2 conversion register (DA2) AD conversion register 2 (AD2) Interrupt source selection register (INTSEL) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 003F16 Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0FE016 Flash memory control register 0 (FMCR0) 0FE116 Flash memory control register 1 (FMCR1) 0FE216 Flash memory control register 2 (FMCR2) 0FE316 Reserved (Note 1) 0FE416 Reserved (Note 1) 0FE516 Reserved (Note 1) 0FE616 Reserved (Note 1) 0FE716 Reserved (Note 1) 0FE816 Reserved (Note 1) 0FE916 Reserved (Note 1) 0FEA16 Reserved (Note 1) 0FEB16 Reserved (Note 1) 0FEC16 Reserved (Note 1) 0FED16 Reserved (Note 1) 0FEE16 Reserved (Note 1) 0FEF16 Reserved (Note 1) 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Port P2 pull-up control register (PULL2) Port P3 pull-up control register (PULL3) Port P4 pull-up control register (PULL4) Port P5 pull-up control register (PULL5) Port P6 pull-up control register (PULL6) Notes1: Do not write any data to these addresses, because these are reserved area. 2: Do not access to the SFR area including nothing. Fig 12. Memory map of special function register (SFR) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 15 of 117 3803 Group (Spec.L) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to Table 6 I/O port function Pin P00/AN8−P07/AN15 P10/INT41 P11/INT01 P12−P17 P20(LED0)− P27(LED7) P30/DA1 P31/DA2 P32, P33 Name Input/ Output I/O Structure Non-Port Function Related SFRs AD/DA control register Interrupt edge selection register Ref. No. (1) (2) (3) input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. By setting the port P0 pull-up control register (address 0FF016) to the port P6 pull-up control register (address 0FF616) ports can control pull-up with a program. However, the contents of these registers do not affect ports programmed as the output ports. Port P0 Input/output, CMOS compatible A/D converter input input level Port P1 individual External interrupt input CMOS 3-state bits output Port P2 Port P3 CMOS compatible input level N-channel open-drain output CMOS compatible Serial I/O3 function I/O input level CMOS 3-state output Port P4 D/A converter output AD/DA control register (4) (5) P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P40/INT40/XCOUT P41/INT00/XCIN P42/INT1 P43/INT2 P44/RXD1 P45/TXD1 P46/SCLK1 P47/SRDY1/CNTR2 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR0 P55/CNTR1 P56/PWM P57/INT3 P60/AN0−P67/AN7 Port P6 Port P5 Serial I/O3 control register UART3 control register (6) (7) (8) (9) External interrupt input Interrupt edge selection register (10) Sub-clock generating circuit CPU mode register (11) External interrupt input Serial I/O1 function I/O Interrupt edge selection register Serial I/O1 control register UART1 control register Serial I/O1 control register Timer Z mode register Serial I/O2 control register (2) (6) (7) (8) (12) (13) (14) (15) (16) (17) (18) (2) (1) Serial I/O1 function I/O Timer Z function I/O Serial I/O2 function I/O Timer X, Y function I/O PWM output External interrupt input A/D converter input Timer XY mode register PWM control register Interrupt edge selection register AD/DA control register NOTES: 1. Refer to the applicable sections how to use double-function ports as function I/O ports. 2. Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 16 of 117 3803 Group (Spec.L) (1) Ports P0, P6 Pull-up control bit (2) Ports P10, P11, P42, P43, P57 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch A/D converter input Analog input pin selection bit Interrupt input (3) Ports P12 to P17, P2 Pull-up control bit (4) Ports P30, P31 Pull-up control bit Direction register Direction register Data bus Port latch Data bus Port latch D/A converter output DA1 output enable bit (P30) DA2 output enable bit (P31) (5) Ports P32, P33 (6) Ports P34, P44 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Direction register Data bus Port latch Data bus Port latch Serial I/O input (7) Ports P35, P45 Pull-up control bit Serial I/O enable bit Transmit enable bit Direction register Data bus P-channel output disable bit (8) Ports P36, P46 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Pull-up control bit Port latch Serial I/O output Serial I/O clock output Serial I/O external clock input Fig 13. Port block diagram (1) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 17 of 117 3803 Group (Spec.L) (9) Port P37 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit SRDY3 output enable bit Direction register (10) Port P40 Pull-up control bit Port XC switch bit Direction register Data bus Data bus Port latch Port latch INT40 Interrupt input Serial I/O3 ready output Port XC switch bit (11) Port P41 Pull-up control bit Port XC switch bit Direction register (12) Port P47 Timer Z operating mode bits Bit 2 Bit 1 Bit 0 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register INT00 Interrupt input Port XC switch bit Sub-clock generating circuit input Pull-up control bit Data bus Port latch Data bus Port latch Timer output Serial I/O1 ready output CNTR2 interrupt input (13) Port P50 Pull-up control bit Direction register (14) Port P51 Pull-up control bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register P-channel output disable bit Data bus Port latch Data bus Port latch Serial I/O2 input Serial I/O2 output Fig 14. Port block diagram (2) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 18 of 117 3803 Group (Spec.L) (15) Port P52 Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register (16) Port P53 Pull-up control bit SRDY2 output enable bit Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P54, P55 Pull-up control bit (18) Port P56 Pull-up control bit PWM function enable bit Direction register Direction register Data bus Port latch Data bus Port latch Pulse output mode Timer output PWM output CNTR Interrupt input Fig 15. Port block diagram (3) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 19 of 117 3803 Group (Spec.L) b7 b0 Port P0 pull-up control register (PULL0: address 0FF016) P00 pull-up control bit 0: No pull-up 1: Pull-up P01 pull-up control bit 0: No pull-up 1: Pull-up P02 pull-up control bit 0: No pull-up 1: Pull-up P03 pull-up control bit 0: No pull-up 1: Pull-up P04 pull-up control bit 0: No pull-up 1: Pull-up P05 pull-up control bit 0: No pull-up 1: Pull-up P06 pull-up control bit 0: No pull-up 1: Pull-up P07 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P1 pull-up control register (PULL1: address 0FF116) P10 pull-up control bit 0: No pull-up 1: Pull-up P11 pull-up control bit 0: No pull-up 1: Pull-up P12 pull-up control bit 0: No pull-up 1: Pull-up P13 pull-up control bit 0: No pull-up 1: Pull-up P14 pull-up control bit 0: No pull-up 1: Pull-up P15 pull-up control bit 0: No pull-up 1: Pull-up P16 pull-up control bit 0: No pull-up 1: Pull-up P17 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig 16. Structure of port pull-up control register (1) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 20 of 117 3803 Group (Spec.L) b7 b0 Port P2 pull-up control register (PULL2: address 0FF216) P20 pull-up control bit 0: No pull-up 1: Pull-up P21 pull-up control bit 0: No pull-up 1: Pull-up P22 pull-up control bit 0: No pull-up 1: Pull-up P23 pull-up control bit 0: No pull-up 1: Pull-up P24 pull-up control bit 0: No pull-up 1: Pull-up P25 pull-up control bit 0: No pull-up 1: Pull-up P26 pull-up control bit 0: No pull-up 1: Pull-up P27 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P3 pull-up control register (PULL3: address 0FF316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up Not used (return “0” when read) P34 pull-up control bit 0: No pull-up 1: Pull-up P35 pull-up control bit 0: No pull-up 1: Pull-up P36 pull-up control bit 0: No pull-up 1: Pull-up P37 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig 17. Structure of port pull-up control register (2) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 21 of 117 3803 Group (Spec.L) b7 b0 Port P4 pull-up control register (PULL4: address 0FF416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up P45 pull-up control bit 0: No pull-up 1: Pull-up P46 pull-up control bit 0: No pull-up 1: Pull-up P47 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 Port P5 pull-up control register (PULL5: address 0FF516) P50 pull-up control bit 0: No pull-up 1: Pull-up P51 pull-up control bit 0: No pull-up 1: Pull-up P52 pull-up control bit 0: No pull-up 1: Pull-up P53 pull-up control bit 0: No pull-up 1: Pull-up P54 pull-up control bit 0: No pull-up 1: Pull-up P55 pull-up control bit 0: No pull-up 1: Pull-up P56 pull-up control bit 0: No pull-up 1: Pull-up P57 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig 18. Structure of port pull-up control register (3) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 22 of 117 3803 Group (Spec.L) b7 b0 Port P6 pull-up control register (PULL6: address 0FF616) P60 pull-up control bit 0: No pull-up 1: Pull-up P61 pull-up control bit 0: No pull-up 1: Pull-up P62 pull-up control bit 0: No pull-up 1: Pull-up P63 pull-up control bit 0: No pull-up 1: Pull-up P64 pull-up control bit 0: No pull-up 1: Pull-up P65 pull-up control bit 0: No pull-up 1: Pull-up P66 pull-up control bit 0: No pull-up 1: Pull-up P67 pull-up control bit 0: No pull-up 1: Pull-up Note: Pull-up control is valid when the corresponding bit of the port direction register is “0” (input). When that bit is “1” (output), pull-up cannot be set to the port of which pull-up is selected. Fig 19. Structure of port pull-up control register (4) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 23 of 117 3803 Group (Spec.L) Termination of unused pins • Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. In addition, it is recommended that related registers be overwritten periodically to prevent malfunctions, etc. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Table 7 Termination of unused pins Pins P0, P1, P2, P3, P4, P5, P6 VREF AVSS XOUT Termination • Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to 10 kΩ. • Set to the output mode and open at “L” or “H” output state. Connect to VCC or VSS (GND). Connect to VCC or VSS (GND). Open (only when using external clock) Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (builtin resistor can be used). We recommend processing unused pins through a resistor which can secure IOH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 24 of 117 3803 Group (Spec.L) INTERRUPTS The 3803 group (Spec.L) interrupts are vector interrupts with a fixed priority scheme, and generated by 16 sources among 21 sources: 8 external, 12 internal, and 1 software. The interrupt sources, vector addresses(1), and interrupt priority are shown in Table 8. Each interrupt except the BRK instruction interrupt has the interrupt request bit and the interrupt enable bit. These bits and the interrupt disable flag (I flag) control the acceptance of interrupt requests. Figure 20 shows an interrupt control diagram. An interrupt requests is accepted when all of the following conditions are satisfied: • Interrupt disable flag.................................“0” • Interrupt request bit...................................“1” • Interrupt enable bit....................................“1” Though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag. Table 8 Interrupt vector addresses and priority Priority 1 2 Vector Addresses(1) High Low FFFA16 FFFD16 FFFB16 Interrupt Request Generating Conditions Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks Interrupt Source Reset(2) INT0 Timer Z INT1 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 1 Timer 2 CNTR0 CNTR1 Serial I/O3 reception Serial I/O2 Timer Z INT2 INT3 INT4 CNTR2 A/D conversion Serial I/O3 transmission BRK instruction FFFC16 At reset At detection of either rising or falling edge of INT0 input At timer Z underflow At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data reception At completion of serial I/O1 transmission shift or when transmission buffer is empty At timer X underflow At timer Y underflow 3 4 5 FFF916 FFF716 FFF516 FFF816 FFF616 FFF416 6 7 8 9 10 11 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFF216 FFF016 FFEE16 At timer 1 underflow FFEC16 At timer 2 underflow FFEA16 At detection of either rising or falling edge of CNTR0 input FFE816 At detection of either rising or falling edge of CNTR1 input At completion of serial I/O3 data reception STP release timer underflow External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected Valid when serial I/O2 is selected 12 FFE716 FFE616 At completion of serial I/O2 data transmission or reception At timer Z underflow At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At detection of either rising or falling edge of CNTR2 input 13 14 15 FFE516 FFE316 FFE116 FFE416 FFE216 FFE016 External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O3 is selected 16 FFDF16 FFDE16 At completion of A/D conversion At completion of serial I/O3 transmission shift or when transmission buffer is empty 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt NOTES: 1. Vector addresses contain interrupt jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 25 of 117 3803 Group (Spec.L) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig 20. Interrupt control diagram • Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor status register. This flag controls the acceptance of all interrupt requests except for the BRK instruction. When this flag is set to “1”, the acceptance of interrupt requests is disabled. When it is set to “0”, acceptance of interrupt requests is enabled. This flag is set to “1” with the SET instruction and set to “0” with the CLI instruction. When an interrupt request is accepted, the contents of the processor status register are pushed onto the stack while the interrupt disable flag remaines set to “0”. Subsequently, this flag is automatically set to “1” and multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. The contents of the processor status register are popped off the stack with the RTI instruction. • Interrupt Request Bits Once an interrupt request is generated, the corresponding interrupt request bit is set to “1” and remaines “1” until the request is accepted. When the request is accepted, this bit is automatically set to “0”. Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software. • Interrupt Enable Bits The interrupt enable bits control the acceptance of the corresponding interrupt requests. When an interrupt enable bit is set to “0”, the acceptance of the corresponding interrupt request is disabled. If an interrupt request occurs in this condition, the corresponding interrupt request bit is set to “1”, but the interrupt request is not accepted. When an interrupt enable bit is set to “1”, acceptance of the corresponding interrupt request is enabled. Each interrupt enable bit can be set to “0” or “1” by software. The interrupt enable bit for an unused interrupt should be set to “0”. • Interrupt Source Selection Any of the following combinations can be selected by the interrupt source selection register (003916). 1. INT0 or timer Z 2. CNTR1 or Serial I/O3 reception 3. Serial I/O2 or timer Z 4. INT4 or CNTR2 5. A/D conversion or serial I/O3 transmission • External Interrupt Pin Selection For external interrupts INT0 and INT4, the INT0, INT4 interrupt switch bit in the interrupt edge selection register (bit 6 of address 003A 16 ) can be used to select INT00 a nd INT40 p in input or INT01 and INT41 pin input. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 26 of 117 3803 Group (Spec.L) b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (returns “0” when read) INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit INT0, INT4 interrupt switch bit 0 : INT00, INT40 interrupt 1 : INT01, INT41 interrupt Not used (returns “0” when read) 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0/Timer Z interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1/Serial I/O3 receive interrupt request bit Serial I/O2/Timer Z interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4/CNTR2 interrupt request bit AD converter/Serial I/O3 transmit interrupt request bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0/Timer Z interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1/Serial I/O3 receive interrupt enable bit Serial I/O2/Timer Z interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit INT4/CNTR2 interrupt enable bit AD converter/Serial I/O3 transmit interrupt enable bit Not used (returns “0” when read) (Do not write “1”.) 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt source selection register (INTSEL : address 003916) INT0/Timer Z interrupt source selection bit 0 : INT0 interrupt 1 : Timer Z interrupt (Do not write “1” to these bits simultaneously.) Serial I/O2/Timer Z interrupt source selection bit 0 : Serial I/O2 interrupt 1 : Timer Z interrupt Not used (Do not write “1”.) INT4/CNTR2 interrupt source selection bit 0 : INT4 interrupt 1 : CNTR2 interrupt Not used (Do not write “1”.) CNTR1/Serial I/O3 receive interrupt source selection bit 0 : CNTR1 interrupt 1 : Serial I/O3 receive interrupt AD converter/Serial I/O3 transmit interrupt source selection bit 0 : A/D converter interrupt 1 : Serial I/O3 transmit interrupt Fig 21. Structure of interrupt-related registers Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 27 of 117 3803 Group (Spec.L) • Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to “1”. (ii) Interrupt Request Acceptance Based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance conditions (interrupt request bit, interrupt enable bit, and interrupt disable flag) and interrupt priority levels for accepting interrupt requests. When two or more interrupt requests are generated simultaneously, the highest priority interrupt is accepted. The value of interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next interrupt acceptance timing point. (iii) Handling of Accepted Interrupt Request The accepted interrupt request is processed. Figure 22 shows the time up to execution in the interrupt processing routine, and Figure 23 shows the interrupt sequence. Figure 24 shows the timing of interrupt request generation, interrupt request bit, and interrupt request acceptance. • Interrupt Handling Execution When interrupt handling is executed, the following operations are performed automatically. (1) Once the currently executing instruction is completed, an interrupt request is accepted. (2) The contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3. 1. High-order bits of program counter (PCH) 2. Low-order bits of program counter (PCL) 3. Processor status register (PS) (3) Concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt processing routine) is transferred from the interrupt vector to the program counter. (4) The interrupt request bit for the corresponding interrupt is set to “0”. Also, the interrupt disable flag is set to “1” and multiple interrupts are disabled. (5) The interrupt routine is executed. (6) When the RTI instruction is executed, the contents of the registers pushed onto the stack area are popped off in the order from 3 to 1. Then, the routine that was before running interrupt processing resumes. As described above, it is necessary to set the stack pointer and the jump address in the vector area corresponding to each interrupt to execute the interrupt processing routine. The interrupt request bit may be set to “1” in the following cases. • When setting the external interrupt active edge Related registers: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) • When switching the interrupt sources of an interrupt vector address where two or more interrupt sources are assigned Related registers: Interrupt source selection register (address 003916) If it is not necessary to generate an interrupt synchronized with these settings, take the following sequence. (1) Set the corresponding enable bit to “0” (disabled). (2) Set the interrupt edge selection bit (the active edge switch bit) or the interrupt source bit. (3) Set the corresponding interrupt request bit to “0” after one or more instructions have been executed. (4) Set the corresponding interrupt enable bit to “1” (enabled). Interrupt request generated Interrupt request acceptance Interrupt sequence Interrupt routine starts Main routine Stack push and Vector fetch Interrupt handling routine * 0 to 16 cycles 7 cycles 7 to 23 cycles * When executing DIV instruction Fig 22. Time up to execution in interrupt routine Push onto stack Vector fetch φ SYNC RD WR Address bus Data bus PC Not used S,SPS S-1,SPS S-2,SPS Execute interrupt routine BL AL BH AH AL,AH PCH PCL PS SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH: Vector address of each interrupt AL, AH: Jump destination address of each interrupt SPS : “0016” or “0116” ([SPS] is a page selected by the stack page selection bit of CPU mode register.) Fig 23. Interrupt sequence Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 28 of 117 3803 Group (Spec.L) Instruction cycle Internal clock φ Push onto stack Vector fetch Instruction cycle SYNC 1 2 T1 IR1 T2 IR2 T3 T1 T2 T3 : Interrupt acceptance timing points IR1 IR2 : Timings points at which the interrupt request bit is set to “1”. Note : Period 2 indicates the last φ cycle during one instruction cycle. (1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1. (2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2. The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately. Fig 24. Timing of interrupt request generation, interrupt request bit, and interrupt acceptance Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 29 of 117 3803 Group (Spec.L) TIMERS • 8-bit Timers The 3803 group (Spec.L) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and timer Y use each prescaler. Those are 8-bit prescalers. Each of the timers and prescalers has a timer latch or a prescaler latch. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are down-counters. When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of the corresponding timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. • Timer divider The divider count source is switched by the main clock division ratio selection bits of CPU mode register (bits 7 and 6 at address 003B16). When these bits are “00” (high-speed mode) or “01” (middle-speed mode), XIN is selected. When these bits are “10” (low-speed mode), XCIN is selected. • Prescaler 12 The prescaler 12 counts the output of the timer divider. The count source is selected by the timer 12, X count source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(XIN) or f(XCIN). • Timer 1 and Timer 2 The timer 1 and timer 2 counts the output of prescaler 12 and periodically set the interrupt request bit. • Prescaler X and prescaler Y The prescaler X and prescaler Y count the output of the timer divider or f(XCIN). The count source is selected by the timer 12, X count source selection register (address 000E16) and the timer Y, Z count source selection register (address 000F16) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of f(XIN) or f(XCIN); and f(XCIN). • Timer X and Timer Y The timer X and timer Y can each select one of four operating modes by setting the timer XY mode register (address 002316). (1) Timer mode • Mode selection This mode can be selected by setting “00” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation The timer count operation is started by setting “0” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). When the timer reaches “0016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) Pulse Output Mode • Mode selection This mode can be selected by setting “01” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. Regardless of the timer counting or not the output of CNTR0/CNTR1 pin is initialized to the level of specified by their active edge switch bits when writing to the timer. When the CNTR0 active edge switch bit (bit 2) and the CNTR 1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. Switching the CNTR 0 o r CNTR 1 a ctive edge switch bit will reverse the output level of the corresponding CNTR0 or CNTR1 pin. • Precautions Set the double-function port of CNTR0 /CNTR 1 p in and port P54/P55 to output in this mode. (3) Event Counter Mode • Mode selection This mode can be selected by setting “10” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation The operation is the same as the timer mode’s except that the timer counts signals input from the CNTR0 or CNTR1 pin. The valid edge for the count operation depends on the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. • Precautions Set the double-function port of CNTR0 /CNTR 1 p in and port P54/P55 to input in this mode. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 30 of 117 3803 Group (Spec.L) (4) Pulse Width Measurement Mode • Mode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and 4) of the timer XY mode register (address 002316). • Explanation of operation When the CNTR0 active edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6) of the timer XY mode register (address 002316) is “1”, the timer counts during the term of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input (“L” term). When it is “0”, the timer counts during the term of one rising edge input until the next falling edge input (“H” term). • Precautions Set the double-function port of CNTR0 /CNTR 1 p in and port P54/P55 to input in this mode. The count operation can be stopped by setting “1” to the timer X count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the timer XY mode register (address 002316). The interrupt request bit is set to “1” each time the timer underflows. • Precautions when switching count source When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 31 of 117 3803 Group (Spec.L) XIN “00” “11” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Divider Count source selection bit Data bus XCIN “10” Clock for timer 12 Clock for timer Y Main clock division ratio selection bits Clock for timer X Prescaler X latch (8) f(XCIN) Pulse width Timer mode measurement Pulse output mode mode Prescaler X (8) Timer X latch (8) Timer X (8) P54/CNTR0 CNTR0 active edge switch bit “0” To timer X interrupt request bit Event counter mode Timer X count stop bit To CNTR0 interrupt request bit “1” CNTR0 active edge switch bit “1” Q “0” Q Toggle flip-flop T R Timer X latch write pulse Pulse output mode Port P54 direction register Port P54 latch Pulse output mode Data bus Count source selection bit Clock for timer Y f(XCIN) Prescaler Y latch (8) Pulse width Timer mode measurement Pulse output mode mode Prescaler Y (8) Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit P55/CNTR1 CNTR1 active edge switch bit “0” “1” Event counter mode Timer Y count stop bit To CNTR1 interrupt request bit CNTR1 active edge switch bit “1” Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode Port P55 direction register Port P55 latch Pulse output mode “0” Data bus Prescaler 12 latch (8) Timer 1 latch (8) Timer 2 latch (8) Clock for timer 12 Prescaler 12 (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit Fig 25. Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 32 of 117 3803 Group (Spec.L) b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bits b1 b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5 b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig 26. Structure of timer XY mode register Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 33 of 117 3803 Group (Spec.L) b7 b0 Timer 12, X count source selection register (T12XCSS : address 000E16) Timer 12 count source selection bits b3 b2 b1 b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 Timer X count source selection bits b7 b6 b5 b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) 1010: 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used b7 b0 Timer Y, Z count source selection register (TYZCSS : address 000F16) Timer Y count source selection bits b3 b2 b1 b0 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) Timer Z count source selection bits b7 b6 b5 b4 0 0 0 0 : f(XIN)/2 or f(XCIN)/2 0 0 0 1 : f(XIN)/4 or f(XCIN)/4 0 0 1 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 0 : f(XIN)/32 or f(XCIN)/32 0 1 0 1 : f(XIN)/64 or f(XCIN)/64 0 1 1 0 : f(XIN)/128 or f(XCIN)/128 0 1 1 1 : f(XIN)/256 or f(XCIN)/256 1 0 0 0 : f(XIN)/512 or f(XCIN)/512 1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024 1 0 1 0 : f(XCIN) 1011: 1100: 1101: 1110: 1111: Not used 1011: 1100: 1101: 1110: 1111: Not used Fig 27. Structure of timer 12, X and timer Y, Z count source selection registers Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 34 of 117 3803 Group (Spec.L) • 16-bit Timer The timer Z is a 16-bit timer. When the timer reaches “000016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to the timer Z is set to “1”. When reading/writing to the timer Z, perform reading/writing to both the high-order byte and the low-order byte. When reading the timer Z, read from the high-order byte first, followed by the low-order byte. Do not perform the writing to the timer Z between read operation of the high-order byte and read operation of the low-order byte. When writing to the timer Z, write to the low-order byte first, followed by the high-order byte. Do not perform the reading to the timer Z between write operation of the low-order byte and write operation of the high-order byte. The timer Z can select the count source by the timer Z count source selection bits of timer Y, Z count source selection register (bits 7 to 4 at address 000F16). Timer Z can select one of seven operating modes by setting the timer Z mode register (address 002A16). (1) Timer mode • Mode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. • Interrupt When an underflow occurs, the INT0/timer Z interrupt request bit (bit 0) of the interrupt request register 1 (address 003C16) is set to “1”. • Explanation of operation During timer stop, usually write data to a latch and a timer at the same time to set the timer value. The timer count operation is started by setting “0” to the timer Z count stop bit (bit 6) of the timer Z mode register (address 002A16). When the timer reaches “000016”, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. When writing data to the timer during operation, the data is written only into the latch. Then the new latch value is reloaded into the timer at the next underflow. (2) Event counter mode • Mode selection This mode can be selected by setting “000” to the timer Z operating mode bits (bits 2 to 0) and setting “1” to the timer/event counter mode switch bit (bit 7) of the timer Z mode register (address 002A16). The valid edge for the count operation depends on the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16). When it is “0”, the rising edge is valid. When it is “1”, the falling edge is valid. • Interrupt The interrupt at an underflow is the same as the timer mode’s. • Explanation of operation The operation is the same as the timer mode’s. Set the double-function port of CNTR2 pin and port P47 to input in this mode. Figure 30 shows the timing chart of the timer/event counter mode. (3) Pulse output mode • Mode selection This mode can be selected by setting “001” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. • Explanation of operation The operation is the same as the timer mode’s. Moreover the pulse which is inverted each time the timer underflows is output from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the output starts with “H” level. When it is “1”, the output starts with “L” level. • Precautions The double-function port of CNTR 2 p in and port P4 7 i s automatically set to the timer pulse output port in this mode. The output from CNTR2 pin is initialized to the level depending on CNTR2 active edge switch bit by writing to the timer. When the value of the CNTR2 active edge switch bit is changed, the output level of CNTR2 pin is inverted. Figure 31 shows the timing chart of the pulse output mode. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 35 of 117 3803 Group (Spec.L) (4) Pulse period measurement mode • Mode selection This mode can be selected by setting “010” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse period measurement is completed, the INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to “1”. • Explanation of operation The cycle of the pulse which is input from the CNTR 2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the timer counts during the term from one falling edge of CNTR2 pin input to the next falling edge. When it is “1”, the timer counts during the term from one rising edge input to the next rising edge input. When the valid edge of measurement completion/start is detected, the 1’s complement of the timer value is written to the timer latch and “FFFF16” is set to the timer. Furthermore when the timer underflows, the timer Z interrupt request occurs and “FFFF16” is set to the timer. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. • Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period m e a s u r em e n t d e p e n d s o n t h e t i m e r v a l u e j u s t b ef o r e measurement start. Figure 32 shows the timing chart of the pulse period measurement mode. (5) Pulse width measurement mode • Mode selection This mode can be selected by setting “011” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. When the pulse widths measurement is completed, the INT4/CNTR2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003D16) is set to “1”. • Explanation of operation The pulse width which is input from the CNTR2 pin is measured. When the CNTR2 active edge switch bit (bit 5) of the timer Z mode register (address 002A16) is “0”, the timer counts during the term from one rising edge input to the next falling edge input (“H” term). When it is “1”, the timer counts during the term from one falling edge of CNTR2 pin input to the next rising edge of input (“L” term). When the valid edge of measurement completion is detected, the 1’s complement of the timer value is written to the timer latch. When the valid edge of measurement completion/start is detected, “FFFF16” is set to the timer. When the timer Z underflows, the timer Z interrupt occurs and “FFFF16” is set to the timer Z. When reading the timer Z, the value of the timer latch (measured value) is read. The measured value is retained until the next measurement completion. • Precautions Set the double-function port of CNTR2 pin and port P47 to input in this mode. A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width m e a s u r em e n t d ep e n d s o n t h e t i m e r v a l u e j u s t b ef o r e measurement start. Figure 33 shows the timing chart of the pulse width measurement mode. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 36 of 117 3803 Group (Spec.L) (6) Programmable waveform generating mode • Mode selection This mode can be selected by setting “100” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. • Explanation of operation The operation is the same as the timer mode’s. Moreover the timer outputs the data set in the output level latch (bit 4) of the timer Z mode register (address 002A16) from the CNTR2 pin each time the timer underflows. Changing the value of the output level latch and the timer latch after an underflow makes it possible to output an optional waveform from the CNTR2 pin. • Precautions The double-function port of CNTR 2 p in and port P4 7 i s automatically set to the programmable waveform generating port in this mode. Figure 34 shows the timing chart of the programmable waveform generating mode. (7) Programmable one-shot generating mode • Mode selection This mode can be selected by setting “101” to the timer Z operating mode bits (bits 2 to 0) and setting “0” to the timer/event counter mode switch bit (b7) of the timer Z mode register (address 002A16). • Count source selection In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(X IN ); or f(X CIN ) can be selected as the count source. • Interrupt The interrupt at an underflow is the same as the timer mode’s. The trigger to generate one-shot pulse can be selected by the INT1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003A16). When it is “0”, the falling edge active is selected; when it is “1”, the rising edge active is selected. When the valid edge of the INT 1 p in is detected, the INT 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003C16) is set to “1”. • Explanation of operation 1. “H” one-shot pulse; Bit 5 of timer Z mode register = “0” The output level of the CNTR2 pin is initialized to “L” at mode selection. When trigger generation (input signal to INT1 pin) is detected, “H” is output from the CNTR2 pin. When an underflow occurs, “L” is output. The “H” one-shot pulse width is set by the setting value to the timer Z register low-order and high-order. When trigger generating is detected during timer count stop, although “H” is output from the CNTR2 pin, “H” output state continues because an underflow does not occur. 2. “L” one-shot pulse; Bit 5 of timer Z mode register = “1” The output level of the CNTR2 pin is initialized to “H” at mode selection. When trigger generation (input signal to INT1 pin) is detected, “L” is output from the CNTR2 pin. When an underflow occurs, “H” is output. The “L” one-shot pulse width is set by the setting value to the timer Z loworder and high-order. When trigger generating is detected during timer count stop, although “L” is output from the CNTR2 pin, “L” output state continues because an underflow does not occur. • Precautions Set the double-function port of INT1 pin and port P42 to input in this mode. The double-function port of CNTR 2 p in and port P4 7 i s automatically set to the programmable one-shot generating port in this mode. This mode cannot be used in low-speed mode. If the value of the CNTR2 a ctive edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. Figure 35 shows the timing chart of the programmable one-shot generating mode. • Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. • Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. • Switch of interrupt active edge of CNTR2 and INT1 E ach interrupt active edge depends on setting of the CNTR 2 active edge switch bit and the INT1 active edge selection bit. • Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. • Usage of CNTR2 pin as normal I/O port P47 To use the CNTR 2 p in as normal I/O port P4 7 , set timer Z operating mode bits (b2, b1, b0) of timer Z mode register (address 002A16) to “000”. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 37 of 117 3803 Group (Spec.L) P42/INT1 Programmable one-shot generating mode CNTR2 active edge Data bus switch bit Programmable one-shot “1” generating mode Programmable one-shot generating circuit “0” To INT1 interrupt request bit Output level latch D T Programmable waveform generating mode Q Pulse output mode S Q T Q CNTR2 active edge switch bit “0” “1” Pulse output mode “001 ” “100 ” “101 Timer Z ” operating mode bits Port P47 direction register Timer Z low-order latch Port P47 latch Timer Z low-order Timer Z high-order latch Timer Z high-order To timer Z interrupt request bit Pulse period measurement mode Pulse width measurement mode Edge detection circuit To CNTR2 interrupt request bit “1 ” Clock for timer z P47/SRDY2/ CNTR2 “0 ” CNTR2 active edge switch bit XIN f(XCIN) “1 ” “0 Timer Z count stop bit ” Timer/Event counter mode switch bit XCIN Count source Divider selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) Fig 28. Block diagram of timer Z Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 38 of 117 3803 Group (Spec.L) b7 b0 Timer Z mode register (TZM : address 002A16) Timer Z operating mode bits b2 b1 b0 0 0 0 : Timer/Event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : Not available 1 1 1 : Not available Timer Z write control bit 0 : Writing data to both latch and timer simultaneously 1 : Writing data only to latch Output level latch 0 : “L” output 1 : “H” output CNTR2 active edge switch bit 0 : •Event counter mode: Count at rising edge •Pulse output mode: Start outputting “H” •Pulse period measurement mode: Measurement between two falling edges •Pulse width measurement mode: Measurement of “H” term •Programmable one-shot generating mode: After start outputting “L”, “H” one-shot pulse generated •Interrupt at falling edge 1 : •Event counter mode: Count at falling edge •Pulse output mode: Start outputting “L” •Pulse period measurement mode: Measurement between two rising edges •Pulse width measurement mode: Measurement of “L” term •Programmable one-shot generating mode: After start outputting “H”, “L” one-shot pulse generated •Interrupt at rising edge Timer Z count stop bit 0 : Count start 1 : Count stop Timer/Event counter mode switch bit (1) 0 : Timer mode 1 : Event counter mode Note 1: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig 29. Structure of timer Z mode register Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 39 of 117 3803 Group (Spec.L) FFFF16 TL 000016 TR TR TR TL : Value set to timer latch TR : Timer interrupt request Fig 30. Timing chart of timer/event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR2 pin CNTR2 CNTR2 TL : Value set to timer latch TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig 31. Timing chart of pulse output mode Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 40 of 117 3803 Group (Spec.L) 000016 T3 T2 T1 FFFF16 TR FFFF16 + T1 Signal input from CNTR2 pin CNTR2 CNTR2 CNTR2 of rising edge active TR : Timer interrupt request CNTR2 : CNTR2 interrupt request CNTR2 CNTR2 T2 T3 FFFF16 TR Fig 32. Timing chart of pulse period measurement mode (Measuring term between two rising edges) 000016 T3 T2 T1 FFFF16 TR Signal input from CNTR2 pin FFFF16 + T2 T3 T1 CNTR2 CNTR2 CNTR2 CNTR2 interrupt of rising edge active; Measurement of “L” width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request Fig 33. Timing chart of pulse width measurement mode (Measuring “L” term) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 41 of 117 3803 Group (Spec.L) FFFF16 T3 L T2 T1 000016 Signal output from CNTR2 pin L TR T1 TR CNTR2 T3 TR T2 TR CNTR2 L : Timer initial value TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig 34. Timing chart of programmable waveform generating mode FFFF16 L Signal input from INT1 pin Signal output from CNTR2 pin TR TR TR L CNTR2 L CNTR2 L L : One-shot pulse width TR : Timer interrupt request CNTR2 : CNTR2 interrupt request (CNTR2 active edge switch bit = “0”; Falling edge active) Fig 35. Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 42 of 117 3803 Group (Spec.L) SERIAL INTERFACE • Serial I/O1 S erial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O1 control register Receive buffer full flag (RBF) Receive interrupt request (RI) Address 001A16 Address 001816 Receive buffer register 1 P44/RXD1 Receive shift register 1 Shift clock Clock control circuit P46/SCLK1 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 1/4 Address 001C16 P47/SRDY1/CNTR2 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P45/TXD1 Transmit shift register 1 Transmit buffer register 1 Address 001816 Data bus Fig 36. Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD1 Serial input RXD1 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register 1 (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. Fig 37. Operation of clock synchronous serial I/O1 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 43 of 117 3803 Group (Spec.L) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) OE P44/RXD1 ST detector Address 001816 Receive buffer register 1 Character length selection bit 7 bits 8 bits PE FE SP detector Receive shift register 1 1/16 UART1 control register Clock control circuit Serial I/O1 synchronous clock selection bit Address 001B16 P46/SCLK1 Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 P45/TXD1 Character length selection bit Transmit buffer register 1 Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Transmit shift register 1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Fig 38. Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output T XD 1 ST D0 TBE=0 TBE=1 TSC=1* ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP Receive buffer read signal RBF=0 RBF=1 Serial input RXD1 RBF=1 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig 39. Operation of UART serial I/O1 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 44 of 117 3803 Group (Spec.L) [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 001816 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 Control Register (UART1CON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD1 pin. [Baud Rate Generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 45 of 117 3803 Group (Spec.L) b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P47 pin operates as normal I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as normal I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O1 pins) b7 b0 UART1 control register (UART1CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig 40. Structure of serial I/O1 control registers Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 46 of 117 3803 Group (Spec.L) 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 1 , R X D 1 , S CLK1 , and S RDY1 f unction as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. 1.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to “0” (serial I/O disabled). 1.3 Stop of transmit/receive operation • Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) • Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O disabled) (refer to 1.1). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation • Note Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 1 , R X D 1 , S CLK1 , and S RDY1 f unction as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. 2.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled). 2.3 Stop of transmit/receive operation • Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O1 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 1 , R X D 1 , S CLK1 , and S RDY1 f unction as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD1 pin and an operation failure occurs. • Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 47 of 117 3803 Group (Spec.L) 3. SRDY1 output of reception side • Note When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O1 control register again • Note Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0”. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” 7. Transmit interrupt request when transmit enable bit is set • Note When using the transmit interrupt, take the following sequence. 1. Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). 2. Set the transmit enable bit to “1”. 3. Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instruction has executed. 4. Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). • Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” 5.Data transmission control with referring to transmit shift register completion flag • Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected • Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK1 input level. Also, write data to the transmit buffer register at “H” of the SCLK1 input level. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 48 of 117 3803 Group (Spec.L) • Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register (address 001F16). [Serial I/O2 Control Register (SIO2CON)] 001D16 The serial I/O2 control register contains eight bits which control various serial I/O2 functions. b7 b0 Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2, SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: SRDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P51/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Fig 41. Structure of Serial I/O2 control register 1/8 1/16 Internal synchronous clock selection bits Data bus Divider P53 latch “0” Serial I/O2 synchronous clock selection bit “1” S CLK2 f(XIN) (f(XCIN) in low-speed mode) 1/32 1/64 1/128 1/256 P53/SRDY2 SRDY2 Synchronization circuit “1” SRDY2 output enable bit External clock “0” P52 latch “0” P52/SCLK2 “1” Serial I/O2 port selection bit P51 latch “0” Serial I/O counter 2 (3) Serial I/O2 interrupt request P51/SOUT2 “1” Serial I/O2 port selection bit P50/SIN2 Serial I/O2 register (8) Address 001F16 Fig 42. Block diagram of serial I/O2 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 49 of 117 3803 Group (Spec.L) Transfer clock (1) Serial I/O2 register write signal (2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or (f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Fig 43. Timing of serial I/O2 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 50 of 117 3803 Group (Spec.L) • Serial I/O3 S erial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O3 mode can be selected by setting the serial I/O3 mode selection bit of the serial I/O3 control register (bit 6 of address 003216) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. Data bus Serial I/O3 control register Receive buffer full flag (RBF) Receive interrupt request (RI) Address 003216 Address 003016 Receive buffer register 3 P34/RXD3 Receive shift register 3 Shift clock Clock control circuit P36/SCLK3 BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Serial I/O3 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 3 1/4 Address 002F16 P37/SRDY3 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 P35/TXD3 Transmit shift register 3 Transmit buffer register 3 Address 003016 Data bus Fig 44. Block diagram of clock synchronous serial I/O3 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD3 Serial input RXD3 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY3 Write pulse to receive/transmit buffer register (address 003016) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. Fig 45. Operation of clock synchronous serial I/O3 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 51 of 117 3803 Group (Spec.L) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit (b6) of the serial I/O3 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Serial I/O3 control register Address 003216 Receive buffer full flag (RBF) Receive interrupt request (RI) OE P34/RXD3 ST detector Address 003016 Receive buffer register 3 Character length selection bit 7 bits 8 bits PE FE SP detector Receive shift register 3 1/16 UART3 control register Clock control circuit Serial I/O3 synchronous clock selection bit Address 003316 P36/SCLK3 Frequency division ratio 1/(n+1) Baud rate generator 3 Address 002F16 ST/SP/PA generator 1/16 P35/TXD3 Character length selection bit Transmit buffer register 3 Address 003016 Data bus Transmit buffer empty flag (TBE) Serial I/O3 status register Address 003116 Transmit shift register 3 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) BRG count source selection bit f(XIN) (f(XCIN) in low-speed mode) 1/4 Fig 46. Block diagram of UART serial I/O3 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output T XD 3 ST D0 TBE=0 TBE=1 TSC=1* ST D0 D1 SP * Generated at 2nd bit in 2-stop-bit mode D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD3 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O3 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1”. 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0. Fig 47. Operation of UART serial I/O3 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 52 of 117 3803 Group (Spec.L) [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 003016 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O3 Status Register (SIO3STS)] 003116 The read-only serial I/O3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O3 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O3 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE (bit 7 of the serial I/O3 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O3 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O3 Control Register (SIO3CON)] 003216 The serial I/O3 control register consists of eight control bits for the serial I/O3 function. [UART3 Control Register (UART3CON)] 003316 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the P35/TXD3 pin. [Baud Rate Generator 3 (BRG3)] 002F16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 53 of 117 3803 Group (Spec.L) b7 b0 Serial I/O3 status register (SIO3STS : address 003116) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O3 control register (SIO3CON : address 003216) BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O3 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O3 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O3 is selected, external clock input divided by 16 when UART is selected. SRDY3 output enable bit (SRDY) 0: P37 pin operates as normal I/O pin 1: P37 pin operates as SRDY3 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O3 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O3 enable bit (SIOE) 0: Serial I/O3 disabled (pins P34 to P37 operate as normal I/O pins) 1: Serial I/O3 enabled (pins P34 to P37 operate as serial I/O3 pins) b7 b0 UART3 control register (UART3CON : address 003316) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P35/TXD3 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig 48. Structure of serial I/O3 control registers Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 54 of 117 3803 Group (Spec.L) 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O3 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 3 , R X D 3 , S CLK3 , and S RDY3 f unction as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. 1.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O3 enable bit to “0” (serial I/O disabled). 1.3 Stop of transmit/receive operation • Note Clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) • Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O3 enable bit to “0” (serial I/O disabled) (refer to 1.1). 2. Notes when selecting clock asynchronous serial I/O 2.1 Stop of transmission operation • Note Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 3 , R X D 3 , S CLK3 , and S RDY3 f unction as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. 2.2 Stop of receive operation • Note Clear the receive enable bit to “0” (receive disabled). 2.3 Stop of transmit/receive operation • Note 1 (only transmission operation is stopped) Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/O3 enable bit to “0”. • Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O3 enable bit is cleared to “0” (serial I/O disabled), the internal transmission is running (in this case, since pins T X D 3 , R X D 3 , S CLK3 , and S RDY3 f unction as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O3 enable bit is set to “1” at this time, the data during internally shifting is output to the TXD3 pin and an operation failure occurs. • Note 2 (only receive operation is stopped) Clear the receive enable bit to “0” (receive disabled). Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 55 of 117 3803 Group (Spec.L) 3. SRDY3 output of reception side • Note When signals are output from the SRDY3 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY3 output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/O3 control register again • Note Set the serial I/O3 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0”. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” 7. Transmit interrupt request when transmit enable bit is set • Note When using the transmit interrupt, take the following sequence. 1. Set the serial I/O3 transmit interrupt enable bit to “0” (disabled). 2. Set the transmit enable bit to “1”. 3. Set the serial I/O3 transmit interrupt request bit to “0” after 1 or more instruction has executed. 4. Set the serial I/O3 transmit interrupt enable bit to “1” (enabled). • Reason When the transmit enable bit is set to “1”, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. Set the bits 0 to 3 and bit 6 of the serial I/O3 control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” 5.Data transmission control with referring to transmit shift register completion flag • Note After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected • Note When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK3 input level. Also, write data to the transmit buffer register at “H” of the SCLK input level. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 56 of 117 3803 Group (Spec.L) PULSE WIDTH MODULATION (PWM) The 3803 group (Spec.H QzROM version) has PWM functions with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2 or the clock input XCIN or that clock input divided by 2 in low-speed mode. • Data Setting The PWM output pin also functions as port P56. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255): PWM period = 255 × (n+1) / f(XIN) = 31.875 × (n+1) µs (when f(XIN) = 8 MHz, count source selection bit = “0”) Output pulse “H” term = PWM period × m / 255 = 0.125 × (n+1) × m µs (when f(XIN) = 8 MHz, count source selection bit = “0”) • PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 31.875 × m × (n+1) 255 µs PWM output T = [31.875 × (n+1)] µs m : Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source selection bit = “0”) Fig 49. Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch Count source selection bit XIN (XCIN at lowspeed mode) “0” “1” PWM prescaler PWM register latch Port P56 PWM register 1/2 Port P56 latch PWM function enable bit Fig 50. Block diagram of PWM function Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 57 of 117 3803 Group (Spec.L) b7 b0 PWM control register (PWMCON: address 002B16) PWM function enable bit 0 : PWM disabled 1 : PWM enabled Count source selection bit 0 : f(XIN) (f(XCIN) at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return “0” when read) Fig 51. Structure of PWM control register A PWM output T PWM register write signal PWM prescaler write signal B C B C T = T2 T T2 (Changes “H” term from “A” to “ B”.) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig 52. PWM output timing when PWM register or PWM prescaler is changed The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows: n+1 ---------------------- sec 2 × f ( X IN ) n + 1--------------- sec f ( X IN ) (Count source selection bit = 0, where n is the value set in the prescaler) (Count source selection bit = 1, where n is the value set in the prescaler) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 58 of 117 3803 Group (Spec.L) A/D CONVERTER (successive approximation type) [AD Conversion Register 1, 2 (AD1, AD2)] 0035 16 , 003816 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. Bit 7 of the AD conversion register 2 is the conversion mode selection bit. When this bit is set to “0”, the A/D converter becomes the 10-bit A/D mode. When this bit is set to “1”, that becomes the 8-bit A/D mode. The conversion result of the 8-bit A/D mode is stored in the AD conversion register 1. As for 10-bit A/D mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the AD conversion registers 1, 2 after A/D conversion is completed (in Figure 54). As for 10-bit A/D mode, the 8-bit reading inclined to MSB is performed when reading the AD converter register 1 after A/D conversion is started; and when the AD converter register 1 is read after reading the AD converter register 2, the 8-bit reading inclined to LSB is performed. [AD/DA Control Register (ADCON)] 003416 The AD/DA control register controls the A/D conversion process. Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion, and changes to “1” when an A/D conversion ends. Writing “0” to this bit starts the A/D conversion. • Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS a nd V REF i nto 1024, and that outputs the comparison voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode). The A/D converter successively compares the comparison voltage Vref in each mode, dividing the V REF v oltage (see below), with the input voltage. • 10-bit A/D mode (10-bit reading) V REF Vref = ------------- × n (n = 0 − 1023) 1024 • 10-bit A/D mode (8-bit reading) V REF Vref = ------------- × n (n = 0 − 255) 256 • 8-bit A/D mode V REF Vref = ------------- × (n − 0.5) (n = 1 − 255) 256 =0 (n = 0) • Channel Selector The channel selector selects one of ports P67/AN7 to P60/AN0 or P07/AN15 to P00/AN8, and inputs the voltage to the comparator. • Comparator and Control Circuit The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(X IN ) t o 500 kHz or more during an A/D conversion. b7 b0 AD/DA control register (ADCON : address 003416) Analog input pin selection bits 1 b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: 1: 0: 1: 0: 1: 0: 1: P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 or or or or or or or or P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Analog input pin selection bit 2 0: AN0 to AN7 side 1: AN8 to AN15 side Not used (returns “0” when read) DA1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA2 output enable bit 0: DA2 output disabled 1: DA2 output enabled Fig 53. Structure of AD/DA control register 10-bit reading (Read address 003816 before 003516) AD conversion register 2 (AD2: address 003816) AD conversion register 1 (AD1: address 003516) b7 0 b0 b9 b8 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : Bits 2 to 6 of address 003816 become “0” at reading. 8-bit reading (Read only address 003516) AD conversion register 1 (AD1: address 003516) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 Fig 54. Structure of 10-bit A/D mode reading Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 59 of 117 3803 Group (Spec.L) Data bus AD/DA control register b7 (Address 003416) 4 b0 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 A/D control circuit AD conversion register 2 AD conversion register 1 10 Resistor ladder A/D converter interrupt request Comparator Channel selector (Address 003816) (Address 003516) VREF AVSS Fig 55. Block diagram of A/D converter Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 60 of 117 3803 Group (Spec.L) D/A CONVERTER The 3803 group (Spec.L) has two internal D/A converters (DA1 and DA2) with 8-bit resolution. The D/A conversion is performed by setting the value in each DA conversion register. The result of D/A conversion is output from the DA1 or DA2 pin by setting the DA output enable bit to “1”. When using the D/A converter, the corresponding port direction register bit (P30 /DA 1 o r P3 1 /DA 2 ) must be set to “0” (input status). The output analog voltage V is determined by the value n (decimal notation) in the DA conversion register as follows: V = VREF × n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the DA conversion registers are cleared to “0016”, and the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/DA2 pins become high impedance. The DA output does not have buffers. Accordingly, connect an external buffer when driving a low-impedance load. DA1 conversion register (8) DA1 output enable bit Data bus R-2R resistor ladder P30/DA1 DA2 conversion register (8) DA2 output enable bit R-2R resistor ladder P31/DA2 Fig 56. Block diagram of D/A converter “0” DA1 output enable bit R P30/DA1 “1” 2R MSB DA1 conversion register “0” “1” R 2R R 2R R 2R R 2R R 2R R 2R 2R 2R LSB AVSS VREF Fig 57. Equivalent connection circuit of D/A converter (DA1) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 61 of 117 3803 Group (Spec.L) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. • Watchdog Timer Initial Value Watchdog timer L is set to “FF16” and watchdog timer H is set to “FF16” by writing to the watchdog timer control register (address 001E16) or at a reset. Any write instruction that causes a write signal can be used, such as the STA, LDM, CLB, etc. Data can only be written to bits 6 and 7 of the watchdog timer control register. Regardless of the value written to bits 0 to 5, the abovementioned value will be set to each timer. Bit 6 can be written only once after releasing reset. After rewriting it is disable to write any data to this bit. • Watchdog Timer Operations The watchdog timer stops at reset and starts to count down by writing to the watchdog timer control register (address 001E16). An internal reset occurs at an underflow of the watchdog timer H. The reset is released after waiting for a reset release time and the program is processed from the reset vector address. Accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. If writing to the watchdog timer control register is not performed once, the watchdog timer does not function. • Bit 6 of Watchdog Timer Control Register • When bit 6 of the watchdog timer control register is “0”, the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting (Note.) . When executing the WIT instruction, the watchdog timer does not stop. • When bit 6 is “1”, execution of STP instruction causes an internal reset. When this bit is set to “1” once, it cannot be rewritten to “0” by program. Bit 6 is “0” at reset. The following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer H. Bit 7 of the watchdog timer control register is “0”: when XCIN = 32.768 kHz; 32 s when XIN = 16 MHz; 65.536 ms Bit 7 of the watchdog timer control register is “1”: when XCIN = 32.768 kHz; 125 ms when XIN = 16 MHz; 256 µs Note. The watchdog timer continues to count even while waiting for a XCIN “10” Main clock division ratio selection bits(1) “FF16” is set when watchdog timer control register is written to. Watchdog timer L (8) “0” “1” Watchdog timer H (8) Data bus “FF16” is set when watchdog timer control register is written to. 1/16 “00” “01” XIN Watchdog timer H count source selection bit STP instruction function selection bit STP instruction Reset circuit Internal reset RESET Note 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig 58. Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001E16) Watchdog timer H (for read-out of high-order 6 bit) STP instruction function selection bit 0: Entering stop mode by execution of STP instruction 1: Internal reset by execution of STP instruction Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig 59. Structure of Watchdog timer control register Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 62 of 117 3803 Group (Spec.L) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of X IN . Then the RESET p in is returned to an “H” level (the power source voltage should be between 1.8 V and 5.5 V (between 2.7 V to 5.5 V for flash memory version), and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 ( high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage for the mask ROM version is less than 0.29 V for VCC of 1.8 V. In the flash memory version, input to the RESET p in in the following procedure. • When power source is stabilized (1) Input “L” level to RESET pin. (2) Input “L” level for 16 cycles or more to XIN pin. (3) Input “H” level to RESET pin. • At power-on (1) Input “L” level to RESET pin. (2) Increase the power source voltage to 2.7 V. (3) Wait for td(P-R) until internal power source has stabilized. (4) Input “L” level for 16 cycles or more to XIN pin. (5) Input “H” level to RESET pin. VCC RESET VCC 0V RESET 0V (1) 0.2VCC or less (2) 5V VCC RESET VCC Power source voltage detection circuit 0V 5V 2.7 V RESET 0V td(P-R)+XIN16 cycles or more Example at VCC = 5 V Notes 1: Reset release voltage mask ROM version: VCC = 1.8 V Flash memory version: VCC = 2.7 V 2: In the flash memory version, this time is required td(P-R)+XIN 16 cycles or more. • • Fig 60. Reset circuit example XIN φ RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN : 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig 61. Reset sequence Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 63 of 117 3803 Group (Spec.L) Address (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) Timer Z (low-order) (TZL) (35) Timer Z (high-order) (TZH) (36) Timer Z mode register (TZM) (37) PWM control register (PWMCON) (38) PWM prescaler (PREPWM) (39) PWM register (PWM) (40) Baud rate generator 3 (BRG3) Address 002816 002916 002A16 002B16 Register contents FF16 FF16 0016 0016 002C16 X X X X X X X X 002D16 X X X X X X X X 002F16 X X X X X X X X (41) Transmit/Receive buffer register 3 (TB3/RB3) 003016 X X X X X X X X (42) Serial I/O3 status register (SIO3STS) (43) Serial I/O3 control register (SIO3CON) (44) UART3 control register (UART3CON) (45) AD/DA control register (ADCON) (46) AD conversion register 1 (AD1) (47) DA1 conversion register (DA1) (48) DA2 conversion register (DA2) (49) AD conversion register 2 (AD2) (50) Interrupt source selection register (INTSEL) (51) Interrupt edge selection register (INTEDGE) (52) CPU mode register (CPUM) (53) Interrupt request register 1 (IREQ1) (54) Interrupt request register 2 (IREQ2) (55) Interrupt control register 1 (ICON1) (56) Interrupt control register 2 (ICON2) (57) Flash memory control register 0 (FMCR0) (58) Flash memory control register 1 (FMCR1) (59) Flash memory control register 2 (FMCR2) (60) Port P0 pull-up control register (PULL0) (61) Port P1 pull-up control register (PULL1) (62) Port P2 pull-up control register (PULL2) (63) Port P3 pull-up control register (PULL3) (64) Port P4 pull-up control register (PULL4) (65) Port P5 pull-up control register (PULL5) (66) Port P6 pull-up control register (PULL6) (67) Processor status register 003116 1 0 0 0 0 0 0 0 003216 0016 (10) Port P4 direction register (P4D) (11) Port P5 (P5) (12) Port P5 direction register (P5D) (13) Port P6 (P6) (14) Port P6 direction register (P6D) 003316 1 1 1 0 0 0 0 0 003416 0 0 0 0 1 0 0 0 003516 X X X X X X X X 003616 003716 0016 0016 (15) Timer 12, X count source selection register (T12XCSS) 000E16 0 0 1 1 0 0 1 1 (16) Timer Y, Z count source selection register (TYZCSS) (17) MISRG 000F16 0 0 1 1 0 0 1 1 001016 0016 003816 0 0 0 0 0 0 X X 003916 003A16 0016 0016 (18) Transmit/Receive buffer register 1 (TB1/RB1) 001816 X X X X X X X X (19) Serial I/O1 status register (SIO1STS) (20) Serial I/O1 control register (SIO1CON) (21) UART1 control register (UART1CON) (22) Baud rate generator 1 (BRG1) (23) Serial I/O2 control register (SIO2CON) (24) Watchdog timer control register (WDTCON) (25) Serial I/O2 register (SIO2) (26) Prescaler 12 (PRE12) (27) Timer 1 (T1) (28) Timer 2 (T2) (29) Timer XY mode register (TM) (30) Prescaler X (PREX) (31) Timer X (TX) (32) Prescaler Y (PREY) (33) Timer Y (TY) 001916 1 0 0 0 0 0 0 0 001A16 0016 003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0016 0016 0016 0016 001B16 1 1 1 0 0 0 0 0 001C16 X X X X X X X X 001D16 0016 001E16 0 0 1 1 1 1 1 1 001F16 X X X X X X X X 002016 002116 002216 002316 002416 002516 002616 002716 FF16 0116 FF16 0016 FF16 FF16 FF16 FF16 0FE016 0 0 0 0 0 0 0 1 0FE016 0 1 0 0 0 0 0 0 0FE216 0 1 0 0 0 1 0 1 0FF016 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 (PS) (PCH) (PCL) 0016 0016 0016 0016 0016 0016 0016 XXXXX1XX FFFD16 contents FFFC16 contents Note : X: Not fixed. Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. (68) Program counter Fig 62. Internal status at reset Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 64 of 117 3803 Group (Spec.L) CLOCK GENERATING CIRCUIT The 3803 group (Spec.L) has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub clock XCINXCOUT oscillation circuit. An oscillation circuit can be formed by connecting a resonator between X IN a nd X OUT ( X CIN a nd X COUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN a nd X OUT s ince a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feedback resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN o scillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. • Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and X IN a nd X CIN o scillators stop. When the oscillation stabilizing time set after STP instruction released bit (bit 0 of address 001016) is “0”, the prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the oscillation stabilizing time set after STP instruction released bit is “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains at “H”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruction. • If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(X IN ) > 3×f(XCIN). • When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. • When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 65 of 117 3803 Group (Spec.L) XCIN XCOUT Rf CCIN XIN XOUT Rd Rd CCOUT CIN COUT Note 1 : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig 63. Ceramic resonator circuit X CIN Rf X COUT Rd X IN X OUT Open C CIN V CC V SS External oscillation circuit V CC V SS Fig 64. External clock input circuit Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 66 of 117 3803 Group (Spec.L) XCIN XCOUT “0” “1” Port XC switch bit XIN (4) XOUT Main clock division ratio selection bits(1) Low-speed mode 1/2 1/4 Divider Prescaler 12 Timer 1 High-speed or middle-speed mode (3) Reset or STP instruction(2) Main clock division ratio selection bits(1) Middle-speed mode High-speed or low-speed mode Main clock stop bit Timing φ (internal clock) Q S R STP instruction WIT instruction S R Q QS R STP instruction Reset Reset Interrupt disable flag l Interrupt request Notes1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port XC switch bit (b4) to “1”. 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is “1” , set the appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig 65. System clock generating circuit block diagram (Single-chip mode) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 67 of 117 3803 Group (Spec.L) Reset Middle-speed mode (f(φ) = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM6 “1”←→”0” High-speed mode (f(φ) = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM 4 “1”←→ ”0” 4 → C M ”← 0” “1 M 6 → ” C ”← “1 ”0 ” C “0 M 4 ”← C “1 M 6 → ” 1” ”← → ”0 ” Middle-speed mode (f(φ) = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM6 “1”←→”0” “1 ”← 6 → ”1 ” ”0 ” Low-speed mode (f(φ) = 16 kHz) CM7=1 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM 7 “1”←→ ”0” C “0 M 7 C M ”← → High-speed mode (f(φ) = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM 4 “1”←→ ”0” b7 b4 CPU mode register (CPUM : address 003B16) CM 5 “1”←→ ”0” Low-speed mode (f(φ) = 16 kHz) CM7=1 CM6=0 CM5=1 (8 MHz stopped) CM4=1 (32 kHz oscillating) CM4 : Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN-XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 (High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/highspeed mode. 5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/ high-speed mode. 7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal clock. Fig 66. State transitions of system clock Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 68 of 117 3803 Group (Spec.L) FLASH MEMORY MODE The 3803 group (Spec.L)’s flash memory version has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). This flash memory version has some blocks on the flash memory as shown in Figure 67 and each block can be erased. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Summary Table 9 lists the summary of the 3803 group (Spec.L) flash memory version. Table 9 Summary of 3803 group (Spec.L)’s flash memory version Item Power source voltage (VCC) Program/Erase VPP voltage (VPP) Flash memory mode Erase block division User ROM area/Data ROM area Boot ROM area (1) Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection NOTE: Specifications VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode Refer to Figure 67. Not divided (4 Kbytes) In units of bytes Block erase Program/Erase control by software command 5 commands 100(Max.) Available in parallel I/O mode and standard serial I/O mode 1. The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and written in only parallel I/O mode. Table 10 Electrical characteristics of flash memory (program ROM) Symbol − − Parameter Byte programming time (Block 1) (Block 2) Block erase time (Block 3) (Block A, B) Test conditions VCC = 5.0 V, Topr = 25 °C VCC = 5.0 V, Topr = 25 °C Min. − − − − − Limits Typ. 60 0.5 0.9 1.3 0.3 Max. 400 9 9 9 9 Unit µs s s s s NOTES: 1. VCC = AVCC = 2.7 V to 5.5 V, Topr = 0 °C to 60 °C, unless otherwise noted. 2. Definition of programming/erase count The programming/erase count refers to the number of erase operations per block. For example, if block A is a 2 Kbyte block and 2,048 1-byte writes are performed, all to different addresses, after which block A is erased, the programming/erase count is 1. Note that for each erase operation it is not possible to perform more than one programming (write) operation to the same address (overwrites prohibited). 3. This is the number of times for which all electrical characteristics are guaranteed after a programming or erase operation. (The guarantee covers the range from 1 to maximum value.) 4. On systems where reprogramming is performed a large number of times, it is possible to reduce the effective number of overwrites by sequentially shifting the write address, so that as much of the available area of the block is used up through successive programming (write) operations before an erase operation is performed. For example, if each programming operation uses 16 bytes of space, a maximum of 128 programming operations may be performed before it becomes necessary to erase the block in order to continue. In this way the effective number of overwrites can be kept low. The effective overwrite count can be further reduced by evenly dividing operations between block A and block B. It is recommended that data be retained on the number of times each block has been erased and a limit count set. 5. If a block erase error occurs, execute the clear status register command followed by the block erase command a minimum of three times and until the erase error is no longer generated. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 69 of 117 3803 Group (Spec.L) Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 67 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset and the CNVSS pin high after pulling the P45/TxD1 pin and CNVSS pin high, the CPU starts operating (start address of program is stored into addresses FFFC 16 a nd FFFD 16 ) using the control program in the Boot ROM area. This mode is called the “Boot mode”. Also, User ROM area can be rewritten using the control program in the Boot ROM area. Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. CPU Rewrite Mode In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 67 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed. 000016 User ROM area SFR area 004016 RAM 083F16 Internal RAM area (2 Kbytes) 180016 200016 100016 Data block B: 2 Kbytes Data block A: 2 Kbytes Block 3: 24 Kbytes Notes 1: The boot ROM area can be rewritten in a parallel I/O mode. (Access to except boot ROM area is disabled.) 2: To specify a block, use the maximum address in the block. 3: The mask ROM version has the reserved ROM area. Note the difference of the area. F00016 E00016 Block 0: 8 Kbytes FFFF16 FFFF16 FFFF16 Boot ROM area 4 Kbytes 0FE016 SFR area 0FFF16 100016 C00016 Internal flash memory area (60 Kbytes) Block 1: 8 Kbytes 800016 Block 2: 16 Kbytes Fig 67. Block diagram of built-in flash memory Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 70 of 117 3803 Group (Spec.L) Outline Performance CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM area before it can be executed. The MCU enters CPU rewrite mode by setting “1” to the CPU rewrite mode select bit (bit 1 of address 0FE016). Then, software commands can be accepted. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 68 shows the flash memory control register 0. Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. And then, software commands can be accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in the internal RAM for write to bit 1. To set this bit 1 to “1”, it is necessary to write “0” and then write “1” in succession to bit 1. The bit can be set to “0” by only writing “0”. Bit 2 of the flash memory control register 0 is the 8 KB user block E/W enable bit. By setting combination of bit 4 of the flash memory control register 2 and this bit as shown in Table 11, E/W is disabled to user block in the CPU rewriting mode. Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when flash memory access has failed. When the CPU rewrite mode select bit is “1”, setting “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 5 of the flash memory control register 0 is the User ROM area select bit and is valid only in the boot mode. Setting this bit to “1” in the boot mode switches an accessible area from the boot ROM area to the user ROM area. To use the CPU rewrite mode in the boot mode, set this bit to “1”. To rewrite bit 5, execute the useroriginal reprogramming control software transferred to the internal RAM in advance. Bit 6 of the flash memory control register 0 is the program status flag. This bit is set to “1” when writing to flash memory is failed. When program error occurs, the block cannot be used. Bit 7 of the flash memory control register 0 is the erase status flag. This bit is set to “1” when erasing flash memory is failed. When erase error occurs, the block cannot be used. Figure 69 shows the flash memory control register 1. Bit 0 of the flash memory control register 1 is the Erase suspend enable bit. By setting this bit to “1”, the erase suspend mode to suspend erase processing temporaly when block erase command is executed can be used. In order to set this bit to “1”, writing “0” and “1” in succession to bit 0. In order to set this bit to “0”, write “0” only to bit 0. Bit 1 of the flash memory control register 1 is the erase suspend request bit. By setting this bit to “1” when erase suspend enable bit is “1”, the erase processing is suspended. Bit 6 of the flash memory control register 1 is the erase suspend flag. This bit is cleared to “0” at the flash erasing. b7 b0 Flash memory control register 0 (FMCR0: address : 0FE016: initial value: 0116) RY/BY status flag 0 : Busy (being written or erased) 1 : Ready CPU rewrite mode select bit(1) 0 : CPU rewrite mode invalid 1 : CPU rewrite mode valid 8 KB user block E/W enable bit(1, 2) 0 : E/W disabled 1 : E/W enabled Flash memory reset bit(3, 4) 0 : Normal operation 1 : reset Not used (do not write “1” to this bit.) User ROM area select bit(5) 0 : Boot ROM area is accessed 1 : User ROM area is accessed Program status flag 0: Pass 1: Error Erase status flag 0: Pass 1: Error Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: This bit can be written only when CPU rewrite mode select bit is “1”. 3: Effective only when the CPU rewrite mode select bit = “1”. Fix this bit to “0” when the CPU rewrite mode select bit is “0”. 4: When setting this bit to “1” (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 µs. 5: Write to this bit in program on RAM Fig 68. Structure of flash memory control register 0 b7 b0 Flash memory control register 1 (FMCR1: address : 0FE116: initial value: 4016) Erase Suspend enble bit(1) 0 : Suspend invalid 1 : Suspend valid Erase Suspend request bit(2) 0 : Erase restart 1 : Suspend request Not used (do not write “1” to this bit.) Erase Suspend flag 0 : Erase active 1 : Erase inactive (Erase Suspend mode) Not used (do not write “1” to this bit.) Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the suspend enable bit = “1”. Fig 69. Structure of flash memory control register 1 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 71 of 117 3803 Group (Spec.L) b7 b0 Flash memory control register 2 (FMCR2: address : 0FE216: initial value: 4516) Not used Not used (do not write “1” to this bit.) Not used All user block E/W enable bit(1, 2) 0 : E/W disabled 1 : E/W enabled Not used Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the CPU rewrite mode select bit = “1”. Fig 70. Structure of flash memory control register 2 Table 11 State of E/W inhibition function All user block E/W enable bit 0 0 1 1 8 KB user block E/W enable bit 0 1 0 1 8 KB × 2 block Addresses C00016 to FFFF16 E/W disabled E/W disabled E/W disabled E/W enabled 16 KB + 24 KB block Addresses 200016 to BFFF16 E/W disabled E/W disabled E/W enabled E/W enabled Data block Addresses 100016 to 1FFF16 E/W enabled E/W enabled E/W enabled E/W enabled Figure 71 shows a flowchart for setting/releasing CPU rewrite mode. Start Single-chip mode or Boot mode Set CPU mode register(1) Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal RAM (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Set all user block E/W enable bit to “1” (by writing “0” and then “1” in succession) Set 8 KB user block E/W enable bit (At E/W disabled; writing “0” , at E/W enabled; writing “0” and then “1” in succession Using software command executes erase, program, or other operation Execute read array command(2) Set all user block E/W enable bit to “0” Set 8 KB user block E/W enable bit to “0” Write “0” to CPU rewrite mode select bit End Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command. Fig 71. CPU rewrite mode set/release flowchart be sure to execute Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 72 of 117 3803 Group (Spec.L) Take the notes described below when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the clock division ratio selection bits (bits 6 and 7 of address 003B16). (2) Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. (3) Interrupts The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. (4) Watchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. (5) Reset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVSS = “H”, so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 73 of 117 3803 Group (Spec.L) Software Commands Table 12 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. • Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained until another command is written. • Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. • Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. • Program Command (4016) Program operation starts when the command code “40 16 ” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by read status register or the RY/BY status flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written. Write The RY/BY status flag of the flash memory control register is “0” during write operation and “1” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Start Write “4016” Write address Write data Read status register SR7 = “1”? or RY/BY = “1”? NO YES NO SR4 = “0”? YES Program completed Program error Fig 72. Program flowchart Table 12 List of software commands (CPU rewrite mode) Command Read array Read status register Clear status register Program Block erase cycle number 1 2 1 2 2 First bus cycle Second bus cycle Mode Write Write Write Write Write Address X(4) X X X X Data (D0 to D7) FF16 7016 5016 4016 2016 Mode Address Data (D0 to D7) SRD(1) WD(2) D016 Read Write Write X WA(2) BA(3) NOTES: 1. 2. 3. 4. SRD = Status Register Data WA = Write Address, WD = Write Data BA = Block Address to be erased (Input the maximum address of each block.) X denotes a given address in the User ROM area. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 74 of 117 3803 Group (Spec.L) • Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed by read status register or the RY/BY status flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Start Write “2016” Write “D016” Blockaddress Read status register SR7 = “1”? or RY/BY = “1”? NO YES SR5 = “0”? YES Erase completed (write read command “FF16”) NO Erase error Fig 73. Erase flowchart Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 75 of 117 3803 Group (Spec.L) • Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 13 shows the status register. Each bit in this register is explained below. • Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). • Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is reset to “0”. • Program status (SR4) T he program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is reset to “0” when it is cleared. If “1” is written for any of the SR5 and SR4 bits, the read array, program, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. Table 13 Definition of each bit in status register Each bit of SRD bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition “1” Ready − Terminated in error Terminated in error − − − − “0” Busy − Terminated normally Terminated normally − − − − Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 76 of 117 3803 Group (Spec.L) Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 74 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = “1” and YES SR5 = “1”? Command sequence error Execute the clear status register command (50 16) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. NO SR5 = “0”? YES SR4 = “0”? YES End (block erase, program) NO Program error Should a program error occur, the block in error cannot be used. NO Erase error Should an erase error occur, the block in error cannot be used. Note: When one of SR5 and SR4 is set to “1”, none of the read array, program, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig 74. Full status check flowchart and remedial procedure for errors Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 77 of 117 3803 Group (Spec.L) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. • ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address (address FFDB 16 ) in parallel I/O mode. Figure 75 shows the ROM code protect control address (address FFDB16). (This address exists in the User ROM area.) If one or both of the pair of ROM code protect bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be readout or modified. Once the ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits. Rewriting of only the ROM code protect control address (address FFDB16) cannot be performed. When rewriting the ROM code protect reset bit, rewrite the whole user ROM area (block 0) containing the ROM code protect control address. b7 1 b0 1 ROM code protect control address (address FFDB16) ROMCP (FF16 when shipped) Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2)(1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (ROMCR)(3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1)(1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode. Fig 75. Structure of ROM code protect control address Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 78 of 117 3803 Group (Spec.L) • ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD416 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ROM code protect control Interrupt vector area Fig 76. ID code store addresses Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 79 of 117 3803 Group (Spec.L) Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 3803 group (Spec.L) flash memory version. For details, refer to the userÅfs manual of each writer manufacturer. • User ROM and Boot ROM Areas In parallel I/O mode, the User ROM and Boot ROM areas shown in Figure 67 can be rewritten. Both areas of flash memory can be operated on in the same way. The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF 16 . Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the fac-tory. Therefore, using the MCU in standard serial I/O mode, do not rewrite to the Boot ROM area. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 80 of 117 3803 Group (Spec.L) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the CNVSS pin and “H” to the P4 5 ( BOOTENT) pin, and releasing the reset operation. (In the ordinary microcomputer mode, set CNVSS pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. The standard serial I/ O mode has standard serial I/O mode 1 of the clock synchronous serial and standard serial I/O mode 2 of the clock asynchronous serial. Table 14 and 15 show description of pin function (standard serial I/O mode). Figure 77 to 80 show the pin connections for the standard serial I/O mode. In standard serial I/O mode, only the User ROM area shown in Figure 67 can be rewritten. The Boot ROM area cannot be written. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, this function determines whether the ID code sent from the peripheral unit (programmer) and those written in the flash memory match. The commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 81 of 117 3803 Group (Spec.L) Table 14 Description of pin function (Flash Memory Serial I/O Mode 1) Pin name VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00−P07, P10−P17, P20−P27, P30−P37, P40−P43, P50−P57, P60−P67 P44 P45 P46 P47 CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port I I/O Signal name Power supply I/O I I I I O Function Apply 2.7 to 5.5 V to the VCC pin and 0 V to the VSS pin. After input of port is set, input “H” level. Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. Connect AVSS to VSS. Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. RxD input TxD output SCLK input BUSY output I O I O Serial data input pin. Serial data output pin. Serial clock input pin. BUSY signal output pin. Table 15 Description of pin function (Flash Memory Serial I/O Mode 2) Pin name VCC,VSS CNVSS RESET XIN XOUT AVSS VREF P00−P07, P10−P17, P20−P27, P30−P37, P40−P43, P50−P57, P60−P67 P44 P45 P46 P47 CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port I I/O Signal name Power supply I/O I I I I O Function Apply 2.7 to 5.5 V to the VCC pin and 0 V to the VSS pin. After input of port is set, input “H” level. Reset input pin. To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. Connect AVSS to VSS. Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. RxD input TxD output SCLK input BUSY output I O I O Serial data input pin. Serial data output pin. Input “L” level. BUSY signal output pin. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 82 of 117 3803 Group (Spec.L) P1 0/INT 41 P0 0/AN 8 P1 1/INT 01 P0 3/AN 11 P0 4/AN 12 P0 5/AN 13 P0 6/AN 14 P0 2/AN 10 P0 1/AN 9 P0 7/AN 15 P1 2 P1 3 P1 4 P1 5 P1 6 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33 P32 P31/DA2 P30/DA1 VCC VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 33 P1 7 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 RESET CNVSS VSS M38039FFLHP/KP * P5 5/CNTR 1 P5 4/CNTR 0 P5 1/S OUT2 P6 2/AN 2 P6 1/AN 1 P6 0/AN 0 P5 7 /INT 3 P4 7/S RDY1/CNTR 2 P4 5/T XD 1 P4 4/R XD 1 P5 3/S RDY2 P5 2/S CLK2 *Connect oscillation circuit. indicates flash memory pin. P4 6/S CLK1 P5 6/PWM P4 3/INT 2 P5 0/S IN2 RxD TxD SCLK BUSY Package code: PLQP0064KB-A (64P6Q-A) / PLQP0064GA-A (64P6U-A) Fig 77. Connection for standard serial I/O mode 1 (M38039FFLHP/KP) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 83 of 117 3803 Group (Spec.L) P1 0/INT 41 P0 0/AN 8 P1 1/INT 01 P0 3/AN 11 P0 4/AN 12 P0 5/AN 13 P0 6/AN 14 P0 2/AN 10 P0 1/AN 9 P0 7/AN 15 P1 2 P1 3 P1 4 P1 5 P1 6 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P37/SRDY3 P36/SCLK3 P35/TXD3 P34/RXD3 P33 P32 P31/DA2 P30/DA1 VCC VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 33 P1 7 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) VSS XOUT XIN P40/INT40/XCOUT P41/INT00/XCIN RESET CNVSS P42/INT1 RESET CNVSS VSS M38039FFLHP/KP * P5 5/CNTR 1 P5 4/CNTR 0 P5 1/S OUT2 P6 2/AN 2 P6 1/AN 1 P6 0/AN 0 P5 7 /INT 3 P4 7/S RDY1/CNTR 2 P4 5/T XD 1 P4 4/R XD 1 P5 3/S RDY2 P5 2/S CLK2 *Connect oscillation circuit. indicates flash memory pin. P4 6/S CLK1 P5 6/PWM P4 3/INT 2 P5 0/S IN2 RxD TxD “L” input BUSY Package code: PLQP0064KB-A (64P6Q-A) / PLQP0064GA-A (64P6U-A) Fig 78. Connection for standard serial I/O mode 2 (M38039FFLHP/KP) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 84 of 117 3803 Group (Spec.L) VCC BUSY SCLK TXD RXD CNVSS RESET VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN * XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) Package code: PRDP0064BA-A (64P4B) M38039FFLSP *Connect oscillation circuit. indicates flash memory pin. Fig 79. Connection for standard serial I/O mode 1 (M38039FFLSP) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 85 of 117 3803 Group (Spec.L) VCC BUSY “L” input TXD RXD CNVSS RESET VSS VCC VREF AVSS P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR1 P54/CNTR0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1/CNTR2 P46/SCLK1 P45/TXD1 P44/RXD1 P43/INT2 P42/INT1 CNVSS RESET P41/INT00/XCIN P40/INT40/XCOUT XIN * XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P30/DA1 P31/DA2 P32 P33 P34/RXD3 P35/TXD3 P36/SCLK3 P37/SRDY3 P00/AN8 P01/AN9 P02/AN10 P03/AN11 P04/AN12 P05/AN13 P06/AN14 P07/AN15 P10/INT41 P11/INT01 P12 P13 P14 P15 P16 P17 P20(LED0) P21(LED1) P22(LED2) P23(LED3) P24(LED4) P25(LED5) P26(LED6) P27(LED7) Package code: PRDP0064BA-A (64P4B) M38039FFLSP *Connect oscillation circuit. indicates flash memory pin. Fig 80. Connection for standard serial I/O mode 2 (M38039FFLSP) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 86 of 117 3803 Group (Spec.L) PIN CONFIGURATION (TOP VIEW) A B C D E F G H 8 50 P36/SCLK3 46 P02/AN10 44 P04/AN12 41 P07/AN15 40 P10/INT41 32 P20(LED0) 31 P21(LED1) 30 P22(LED2) 8 7 51 P35/TXD3 47 P01/AN9 45 P03/AN11 42 P06/AN14 39 P11/INT01 27 P25(LED5) 29 P23(LED3) 28 P24(LED4) 7 6 53 P33 52 P34/RXD3 48 P00/AN8 43 P05/AN13 38 P12 37 P13 26 P26(LED6) 25 P27(LED7) 6 VSS 5 56 P30/DA1 55 P31/DA2 54 P32 49 P37/SRDY3 33 P17 36 P14 35 P15 34 P16 5 * 4 BUSY 1 P62/AN2 64 P63/AN3 58 VREF 59 AVSS 57 VCC 24 VSS 22 XIN 23 XOUT 4 VCC 3 TXD 60 P67/AN7 61 P66/AN6 4 P57/INT3 7 P54/CNTR0 12 P47/SRDY1/CNTR2 14 P45/TXD1 21 P40/INT40/XCOUT 20 P41/INT00/XCIN 3 2 SCLK 62 P65/AN5 63 P64/AN4 5 P56/PWM 8 P53/SRDY2 10 P51/SOUT2 13 P46/SCLK1 17 P42/INT1 19 RESET RESET 2 1 RXD 2 P61/AN1 3 P60/AN0 6 P55/CNTR1 9 P52/SCLK2 11 P50/SIN2 15 P44/RXD1 16 P43/INT2 18 CNVSS CNVSS 1 A B C D E F G H * Connect oscillation circuit. Package code: PTLG0064JA-A (64F0G) indicates flash memory pin. Fig 81. Connection for standard serial I/O mode 1 (M38039FFLWG) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 87 of 117 3803 Group (Spec.L) PIN CONFIGURATION (TOP VIEW) A B C D E F G H 8 50 P36/SCLK3 46 P02/AN10 44 P04/AN12 41 P07/AN15 40 P10/INT41 32 P20(LED0) 31 P21(LED1) 30 P22(LED2) 8 7 51 P35/TXD3 47 P01/AN9 45 P03/AN11 42 P06/AN14 39 P11/INT01 27 P25(LED5) 29 P23(LED3) 28 P24(LED4) 7 6 53 P33 52 P34/RXD3 48 P00/AN8 43 P05/AN13 38 P12 37 P13 26 P26(LED6) 25 P27(LED7) 6 VSS 5 56 P30/DA1 55 P31/DA2 54 P32 49 P37/SRDY3 33 P17 36 P14 35 P15 34 P16 5 * 4 BUSY 1 P62/AN2 64 P63/AN3 58 VREF 59 AVSS 57 VCC 24 VSS 22 XIN 23 XOUT 4 VCC 3 TXD 60 P67/AN7 61 P66/AN6 4 P57/INT3 7 P54/CNTR0 12 P47/SRDY1/CNTR2 14 P45/TXD1 21 P40/INT40/XCOUT 20 P41/INT00/XCIN 3 2 “L”input 62 P65/AN5 63 P64/AN4 5 P56/PWM 8 P53/SRDY2 10 P51/SOUT2 13 P46/SCLK1 17 P42/INT1 19 RESET RESET 2 1 RXD 2 P61/AN1 3 P60/AN0 6 P55/CNTR1 9 P52/SCLK2 11 P50/SIN2 15 P44/RXD1 16 P43/INT2 18 CNVSS CNVSS 1 A B C D E F G H * Connect oscillation circuit. indicates flash memory pin. Package code: PTLG0064JA-A (64F0G) Fig 82. Connection for standard serial I/O mode 2 (M38039FFLWG) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 88 of 117 3803 Group (Spec.L) td(CNVSS-RESET) td(P45-RESET) Power source RESET CNVSS P45(TXD) P46(SCLK) P47(BUSY) P44(RXD) Symbol td(CNVSS-RESET) td(P45-RESET) Limits Min. 0 0 Typ. − Max. − Unit ms ms Notes: In the standard serial I/O mode 1, input “H” to the P46 pin. Be sure to set the CNVSS pin to “H” before rising RESET. Be sure to set the P45 pin to “H” before rising RESET. Fig 83. Operating waveform for standard serial I/O mode 1 td(CNVSS-RESET) td(P45-RESET) Power source RESET CNVSS P45(TXD) P46(SCLK) P47(BUSY) P44(RXD) Symbol td(CNVSS-RESET) td(P45-RESET) Limits Min. 0 0 Typ. − Max. − Unit ms ms Notes: In the standard serial I/O mode 2, input “H” to the P46 pin. Be sure to set the CNVSS pin to “H” before rising RESET. Be sure to set the P45 pin to “H” before rising RESET. Fig 84. Operating waveform for standard serial I/O mode 2 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 89 of 117 3803 Group (Spec.L) 3803 Group (Spec. L) T_VDD T_VPP T_RXD T_TXD T_SCLK T_PGM/OE/MD 4.7kΩ VCC N.C. 4.7kΩ P45 (TXD) P44 (RXD) P46 (SCLK) CNVSS T_BUSY RESET circuit T_RESET GND P47 (BUSY) RESET VSS AVSS XIN XOUT Set the same termination as the single-chip mode. Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig 85. When using programmer (in standard serial I/O mode 1) of Suisei Electronics System Co., LTD, connection example Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 90 of 117 3803 Group (Spec.L) 3803 Group (Spec. L) VCC VCC CNVSS 4.7 kΩ 4.7 kΩ 4.7 kΩ P45 (TXD) P44 (RXD) P46 (SCLK) P47 (BUSY) 14 12 10 8 6 4 2 13 11 9 7 5 3 1 RESET circuit *1 RESET VSS AVSS XIN XOUT Set the same termination as the single-chip mode. *1 : Open-collector buffer Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig 86. When using E8 programmer (in standard serial I/O mode 1), connection example Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 91 of 117 3803 Group (Spec.L) NOTES NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Set D flag to “1” ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Reset Fig 89. Execution of decimal calculations Initializing of flags Main program 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. 5. Ports The contents of the port direction registers cannot be read. The following cannot be used: • The data transfer instruction (LDA, etc.) • The operation instruction when the index X mode flag (T) is “1” • The instruction with the addressing mode which uses the value of a direction register as an index • The bit-test instruction (BBC or BBS, etc.) to a direction register • The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. 6. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles mentioned in the 740 Family Software Manual. The frequency of the internal clock φ is the twice the XIN cycle in high-speed mode, 8 times the XIN cycle in middle-speed mode, and the twice the XCIN in low-speed mode. Fig 87. Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. (S) (S) + 1 Stored PS Fig 88. Stack memory contents after PHP instruction execution 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 92 of 117 3803 Group (Spec.L) Countermeasures against noise (1) Shortest wiring length 1. Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET p in and the V SS pin with the shortest possible wiring (within 20mm). The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise XIN XOUT VSS XIN XOUT VSS N.G. Fig 91. Wiring for clock I/O pins O.K. Noise Reset circuit VSS RESET VSS N.G. Reset circuit VSS RESET VSS (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. O.K. Fig 90. Wiring for the RESET pin 2. Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS pat-terns. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. VCC VCC VSS VSS N.G. O.K. Fig 92. Bypass capacitor across the VSS line and the VCC line Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 93 of 117 3803 Group (Spec.L) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe-cially when range of votage and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. 1. Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. 2. Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (4) Analog input The analog input pin is connected to the capacitor of a voltage com-parator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory size When memory size differ in one group, actual values such as an electrical characteristics, A/D conversion accuracy, and the amount of -proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evalua-tion for each product of every after confirming product specification. (6) Wiring to CNVSS pin The CNVSS pin determines the flash memory mode. Connect the CNVSS pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 kΩ. resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S p in of the microcomputer. Note. When the boot mode or the standard serial I/O mode is used, a switch of the input level to the CNVSS pin is required. (Note) The shortest 1. Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M Large current GND XIN XOUT VSS CNVSS Approx. 5kΩ VSS (Note) The shortest Note: Shows the microcomputer’s pin. 2. Installing oscillator away from signal lines where potential levels change frequently Do not cross CNTR XIN XOUT VSS Fig 94. Wiring for the CNVSS N.G. Fig 93. Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 94 of 117 3803 Group (Spec.L) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state In standby state*1 for low-power dissipation, do not make input levels of an I/O port “undefined”. Even when an I/O port of Nchannel open-drain is set as output mode, if output data is “1”, the aforementioned notes are necessary. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: • External circuit • Variation of output levels during the ordinary operation When using built-in pull-up resistor, note on varied current values: • When setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external Exclusive input ports are always in a high-impedance state. An output transistor becomes an OFF state when an I/O port is set as input mode by the direction register, so that the port enter a highimpedance state. At this time, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels are “undefined”. This may cause power source current. Even when an I/O port of N-channel open-drain is set as output mode by the direction register, if the contents of the port latch is “1”, the same phenomenon as that of an input port will occur. *1 Termination of Unused Pins 1. Terminate unused pins (1) Output ports : Open (2) I/O ports : • Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 kΩ to 10 kΩ. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/O ports for the output mode and open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (3) The AVSS pin when not using the A/D converter : • When not using the A/D converter, handle a power source pin for the A/D converter, AVSS pin as follows: AVSS: Connect to the VSS pin. 2. Termination remarks (1) I/O ports : Do not open in the input mode. • The power source current may increase depending on the firststage circuit. • An effect due to noise may be easily produced as compared with proper termination (2) in 1 and shown on the above. (2) I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). (3) I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. • At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Standby state : stop mode by executing STP instruction wait mode by executing WIT instruction 2. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*1, the value of the unspecified bit may be changed. I/O ports are set to input or output mode in bit units. Reading from a port register or writing to it involves the following operations. • Port in input mode Read: Read the pin level. Write: Write to the port latch. • Port in output mode Read: Read the port latch or read the output from the peripheral function (specifications differ depending on the port). Write: Write to the port latch. (The port latch value is output from the pin.) Since bit managing instructions *1 a re read-modify-write instructions,*2 using such an instruction on a port register causes a read and write to be performed simultaneously on the bits other than the one specified by the instruction. When an unspecified bit is in input mode, its pin level is read and that value is written to the port latch. If the previous value of the port latch differs from the pin level, the port latch value is changed. If an unspecified bit is in output mode, the port latch is generally read. However, for some ports the peripheral function output is read, and the value is written to the port latch. In this case, if the previous value of the port latch differs from the peripheral function output, the port latch value is changed. *1 Bit managing instructions: SEB and CLB instructions *2 Read-modify-write instructions: Instructions that read memory in byte units, modify the value, and then write the result to the same location in memory in byte units Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 95 of 117 3803 Group (Spec.L) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. • Interrupt edge selection register (address 003A16) • Timer XY mode register (address 002316) • Timer Z mode register (address 002A16) Set the above listed registers or bits as the following sequence. 2. Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0”, execute one or more instructions before executing the BBC or BBS instruction. Clear the interrupt request bit to “0” (no interrupt issued) NOP (one or more instructions) Set the corresponding interrupt enable bit to “0” (disabled). Execute the BBC or BBS instruction Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to “1”. Fig 96. Sequence of check of interrupt request bit If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. NOP (one or more instructions) Set the corresponding interrupt request bit to “0” (no interrupt request issued). Set the corresponding interrupt enable bit to “1” (enabled). Fig 95. Sequence of changing relevant register When setting the followings, the interrupt request bit may be set to “1”. • When setting external interrupt active edge Concerned register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) Timer Z mode register (address 002A16) • When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated. Concerned register: Interrupt source selection register (address 003916) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 96 of 117 3803 Group (Spec.L) Notes on 8-bit Timer (timer 1, 2, X, Y) • If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). • When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. • Set the double-function port of the CNTR0/CNTR1 pin and port P54/P55 to output in the pulse output mode. • Set the double-function port of CNTR0/CNTR1 pin and port P54/P55 to input in the event counter mode and the pulse width measurement mode. 5. Programmable one-shot generating mode • Set the double-function port of CNTR2 pin and port P47 to output, and of INT1 pin and port P42 to input in this mode. • This mode cannot be used in low-speed mode. • If the value of the CNTR2 active edge switch bit is changed during one-shot generating enabled or generating one-shot pulse, then the output level from CNTR2 pin changes. 6. All modes • Timer Z write control Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode register (address 002A16), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the address of timer Z and the timer is updated at next underflow. After reset release, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer Z. In the case of writing data only to the latch, if writing data to the latch and an underflow are performed almost at the same time, the timer value may become undefined. • Timer Z read control A read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. In the other modes, a read-out of timer value is possible regardless of count operating or stopped. However, a read-out of timer latch value is impossible. • Switch of interrupt active edge of CNTR2 and INT1 Each interrupt active edge depends on setting of the CNTR 2 active edge switch bit and the INT1 active edge selection bit. • Switch of count source When switching the count source by the timer Z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. Therefore, select the timer count source before setting the value to the prescaler and the timer. Notes on 16-bit Timer (timer Z) 1. Pulse output mode • Set the double-function port of the CNTR2 pin and port P47 to output. 2. Pulse period measurement mode • Set the double-function port of the CNTR2 pin and port P47 to input. • A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). • Since the timer latch in this mode is specialized for the readout of measured values, do not perform any write operation during measurement. • “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. 3. Pulse width measurement mode • Set the double-function port of the CNTR2 pin and port P47 to input. • A read-out of timer value is impossible in this mode. The timer can be written to only during timer stop (no measurement of pulse period). • Since the timer latch in this mode is specialized for the readout of measured values, do not perform any write operation during measurement. • “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. Consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. 4. Programmable waveform generating mode • Set the double-function port of the CNTR2 pin and port P47 to output. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 97 of 117 3803 Group (Spec.L) Notes on Serial Interface 1. Notes when selecting clock synchronous serial I/O (1) Stop of transmission operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and transmit disabled). Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/Oi enable bit is set to “1” at this time, the data during internally shifting is output to the TxDi pin and an operation failure occurs. (2) Stop of receive operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/Oi enable bit to “0” (serial I/Oi disabled). (3) Stop of transmit/receive operation As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/Oi enable bit to “0” (serial I/Oi disabled) (refer to (1) in 1.). 2. Notes when selecting clock asynchronous serial I/O (1) Stop of transmission operation Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/Oi enable bit (i = 1, 3) to “0”. This is the same as (1) in 1. (2) Stop of receive operation Clear the receive enable bit to “0” (receive disabled). (3) Stop of transmit/receive operation Only transmission operation is stopped. Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop by clearing the serial I/Oi enable bit (i = 1, 3) to “0”. This is the same as (1) in 1. Only receive operation is stopped. Clear the receive enable bit to “0” (receive disabled). 3. SRDYi (i = 1, 3) output of reception side When signals are output from the SRDYi pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDYi output enable bit, and the transmit enable bit to “1” (transmit enabled). 4. Setting serial I/Oi (i = 1, 3) control register again Set the serial I/Oi control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/Oi control register Can be set with the LDM instruction at the same time Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Fig 97. Sequence of setting serial I/Oi (i = 1, 3) control register again 5. Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit buffer register at “H” of the SCLKi input level. 7. Transmit interrupt request when transmit enable bit is set When using the transmit interrupt, take the following sequence. (1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “0” (disabled). (2) Set the tranasmit enable bit to “1”. (3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to “0” after 1 or more instruction has executed. (4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “1” (enabled). When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift register shift completion flag are also set to “1”. Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 8. Writing to baud rate generator i (BRGi) (i = 1, 3) Write data to the baud rate generator i (BRGi) (i = 1, 3) while the transmission/reception operation is stopped. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 98 of 117 3803 Group (Spec.L) Notes on PWM The PWM starts from “H” level after the PWM enable bit is set to enable and “L” level is temporarily output from the PWM pin. The length of this “L” level output is as follows: n+1 2 × f(XIN) n+1 f(XIN) (s) (s) (Count source selection bit = “0”, where n is the value set in the prescaler) (Count source selection bit = “1”, where n is the value set in the prescaler) Notes on Watchdog Timer • Make sure that the watchdog timer H does not underflow while waiting Stop release, because the watchdog timer keeps counting during that term. • When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program. Notes on A/D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the user side. An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion precision to be worse. 2. A/D converter power source pin The AVSS pin is A/D converter power source pins. Regardless of using the A/D conversion function or not, connect it as following : • AVSS : Connect to the VSS line If the AVSS pin is opened, the microcomputer may have a failure because of noise or others. 3. Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion. • f(XIN) is 500 kHz or more • Do not execute the STP instruction 4. Difference between at 8-bit reading in 10-bit A/D mode and at 8-bit A/D mode At 8-bit reading in the 10-bit A/D mode, “–1/2 LSB” correction is not performed to the A/D conversion result. In the 8-bit A/D mode, the A/D conversion characteristics is the same as 3802 group’s characteristics because “–1/2 LSB” correction is performed. Notes on D/A Converter 1. VCC when using D/A converter The D/A converter accuracy when VCC is 4.0 V or less differs from that of when VCC is 4.0 V or more. When using the D/A converter, we recommend using a VCC of 4.0 V or more. 2. DAi conversion register when not using D/A converter When a D/A converter is not used, set all values of the DAi conversion registers (i = 1, 2) to “0016”. The initial value after reset is “0016”. Notes on RESET Pin Connecting capacitor In case where the RESET s ignal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • Make the length of the wiring which is connected to a capacitor as short as possible. • Be sure to verify the operation of application products on the user side. If the several nanosecond or several ten nanosecond impulse noise enters the RESET p in, it may cause a microcomputer failure. Notes on Low-speed Operation Mode 1. Using sub-clock To use a sub-clock, fix bit 3 of the CPU mode register to “1” or control the Rd (refer to Figure 98) resistance value to a certain level to stabilize an oscillation. For resistance value of Rd, consult the oscillator manufacturer. XCIN Rf XCOUT Rd CCIN CCOUT Fig 98. Ceramic resonator circuit When bit 3 of the CPU mode register is set to “0”, the sub-clock oscillation may stop. 2. Switch between middle/high-speed mode and lowspeed mode If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode between middle/high-speed and lowspeed, set the frequency on condition that f(XIN) > 3 × f(XCIN). Quartz-Crystal Oscillator When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to select a specific oscillator with the specification demanded. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 99 of 117 3803 Group (Spec.L) Notes on Restarting Oscillation • Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = “0116 ”, Prescaler 12 = “FF 16 ”) are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 001016). However, by setting this bit to “1”, the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. Oscillation will restart when an external interrupt is received. However, internal clock φ is supplied to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. Notes on Using Stop Mode • Register setting Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP instruction released bit is “0”) • Clock restoration After restoration from the stop mode to the normal mode by an interrupt request, the contents of the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both main clock and sub clock were oscillating before execution of the STP instruction, the oscillation of both clocks is resumed at restoration. In the above case, when the main clock side is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode. At this time, note that the oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side. Notes on Wait Mode • Clock restoration If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillations starts, and XIN is set as the system clock. In the above case, the RESET pin should be held at “L” until the oscillation is stabilized. Notes on CPU rewrite mode of flash memory version 1. Operation speed During CPU rewrite mode, set the system clock φ 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B16). 2. Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode. 3. Interrupts inhibited against use The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory. 4. Watchdog timer In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. 5. Reset Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area. Notes on flash memory version The CNVSS pin determines the flash memory mode. Connect the CNVSS pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 kΩ. resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S p in of the microcomputer. Note. When the boot mode or the standard serial I/O mode is used, a switch of the input level to the CNVSS pin is required. (Note) The shortest CNVSS Approx. 5kΩ VSS (Note) The shortest Note: Shows the microcomputer’s pin. Fig 99. Wiring for the CNVSS Notes on electric characteristic differences between mask ROM and flash nemory version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes, built-in ROM, and layout pattern etc. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version, please conduct evaluations equivalent to the system evaluations conducted for the flash memory version. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Confirmation Form* 2. Mark Specification Form* 3. Data to be written to ROM, in EPROM form (three identical copies) * For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom). Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 100 of 117 3803 Group (Spec.L) Notes on Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin), and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recommended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 101 of 117 3803 Group (Spec.L) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 16 Absolute maximum ratings Symbol VCC VI Parameter Power source voltages Input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, VREF Input voltage P32, P33 Input voltage RESET, XIN Input voltage Output voltage CNVSS P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67, XOUT P32, P33 Ta=25 °C Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. Ratings −0.3 to 6.5 −0.3 to VCC + 0.3 Unit V V VI VI VI VO −0.3 to 5.8 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 −0.3 to VCC + 0.3 V V V V VO Pd Topr Tstg Output voltage Power dissipation −0.3 to 5.8 Operating temperature Storage temperature 1000(1) −20 to 85 −65 to 125 V mW °C °C NOTE: 1. This value is 300 mW except SP package. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 102 of 117 3803 Group (Spec.L) Mask ROM Version Recommended operating conditions Table 17 Recommended operating conditions (1) (Mask ROM version) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Power source voltage(1) Conditions When start oscillating(2) f(XIN) ≤ 2.1 MHz High-speed mode f(φ) = f(XIN)/2 f(XIN) ≤ 4.2 MHz f(XIN) ≤ 8.4 MHz f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz Middle-speed mode f(XIN) ≤ 6.3 MHz f(φ) = f(XIN)/8 f(XIN) ≤ 8.4 MHz f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz 1.8 ≤ VCC < 2.7 V 2.7 ≤ VCC ≤ 5.5 V Limits Min. 2.2 2.0 2.2 2.7 4.0 4.5 1.8 2.2 2.7 4.5 0.85 VCC 0.8 VCC Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC VCC Unit V V Symbol VCC V VSS VIH VIH VIH Power source voltage “H” input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 “H” input voltage P32, P33 “H” input voltage RESET, XIN, XCIN, CNVSS “L” input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” input voltage RESET, CNVSS “L” input voltage XIN, XCIN Main clock input oscillation frequency(3) V V 1.8 ≤ VCC < 2.7 V 2.7 ≤ VCC ≤ 5.5 V 1.8 ≤ VCC < 2.7 V 2.7 ≤ VCC ≤ 5.5 V 1.8 ≤ VCC < 2.7 V 2.7 ≤ VCC ≤ 5.5 V 0.85 VCC 0.8 VCC 0.85 VCC 0.8 VCC 0 0 5.5 5.5 VCC VCC 0.16 VCC 0.2 VCC V V VIL V VIL VIL f(XIN) 1.8 ≤ VCC < 2.7 V 2.7 ≤ VCC ≤ 5.5 V 1.8 ≤ VCC ≤ 5.5 V High-speed mode f(φ) = f(XIN)/2 2.0 ≤ VCC < 2.2 V 2.2 ≤ VCC < 2.7 V 2.7 ≤ VCC < 4.0 V 4.0 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 1.8 ≤ VCC < 2.2 V 2.2 ≤ VCC < 2.7 V 2.7 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 0 0 0 0.16 VCC 0.2 VCC 0.16 VCC ( 20 × V CC – 36 ) × 1.05 ----------------------------------------------------------2 ( 24 × V CC – 40.8 ) × 1.05 ---------------------------------------------------------------3 ( 9 × V CC – 0.3 ) × 1.05 --------------------------------------------------------3 ( 24 × V CC – 60 ) × 1.05 ----------------------------------------------------------3 V V MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz 16.8 ( 15 × V CC – 9 ) × 1.05 ------------------------------------------------------3 ( 24 × V CC – 28.8 ) × 1.05 ---------------------------------------------------------------3 ( 15 × V C C + 39 ) × 1.1 -------------------------------------------------------7 16.8 Middle-speed mode f(φ) = f(XIN)/8 f(XCIN) Sub-clock input oscillation frequency(3, 4) 32.768 50 NOTES: 1. When using A/D converter, see A/D converter recommended operating conditions. 2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. 3. When the oscillation frequency has a duty cycle of 50%. 4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 103 of 117 3803 Group (Spec.L) Flash Memory Version Table 18 Recommended operating conditions (2) (Flash memory version) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Parameter Power source voltage(1) Conditions When start oscillating(2) f(XIN) ≤ 8.4 MHz High-speed mode f(φ) = f(XIN)/2 f(XIN) ≤ 12.5 MHz f(XIN) ≤ 16.8 MHz Middle-speed mode f(XIN) ≤ 12.5 MHz f(φ) = f(XIN)/8 f(XIN) ≤ 16.8 MHz Limits Min. 2.2 2.7 4.0 4.5 2.7 4.5 0.8 VCC Typ. 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 VCC Unit V V Symbol VCC V V V VSS VIH VIH VIH VIH VIL Power source voltage “H” input voltage P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 “H” input voltage P32, P33 “H” input voltage RESET, XIN, CNVSS “H” input voltage XCIN “L” input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” input voltage RESET, CNVSS “L” input voltage XIN “L” input voltage XCIN Main clock input oscillation frequency(3) 0.8 VCC 0.8 VCC 5.5 VCC V V 2 0 VCC 0.2 VCC V V VIL VIL VIL f(XIN) 0 0.2 VCC 0.16 VCC 0.4 V V V MHz MHz MHz MHz MHz kHz High-speed mode f(φ) = f(XIN)/2 2.7 ≤ VCC < 4.0 V 4.0 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V 2.7 ≤ VCC < 4.5 V 4.5 ≤ VCC ≤ 5.5 V ( 9 × V CC – 0.3 ) × 1.05 --------------------------------------------------------3 ( 24 × V CC – 60 ) × 1.05 ----------------------------------------------------------3 16.8 ( 15 × V C C + 39 ) × 1.1 -------------------------------------------------------7 16.8 Middle-speed mode f(φ) = f(XIN)/8 f(XCIN) Sub-clock input oscillation frequency(3, 4) 32.768 50 NOTES: 1. When using A/D converter, see A/D converter recommended operating conditions. 2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. 3. When the oscillation frequency has a duty cycle of 50%. 4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 104 of 117 3803 Group (Spec.L) Table 19 Recommended operating conditions (3) (Mask ROM version: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) (Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) Parameter “H” total peak output current(1) “H” total peak output current(1) “L” total peak output current(1) “L” total peak output current(1) “L” total peak output current(1) “H” total average output current(1) “H” total average output current(1) “L” total average output current(1) “L” total average output current(1) “L” total average output current(1) “H” peak output current(2) “L” peak output current(2) “L” peak output current(2) “H” average output current(3) “L” average output current(3) “L” average output current(3) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37 P20-P27 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P20-P27, P30, P31, P34-P37 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37 P20-P27 P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 P20-P27 P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 P00-P07, P10-P17, P30-P37, P40-P47, P50-P57, P60-P67 P20-P27 Min. Limits Typ. Max. −80 −80 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 80 80 80 −40 −40 40 40 40 −10 IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) 10 20 −5 5 10 NOTES: 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 105 of 117 3803 Group (Spec.L) Electrical characteristics Table 20 Electrical characteristics (1) (Mask ROM version: VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) (Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VOH Parameter “H” output voltage(1) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 “L” output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” output voltage P20-P27 Test conditions IOH = −10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 1.8 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V IOL = 20 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 1.8 to 5.5 V Min. VCC − 2.0 VCC − 1.0 2.0 1.0 2.0 0.4 0.4 0.5 0.5 VI = VCC (Pin floating, Pull-up transistor “off”) VI = VCC VI = VCC VI = VSS (Pin floating, Pull-up transistor “off”) VI = VSS VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped −80 −30 −4.0 −210 −70 −420 −140 Limits Typ. Max. Unit V VOL V VOL V VT+ − VT− VT+ − VT− VT+ − VT− IIH IIH IIH IIL IIL IIL IIL Hysteresis CNTR0, CNTR1, CNTR2, INT0-INT4 Hysteresis RxD1, SCLK1, SIN2, SCLK2, RxD3, SCLK3 Hysteresis RESET “H” input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “H” input current RESET, CNVSS “H” input current XIN “L” input current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67 “L” input current RESET, CNVSS “L” input current XIN “L” input current (at Pull-up) P00-P07, P10-P17, P20-P27, P30, P31, P34-P37, P40-P47, P50-P57, P60-P67 RAM hold voltage V V V 5.0 µA 5.0 4.0 −5.0 µA µA µA −5.0 µA µA µA VRAM 1.8 VCC V NOTE: 1. P35 is measured when the P35/TXD3 P-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. P45 is measured when the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 106 of 117 3803 Group (Spec.L) Mask ROM Version Table 21 Electrical characteristics (2) (Mask ROM version) (VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768 kHz (Stopped in middle-speed mode), Output transistors “off”, AD converter not operated) Symbol ICC Parameter Power source High-speed current mode Test conditions VCC = 5.0 V f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 °C Ta = 85 °C f(XIN) = 16.8 MHz, VCC = 5.0 V In Middle-, high-speed mode Min. Limits Typ. 8.0 6.5 5.0 2.5 2.0 1.9 1.0 0.6 4.0 3.0 2.5 1.8 1.5 1.2 1.0 55 40 15 8 6 3 0.1 500 Max. 15.0 12.0 9.0 5.0 3.6 3.8 2.0 1.2 7.0 6.0 5.0 3.3 3.0 2.4 2.0 200 70 40 15 15 6 1.0 10 Unit mA VCC = 3.0 V mA Middle-speed mode VCC = 5.0 V mA VCC = 3.0 V mA Low-speed mode VCC = 5.0 V VCC = 3.0 V VCC = 2.0 V µA µA µA µA µA In STP state (All oscillation stopped) Increment when A/D conversion is executed Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 107 of 117 3803 Group (Spec.L) Flash Memory Version Table 22 Electrical characteristics (3) (Flash memory version) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768 kHz (Stopped in middle-speed mode), Output transistors “off”, AD converter not operated) Symbol ICC Parameter Power source High-speed current mode Test conditions VCC = 5.0 V f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 8.4 MHz f(XIN) = 4.2 MHz f(XIN) = 2.1 MHz f(XIN) = 16.8 MHz f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 16.8 MHz (in WIT state) f(XIN) = 12.5 MHz f(XIN) = 8.4 MHz f(XIN) = 6.3 MHz f(XIN) = stopped In WIT state f(XIN) = stopped In WIT state Ta = 25 °C Ta = 85 °C f(XIN) = 16.8 MHz, VCC = 5.0 V In Middle-, high-speed mode Min. Limits Typ. 5.5 4.5 3.5 2.2 2.2 2.7 1.8 1.1 3.0 2.4 2.0 2.1 1.7 1.5 1.3 410 4.5 400 3.7 0.55 0.75 1000 Max. 8.3 6.8 5.3 3.3 3.3 4.1 2.7 1.7 4.5 3.6 3.0 3.2 2.6 2.3 2.0 630 6.8 600 5.6 3.0 Unit mA VCC = 3.0 V mA Middle-speed mode VCC = 5.0 V mA VCC = 3.0 V mA Low-speed mode VCC = 5.0 V VCC = 3.0 V µA µA µA µA In STP state (All oscillation stopped) Increment when A/D conversion is executed Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 108 of 117 3803 Group (Spec.L) Mask ROM Version A/D converter characteristics Table 23 A/D converter recommended operating conditions (Mask ROM version) (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VREF AVSS VIA f(XIN) Parameter Power source voltage (When A/D converter is used) Analog convert reference voltage Analog power source voltage Analog input voltage AN0-AN15 Main clock input oscillation frequency (When A/D converter is used) Conditions 8-bit A/D mode(1) 10-bit A/D mode(2) Limits Min. 2.0 2.2 2.0 0 2.0 ≤ VCC = VREF < 2.2 V 2.2 ≤ VCC = VREF < 2.7 V 2.7 ≤ VCC = VREF < 4.0 V 4.0 ≤ VCC = VREF < 4.5 V 4.5 ≤ VCC = VREF ≤ 5.5 V 0 0.5 0.5 0.5 0.5 0.5 VCC ( 20 × V CC – 36 ) × 1.05 ----------------------------------------------------------2 ( 24 × V CC – 40.8 ) × 1.05 ---------------------------------------------------------------3 ( 9 × V CC – 0.3 ) × 1.05 --------------------------------------------------------3 ( 24.6 × V C C – 62.7 ) × 1.05 --------------------------------------------------------------------3 Typ. 5.0 5.0 Max. 5.5 5.5 VCC Unit V V V V MHz 16.8 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. Table 24 A/D converter characteristics (Mask ROM version) (VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol − − Parameter Resolution Absolute accuracy (excluding quantization error) Test conditions 8-bit A/D mode(1) 10-bit A/D mode(2) 8-bit A/D mode(1) 10-bit A/D mode(2) 2.0 ≤ VREF < 2.2 V 2.2 ≤ VREF ≤ 5.5 V 2.2 ≤ VREF < 2.7 V 2.7 ≤ VREF ≤ 5.5 V Min. Limits Typ. Max. 8 10 ±3 ±2 ±5 ±4 50 61 Unit bit LSB LSB 2tc(XIN) kΩ µA µA µA tCONV RLADDER IVREF II(AD) Conversion time 8-bit A/D mode(1) mode(2) 12 50 35 150 10-bit A/D Ladder resistor Reference power at A/D converter operated VREF = 5.0 V source input current at A/D converter stopped VREF = 5.0 V A/D port input current 100 200 5.0 5.0 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. D/A converter characteristics Table 25 D/A converter characteristics (Mask ROM version) (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol − − Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current(1) Min. Limits Typ. 4.0 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF < 4.0 V 2 3.5 tsu RO IVREF Max. 8 1.0 2.5 3 5 3.2 Unit bit % µs kΩ mA NOTE: 1. Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 109 of 117 3803 Group (Spec.L) A/D converter characteristics Table 26 A/D converter recommended operating conditions (Flash memory version) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC VREF AVSS VIA f(XIN) Parameter Power source voltage (When A/D converter is used) Analog convert reference voltage Analog power source voltage Analog input voltage AN0-AN15 Main clock input oscillation frequency (When A/D converter is used) Conditions 8-bit A/D mode(1) 10-bit A/D mode(2) Limits Min. 2.7 2.7 2.0 0 2.7 ≤ VCC = VREF < 4.0 V 4.0 ≤ VCC = VREF < 4.5 V 4.5 ≤ VCC = VREF ≤ 5.5 V 0 0.5 0.5 0.5 VCC ( 9 × V CC – 0.3 ) × 1.05 --------------------------------------------------------3 ( 24.6 × V CC – 62.7 ) × 1.05 --------------------------------------------------------------------3 Typ. 5.0 5.0 Max. 5.5 5.5 VCC Unit V V V V MHz 16.8 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. Table 27 A/D converter characteristics (Flash memory version) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol − − Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Test conditions 8-bit A/D mode(1) 10-bit A/D mode(2) 8-bit A/D mode(1) 10-bit A/D 8-bit A/D mode(2) mode(1) 2.7 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF ≤ 5.5 V Min. Limits Typ. Max. 8 10 ±2 ±4 50 61 Unit bit LSB LSB 2tc(XIN) kΩ µA µA µA tCONV RLADDER IVREF II(AD) 10-bit A/D mode(2) Ladder resistor Reference power at A/D converter operated VREF = 5.0 V source input current at A/D converter stopped VREF = 5.0 V A/D port input current 12 50 35 150 100 200 5.0 5.0 NOTES: 1. 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”. 2. 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”. D/A converter characteristics Table 28 D/A converter characteristics (Flash memory version) (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol − − Parameter Resolution Absolute accuracy Setting time Output resistor Reference power source input current(1) Min. Limits Typ. 4.0 ≤ VREF ≤ 5.5 V 2.7 ≤ VREF < 4.0 V 2 3.5 tsu RO IVREF Max. 8 1.0 2.5 3 5 3.2 Unit bit % µs kΩ mA NOTE: 1. Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”. Power source circuit timing characteristics (Flash memory version) Table 29 Power source circuit timing characteristics (Flash memory version) (VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol td(P−R) Parameter Internal power source stable time at power-on Test conditions 2.7 ≤ VCC < 5.5 V Min. Limits Typ. Max. 2 Unit ms Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 110 of 117 3803 Group (Spec.L) Timing requirements and switching characteristics Table 30 Timing requirements (1) (Mask ROM version: VCC = 2.0 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) (Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) Parameter Reset input “L” pulse width Main clock XIN input cycle time 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V Limits Min. 16 59.5 10000/(86 VCC − 219) 26 × 103/(82 VCC − 3) 10000/(84 VCC − 143) 10000/(105 VCC − 189) 25 4000/(86 VCC − 219) 10000/(82 VCC − 3) 4000/(84 VCC − 143) 4000/(105 VCC − 189) 25 4000/(86 VCC − 219) 10000/(82 VCC − 3) 4000/(84 VCC − 143) 4000/(105 VCC − 189) 20 5 5 120 160 250 500 1000 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 48 64 115 230 460 Typ. Max. Unit XIN cycle ns tWH(XIN) Main clock XIN input “H” pulse width ns tWL(XIN) Main clock XIN input “L” pulse width ns tC(XCIN) tWH(XCIN) tWL(XCIN) tC(CNTR) Sub-clock XCIN input cycle time Sub-clock XCIN input “H” pulse width Sub-clock XCIN input “L” pulse width CNTR0−CNTR2 input cycle time µs µs µs tWH(CNTR) CNTR0−CNTR2 input “H” pulse width tWL(CNTR) CNTR0−CNTR2 input “L” pulse width tWH(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “H” pulse width tWL(INT) INT00, INT01, INT1, INT2, INT3, INT40, INT41 input “L” pulse width 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V ns ns ns ns ns Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 111 of 117 3803 Group (Spec.L) Table 31 Timing requirements (2) (Mask ROM version: VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) (Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) Symbol tC(SCLK1) tC(SCLK3) Serial I/O1, serial I/O3 clock input cycle time(1) Parameter 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V Min. 250 320 500 1000 2000 120 150 240 480 950 120 150 240 480 950 70 90 100 200 400 32 40 50 100 200 500 650 1000 2000 4000 200 260 400 950 2000 200 260 400 950 2000 100 130 200 400 800 100 130 150 300 600 Limits Typ. Max. Unit ns tWH(SCLK1) tWH(SCLK3) Serial I/O1, serial I/O3 clock input “H” pulse width(1) ns tWL(SCLK1) tWL(SCLK3) Serial I/O1, serial I/O3 clock input “L” pulse width(1) ns tsu(RxD1-SCLK1) tsu(RxD3-SCLK3) Serial I/O1, serial I/O3 clock input setup time ns th(SCLK1-RxD1) th(SCLK3-RxD3) Serial I/O1, serial I/O3 clock input hold time ns tC(SCLK2) Serial I/O2 clock input cycle time ns tWH(SCLK2) Serial I/O2 clock input “H” pulse width ns tWL(SCLK2) Serial I/O2 clock input “L” pulse width ns tsu(SIN2-SCLK2) Serial I/O2 clock input setup time ns th(SCLK2-SIN2) Serial I/O2 clock input hold time ns NOTE: 1. When bit 6 of address 001A16 and bit 6 of address 003216 are “1” (clock synchronous). Divide this value by four when bit 6 of address 001A16 and bit 6 of address 003216 are “0” (UART). Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 112 of 117 3803 Group (Spec.L) Table 32 Switching characteristics (1) (Mask ROM version: VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) (Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWH(SCLK3) Parameter Serial I/O1, serial I/O3 clock output “H” pulse width 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V Test conditions Limits Min. tC(SCLK1)/2-30, tC(SCLK3)/2-30 tC(SCLK1)/2-35, tC(SCLK3)/2-35 tC(SCLK1)/2-40, tC(SCLK3)/2-40 tC(SCLK1)/2-45, tC(SCLK3)/2-45 tC(SCLK1)/2-50, tC(SCLK3)/2-50 tC(SCLK1)/2-30, tC(SCLK3)/2-30 tC(SCLK1)/2-35, tC(SCLK3)/2-35 tC(SCLK1)/2-40, tC(SCLK3)/2-40 tC(SCLK1)/2-45, tC(SCLK3)/2-45 tC(SCLK1)/2-50, tC(SCLK3)/2-50 Typ. Max. Unit ns tWL(SCLK1) tWL(SCLK3) Serial I/O1, serial I/O3 clock output “L” pulse width ns td(SCLK1-TxD1) td(SCLK3-TxD3) Serial I/O1, serial I/O3 output delay time(1) 140 200 350 400 420 −30 −30 −30 −30 −30 ns tV(SCLK1-TxD1) tV(SCLK3-TxD3) Serial I/O1, serial I/O3 output valid time(1) ns tr(SCLK1) tr(SCLK3) Serial I/O1, serial I/O3 rise time of clock output tf(SCLK1) tf(SCLK3) Serial I/O1, serial I/O3 fall time of clock output Fig.100 30 35 40 45 50 30 35 40 45 50 tC(SCLK2)/2-160 tC(SCLK2)/2-200 tC(SCLK2)/2-240 tC(SCLK2)/2-260 tC(SCLK2)/2-280 tC(SCLK2)/2-160 tC(SCLK2)/2-200 tC(SCLK2)/2-240 tC(SCLK2)/2-260 tC(SCLK2)/2-280 200 250 300 350 400 0 0 0 0 0 ns ns tWH(SCLK2) Serial I/O2 clock output “H” pulse width ns tWL(SCLK2) Serial I/O2 clock output “L” pulse width ns td(SCLK2-SOUT2) Serial I/O2 output delay time ns tV(SCLK2-SOUT2) Serial I/O2 output valid time ns NOTE: 1. When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 113 of 117 3803 Group (Spec.L) Table 33 Switching characteristics (2) (Mask ROM version: VCC = 2.0 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) (Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85 °C, unless otherwise noted) Symbol tf(SCLK2) Parameter Serial I/O2 fall time of clock output 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V 4.5 ≤ VCC ≤ 5.5 V 4.0 ≤ VCC < 4.5 V 2.7 ≤ VCC < 4.0 V 2.2 ≤ VCC < 2.7 V 2.0 ≤ VCC < 2.2 V Test conditions Limits Min. Typ. Max. 30 35 40 45 50 30 35 40 45 50 30 35 40 45 50 Unit ns tr(CMOS) CMOS rise time of output(1) Fig.100 tf(CMOS) CMOS fall time of output(1) 10 12 15 17 20 10 12 15 17 20 ns ns NOTE: 1. When the P35/TXD3 P4-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”. 1kΩ Measurement output pin 100 pF Measurement output pin 100 pF CMOS output N-channel open-drain output Fig 100. Circuit for measuring output switching characteristics Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 114 of 117 3803 Group (Spec.L) Single-chip mode timing diagram tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 CNTR2 0.8VCC INT1, INT2, INT3 INT00, INT40 INT01, INT41 tWH(INT) 0.8VCC 0.2VCC tWL(INT) tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(XCIN) tWH(XCIN) tWL(XCIN) 0.2VCC XCIN 0.8VCC tC(SCLK1), tC(SCLK2), tC(SCLK3) SCLK1 SCLK2 SCLK3 RXD1 RXD3 SIN2 tf tWL(SCLK1), tWL(SCLK2), tWL(SCLK3) tr tWH(SCLK1), tWH(SCLK2), tWH(SCLK3) 0.2VCC tsu(RXD1-SCLK1), tsu(SIN2-SCLK2), tsu(RXD3-SCLK3) 0.8VCC 0.2VCC tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3) 0.8VCC th(SCLK1-RXD1), th(SCLK2-SIN2), th(SCLK3-RXD3) td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3) TXD1 TXD3 SOUT2 Fig 101. Timing diagram (in single-chip mode) Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 115 of 117 3803 Group (Spec.L) PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code P-SDIP64-17x56.4-1.78 RENESAS Code PRDP0064BA-A Previous Code 64P4B MASS[Typ.] 7.9g 64 33 *1 e1 E *2 D A A2 c 1 32 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Symbol Dimension in Millimeters L SEATING PLANE e *3 b3 bp *3 b2 e1 D E A A1 A2 bp b2 b3 c e L Min 18.75 56.2 16.85 0.38 0.4 0.65 0.9 0.2 0° 1.528 2.8 Nom 19.05 56.4 17.0 Max 19.35 56.6 17.15 5.08 A1 3.8 0.5 0.6 0.75 1.05 1.0 1.3 0.25 0.32 15° 1.778 2.028 JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 49 32 HE E Reference Symbol *2 c1 Dimension in Millimeters c 64 1 Index mark ZD 16 ZE 17 Terminal cross section F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 e *3 A1 y bp L L1 Detail F x Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 A2 Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 116 of 117 A c 3803 Group (Spec.L) JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 48 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 49 32 bp b1 c1 HE E c Reference Symbol *2 Dimension in Millimeters Terminal cross section 64 17 1 ZD Index mark 16 F L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 bp x Detail F Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0° 8° 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 ZE A A2 JEITA Package Code P-TFLGA64-6x6-0.65 RENESAS Code PTLG0064JA-A Previous Code 64F0G MASS[Typ.] 0.07g A1 b1 S b AB S AB wSB D wSA A e H G F E c D C B A E e x4 v Index mark (Laser mark) yS 1 2 3 4 5 6 7 8 Reference Dimension in Millimeters Symbol Index mark D E v w A e b b1 x y Nom Max 6.0 6.0 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08 0.10 Min Rev.1.01 Jan 25, 2008 REJ03B0212-0101 Page 117 of 117 REVISION HISTORY Rev. 1.00 1.01 Date Page Apr.2, 2007 Jan.25, 2008 110 First edition issued 3803 Group (Spec.L) Data Sheet Description Summary The title “Power source circuit timing characteristics (Flash memory version)” is added and the value “2 ms” is revised from minimum value to maximum value. (1/1) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2

大小:2052.34KB

所需财富值1

更多
0

已有0人评价

浏览:17959

贡献者:foooy

贡献时间:2013年04月03日

文档关键词

相关推荐

热门文档

您最近浏览过的文档