MK2049-36SITR

DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications frequencies. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. • • • • This part also has a jitter-attenuated Buffer capability. In this mode, the MK2049-36 is ideal for filtering jitter from clocks with high jitter. • Accepts multiple inputs: 8 kHz backplane clock or 10 to Packaged in 20 pin SOIC Available in Pb (lead) free package 3.3 V + 5% operation Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E 50 MHz • Locks to 8 kHz + 100 ppm (External mode) • Buffer Mode allows jitter attenuation of 10 - 50 MHz input IDT can customize these devices for many other different frequencies. Contact your IDT representative for more details. and x1/x0.5 or x1/x2 outputs • Exact internal ratios enable zero ppm error • Output clock rates include T1, E1, T3, E3, and OC3 submultiples • See also the MK2049-34 and MK2049-45 NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram EXTERNAL PULLABLE CRYSTAL INPUT REFERENCE CLOCK (TYPICALLY 8KHZ) VCXO-BASED PLL FREQUENCY MULTIPLYING PLL (MASTER CLOCK GENERATOR) FREQUENCY SELECT 2 CLOCK OUTPUT / 2 8 KHZ (REGENERATED) 4 IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL CLOCK OUTPUT 1 MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER Pin Assignment FS1 X2 1 2 20 19 FS0 RES X1 VDD 3 4 18 17 CAP2 GND FCAP VDD GND CLK CLK/2 8k 5 6 16 15 CAP1 VDD 7 8 9 10 14 13 GND ICLK FS3 FS2 12 11 20 pin (300) mil SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 FS1 Input 2 X2 XO Crystal connection. Connect to a MHz crystal as shown in table on page 3. 3 X1 XI Crystal connection. Connect to a MHz crystal as shown in table on page 3. 4 VDD Power 5 FCAP - 6 VDD Power Power supply. Connect to +3.3 V. 7 GND Power Connect to ground 8 CLK Output Clock output determined by status of FS3:0 per tables on page 3. 9 CLK/2 Output 10 8k Output Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of CLK. Recovered 8 kHz clock output. 11 FS2 Input Frequency select 2. Determines CLK input/outputs per tables on page 3. Internal pull-up resistor. 12 FS3 Input Frequency select 3. Determines CLK input/outputs per tables on page 3. Internal pull-up resistor. 13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock. 14 GND Power Connect to ground. 15 VDD Power Power Supply. Connect to +3.3 V. 16 CAP1 17 GND Loop Filter Power Connect the loop filter ceramic capacitors and resistor between this pin and CAP2. Connect to ground. 18 CAP2 Loop Connect the loop filter ceramic capacitors and resistor between this pin and IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL Pin Description Frequency select 1. Determines CLK input/outputs per table on page 3. Internal pull-up resistor. Power supply. Connect to +3.3 V. Filter capacitor. Connect a 1000 pF ceramic capacitor to ground. 2 MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Pin Number Pin Name Pin Type 19 RES - 20 FS0 Input VCXO AND SYNTHESIZER Pin Description Connect a 10-200kΩ resistor to ground. Contact IDTfor recommended value for your application. Frequency select 0. Determines CLK input/outputs per table on page 3. Internal pull-up resistor. Output Decoding Table - External Mode (MHz) ICLK 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK/2 1.544 2.048 22.368 17.184 77.76 16.384 14.352 TEST 18.528 12.352 7.68 TEST 12.288 16.384 CLK 3.088 4.096 44.736 34.368 155.52 32.768 28.704 TEST 37.056 24.704 15.36 TEST 24.576 32.768 Crystal Used (MHz) 12.352 12.288 11.184 11.456 19.44 16.384 14.352 TEST 18.528 24.704 15.36 TEST 24.576 12.288 8k 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz 8 kHz TEST 8 kHz 8 kHz 8 kHz TEST 8 kHz 8 kHz N 1544 1536 1398 1432 2430 2048 1794 TEST 2316 3088 1920 1344 3072 1536 Output Decoding Table - Buffer Mode (MHz) ICLK FS3 FS2 FS1 FS0 22 - 36 1 1 1 0 11 - 18 1 1 1 1 CLK/2 CLK 8k Crystal N ICLK/2 ICLK N/A ICLK/2 3 2*ICLK 4*ICLK N/A ICLK 3 0 = connect directly to ground, 1 = connect directly to VDD or leave open. Crystal is connected to pins 2 and 3; clock input is applied to pin 13. Operating Modes The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock to generate various output clocks, there are important differences in their input and crystal requirements. External Mode The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10 ns is acceptable. Buffer Mode Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range of input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs. IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL 3 MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER Frequency Locking to the Input In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked. PC Board Layout A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output clocks on pins 8 and 9 should have a series termination of 33Ω connected close to the pin. Additional improvements will come from keeping all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away from the MK2049. You may also refer to application note MAN05 for additional suggestions on layout of the crystal selection. The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not adjusted with these fixed capacitors. However, IDT recommends that the adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature, and aging. The value of these capacitors (typically 0 - 4 pF) is determined once for a given board layout, using the procedure found in application note MAN05 (http://www.icst.com/appnotes/man05.pdf). Cutout in ground and power plane. Route all traces away from this area. cap cap cap resist resist 20 19 3 4 5 18 17 16 6 7 8 9 10 15 14 13 12 G resist resist cap V 1 2 G cap G cap Optional see text cap V 11 V = connect to VDD G = connect to GND Figure 2. Typical MK2049-34 Layout External Component Selection The MK2049-36 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17), and 33Ω series terminating resistors should be used on clock outputs with traces longer than one inch (assuming 50Ω traces). The selection of additional external components is described in the following sections. IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL 4 MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER Loop Filter Information on how to configure the external loop filter (connected between pins CAP1 and CAP2) can be found on our web site at http://www.icst.com under “Design Resources”, then select “Calculators”. Crystal Operation The MK2049-36 operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO crystals and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and reliability, the layout guidelines shown on the previous page should be closely followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2049 has variable load capacitors on-chip which “pull” or change the frequency of the crystal. External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should use short traces between the MK2049 and the crystal. For the VCXO to operate correctly, a pullable crystal must be used. For more information, including a list of approved crystals, please refer to application note MAN05 (http://www.icst.com/appnotes/man05.htm). Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2049-36. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 175° C Soldering Temperature 250° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured in respect to GND) IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL Typ. 5 +3.15 +3.3 Max. Units +85 °C +3.45 V MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Conditions Min. Typ. Max. Units 3.3 3.45 V Operating Voltage VDD 3.15 Input High Voltage VIH 2 Input Low Voltage VIL Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -8 mA 2.4 V Output Low Voltage VOL IOL = 8 mA Operating Supply Current IDD No Load, VDD=3.3 V Short Circuit Current IOS Each Output Input Capacitance CIN FS3:0 Internal Pull-up Resistor RPU V 0.8 0.4 V V 7 mA ±50 mA 5 pF 350 kΩ AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol Input Frequency Input Clock Pulse Width Conditions Min. External Mode, Note 1 ICLK Max. Units 8 kHz 10 tpi Propagation Delay Typ. ICLK to 8 kHz Delay, CLK/2 after CLK ns 7 ns 1 ns Output Clock Rise Time tOR 0.8 to 2.0 V 2 ns Output Fall Time tOF 2.0 to 0.8 V 2 ns 60 % 0 ppm Output Clock Duty Cycle, High Time at VDD/2, except 8 kHz Actual mean frequency error versus target Any clock selection 40 0 Note 1: For loop timing modes and buffer modes, see tables on page 3 for required input clock frequencies IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL 6 MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER Package Outline and Package Dimensions (20-pin SOIC, 300 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Inches* 20 Symbol E A A1 B C D E e H h L α H INDEX AREA 1 2 D Min Max -2.65 0.10 -0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 BASIC 10.00 10.65 0.25 0.75 0.40 1.27 0° 8° Min Max -.104 .0040 -.013 .020 .007 .013 .496 .512 .291 .299 0.050 BASIC .394 .419 .010 .029 .016 .050 0° 8° *For reference only. Controlling dimensions in mm. A h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK2049-36SI* MK2049-36SI Tubes 20-pin SOIC -40 to +85° C MK2049-36SITR* MK2049-36SI Tape and Reel 20-pin SOIC -40 to +85° C MK2049-36SILF MK2049-36SILF Tubes 20-pin SOIC -40 to +85° C MK2049-36SILFTR MK2049-36SILF Tape and Reel 20-pin SOIC -40 to +85° C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ 3.3 VOLT COMMUNICATIONS CLOCK PLL 7 MK2049-36 REV F 121809 MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 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