MPC9774FAR2

3.3 V 1:14 LVCMOS PLL Clock Generator MPC9774 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 3.3 V 1:14 LVCMOS PLL Clock Generator The MPC9774 is a 3.3 V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to highperformance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications. DATASHEET MPC9774 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Features • • • • • • • • • • • • • • 1:14 PLL Based Low-Voltage Clock Generator 3.3 V Power Supply Internal Power-On Reset Generates Clock Signals Up to 125 MHz Maximum Output Skew of 175 ps Two LVCMOS PLL Reference Clock Inputs External PLL Feedback Supports Zero-Delay Capability Various Feedback and Output Dividers (See Applications Information) Supports Up to Three Individual Generated Output Clock Frequencies Drives Up to 28 Clock Lines Ambient Temperature Range 0°C to +70°C Pin and Function Compatible to the MPC974 52-Lead LQFP Package, Pb-free For drop in replacement use 87974 AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 848D-03 The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9774 has an internal power-on reset. The MPC9774 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. MPC9774 REVISION 5 3/16/16 1 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR All input resistors have a value of 25 k QA0 VCC CCLK0 Bank A 0 CCLK1 Ref 1 CCLK_SEL VCO 0 2 0 1 4 1 CLK Stop  2, 4 2, 4 PLL QA1 QA2 QA3 4, 6 QA4 4, 6, 8, 12 200–500 MHz Bank B VCC QB0 QB1 CLK Stop FB FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QB2 QB3 QB4 2 Bank C CLK Stop VCC CLK_STOP QC0 QC1 QC2 QC3 VCC Power-On Reset QFB MR/OE GND QB1 VCC QB2 GND QB3 VCC QB4 FB_IN GND QFB VCC NC Figure 1. MPC9774 Logic Diagram VCC QA0 GND QA1 VCC QA2 FSEL_FB1 GND QA3 VCC QA4 GND FSEL_FB0 VCC_PLL NC VCC 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 MPC9774 20 46 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE CLK_STOP FSEL_B FSEL_C PLL_EN FSEL_A CCLK_SEL CCLK0 CCLK1 QB0 VCC NC GND QC3 VCC QC2 GND QC1 VCC QC0 GND VCO_SEL Figure 2. MPC9774 52-Lead Package Pinout (Top View) MPC9774 REVISION 5 3/16/16 2 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configuration Pin I/O Type Function CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock FB_IN Input LVCMOS PLL feedback signal input, connect to QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL enable/PLL bypass mode select MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset CLK_STOP Input LVCMOS Output enable/clock stop (logic low state) FSEL_A Input LVCMOS Frequency divider select for bank A outputs FSEL_B Input LVCMOS Frequency divider select for bank B outputs FSEL_C Input LVCMOS Frequency divider select for bank C outputs FSEL_FB[1:0] Input LVCMOS Frequency divider select for the QFB output QA[4:0] Output LVCMOS Clock outputs (Bank A) QB[4:0] Output LVCMOS Clock outputs (Bank B) QC[3:0] Output LVCMOS Clock outputs (Bank C) QFB Output LVCMOS PLL feedback output. Connect to FB_IN. GND Supply Ground VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Negative power supply Table 2. Function Table (Configuration Controls) Control Default CCLK_SEL 0 Selects CCLK0 as PLL references signal input Selects CCKL1 as PLL reference signal input VCO_SEL 0 Selects VCO  2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Selects VCO  4. The VCO frequency is scaled by a factor of 4 (low input frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9774 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Normal operation mode with PLL enabled. CLK_STOP 1 QA, QB an QC outputs disabled in logic low state. QFB is not affected by CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse to be distorted. Outputs enabled (active) MR/OE 1 Outputs disabled (high-impedance state) and reset of the device. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9774 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal poweron reset (POR) circuitry during power-up. Outputs enabled (active) MPC9774 REVISION 5 3/16/16 0 1 3 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 2. Function Table (Configuration Controls) Control Default 0 1 VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 3 and Table 4 for the device frequency configuration. Table 3. Function Table (Output Dividers Bank A, B, and C) VCO_SEL FSEL_A QA[4:0] VCO_SEL FSEL_B QB[4:0] VCO_SEL FSEL_C QC[3:0] 0 0 VCO  4 0 0 VCO  4 0 0 VCO  8 0 1 VCO  8 0 1 VCO  8 0 1 VCO  12 1 0 VCO  8 1 0 VCO  8 1 0 VCO  16 1 1 VCO  16 1 1 VCO  16 1 1 VCO  24 Table 4. Function Table (QFB) VCO_SEL FSEL_B1 FSEL_B0 QFB 0 0 0 VCO  8 0 0 1 VCO  16 0 1 0 VCO  12 0 1 1 VCO  24 1 0 0 VCO  16 1 0 1 VCO  32 1 1 0 VCO  24 1 1 1 VCO  48 Table 5. General Specifications Symbol Characteristics Min Typ Max VCC  2 Unit Condition VTT Output Termination Voltage MM ESD protection (Machine Model) 200 V HBM ESD protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs V Table 6. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V DC Input Current 20 mA DC Output Current 50 mA 125 C VOUT IIN IOUT TS Storage Temperature –65 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MPC9774 REVISION 5 3/16/16 4 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 7. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C) Symbol Characteristics Min Typ Max Unit Condition VCC_PLL PLL Supply Voltage 3.02 VCC V LVCMOS VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VOH Output High Voltage V IOH = –24 mA(1) VOL Output Low Voltage V V IOL = 24 mA IOL = 12 mA ZOUT Output Impedance IIN ICC_PLL ICCQ 2.4 0.55 0.30 14 – 17 Input Current(2) Maximum PLL Supply Current 5.0 Maximum Quiescent Supply Current W 200 A VIN = VCC or GND 7.5 mA VCC_PLL Pin 8.0 mA All VCC Pins 1. The MPC9774 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines. 2. Inputs have pull-down or pull-up resistors affecting the input current. Table 8. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1) Symbol fREF Characteristics Input Reference Frequency Min 8 feedback 12 feedback 16 feedback 24 feedback 32 feedback 48 feedback Typ Max Unit Condition 62.5 41.6 31.25 20.83 15.625 10.41 MHz MHz MHz MHz MHz MHz PLL locked 250 MHz 200 500 MHz 50.0 25.0 16.6 12.5 8.33 125.0 62.5 41.6 31.25 20.83 MHz MHz MHz MHz MHz 25.0 16.6 12.5 8.33 6.25 4.16 Input Reference Frequency in PLL Bypass Mode(2) Range(3) fVCO VCO Frequency fMAX Output Frequency tPW,MIN Input Reference Pulse Width(4) tR, tF CCLKx Input Rise/Fall Time t() 4 output 8 output  12 output 16 output 24 output 2.0 1.0 ns 0.8 to 2.0 V +100 ps PLL locked 100 125 100 175 ps ps ps ps 53 % 1.0 ns (5) Propagation Delay (static phase offset) CCLKx to FB_IN (FB = 8 and fREF = 50 MHz) (6) –250 Output-to-Output Skew DC Output Duty Cycle 47 tR, tF Output Rise/Fall Time 0.1 tPLZ, HZ Output Disable Time 10 ns tPZL Output Enable Time 10 ns 90 ps 90 ps tJIT(PER) PLL locked ns tSK(O) tJIT(CC) PLL bypass within QA bank within QB bank within QC bank any output (7) Cycle-to-Cycle Jitter (6) Period Jitter MPC9774 REVISION 5 3/16/16 5 50 0.55 to 2.4 V ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Table 8. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1) (Continued) Symbol Characteristics Min tJIT() I/O Phase Jitter RMS (1 )(8) FB = 8 FB = 12 FB =16 FB =24 FB =32 FB = 48 BW PLL Closed Loop Bandwidth(9) FB = 8 FB = 12 FB = 16 FB = 24 FB = 32 FB = 48 tLOCK Maximum PLL Lock Time 1. 2. 3. 4. 5. 6. 7. 8. 9. Typ Max Unit 15 49 18 22 26 34 ps ps ps ps ps ps Condition MHz MHz MHZ MHz MHz MHz 0.50 – 1.80 0.30 – 1.00 0.25 – 0.70 0.17 – 0.40 0.12 – 0.30 0.07 – 0.20 10 ms AC characteristics apply for parallel output termination of 50  to VTT. In bypass mode, the MPC9774 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): fREF = fVCO (M  VCO_SEL). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN  fREF  100% and DCREF,MAX = 100% – DCREF,MIN. E.g. at fREF = 62.5 MHz the input duty cycle range is 12.5% < DC < 87.5%. Static phase offset depends on the reference frequency: t() = +50 ps ± (1(120  fREF)) for any reference frequency. Refer to Application section for part-to-part skew calculation. Valid for all outputs at the same frequency. I/O jitter for fVCO = 400 MHz. Refer to Applications Information for I/O jitter at other frequencies and for a jitter calculation for confidence factors other than 1 . –3 dB point of PLL transfer characteristics. MPC9774 REVISION 5 3/16/16 6 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR APPLICATIONS INFORMATION MPC9774 Configurations Configuring the MPC9774 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fREF = 20.83 MHz fOUT = fREF  M  N fREF PLL VCO_SEL QA[4:0] 125 MHz 0 VCO_SEL FB_IN QB[4:0] 62.5 MHz QC[3:0] 62.5 MHz 0 1 0 11 fOUT N CCLK0 CCLK1 0 CCLK_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QFB MPC9774 M 20.83 MHz (Feedback) MPC9774 example configuration (feedback of QFB = 20.83 MHz, VCO_SEL = 2, M = 12, NA = 2, NB = 4, NC = 4, fVCO = 500 MHz). where fREF is the reference frequency of the selected input clock source (CCLK0 or CCLK1), M is the PLL feedback divider and N is a output divider. M is configured by the FSEL_FB[0:1] and N is individually configured for each output bank by the FSEL_A, FSEL_B and FSEL_C inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 500 MHz in order to achieve stable PLL operation: fVCO,MIN  (fREF  VCO_SEL  M)  fVCO,MAX Frequency Range Min Max Input 8.33 MHz 20.83 MHz QA outputs 50 MHz 125 MHz QB outputs 25 MHz 62.5 MHz QC outputs 25 MHz 62.5 MHz Figure 3. Example Configuration The PLL post-divider VCO_SEL is either a divide-by-two or a divide-by-four and can be used to situate the VCO into the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fREF = 25 MHz CCLK0 CCLK1 0 CCLK_SEL QA[4:0] 100 MHz 0 VCO_SEL FB_IN QB[4:0] 50 MHz QC[3:0] 33.3 MHz 0 1 1 01 fQA[4:0] = fVCO  (VCO_SEL  NA) fQB[4:0] = fVCO  (VCO_SEL  NB) fQC[3:0] = fVCO  (VCO_SEL  NC) FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QFB MPC9774 25 MHz (Feedback) Table 9. MPC9774 Divider MPC9774 example configuration (feedback of QFB = 25 MHz, VCO_SEL = 2, M = 8, NA = 2, NB = 4, NC = 6, fVCO = 400 MHz). Divider Function VCO_SEL Values M PLL Feedback FSEL_FB[0:1] 2 8, 12, 16, 24 4 16, 24, 32, 48 Frequency Range Min Bank A Output Divider FSEL_A 2 4, 8 Input 20 MHz 48 MHz 4 8, 16 QA outputs 50 MHz 120 MHz Bank B Output Divider FSEL_B 2 4, 8 QB outputs 50 MHz 120 MHz 4 QC outputs 100 MHz 200 MHz 8, 16 Bank C Output Divider FSEL_C 2 8, 12 4 16, 24 NA NB NC Max Figure 4. Example Configuration Table 9 shows the various PLL feedback and output dividers. The output dividers for the three output banks allow the user to configure the outputs into 1:1, 2:1, 3:2, and 3:2:1 frequency ratios. Figure 3 and Figure 4 display example configurations for the MPC9774. MPC9774 REVISION 5 3/16/16 7 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Using the MPC9774 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9774. Designs using the MPC9774 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback of the MPC9774 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or longterm jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Table 10. Confidence Factor CF  1 0.68268948  2 0.95449988  3 0.99730007  4 0.99993663  5 0.99999943  6 0.99999999 tSK(PP) = [–250 ps...+100 ps] + [-175 ps...175 ps] + This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: [(15 ps  –3)...(15 ps  3)] + tPD, LINE(FB) tSK(PP) = [–470 ps...+320 ps] + tPD, LINE(FB) Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB tPD,LINE(FB) –t() Probability of Clock Edge within the Distribution Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 6 and Figure 7 to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of –470 ps to +320 ps relative to CCLK (PLL feedback = 8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 15 ps RMS max., static phase offset t() = –250 ps to +100 ps): Calculation of Part-to-Part Skew The MPC9774 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9774 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()  CF CCLKCommon CF 100 tjit[] [ps] RMS 80 QFBDevice 1 tJIT() Any QDevice 1 ±tSK(O) FB = 8 0 200 250 300 350 400 450 500 VCO Frequency [MHz] QFBDevice2 Max. skew FB = 16 40 20 +t() Any QDevice 2 FB = 32 60 tJIT() Figure 6. MPC9774 I/O Jitter Maximum I/O Phase Jitter (RMS) versus Frequency Parameter: PLL Feedback Divider FB ±tSK(O) tSK(PP) tjit[] [ps] RMS Figure 5. MPC9774 Maximum Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. 160 140 FB = 12 120 100 80 FB = 48 60 40 FB = 24 20 0 200 250 300 350 400 VCO Frequency [MHz] 450 500 Figure 7. MPC9774 I/O Jitter MPC9774 REVISION 5 3/16/16 8 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR VL = VS (Z0  (RS + R0 + Z0)) Driving Transmission Lines The MPC9774 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20  the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50  resistance to VCC  2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9774 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9774 clock driver is effectively doubled due to its capability to drive multiple lines. Z0 = 50  || 50  RS = 36  || 36  R0 = 14  VL = 3.0 (25  (18 + 17 + 25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 3.0 2.5 In OutB tD = 3.9386 Voltage (V) 2.0 In 1.5 1.0 0.5 MPC9774 Output Buffer 14  OutA tD = 3.8956 RS = 36  0 ZO = 50  2 OutA 4 6 8 Time (ns) 10 12 14 Figure 9. Single versus Dual Waveforms MPC9774 Output Buffer In RS = 36  ZO = 50  RS = 36  ZO = 50  Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutB0 14  OutB1 Figure 8. Single versus Dual Transmission Lines MPC9774 Output Buffer The waveform plots in Figure 9 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9774 output buffer is more than sufficient to drive 50  transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9774. The output waveform in Figure 9 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36  series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: MPC9774 REVISION 5 3/16/16 RS = 22  ZO = 50  RS = 22  ZO = 50  14  14  + 22   22  = 50  || 50  25  = 25  Figure 10. Optimized Dual Line Termination 9 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Power Supply Filtering The MPC9774 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9774 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9774. Figure 11 illustrates a typical power supply filter scheme. The MPC9774 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 5 mA (7.5 mA maximum), assuming that a minimum of 3.02 V (VCC_PLL, min) must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 11 must have a resistance of 5–15 to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example, RC filter shown in Figure 11, the filter cut-off frequency is around 3–5 kHz and the noise attenuation at 100 kHz is better than 42 dB. RF = 5–15  VCC CF = 22 F RF VCC_PLL CF 10 nF MPC9774 VCC 33...100 nF Figure 11. VCC_PLL Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9774 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. MPC9774 DUT Pulse Generator Z = 50  Z = 50  Z = 50  RT = 50  RT = 50  VTT VTT Figure 12. CCLK MPC9774 AC Test Reference MPC9774 REVISION 5 3/16/16 10 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR VCC VCC2 VCC GND VCC2 CCLKx VCC VCC2 GND GND VCC VCC2 FB_IN tSK(O) GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t() Figure 13. Output-to-Output Skew tSK(O) Figure 14. Propagation Delay (t(), Static Phase Offset) Test Reference VCC VCC2 CCLKx GND tP FB_IN T0 DC = tP/T0 x 100% TJIT() = |T0–T1mean| The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 15. Output Duty Cycle (DC) TN TN+1 Figure 16. I/O Jitter TJIT(CC) = |TN–TN+1| TJIT(PER) = |TN–1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle-to-Cycle Jitter Figure 18. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 19. Output Transition Time Test Reference MPC9774 REVISION 5 3/16/16 11 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR PACKAGE DIMENSIONS 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 40 1 CL 39 AB G 3X VIEW Y -L- -M- AB B B1 13 V VIEW Y BASE METAL F PLATING V1 27 14 J 26 U -N- A1 D 0.13 (0.005) M T L-M S N S S1 SECTION AB-AB A ROTATED 90˚ CLOCKWISE S 4X θ2 C 0.10 (0.004) T HT- 4X θ3 EATING LANE VIEW AA 0.05 (0.002) S W 2X R θ1 R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA CASE 848D-03 ISSUE D 52-LEAD LQFP PACKAGE MPC9774 REVISION 5 3/16/16 12 NOTES: 1. CONTROLLING DIMENSIONS: MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSTION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date 5 1 NRND – Not Recommend for New Designs 1/8/13 5 1 Removed NRND and removed bullet referencing the replacement part. 5/5/15 1 Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02 3/16/16 5 MPC9774 REVISION 5 3/16/16 13 ©2016 Integrated Device Technology, Inc. MPC9774 Data Sheet 3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support clocks@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2016. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.