R1LP0408DSP-5SR#S0

R1LP0408D Series 4Mb Advanced LPSRAM (512-kword × 8-bit) R10DS0104EJ0200 Rev.2.00 2012.5.30 Description The R1LP0408D Series is a family of 4-Mbit static RAMs organized 512-kword × 8-bit, fabricated by Renesas’s high-performance CMOS and TFT technologies. The R1LP0408D Series has realized higher density, higher performance and low power consumption. The R1LP0408D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP and 32-pin TSOP. Features • Single 5V supply: 4.5V to 5.5V • Access time: 55/70ns (max) • Power dissipation: ── Standby: 4µW (typ) • Equal access and cycle times • Common data input and output ── Three state output • Directly TTL compatible ── All inputs and outputs • Battery backup operation Part Name Information Part Name R1LP0408DSP-5SR#B* R1LP0408DSP-5SI#B* R1LP0408DSP-7SR#B* R1LP0408DSP-7SI#B* R1LP0408DSP-5SR#S* R1LP0408DSP-5SI#S* R1LP0408DSP-7SR#S* R1LP0408DSP-7SI#S* R1LP0408DSB-5SR#B* R1LP0408DSB-5SI#B* R1LP0408DSB-7SR#B* R1LP0408DSB-7SI#B* R1LP0408DSB-5SR#S* R1LP0408DSB-5SI#S* R1LP0408DSB-7SR#S* R1LP0408DSB-7SI#S* Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns R10DS0104EJ0200 Rev.2.00 2012.5.30 Temperature Range Package Shipping Container Quantity Tube Max. 25pcs/Tube Max. 225pcs/Inner Bag Max. 900pcs/Inner Box Embossed tape 1000pcs/Reel Tray Max. 117pcs/Tray Max. 936pcs/Inner Box Embossed tape 1000pcs/Reel 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 525-mil 32-pin plastic SOP PRSP0032DF-A (032P2S-A) 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C -40 ~ +85°C 0 ~ +70°C 400-mil 32-pin plastic TSOP(II) PTSB0032DC-A (032PTY-A) -40 ~ +85°C Page 1 of 1 R1LP0408D Series Pin Arrangement A18 1 32 Vcc A16 2 31 A15 A14 3 30 A17 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE# A2 10 23 A10 A1 11 22 CS# A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 Vss 16 17 I/O3 32-pin SOP 32-pin TSOP Pin Description Pin name Function Vcc Vss A0 to A18 I/O0 to I/O7 CS# Power supply Ground Address input Data input/output Chip select WE# OE# Write enable Output enable R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 2 of 11 R1LP0408D Series Block Diagram LSB A11 A9 A8 A13 A17 A15 A18 A16 A14 A12 A7 Vcc Vss Row Decoder ・ ・ ・ ・ ・ Memory Matrix 2,048 x 2,048 MSB I/O0 ・ ・ Input Data Control Column I/O ・ ・ Column Decoder I/O7 LSB A5 A4 A10 A0 A1 A2 A3 A6 MSB ・ ・ CS# Timing Pulse Generator WE# Read/Write Control OE# R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 3 of 11 R1LP0408D Series Operation Table WE# CS# OE# Mode Vcc current I/O0 to I/O7 Ref. cycle × H × Not selected ISB, ISB1 High-Z ─ H L H Output disable Icc High-Z ─ H L L Read Icc Dout Read cycle L L H Write Icc Din Write cycle (1) L Write Icc Din Write cycle (2) L Note 1. L H: VIH L:VIL ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr*3 Value -0.5 to +7.0 -0.5*1 to Vcc+0.3*2 0.7 R Ver. 0 to +70 I Ver. Tstg Tbias*3 -40 to +85 -65 to 150 R Ver. I Ver. unit V V W °C °C 0 to +70 -40 to +85 °C 1. -3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +7.0V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 4 of 11 R1LP0408D Series DC Operating Conditions Parameter Supply voltage Symbol Min. Typ. Max. Unit Vcc 4.5 5.0 5.5 V Vss 0 0 0 V Note Input high voltage VIH 2.2 ─ Vcc+0.3 V Input low voltage VIL -0.3 ─ 0.8 V 1 0 ─ +70 °C 2 -40 ─ +85 °C 2 R Ver. Ambient temperature range Note Ta I Ver. 1. -3.0V for pulse ≤ 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. DC Characteristics Parameter Input leakage current Symbol Min. Typ. Max. Unit | ILI | ─ ─ 1 μA | ILO | ─ ─ 1 μA Icc ─ 5*1 10 mA ICC1 ─ 15*1 25 mA ICC2 ─ 3*1 5 mA ISB ─ 0.1*1 0.5 mA ─ 0.8*1 2.5 μA ~+25°C ─ 1*2 3 μA ~+40°C ─ ─ 8 μA ~+70°C ─ ─ 10 μA ~+85°C VOH 2.4 ─ ─ V IOH = -1mA VOH2 Vcc-0.5 ─ ─ V IOH = -0.1mA VOL ─ ─ 0.4 V IOL = 2.1mA Output leakage current Operating current Average operating current Standby current Standby current Test conditions Vin = Vss to Vcc CS# =VIH or OE# =VIH, VI/O =Vss to Vcc CS# =VIL, Others = VIH/VIL, II/O = 0mA Min. cycle, duty =100%, II/O = 0mA CS# =VIL, Others = VIH/VIL Cycle =1μs, duty =100%, II/O = 0mA CS# ≤ 0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V CS# =VIH, Others = Vss to Vcc Vin = Vss to Vcc, CS# ≥ Vcc-0.2V ISB1 Output high voltage Output low voltage Note 1. Typical parameter indicates the value for the center of distribution at 5.0V (Ta=25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 5.0V (Ta=40ºC), and not 100% tested. Capacitance (Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2) Parameter Input capacitance Input / output capacitance Note Symbol C in C I/O Min. ─ ─ Typ. ─ ─ Max. 8 10 Unit pF pF Test conditions Vin =0V VI/O =0V Note 1 1 1. This parameter is sampled and not 100% tested. 2. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 5 of 11 R1LP0408D Series AC Characteristics Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70°C / -40 ~ +85°C*1) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm I/O CL = 50 pF ( -5SI, -5SR) CL = 100 pF ( -7SI, -7SR) Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 6 of 11 R1LP0408D Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Output hold from address change Symbol tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH R1LP0408DS*-5S* R1LP0408DS*-7S* Min. 55 ─ ─ ─ 10 5 0 0 10 Min. 70 ─ ─ ─ 10 5 0 0 10 Max. ─ 55 55 25 ─ ─ 20 20 ─ Max. ─ 70 70 35 ─ ─ 25 25 ─ Unit Note ns ns ns ns ns ns ns ns ns 2 2 1,2 1,2 Write Cycle Parameter Symbol R1LP0408DS*-5S* R1LP0408DS*-7S* Max. ─ ─ ─ Min. 70 60 0 Max. ─ ─ ─ ─ ─ ─ 20 ─ ─ ─ 20 60 50 0 0 30 0 5 0 ─ ─ ─ 25 ─ ─ ─ 25 Write cycle time Chip select to end of write Address setup time tWC tCW tAS Min. 55 50 0 Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z tAW tWP tWR tWHZ tDW tDH tOW tOHZ 50 40 0 0 25 0 5 0 Note Unit Note ns ns ns 4 5 ns ns ns ns ns ns ns ns 3,12 6 1,2,7 2 1,2,7 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS# going low to end of write. 5. tAS is measured the address valid to the beginning of write. 6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 7 of 11 R1LP0408D Series Timing Waveforms Read Cycle (WE# = VIH ) tRC Valid address Address tAA tACS CS# tCLZ tCHZ tOE tOLZ OE# tOHZ Dout High impedance Valid Data tOH R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 8 of 11 R1LP0408D Series Write Cycle (1) (OE# CLOCK) tWC Valid address Address tWR tAW OE# tCW CS# tAS *8 tWP WE# tOHZ Dout High impedance tDW Din R10DS0104EJ0200 Rev.2.00 2012.5.30 tDH Valid Data Page 9 of 11 R1LP0408D Series Write Cycle (2) (OE# Low Fixed) tWC Valid address Address tCW tWR CS# *8 tAW tWP WE# tOH tAS tWHZ tOW *9 Dout *10 High impedance tDW tDH *11 Din R10DS0104EJ0200 Rev.2.00 2012.5.30 Valid Data Page 10 of 11 R1LP0408D Series Low Vcc Data Retention Characteristics Test conditions*3 Parameter Symbol Min. Typ. Max. Unit VCC for data retention VDR 2.0 ─ 5.5 V Vin ≥ 0V, CS# ≥ Vcc-0.2V ─ 0.8*1 2.5 μA ~+25°C ─ 1*2 3 μA ~+40°C ─ ─ 8 μA ~+70°C ─ ─ 10 μA ~+85°C Data retention current ICCDR Vcc=3.0V, Vin ≥ 0V, CS# ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ─ ─ ns See retention waveform. Operation recovery time tR 5 ─ ─ ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested. 3. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high impedance state. Low Vcc Data Retention Timing Waveforms CS# Controlled Vcc tCDR 2.2V 4.5V 4.5V VDR tR 2.2V CS# ≥ Vcc - 0.2V CS# R10DS0104EJ0200 Rev.2.00 2012.5.30 Page 11 of 11 Revision History R1LP0408D Series Data Sheet Rev. Date Page 1.00 2.00 2012.4.13 2012.5.30 ─ P.1 Description Summary First Edition issued (SOP package) Add TSOP package to Part Name Information All trademarks and registered trademarks are the property of their respective owners. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics 3. 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