R1WV6416RSD-7SR

Preliminary R1WV6416R Series 64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit) REJ03C0368-0001 Preliminary Rev.0.01 2008.03.24 Description The R1WV6416R Series is a family of low voltage 64-Mbit static RAMs organized as 4,194,304-word by 16-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1WV6416R Series is suitable for memory applications where a simple interfacing, battery operating and battery backup are the important design objectives. The R1WV6416R Series is provided in 48-pin thin small outline package [TSOP (I): 12mm x 20mm with pin pitch of 0.5mm], 52-pin micro thin small outline package [µTSOP (II): 10.79mm x 10.49mm with pin pitch of 0.4mm] and 48-ball fine pitch ball grid array [f-BGA] package. It gives the best solution for compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • • • • • • • • Single 2.7~3.6V power supply Small stand-by current: 8 µA (3.0V, typical) No clocks, No refresh All inputs and outputs are TTL compatible. Easy memory expansion by CS1#, CS2, LB# and UB# Common Data I/O Three-state outputs: OR-tie Capability OE# prevents data contention on the I/O bus Ordering Information Type No. R1WV6416RSA-5S% R1WV6416RSA-7S% R1WV6416RSD-5S% R1WV6416RSD-7S% R1WV6416RBG-5S% R1WV6416RBG-7S% Access time 55 ns*1 70 ns 55 ns*1 70 ns 55 ns*1 70 ns Package 12mm x 20mm 48-pin plastic TSOP (I) (normal-bend type) (48P3R) 350 mil 52-pin plastic μ-TSOP (II) (normal-bend type) (52PTG) f-BGA 0.75mm pitch 48-ball Note1. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts. % - Temperature version; see table below Temperature Range 0 ~ +70 °C -40 ~ +85 °C % R I REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 1 of 16 R1WV6416R Series Preliminary Pin Arrangement A15 A14 A13 A12 A11 A10 A9 A8 A19 CS1# WE# NC NC Vcc CS2 A21 A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 A16 BYTE# UB# Vss LB# DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 NC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss NC A0 1 A B C D E F G H LB# DQ15 2 OE# UB# 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS1# DQ1 DQ3 DQ4 DQ6 WE# A11 6 CS2 DQ0 DQ2 Vcc Vss DQ5 DQ7 A20 DQ13 DQ14 Vss Vcc DQ10 DQ8 A18 DQ12 DQ11 DQ9 A19 A8 52-pin μTSOP (II) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 A21 A14 A12 A9 48-pin f-BGA (TOP VIEW) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# CS2 A21 UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CS1# A0 48-pin TSOP (I) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 2 of 16 R1WV6416R Series Preliminary Pin Description Pin name Vcc Vss A0 to A21 A-1 to A21 DQ0 to DQ15 CS1# CS2 WE# OE# LB# UB# BYTE# NC Function Power supply Ground Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte enable Upper byte enable Byte control mode enable Non connection Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 3 of 16 R1WV6416R Series Preliminary Block Diagram A0 A1 ADDRESS BUFFER ROW DECODER MEMORY ARRAY 2M-word x16-bit or 4M-word x 8-bit DQ BUFFER DQ0 DQ1 A21 DATA SENSE / WRITE AMPLIFIER SELECTOR DQ7 DQ8 DQ9 DQ COLUMN DECODER CLOCK BUFFER CS2 CS1# LB# UB# BYTE# WE# OE# GENERATOR DQ15 / A -1 X8 / x16 CONTROL Vcc Vss 32Mb SRAM #1 32Mb SRAM #2 Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 4 of 16 R1WV6416R Series Preliminary Operation Table CS1# H X X L L L L L L L L L L CS2 X L X H H H H H H H H H H BYTE# X X H H H H H H H H L L L LB# X X H L L H H L L L L L L UB# X X H H H L L L L L L L L WE# X X X L H L H L H H L H H OE# X X X X L X L X L H X L H DQ0~7 High-Z High-Z High-Z Din Dout High-Z High-Z Din Dout High-Z Din Dout High-Z DQ8~14 High-Z High-Z High-Z High-Z High-Z Din Dout Din Dout High-Z High-Z High-Z High-Z DQ15 High-Z High-Z High-Z High-Z High-Z Din Dout Din Dout High-Z A-1 A-1 A-1 Operation Stand-by Stand-by Stand-by Write in lower byte Read in lower byte Write in upper byte Read in upper byte Word write Word read Output disable Byte write Byte read Output disable Note1. H: VIH L:VIL X: VIH or VIL 2. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. 3. When apply BYTE# =“L”, please assign LB#=UB#=“L”. Absolute Maximum Ratings Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Symbol Vcc VT PT Topr*3 Tstg Tbias*3 R ver. I ver. R ver. I ver. Value -0.5 to +4.6 -0.5*1 to Vcc+0.3*2 0.7 0 to +70 -40 to +85 -65 to 150 0 to +70 -40 to +85 unit V V W °C °C °C °C °C Note 1. –2.0V in case of AC (Pulse width ≤30ns) 2. Maximum voltage is +4.6V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 5 of 16 R1WV6416R Series Preliminary Recommended Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range R ver. Symbol Vcc Vss VIH VIL Min. 2.7 0 2.4 -0.2 0 Typ. 3.0 0 Max. 3.6 0 Vcc+0.2 Unit V V V V °C °C Note 0.4 +70 Ta I ver. -40 +85 Note 1. –2.0V in case of AC (Pulse width ≤ 30ns) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. 1 2 2 DC Characteristics Parameter Input leakage current Output leakage current Symbol | ILI | Min. Typ. Max. 1 Unit μA μA Test conditions*3 Vin = Vss to Vcc BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# =VIH or CS2 =VIL or OE# =VIH or WE# =VIL or LB# = UB# =VIH, VI/O =Vss to Vcc Min. cycle, duty =100%, II/O = 0mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# =VIL, CS2 =VIH, Others = VIH/VIL Cycle =1μs, duty =100%, II/O = 0mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V, VIH ≥ VCC-0.2V, VIL ≤ 0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V CS2 =VIH Vin ≥ 0V ~+25°C BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V ~+40°C (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or ~+70°C (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, ~+85°C CS2 ≥ VCC-0.2V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOH = -0.5mA BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V IOL = 2mA | ILO | - - 1 Average operating current ICC1 45*1 60 mA ICC2 - 5*1 10 mA Standby current Standby current ISB - 0.1*1 8*1 14*2 - 0.3 24 48 100 160 0.4 mA μA μA μA μA V V ISB1 Output high voltage Output low voltage VOH VOL 2.4 - Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested. 3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 6 of 16 R1WV6416R Series Preliminary Capacitance (Ta =25°C, f =1MHz) Parameter Symbol Min. Typ. Input capacitance C in Input / output capacitance C I/O Note1.This parameter is sampled and not 100% tested. Max. 20 20 Unit pF pF Test conditions Vin =0V V I/O =0V Note 1 1 AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1) • • • • Input pulse levels: VIL = 0.4V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.4V Output load: See figures (Including scope and jig) 1.4V RL = 500 ohm DQ CL = 30 pF Note1. Ambient temperature range depends on R/I-version. Please see table on page 1. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 7 of 16 R1WV6416R Series Read Cycle R1WV6416R**-5S Preliminary Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ (Note 0) Min. 55 10 10 10 5 5 0 0 0 0 Max. 70 55 55 25 55 20 20 20 20 R1WV6416R**-7S Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note Min. 70 10 10 10 5 5 0 0 0 0 Max. 70 70 70 35 70 25 25 25 25 2,3 2,3 2,3 2,3 1,2,3 1,2,3 1,2,3 1,2,3 REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 8 of 16 R1WV6416R Series Write Cycle R1WV6416R**-5S Preliminary Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output enable from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ (Note 0) Min. 55 50 50 40 50 0 0 25 0 5 0 0 Max. 20 20 R1WV6416R**-7S Unit ns ns ns ns ns ns ns ns ns ns ns ns Note Min. 70 65 65 55 65 0 0 35 0 5 0 0 Max. 25 25 5 4 6 7 2 1,2 1,2 Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts. In case of tAA =70ns, tRC =70ns. 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 9 of 16 R1WV6416R Series BYTE# Timing Conditions Parameter Byte setup time Byte recovery time Symbol tBS tBR R1WV6416R**-5S R1WV6416R**-7S Preliminary Min. 5 5 Max. - Min. 5 5 Max. - Unit ms ms Note BYTE# Timing Waveforms CS1# CS2 tBS BYTE# tBR REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 10 of 16 R1WV6416R Series Preliminary Timing Waveforms Read Cycle*1 tRC A0~21 (Word Mode) A -1~21 (Byte Mode) tAA tBA tBLZ tACS1 tCLZ1 tOH LB#,UB# tBHZ CS1# tCHZ1 CS2 tCLZ2 WE# WE# = “H” level VIH VIL tACS2 tCHZ2 OE# tOLZ DQ0~15 (Word Mode) tOE tOHZ High impedance Valid Data DQ0~7 (Byte Mode) Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 11 of 16 R1WV6416R Series Write Cycle (1)*1 (WE# CLOCK) Preliminary tWC A0~21 (Word Mode) A -1~21 (Byte Mode) tOH tBW LB#,UB# tCW CS1# tCW CS2 tAW tAS WE# tWP tWR OE# tWHZ tOHZ DQ0~15 (Word Mode) tOLZ tOW Valid Data tDW tDH DQ0~7 (Byte Mode) Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 12 of 16 R1WV6416R Series Write Cycle (2)*1 (CS1#, CS2 CLOCK) Preliminary tWC A0~21 (Word Mode) A -1~21 (Byte Mode) tAW tBW LB#,UB# tAS tCW tWR CS1# tAS CS2 tWP WE# tCW tWR OE# OE# = “H” level VIH VIL tDW DQ0~15 (Word Mode) tDH DQ0~7 (Byte Mode) Valid Data Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 13 of 16 R1WV6416R Series Write Cycle (3)*1 (LB#, UB# CLOCK) Preliminary tWC A0~21 (Word Mode) A -1~21 (Byte Mode) tAW tAS tBW tWR LB#,UB# tCW CS1# tCW CS2 tWP WE# OE# OE# = “H” level VIH VIL tDW DQ0~15 (Word Mode) tDH DQ0~7 (Byte Mode) Valid Data Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 14 of 16 R1WV6416R Series Preliminary Low Vcc Data Retention Characteristics Parameter Symbol Min. Typ Max. Unit Test conditions*3,4 Vin ≥ 0V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V Vin ≥ 0V ~+25°C BYTE# ≥ Vcc -0.2V or BYTE# ≤0.2V ~+40°C (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or ~+70°C (3) LB# = UB# ≥ VCC-0.2V, CS1# ≤ 0.2V, ~+85°C CS2 ≥ VCC-0.2V See retention waveform. VCC for data retention VDR 2.0 - 3.6 V Data retention current ICCDR Chip select to data retention time Operation recovery time tCDR tR 0 5 8*1 14*2 - 24 48 100 160 - μA μA μA μA ns ms Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested. 3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages. 4. CS2 also controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 15 of 16 R1WV6416R Series Low Vcc Data Retention Timing Waveforms*1 (1) CS1# Controlled Vcc Preliminary tCDR 2.2V 2.7V 2.7V tR 2.2V VDR CS1# ≥ Vcc - 0.2V CS1# (2) CS2 Controlled Vcc CS2 tCDR 2.7V 2.7V tR VDR 0.6V 0.6V 0V ≤ CS2 ≤ 0.2V (3) LB#, UB# Controlled Vcc tCDR 2.2V LB#, UB# 2.7V 2.7V tR 2.2V VDR LB#, UB# ≥ Vcc - 0.2V Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V REJ03C0368-0001, Rev.0.01, 2008.03.24 Page 16 of 16 Revision History R1WV6416R Data Sheet Contents pf Revision Description Rev. 0.01 Date Mar.24, 2008 Page - Initial issue: Preliminary Data Sheet Sales Strategic Planning Div. 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