Datasheet
RX230 Group, RX231 Group
R01DS0261EJ0120
Rev.1.20
Sep 28, 2018
Renesas MCUs
54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,
various communication functions including USB 2.0 full-speed host/function/OTG, CAN, SD host
interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC, Encryption
functions
Features
■ 32-bit RXv2 CPU core
• Max. operating frequency: 54 MHz
Capable of 88.56 DMIPS in operation at 54 MHz
• Enhanced DSP: 32-bit multiply-accumulate and 16-bit
multiply-subtract instructions supported
• Built-in FPU: 32-bit single-precision floating point (compliant to
IEEE754)
• Divider (fastest instruction execution takes two CPU clock cycles)
• Fast interrupt
• CISC Harvard architecture with 5-stage pipeline
• Variable-length instructions, ultra-compact code
• On-chip debugging circuit
• Memory protection unit (MPU) supported
■ Low power design and architecture
•
•
•
•
Operation from a single 1.8-V to 5.5-V supply
RTC capable of operating on the battery backup power supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby state
■ On-chip flash memory for code
•
•
•
•
128- to 512-Kbyte capacities
On-board or off-board user programming
Programmable at 1.8 V
For instructions and operands
■ On-chip data flash memory
• 8 Kbytes (1,000,000 program/erase cycles (typ.))
• BGO (Background Operation)
■ On-chip SRAM, no wait states
• 32- to 64-Kbyte size capacities
■ Data transfer functions
• DMAC: Incorporates four channels
• DTC: Four transfer modes
■ ELC
• Module operation can be initiated by event signals without using
interrupts.
• Linked operation between modules is possible while the CPU is sleeping.
■ Reset and supply management
• Eight types of reset, including the power-on reset (POR)
• Low voltage detection (LVD) with voltage settings
■ Clock functions
•
•
•
•
•
Main clock oscillator frequency: 1 to 20 MHz
External clock input frequency: Up to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-chip low-speed
oscillator for the IWDT
• USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz
54 MHz can be set for the system clock and 48 MHz for the USB clock
• Generation of a dedicated 32.768-kHz clock for the RTC
• Clock frequency accuracy measurement circuit (CAC)
■ Realtime clock
•
•
•
•
Adjustment functions (30 seconds, leap year, and error)
Calendar count mode or binary count mode selectable
Time capture function
Time capture on event-signal input through external pins
■ Independent watchdog timer
• 15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ Useful functions for IEC60730 compliance
• Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
■ External address space
• Four CS areas (4 × 16 Mbytes)
• 8- or 16-bit bus space is selectable per area
■ MPC
• Input/output functions selectable from multiple pins
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch
PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch
PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch
PWQN0064KC-A 9 × 9 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch
PTLG0100KA-A 5.5 × 5.5 mm, 0.5 mm pitch
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch
■ Up to 14 communication functions
• USB 2.0 host/function/On-The-Go (OTG) (one channel),
full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supported
• CAN (one channel) compliant to ISO11898-1:
Transfer at up to 1 Mbps
• SCI with many useful functions (up to 7 channels)
Asynchronous mode, clock synchronous mode, smart card interface
Reduction of errors in communications using the bit modulation
function
• IrDA interface (one channel, in cooperation with the SCI5)
• I2C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
• RSPI (one channel): Transfer at up to 16 Mbps
• Serial sound interface (one channel)
• SD host interface (optional: one channel) SD memory/ SDIO 1-bit or
4-bit SD bus supported
■ Up to 20 extended-function timers
• 16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (six channels)
• 16-bit TPU: input capture, output compare, phase counting mode (six
channels)
• 8-bit TMR (four channels)
• 16-bit compare-match timers (four channels)
■ 12-bit A/D converter
•
•
•
•
Capable of conversion within 0.83 μs
24 channels
Sampling time can be set for each channel
Self-diagnostic function and analog input disconnection detection
assistance function
■ 12-bit D/A converter
• Two channels
■ Capacitive touch sensing unit
• Self-capacitance method: A single pin configures a single key,
supporting up to 24 keys
• Mutual capacitance method: Matrix configuration with 24 pins, supporting
up to 144 keys
■ Analog comparator
• Two channels × two units
■ General I/O ports
• 5-V tolerant, open drain, input pull-up, switching of driving capacity
■ Encryption Functions (TSIP-Lite)
• Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
• Safe management of keys
• 128- or 256-bit key length of AES for ECB, CBC, GCM, others
• True random number generator
■ Temperature sensor
■ Operating temperature range
• −40 to +85°C
• −40 to +105°C
■ Applications
• General industrial and consumer equipment
Page 1 of 170
RX230 Group, RX231 Group
1. Overview
1.
Overview
1.1
Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Outline of Specifications (1/4)
Classification
Module/Function
Description
CPU
CPU
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Memory
Maximum operating frequency: 54 MHz
32-bit RX CPU (RX v2)
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Ten 32-bit registers
Accumulator: Two 72-bit registers
Basic instructions: 75 (variable-length instruction format)
Floating-point instructions: 11
DSP instructions: 23
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
On-chip divider: 32-bit ÷ 32-bit → 32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
FPU
• Single precision (32-bit) floating point
• Data types and floating-point exceptions in conformance with the IEEE754 standard
ROM
• Capacity: 128/256/384/512 Kbytes
• Up to 32 MHz: No-wait memory access
32 to 54 MHz: Wait state required. No wait state if the instruction is served by a ROM accelerator hit.
• Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-programming
RAM
• Capacity: 32/64 Kbytes
• 54 MHz, no-wait memory access
E2 DataFlash
• Capacity: 8 Kbytes
• Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode
(software switching)
Clock
• Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip
oscillator
• Oscillation stop detection: Available
• Clock frequency accuracy measurement circuit (CAC)
• Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock
(BCLK), and FlashIF clock (FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 54 MHz (at max.)
MTU2a runs in synchronization with the PCLKA: 54 MHz (at max.)
The ADCLK for the S12AD runs in synchronization with the PCLKD: 54 MHz (at max.)
Peripheral modules other than MTU2a and S12ADE run in synchronization with the PCLKB: 32 MHz
(at max.)
Devices connected to external buses run in synchronization with the BCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
Clock generation circuit
Resets
Voltage detection
RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, and software reset
Voltage detection circuit
(LVDAb)
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
• When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Page 2 of 170
RX230 Group, RX231 Group
Table 1.1
1. Overview
Outline of Specifications (2/4)
Classification
Module/Function
Description
Low power
consumption
Low power consumption
functions
• Module stop function
• Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
• Low power timer that operates during the software standby state
Function for lower operating
power consumption
• Operating power control modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt controller (ICUb)
• Interrupt vectors: 167
• External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
• Non-maskable interrupts: 7 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, WDT interrupt, IWDT interrupt, and VBATT power monitoring
interrupt)
• 16 levels specifiable for the order of priority
Interrupt
External bus extension
• The external address space can be divided into four areas (CS0 to CS3), each with independent
control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8-bit or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
• Wait control
• Write buffer facility
DMA
DMA controller (DMACA)
• 4 channels
• Three transfer modes: Normal transfer, repeat transfer, and block transfer
• Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Data transfer controller
(DTCa)
• Transfer modes: Normal transfer, repeat transfer, and block transfer
• Activation sources: Interrupts
• Chain transfer function
General I/O ports
100-pin/64-pin/48-pin
I/O: 79/43/30 (RX231 Group), 83/47/34 (RX230 Group)
• Input: 1/1/1
Pull-up resistors: 79/43/30(RX231 Group), 83/47/34 (RX230 Group)
• Open-drain outputs: 58/34/26
• 5-V tolerance: 8/5/5
I/O ports
Event link controller (ELC)
• Event signals of 61 types can be directly connected to the module
• Operations of timer modules are selectable at event input
• Capable of event link operation for port B and port E
Multi-function pin controller (MPC)
Capable of selecting the input/output function from multiple pins
Timers
•
•
•
•
•
•
16-bit timer pulse unit
(TPUa)
(16 bits × 6 channels) × 1 unit
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Supports the input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade
connected operation (32 bits × 2 channels) depending on the channel.
• Capable of generating conversion start triggers for the A/D converters
• Signals from the input capture pins are input via a digital filter
• Clock frequency measuring method
Multi-function timer pulse
unit 2 (MTU2a)
• (16 bits × 6 channels) × 1 unit
• Up to 16 pulse-input/output lines and three pulse-input lines are available based on the six 16-bit
timer channels
• Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
• Input capture function
• 21 output compare/input capture registers
• Pulse output mode
• Complementary PWM output mode
• Reset synchronous PWM mode
• Phase-counting mode
• Capable of generating conversion start triggers for the A/D converter
Port output enable 2
(POE2a)
Controls the high-impedance state of the MTU’s waveform output pins
Compare match timer
(CMT)
• (16 bits × 2 channels) × 2 units
• Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
Watchdog timer (WDTA)
• 14 bits x 1 channel
• Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/
2048, PCLK/8192)
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 3 of 170
RX230 Group, RX231 Group
Table 1.1
1. Overview
Outline of Specifications (3/4)
Classification
Module/Function
Description
Timers
Independent watchdog
timer (IWDTa)
• 14 bits × 1 channel
• Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Realtime clock (RTCe)
•
•
•
•
Low power timer (LPT)
• 16 bits × 1 channel
• Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 2, 4, 8, 16, or 32
8-bit timer (TMR)
• (8 bits × 2 channels) × 2 units
• Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
• Pulse output and PWM output with any duty cycle are available
• Two channels can be cascaded and used as a 16-bit timer
Serial communications
interfaces (SCIg, SCIh)
• 7 channels (channel 0, 1, 5, 6, 8, 9: SCIg, channel 12: SCIh)
• SCIg
Serial communications modes: Asynchronous, clock synchronous, and smart-card interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
9-bit transfer mode
Bit rate modulation
Event linking by the ELC (only on channel 5)
• SCIh (The following functions are added to SCIg)
Supports the serial communications protocol, which contains the start frame and information frame
Supports the LIN format
IrDA interface (IRDA)
• 1 channel (SCI5 used)
• Supports encoding/decoding of waveforms conforming to IrDA standard 1.0
I2C bus interface (RIICa)
•
•
•
•
Serial peripheral interface
(RSPIa)
• 1 channel
• Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK
(RSPI clock) enables serial transfer through SPI operation (four lines) or clock-synchronous
operation (three lines)
• Capable of handling serial transfer as a master or slave
• Data formats
• Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
• Double buffers for both transmission and reception
USB 2.0 host/function
module (USBd)
•
•
•
•
•
•
•
•
CAN module (RSCAN)
• 1 channel
• Compliance with the ISO11898-1 specification (standard frame and extended frame)
• 16 Message boxes
Communication
functions
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Clock source: Sub-clock
Time/calendar
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
Time-capture facility for three values
1 channel
Communications formats: I2C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.
Host/function module: 1 port
Compliant with USB version 2.0
Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)
OTG (ON-The-Go) is supported.
Isochronous transfer is supported.
BC1.2 (Battery Charging Specification Revision 1.2) is supported.
Internal power supply for USB (allows operation without external power input to the VCC_USB pin
when VCC = 4.0 to 5.5V)
Page 4 of 170
RX230 Group, RX231 Group
Table 1.1
1. Overview
Outline of Specifications (4/4)
Classification
Module/Function
Description
Communication
Serial Sound Interface (SSI)
•
•
•
•
•
•
•
•
SD Host Interface (SDHIa)
•
•
•
•
•
functions
1 channel
Capable of duplex communications
Various serial audio formats supported
Master/slave function supported
Programmable word clock or bit clock generation function
8/16/18/20/22/24/32-bit data formats supported
On-chip 8-stage FIFO for transmission/reception
Supports WS continue mode in which the SSIWS signal is not stopped.
1 channel
Transfer speed : Default speed mode (8MB/s)
SD memory card interface (1 bit / 4bits SD bus)
MMC, eMMC Backward-compatible are supported.
SD Specifications
Part 1: Compliant with Physical Layer Specification Ver.3.01 (Not support DDR)
Part E1: SDIO Specification Ver. 3.00
• Error check function: CRC7 (command), CRC16 (data)
• Interrupt Source: Card access interrupt, SDIO access interrupt, Card detection interrupt, SD buffer
access interrupt
• DMA transfer sources: SD_BUF write, SD_BUF read
• Card detection, Write protection
Encryption
functions
Trusted Secure IP (TSIPLite)
12-bit A/D converter (S12ADE)
• Access management circuit
• Encryption engine
128- or 256-bit key sizes of AES
Block cipher mode of operation: GCM, ECB, CBC, CMAC, XTS, CTR, GCTR
• Hash function
• True random number generator
• Prevention from illicit copying of a key
•
•
•
•
•
•
•
•
•
•
12 bits (24 channels × 1 unit)
12-bit resolution
Minimum conversion time: 0.83 µs per channel when the ADCLK is operating at 54 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Group A priority control (only for group scan mode)
Sampling variable
Sampling time can be set up for each channel.
Self-diagnostic function
Double trigger mode (A/D conversion data duplicated)
Detection of analog input disconnection
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU, TPU), an external trigger signal, or ELC
Event linking by the ELC
Temperature sensor (TEMPSA)
• 1 channel
• The voltage output from the temperature sensor is converted into a digital value by the 12-bit A/D
converter.
12-bit D/A converter (R12DAA)
• 2 channels
• 12-bit resolution
• Output voltage: 0.4 to AVCC0-0.5V
CRC calculator (CRC)
• CRC code generation for arbitrary amounts of data in 8-bit units
• Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
• Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Comparator B (CMPBa)
• 2 channels × 2 units
• Function to compare the reference voltage and the analog input voltage
• Window comparator operation or standard comparator operation is selectable
Capacitive touch sensing unit (CTSU)
Detection pin: 24 channels
Data operation circuit (DOC)
Comparison, addition, and subtraction of 16-bit data
Power supply voltages/Operating frequencies
VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 5.5 V: 54 MHz
Operating temperature range
D version: −40 to +85°C, G version: −40 to +105°C
Packages
100-pin TFLGA (PTLG0100KA-A) 5.5 × 5.5 mm, 0.5 mm pitch
100-pin LFQFP (PLQP0100KB-B) 14 × 14 mm, 0.5 mm pitch
64-pin WFLGA (PWLG0064KA-A) 5 × 5 mm, 0.5 mm pitch
64-pin HWQFN (PWQN0064KC-A) 9 × 9 mm, 0.5 mm pitch
64-pin LFQFP (PLQP0064KB-C) 10 × 10 mm, 0.5 mm pitch
48-pin HWQFN (PWQN0048KB-A) 7 × 7 mm, 0.5 mm pitch
48-pin LFQFP (PLQP0048KB-B) 7 × 7 mm, 0.5 mm pitch
Debugging interfaces
FINE interface
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 5 of 170
RX230 Group, RX231 Group
Table 1.2
1. Overview
Comparison of Functions for Different Packages
RX230 Group
Module/Functions
External bus
External bus
Interrupts
External interrupts
DMA
DMA controller
100 Pins
16 bit
NMI, IRQ0
to IRQ7
NMI, IRQ0,
IRQ1, IRQ4
to IRQ7
NMI, IRQ0,
IRQ1, IRQ4
to IRQ7
100 Pins
64 Pins
16 bit
48 Pins
Not supported
NMI, IRQ0
to IRQ7
NMI, IRQ0,
IRQ1, IRQ4
to IRQ7
NMI, IRQ0,
IRQ1, IRQ4
to IRQ7
4 channels (DMAC0 to DMAC3)
4 channels (DMAC0 to DMAC3)
Available
Available
16-bit timer pulse unit
6 channels (TPU0 to TPU5)
6 channels (TPU0 to TPU5)
Multi-function timer pulse unit 2
6 channels (MTU0 to MTU5)
6 channels (MTU0 to MTU5)
POE0# to POE3#, POE8#
POE0# to POE3#, POE8#
8-bit timer
2 channels× 2 units
2 channels× 2 units
Compare match timer
2 channels× 2 units
2 channels× 2 units
1 channel
1 channel
Port output enable 2
Low power timer
Realtime clock
Communication
functions
48 Pins
Not supported
Data transfer controller
Timers
RX231 Group
64 Pins
Available
Not
supported
Available
Watchdog timer
Available
Available
Independent watchdog timer
Available
Available
Serial communications
interfaces (SCIg)
6 channels
(SCI0, 1, 5,
6, 8, 9)
5 channels
(SCI1, 5, 6,
8, 9)
4 channels
(SCI1, 5, 6,
8)
6 channels
(SCI0, 1, 5,
6, 8, 9)
Not
supported
5 channels
(SCI1, 5, 6,
8, 9)
4 channels
(SCI1, 5, 6,
8)
IrDA interface
1 channel (SCI5)
1 channel (SCI5)
Serial communications
interfaces (SCIh)
1 channel (SCI12)
1 channel (SCI12)
1 channel
1 channel
Not supported
1 channel*1
I2C bus interface
CAN module
Serial peripheral interface
USB 2.0 host/function module
Serial sound interface
SD Host Interface
1 channel
1 channel
Not supported
1 channel
1 channel
1 channel
Not supported
1 channel*1
Not
supported
Capacitive touch sensing unit
24 channels 10 channels
6 channels
24 channels 10 channels
6 channels
12-bit A/D converter
(including high-precision channels)
24 channels 12 channels
(8
(6
channels)
channels)
8 channels
(4
channels)
24 channels 12 channels
(8
(6
channels)
channels)
8 channels
(4
channels)
Temperature sensor
D/A converter
Available
2 channels
CRC calculator
Not
supported
2 channels
Available
Event link controller
Comparator B
Packages
Available
100-pin
TFLGA
100-pin
LFQFP
Available
Available
Available
4 channels
4 channels
64-pin
WFLGA
64-pin
HWQFN
64-pin
LFQFP
Not
supported
48-pin
HWQFN
48-pin
LFQFP
100-pin
TFLGA
100-pin
LFQFP
64-pin
WFLGA
64-pin
HWQFN
64-pin
LFQFP
48-pin
HWQFN
48-pin
LFQFP
Note 1. Only for chip version B
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 6 of 170
RX230 Group, RX231 Group
1.2
1. Overview
List of Products
Table 1.3 and Table 1.4 are a list of products, and Figure 1.1 shows how to read the product part no., memory capacity,
and package type.
Table 1.3
List of Products: D Version (Ta = –40 to +85°C) (1/2)
Group
Part No.
Order Part No.
Package
ROM
Capacity
RAM
Capacity
E2
DataFlash
Operating
Frequency
Security
Function
SDHI
CAN
Operating
Temperature
RX231
R5F52318ADLA
R5F52318ADLA#20
PTLG0100KA-A
512 Kbytes
64 Kbytes
8 Kbytes
54 MHz
Not
available
Not
available
Available
−40 to +85°C
R5F52318BDLA
R5F52318BDLA#20
R5F52318ADFP
R5F52318ADFP#30
R5F52318BDFP
R5F52318BDFP#30
R5F52318ADND
R5F52318ADND#U0
R5F52318BDND
R5F52318BDND#U0
R5F52318ADFM
R5F52318ADFM#30
R5F52318BDFM
R5F52318BDFM#30
R5F52318ADNE
R5F52318ADNE#U0
R5F52318BDNE
R5F52318BDNE#U0
R5F52318ADFL
R5F52318ADFL#30
R5F52318BDFL
R5F52318BDFL#30
R5F52317ADLA
R5F52317ADLA#20
R5F52317BDLA
R5F52317BDLA#20
R5F52317ADFP
R5F52317ADFP#30
R5F52317BDFP
R5F52317BDFP#30
R5F52317ADND
R5F52317ADND#U0
R5F52317BDND
R5F52317BDND#U0
R5F52317ADFM
R5F52317ADFM#30
Available
Available
Available
PLQP0100KB-B
Not
available
Not
available
Available
Available
Available
Available
PWQN0064KC-A
Not
available
Not
available
Available
Available
Available
Available
PLQP0064KB-C
Not
available
Not
available
Available
Available
Available
Available
PWQN0048KB-A
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
PLQP0048KB-B
PTLG0100KA-A
384 Kbytes
Available
Available
Available
PLQP0100KB-B
Not
available
Not
available
Available
Available
Available
Available
PWQN0064KC-A
Not
available
Not
available
Available
Available
Available
Available
PLQP0064KB-C
Not
available
Not
available
Available
Available
Available
Available
PWQN0048KB-A
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
R5F52317BDFM
R5F52317BDFM#30
R5F52317ADNE
R5F52317ADNE#U0
R5F52317BDNE
R5F52317BDNE#U0
R5F52317ADFL
R5F52317ADFL#30
R5F52317BDFL
R5F52317BDFL#30
R5F52316ADLA
R5F52316ADLA#20
R5F52316CDLA
R5F52316CDLA#20
R5F52316ADFP
R5F52316ADFP#30
R5F52316CDFP
R5F52316CDFP#30
R5F52316CDLF
R5F52316CDLF#U0
PWLG0064KA-A
Not
available
Not
available
Not
available
R5F52316ADND
R5F52316ADND#U0
PWQN0064KC-A
Not
available
Not
available
Available
R5F52316CDND
R5F52316CDND#U0
Not
available
Not
available
Not
available
R5F52316ADFM
R5F52316ADFM#30
Not
available
Not
available
Available
R5F52316CDFM
R5F52316CDFM#30
Not
available
Not
available
Not
available
R5F52316ADNE
R5F52316ADNE#U0
Not
available
Not
available
Available
R5F52316CDNE
R5F52316CDNE#U0
Not
available
Not
available
Not
available
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
PLQP0048KB-B
PTLG0100KA-A
PLQP0100KB-B
PLQP0064KB-C
PWQN0048KB-A
256 Kbytes
32 Kbytes
Page 7 of 170
RX230 Group, RX231 Group
Table 1.3
1. Overview
List of Products: D Version (Ta = –40 to +85°C) (2/2)
Group
Part No.
Order Part No.
Package
ROM
Capacity
RAM
Capacity
E2
DataFlash
Operating
Frequency
Security
Function
SDHI
CAN
Operating
Temperature
RX231
R5F52316ADFL
R5F52316ADFL#30
PLQP0048KB-B
256 Kbytes
32 Kbytes
8 Kbytes
54 MHz
Not
available
Not
available
Available
−40 to +85°C
R5F52316CDFL
R5F52316CDFL#30
Not
available
Not
available
Not
available
R5F52315ADLA
R5F52315ADLA#20
Not
available
Not
available
Available
R5F52315CDLA
R5F52315CDLA#20
Not
available
Not
available
Not
available
R5F52315ADFP
R5F52315ADFP#30
Not
available
Not
available
Available
R5F52315CDFP
R5F52315CDFP#30
Not
available
Not
available
Not
available
R5F52315CDLF
R5F52315CDLF#20
PWLG0064KA-A
Not
available
Not
available
Not
available
R5F52315ADND
R5F52315ADND#U0
PWQN0064KC-A
Not
available
Not
available
Available
R5F52315CDND
R5F52315CDND#U0
Not
available
Not
available
Not
available
R5F52315ADFM
R5F52315ADFM#30
Not
available
Not
available
Available
R5F52315CDFM
R5F52315CDFM#30
Not
available
Not
available
Not
available
R5F52315ADNE
R5F52315ADNE#U0
Not
available
Not
available
Available
R5F52315CDNE
R5F52315CDNE#U0
Not
available
Not
available
Not
available
R5F52315ADFL
R5F52315ADFL#30
Not
available
Not
available
Available
R5F52315CDFL
R5F52315CDFL#30
Not
available
Not
available
Not
available
R5F52306ADLA
R5F52306ADLA#20
PTLG0100KA-A
Not
available
Not
available
Not
available
R5F52306ADFP
R5F52306ADFP#30
PLQP0100KB-B
Not
available
Not
available
Not
available
R5F52306ADLF
R5F52306ADLF#20
PWLG0064KA-A
Not
available
Not
available
Not
available
R5F52306ADND
R5F52306ADND#U0
PWQN0064KC-A
Not
available
Not
available
Not
available
R5F52306ADFM
R5F52306ADFM#30
PLQP0064KB-C
Not
available
Not
available
Not
available
R5F52306ADNE
R5F52306ADNE#U0
PWQN0048KB-A
Not
available
Not
available
Not
available
R5F52306ADFL
R5F52306ADFL#30
PLQP0048KB-B
Not
available
Not
available
Not
available
R5F52305ADLA
R5F52305ADLA#20
PTLG0100KA-A
Not
available
Not
available
Not
available
R5F52305ADFP
R5F52305ADFP#30
PLQP0100KB-B
Not
available
Not
available
Not
available
R5F52305ADLF
R5F52305ADLF#20
PWLG0064KA-A
Not
available
Not
available
Not
available
R5F52305ADND
R5F52305ADND#U0
PWQN0064KC-A
Not
available
Not
available
Not
available
R5F52305ADFM
R5F52305ADFM#30
PLQP0064KB-C
Not
available
Not
available
Not
available
R5F52305ADNE
R5F52305ADNE#U0
PWQN0048KB-A
Not
available
Not
available
Not
available
R5F52305ADFL
R5F52305ADFL#30
PLQP0048KB-B
Not
available
Not
available
Not
available
RX230
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
PTLG0100KA-A
128 Kbytes
32 Kbytes
8 Kbytes
54 MHz
PLQP0100KB-B
PLQP0064KB-C
PWQN0048KB-A
PLQP0048KB-B
256 Kbytes
128 Kbytes
32 Kbytes
8 Kbytes
54 MHz
−40 to +85°C
−40 to +85°C
Page 8 of 170
RX230 Group, RX231 Group
Table 1.4
1. Overview
List of Products: G Version (Ta = –40 to +105°C) (1/2)
Group
Part No.
Order Part No.
Package
ROM
Capacity
RAM
Capacity
E2
DataFlash
Operating
Frequency
Security
Function
SDHI
CAN
RX231
R5F52318AGFP
R5F52318AGFP#30
PLQP0100KB-B
512 Kbytes
64 Kbytes
8 Kbytes
54 MHz
Not
available
Not
available
Available
R5F52318BGFP
R5F52318BGFP#30
R5F52318AGND
R5F52318AGND#U0
R5F52318BGND
R5F52318BGND#U0
R5F52318AGFM
R5F52318AGFM#30
R5F52318BGFM
R5F52318BGFM#30
R5F52318AGNE
R5F52318AGNE#U0
R5F52318BGNE
R5F52318BGNE#U0
R5F52318AGFL
R5F52318AGFL#30
R5F52318BGFL
R5F52318BGFL#30
R5F52317AGFP
R5F52317AGFP#30
R5F52317BGFP
R5F52317BGFP#30
R5F52317AGND
R5F52317AGND#U0
R5F52317BGND
R5F52317BGND#U0
R5F52317AGFM
R5F52317AGFM#30
R5F52317BGFM
R5F52317BGFM#30
R5F52317AGNE
R5F52317AGNE#U0
R5F52317BGNE
R5F52317BGNE#U0
R5F52317AGFL
R5F52317AGFL#30
R5F52317BGFL
R5F52317BGFL#30
R5F52316AGFP
R5F52316AGFP#30
R5F52316CGFP
R5F52316CGFP#30
R5F52316AGND
R5F52316AGND#U0
R5F52316CGND
R5F52316CGND#U0
R5F52316AGFM
R5F52316AGFM#30
R5F52316CGFM
R5F52316CGFM#30
R5F52316AGNE
R5F52316AGNE#U0
R5F52316CGNE
R5F52316CGNE#U0
R5F52316AGFL
R5F52316AGFL#30
R5F52316CGFL
R5F52316CGFL#30
R5F52315AGFP
R5F52315AGFP#30
R5F52315CGFP
R5F52315CGFP#30
R5F52315AGND
R5F52315AGND#U0
R5F52315CGND
R5F52315CGND#U0
R5F52315AGFM
R5F52315AGFM#30
R5F52315CGFM
R5F52315CGFM#30
R5F52315AGNE
R5F52315AGNE#U0
R5F52315CGNE
R5F52315CGNE#U0
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Operating
Temperature
Available
Available
Available
PWQN0064KC-A
Not
available
Not
available
Available
Available
Available
Available
PLQP0064KB-C
Not
available
Not
available
Available
Available
Available
Available
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
PWQN0048KB-A
PLQP0048KB-B
PLQP0100KB-B
384 Kbytes
Available
Available
Available
PWQN0064KC-A
Not
available
Not
available
Available
Available
Available
Available
PLQP0064KB-C
Not
available
Not
available
Available
Available
Available
Available
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
Available
Not
available
Available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
Not
available
Not
available
Available
Not
available
Not
available
Not
available
PWQN0048KB-A
PLQP0048KB-B
PLQP0100KB-B
256 Kbytes
PWQN0064KC-A
PLQP0064KB-C
PWQN0048KB-A
PLQP0048KB-B
PLQP0100KB-B
PWQN0064KC-A
PLQP0064KB-C
PWQN0048KB-A
128 Kbytes
32 Kbytes
−40 to
+105°C
Page 9 of 170
RX230 Group, RX231 Group
Table 1.4
1. Overview
List of Products: G Version (Ta = –40 to +105°C) (2/2)
Group
Part No.
Order Part No.
Package
ROM
Capacity
RAM
Capacity
E2
DataFlash
Operating
Frequency
Security
Function
SDHI
CAN
RX231
R5F52315AGFL
R5F52315AGFL#30
PLQP0048KB-B
128 Kbytes
32 Kbytes
8 Kbytes
54 MHz
Not
available
Not
available
Available
R5F52315CGFL
R5F52315CGFL#30
Not
available
Not
available
Not
available
R5F52306AGFP
R5F52306AGFP#30
PLQP0100KB-B
Not
available
Not
available
Not
available
R5F52306AGND
R5F52306AGND#U0
PWQN0064KC-A
Not
available
Not
available
Not
available
R5F52306AGFM
R5F52306AGFM#30
PLQP0064KB-C
Not
available
Not
available
Not
available
R5F52306AGNE
R5F52306AGNE#U0
PWQN0048KB-A
Not
available
Not
available
Not
available
R5F52306AGFL
R5F52306AGFL#30
PLQP0048KB-B
Not
available
Not
available
Not
available
R5F52305AGFP
R5F52305AGFP#30
PLQP0100KB-B
Not
available
Not
available
Not
available
R5F52305AGND
R5F52305AGND#U0
PWQN0064KC-A
Not
available
Not
available
Not
available
R5F52305AGFM
R5F52305AGFM#30
PLQP0064KB-C
Not
available
Not
available
Not
available
R5F52305AGNE
R5F52305AGNE#U0
PWQN0048KB-A
Not
available
Not
available
Not
available
R5F52305AGFL
R5F52305AGFL#30
PLQP0048KB-B
Not
available
Not
available
Not
available
RX230
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
256 Kbytes
128 Kbytes
32 Kbytes
8 Kbytes
54 MHz
Operating
Temperature
−40 to
+105°C
−40 to
+105°C
Page 10 of 170
RX230 Group, RX231 Group
R
5
F
5
2 3
1. Overview
1
8
A
D
F M
Package type, number of pins, and pin pitch
FP: LFQFP/100/0.50
FM: LFQFP/64/0.50
FL: LFQFP/48/0.50
LA: TFLGA/100/0.50
LF: WFLGA/64/0.50
ND: HWQFN/64/0.50
NE: HWQFN/48/0.50
D: Operating ambient temperature: –40 to +85°C
G: Operating ambient temperature: –40 to +105°C
Chip versions
RX231 Group
A: Security function not included, SDHI module not
included, CAN module included
B: Security function included, SDHI module included
(except 48-pin package products), CAN module
included
C: Security function not included, SDHI module not
included, CAN module not included
RX230 Group
A: USB module not included
ROM, RAM, and E2 DataFlash capacity
8: 512 Kbytes/64 Kbytes/8 Kbytes
7: 384 Kbyte/64 Kbytes/8 Kbytes
6: 256 Kbytes/32 Kbytes/8 Kbytes
5: 128 Kbytes/32 Kbytes/8 Kbytes
Group name
31: RX231 Group
30: RX230 Group
Series name
RX200 Series
Type of memory
F: Flash memory version
Renesas MCU
Renesas semiconductor product
Figure 1.1
How to Read the Product Part Number
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 11 of 170
RX230 Group, RX231 Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram.
SDHIa
E2 DataFlash
RSCAN
WDTA
CTSU
IWDTa
LPT
ELC
CRC
SCIg × 6 channels
(including IrDA × 1 channel)
SCIh × 1 channel
RSPIa × 1 channel
RIICa × 1 channel
Internal peripheral buses 1 to 6
SSI
MPU
Clock
generation
circuit
Internal main bus 1
RX CPU
Internal main bus 2
DTCa
Operand bus
Instruction bus
RAM
Figure 1.2
TPUa × 6 channels
MTU2a × 6 channels
POE2a
TMR × 2 channels (unit 0)
ICUb
ROM
ICUb:
DTCa:
DMACA:
BSC:
WDTA:
IWDTa:
ELC:
CRC:
SCIg/SCIh:
RSPIa:
SSI:
RIICa:
TPUa:
USB 2.0 host/function module
Interrupt controller
Data transfer controller
DMA controller
Bus controller
Watchdog timer
Independent watchdog timer
Event link controller
CRC (cyclic redundancy check) calculator
Serial communications interface
Serial peripheral interface
Serial sound interface
I2C bus interface
16-bit timer pulse unit
TMR × 2 channels (unit 1)
Port 1
CMT × 2 channels (unit 0)
Port 2
CMT × 2 channels (unit 1)
Port 3
RTCe
Port 4
12-bit A/D converter × 24 channels
Temperature sensor
DMACA
× 4 channels
Port 0
Port 5
Port A
12-bit D/A converter × 2 channels
DOC
Comparator B × 4 channels
CAC
Port B
Port C
Port D
Port E
Port H
BSC
MTU2a:
POE2a:
CMT:
RTCe:
DOC:
CAC:
CTSU:
SDHIa:
MPU:
TMR:
RSCAN:
LPT:
External bus
Port J
Multi-function timer pulse unit 2
Port output enable 2
Compare match timer
Realtime clock
Data operation circuit
Clock frequency accuracy measurement circuit
Capacitive touch sensing unit
SD host interface
Memory protection unit
8-bit timer
CAN module
Low power timer
Block Diagram
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 12 of 170
RX230 Group, RX231 Group
1.4
1. Overview
Pin Functions
Table 1.5 lists the pin functions.
Table 1.5
Pin Functions (1/4)
Classifications
Pin Name
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply.
VCL
—
Connect this pin to the VSS pin via a 4.7 μF smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
VBATT
Input
Backup power pin
XTAL
Output
EXTAL
Input
Pins for connecting a crystal. An external clock can be input through the
EXTAL pin.
BCLK
Output
Outputs the external bus clock for external devices.
Input/output pins for the sub-clock oscillator. Connect a crystal between
XCIN and XCOUT.
Clock
Operating mode
control
XCIN
Input
XCOUT
Output
CLKOUT
Output
Clock output pin.
MD
Input
Pin for setting the operating mode. The signal levels on this pin must not
be changed during operation.
UB
Input
Pin used for boot mode (USB interface).
UPSEL
Input
Pin used for boot mode (USB interface).
System control
RES#
Input
Reset pin. This MCU enters the reset state when this signal goes low.
CAC
CACREF
Input
Input pin for the clock frequency accuracy measurement circuit.
On-chip
emulator
FINED
I/O
FINE interface pin.
Address bus
A0 to A23
Output
Output pins for the address.
Data bus
D0 to D15
I/O
Input and output pins for the bidirectional data bus.
Multiplexed bus
A0/D0 to A15/D15
I/O
Address/data multiplexed bus
Bus control
RD#
Output
Strobe signal which indicates that reading from the external bus interface
space is in progress.
WR#
Output
Strobe signal which indicates that writing to the external bus interface
space is in progress, in single-write strobe mode.
WR0#, WR1#
Output
Strobe signals which indicate that either group of data bus pins (D7 to D0,
and D15 to D8) is valid in writing to the external bus interface space, in
byte strobe mode.
BC0#, BC1#
Output
Strobe signals which indicate that either group of data bus pins (D7 to D0
and D15 to D8) is valid in access to the external bus interface space, in
single-write strobe mode.
CS0# to CS3#
Output
Select signals for areas 0 to 3.
WAIT#
Input
Input pin for wait request signals in access to the external space.
ALE
Output
Address latch signal when address/data multiplexed bus is selected.
LVD
CMPA2
Input
Detection target voltage pin for voltage detection 2.
Interrupts
NMI
Input
Non-maskable interrupt request pin.
IRQ0 to IRQ7
Input
Interrupt request pins.
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 13 of 170
RX230 Group, RX231 Group
Table 1.5
1. Overview
Pin Functions (2/4)
Classifications
Pin Name
I/O
Description
16-bit timer
pulse unit
TIOCA0, TIOCB0
TIOCC0, TIOCD0
I/O
The TGRA0 to TGRD0 input capture input/output compare output/PWM
output pins.
TIOCA1, TIOCB1
I/O
The TGRA1 and TGRB1 input capture input/output compare output/PWM
output pins.
TIOCA2, TIOCB2
I/O
The TGRA2 and TGRB2 input capture input/output compare output/PWM
output pins.
TIOCA3, TIOCB3
TIOCC3, TIOCD3
I/O
The TGRA3 to TGRD3 input capture input/output compare output/PWM
output pins.
TIOCA4, TIOCB4
I/O
The TGRA4 and TGRB4 input capture input/output compare output/PWM
output pins.
TIOCA5, TIOCB5
I/O
The TGRA5 and TGRB5 input capture input/output compare output/PWM
output pins.
TCLKA, TCLKB
TCLKC, TCLKD
Input
Input pins for external clock signals.
Multi-function
MTIOC0A, MTIOC0B
timer pulse unit 2 MTIOC0C, MTIOC0D
I/O
The TGRA0 to TGRD0 input capture input/output compare output/PWM
output pins.
MTIOC1A, MTIOC1B
I/O
The TGRA1 and TGRB1 input capture input/output compare output/PWM
output pins.
MTIOC2A, MTIOC2B
I/O
The TGRA2 and TGRB2 input capture input/output compare output/PWM
output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D
I/O
The TGRA3 to TGRD3 input capture input/output compare output/PWM
output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D
I/O
The TGRA4 to TGRD4 input capture input/output compare output/PWM
output pins.
MTIC5U, MTIC5V, MTIC5W
Input
The TGRU5, TGRV5, and TGRW5 input capture input/external pulse input
pins.
MTCLKA, MTCLKB,
MTCLKC, MTCLKD
Input
Input pins for the external clock.
POE0# to POE3#, POE8#
Input
Input pins for request signals to place the MTU pins in the high impedance
state.
Port output
enable 2
Realtime clock
8-bit timer
Serial
communications
interface (SCIg)
RTCOUT
Output
Output pin for the 1-Hz/64-Hz clock.
RTCIC0 to RTCIC2
Input
Time capture event input pins.
TMO0 to TMO3
Output
Compare match output pins.
TMCI0 to TMCI3
Input
Input pins for the external clock to be input to the counter.
TMRI0 to TMRI3
Input
Counter reset input pins.
• Asynchronous mode/clock synchronous mode
SCK0, SCK1, SCK5, SCK6,
SCK8, SCK9
I/O
Input/output pins for the clock.
RXD0, RXD1, RXD5, RXD6,
RXD8, RXD9
Input
Input pins for received data.
TXD0, TXD1, TXD5, TXD6,
TXD8, TXD9
Output
Output pins for transmitted data.
CTS0#, CTS1#, CTS5#,
CTS6#, CTS8#, CTS9#
Input
Input pins for controlling the start of transmission and reception.
RTS0#, RTS1#, RTS5#,
RTS6#, RTS8#, RTS9#
Output
Output pins for controlling the start of transmission and reception.
SSCL0, SSCL1, SSCL5,
SSCL6, SSCL8, SSCL9
I/O
Input/output pins for the I2C clock.
SSDA0, SSDA1, SSDA5,
SSDA6, SSDA8, SSDA9
I/O
Input/output pins for the I2C data.
• Simple I2C mode
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 14 of 170
RX230 Group, RX231 Group
Table 1.5
1. Overview
Pin Functions (3/4)
Classifications
Pin Name
Serial
communications
interface (SCIg)
• Simple SPI mode
IrDA interface
Serial
communications
interface (SCIh)
I/O
Description
SCK0, SCK1, SCK5, SCK6,
SCK8, SCK9
I/O
Input/output pins for the clock.
SMISO0, SMISO1, SMISO5,
SMISO6, SMISO8, SMISO9
I/O
Input/output pins for slave transmit data.
SMOSI0, SMOSI1, SMOSI5,
SMOSI6, SMOSI8, SMOSI9
I/O
Input/output pins for master transmit data.
SS0#, SS1#, SS5#, SS6#,
SS8#, SS9#
Input
Slave-select input pins.
IRTXD5
Output
Data output pin in the IrDA format.
IRRXD5
Input
Data input pin in the IrDA format.
• Asynchronous mode/clock synchronous mode
SCK12
I/O
Input/output pin for the clock.
RXD12
Input
Input pin for receiving data.
TXD12
Output
Output pin for transmitting data.
CTS12#
Input
Input pin for controlling the start of transmission and reception.
RTS12#
Output
Output pin for controlling the start of transmission and reception.
SSCL12
I/O
Input/output pin for the I2C clock.
SSDA12
I/O
Input/output pin for the I2C data.
• Simple I2C mode
• Simple SPI mode
SCK12
I/O
Input/output pin for the clock.
SMISO12
I/O
Input/output pin for slave transmit data.
SMOSI12
I/O
Input/output pin for master transmit data.
SS12#
Input
Slave-select input pin.
• Extended serial mode
I2 C
bus interface
Serial peripheral
interface
RXDX12
Input
Input pin for data reception by SCIf.
TXDX12
Output
Output pin for data transmission by SCIf.
SIOX12
I/O
Input/output pin for data reception or transmission by SCIf.
SCL
I/O
Input/output pin for I2C bus interface clocks. Bus can be directly driven by
the N-channel open drain output.
SDA
I/O
Input/output pin for I2C bus interface data. Bus can be directly driven by
the N-channel open drain output.
RSPCKA
I/O
Input/output pin for the RSPI clock.
MOSIA
I/O
Input/output pin for transmitting data from the RSPI master.
MISOA
I/O
Input/output pin for transmitting data from the RSPI slave.
SSLA0
I/O
Input/output pin to select the slave for the RSPI.
SSLA1 to SSLA3
Output
Output pins to select the slave for the RSPI.
SSISCK0
I/O
SSI serial bit clock pin.
SSIWS0
I/O
Word selection pin.
SSITXD0
Output
Serial data output pin.
SSIRXD0
Input
Serial data input pin.
AUDIO_MCLK
Input
Master clock pin for audio.
CAN module
CRXD0
Input
Input pin
CTXD0
Output
Output pin
SD host
interface
SDHI_CLK
Output
SD clock output pin
SDHI_CMD
I/O
SD command output, response input signal pin
Serial sound
interface
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 15 of 170
RX230 Group, RX231 Group
Table 1.5
1. Overview
Pin Functions (4/4)
Classifications
Pin Name
I/O
Description
SD host
interface
SDHI_D3 to SD_D0
I/O
SD data bus pins
USB 2.0 host/
function module
12-bit A/D
converter
12-bit D/A
converter
Comparator B
CTSU
Analog power
supply
I/O ports
SDHI_CD
Input
SD card detection pin
SDHI_WP
Input
SD write-protect signal
VCC_USB
Input
Power supply pin for USB. Connect this pin to VCC or connect this pin to
VSS via a 0.33 µF smoothing capacitor for stabilizing the internal power
supply.
VSS_USB
Input
Ground pin for USB. Connect this pin to VSS.
USB0_DP
I/O
D+ I/O pin of the USB on-chip transceiver.
USB0_DM
I/O
D- I/O pin of the USB on-chip transceiver.
USB0_VBUS
Input
USB cable connection monitor pin.
USB0_EXICEN
Output
Low-power control signal for the OTG chip.
USB0_VBUSEN
Output
VBUS (5 V) supply enable signal for the OTG chip.
USB0_OVRCURA,
USB0_OVRCURB
Input
External overcurrent detection pins.
USB0_ID
Input
Mini-AB connector ID input pin during operation in OTG mode.
AN000 to AN007, AN016 to
AN031
Input
Input pins for the analog signals to be processed by the A/D converter.
ADTRG0#
Input
Input pin for the external trigger signal that start the A/D conversion.
DA0, DA1
Output
Analog output pins of the D/A converter.
CMPB0 to CMPB3
Input
Input pin for the analog signal to be processed by comparator B.
CVREFB0 to CVREFB3
Input
Analog reference voltage supply pin for comparator B.
CMPOB0 to CMPOB3
Output
Output pin for comparator B.
TS0 to TS9, TS12, TS13,
TS15 to TS20, TS22, TS23,
TS27, TS30, TS33, TS35
Output
Electrostatic capacitance measurement pins (touch pins).
TSCAP
Output
LPF connection pin.
AVCC0
Input
Analog voltage supply pin for the 12-bit A/D converter and D/A converter.
Connect this pin to VCC when not using the 12-bit A/D converter and D/A
converter.
AVSS0
Input
Analog ground pin for the 12-bit A/D converter and D/A converter. Connect
this pin to VSS when not using the 12-bit A/D converter and D/A converter.
VREFH0
Input
Analog reference voltage supply pin for the 12-bit A/D converter.
VREFL0
Input
Analog reference ground pin for the 12-bit A/D converter.
VREFH
Input
Analog reference voltage supply pin for the 12-bit D/A converter.
VREFL
Input
Analog reference ground pin for the 12-bit D/A converter.
P03, P05, P07
I/O
3-bit input/output pins.
P12 to P17
I/O
6-bit input/output pins.
P20 to P27
I/O
8-bit input/output pins.
P30 to P37
I/O
8-bit input/output pins (P35 input pin).
P40 to P47
I/O
8-bit input/output pins.
P50 to P55
I/O
6-bit input/output pins.
PA0 to PA7
I/O
8-bit input/output pins.
PB0 to PB7
I/O
8-bit input/output pins.
PC0 to PC7
I/O
8-bit input/output pins.
PD0 to PD7
I/O
8-bit input/output pins.
PE0 to PE7
I/O
8-bit input/output pins.
PH0 to PH3
I/O
4-bit input/output pins.
PJ3
I/O
1-bit input/output pin.
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 16 of 170
RX230 Group, RX231 Group
1.5
1. Overview
Pin Assignments
Figure 1.3 to Figure 1.9 show the pin assignments. Table 1.6 to Table 1.10 show the lists of pins and pin functions.
RX230 Group, RX231 Group
PTLG0100KA-A
(100-pin TFLGA)
(Upper perspective view)
10
9
8
7
6
5
4
3
2
1
K
PC2
PC3
PC5
P51
USB0_
DP/PH1
USB0_
DM/PH2
P14
P20
P22
P23
K
J
PC1
PC0
PC4
P50
VCC_
USB/PH3
VSS_
USB/PH0
P13
P17
P21
P24
J
H
PB7
PB6
PC6
PC7
P54
P55
P15
P16
P25
P26
H
G
VCC
PB1
PB4
PB5
P52
P53
P27
P30
P31
P33
G
F
VSS
PA7
PB0
PB2
PB3
P12
P32
P35
VCC
P36/
EXTAL
F
E
PA3
PA5
PA4
PA6
PA2
P41
P34
RES#
VSS
P37/
XTAL
E
D
PA0
PA1
PE7
PE6
P46
P45
VBATT
MD
XCOUT
XCIN
D
C
PE4
PE5
PD5
PD2
P47
P42
VREFH0
PJ3
VREFL
VCL
C
B
PE3
PD7
PD6
PD3
PD1
P44
P40
AVCC0
AVSS0
P03
B
A
PE2
PE1
PE0
PD4
PD0
P43
VREFL0
P07
VREFH
P05
A
10
9
8
7
6
5
4
3
2
1
Note:
Note:
*1
*1
*1
*1
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (100-Pin TFLGA)”.
For the position of A1 pin in the package, see “Package Dimensions”.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
Figure 1.3
Pin Assignments of the 100-Pin TFLGA (Upper Perspective View)
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 17 of 170
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VSS
PB0
VCC
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1. Overview
75
RX230 Group, RX231 Group
PE2
76
50
PE1
77
49
PC2
PC3
PE0
78
48
PC4
PD7
79
47
PC5
PD6
80
46
PC6
PD5
81
45
PC7
PD4
82
44
P50
PD3
83
43
P51
PD2
84
42
P52
PD1
85
41
P53
PD0
86
40
P54
P47
87
39
P55
P46
88
P45
89
RX230 Group, RX231 Group
PLQP0100KB-B
(100-pin LFQFP)
(Top view)
38
VSS_USB/PH0*1
37
USB0_DP/PH1*1
36
USB0_DM/PH2*1
35
VCC_USB/PH3*1
Note:
15
16
17
18
19
20
21
22
23
24
25
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22
14
26
VCC
100
13
P21
P05
P36/EXTAL
27
12
99
VSS
P20
AVSS0
11
28
P37/XTAL
98
10
P17
P07
RES#
29
9
97
XCOUT
P16
AVCC0
8
30
XCIN
96
7
P15
VREFH0
MD
31
6
95
VBATT
P14
P40
5
32
VCL
94
4
P13
VREFL0
PJ3
33
3
P12
93
VREFL
34
P41
2
P42
92
1
91
P03
90
VREFH
P44
P43
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (100-Pin LFQFP)”.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
Figure 1.4
Pin Assignments of the 100-Pin LFQFP
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 18 of 170
RX230 Group, RX231 Group
1. Overview
RX230 Group, RX231 Group
PWLG0064KA-A
(64-pin WFLGA)
(Upper perspective view)
8
PE3
PE4
PA0
PA3
PB0
PB3
PB6
PB7
7
PE2
PE1
PE5
PA1
VSS
PB5
PC3
PC2
6
VREFL
P46
PE0
PA4
VCC
PB1
PC6
P54
5
VREFH
P44
P43
PA6
PC4
P15
PC7
P55
4
VREFL0
P42
P41
P14
P16
PC5
VSS_
USB/PH0
USB0_
DP/PH1
VCC_
USB/PH3
USB0_
DM/PH2
*1
3
VREFH0
P40
P03
P27
P30
P31
*1
Note:
Note:
*1
*1
2
AVCC0
AVSS0
MD
RES#
VBATT
P35
P26
P17
1
P05
VCL
XCIN
XCOUT
VSS
VCC
P36/
EXTAL
P37/
XTAL
A
B
C
D
E
F
G
H
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin WFLGA)”.
For the position of A1 pin in the package, see “Package Dimensions”.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
Figure 1.5
Pin Assignments of the 64-Pin WFLGA
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 19 of 170
33 PB7
34 PB6
35 PB5
36 PB3
37 PB1
38 VCC
39 PB0
40 VSS
41 PA6
42 PA4
43 PA3
44 PA1
32 PC2
PE1 50
31 PC3
PE0 51
30 PC4
VREFL 52
29 PC5
RX230 Group,
RX231 Group
PWQN0064KC-A
(64-pin HWQFN)
(Top view)
VREFH 54
P44 55
P43 56
P42 57
P41 58
VREFL0 59
P40 60
28 PC6
27 PC7
26 P54
25 P55
*1
24 VSS_USB/PH0
*1
23 USB0_DP/PH1
22 USB0_DM/PH2
*1
P26 16
P27 15
P30 14
P31 13
VBATT 12
P36/EXTAL
P35 11
9
VSS
VCC 10
8
P37/XTAL 7
17 P17
RES# 6
18 P16
AVSS0 64
XCOUT 5
19 P15
P05 63
XCIN 4
20 P14
AVCC0 62
MD 3
*1
21 VCC_USB/PH3
VREFH0 61
P03 1
VCL 2
Note:
45 PA0
PE2 49
P46 53
Note:
46 PE5
47 PE4
1. Overview
48 PE3
RX230 Group, RX231 Group
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin LFQFP/HWQFN)”.
It is recommended to connect an exposed die pad to VSS.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
Figure 1.6
Pin Assignments of the 64-Pin HWQFN
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 20 of 170
Note:
VSS
PB0
VCC
PB1
PB3
PB5
PB6
PB7
39
38
37
36
35
34
33
PA3
40
PA1
43
PA4
PA0
44
PA6
PE5
45
41
PE4
46
42
PE3
47
1. Overview
48
RX230 Group, RX231 Group
PE2
49
32
PC2
PE1
50
31
PC3
PE0
51
30
PC4
VREFL
52
29
PC5
P46
53
28
PC6
VREFH
54
27
PC7
P44
55
26
P54
P43
56
25
P55
P42
57
24
VSS_USB/PH0*1
P41
58
23
USB0_DP/PH1*1
VREFL0
59
22
USB0_DM/PH2*1
P40
60
21
VCC_USB/PH3*1
VREFH0
61
20
P14
AVCC0
62
19
P15
P05
63
18
P16
AVSS0
64
17
P17
12
13
14
15
16
P31
P30
P27
P26
8
VSS
VBATT
7
P37/XTAL
11
6
RES#
P35
5
XCOUT
9
4
XCIN
10
3
MD
VCC
2
P36/EXTAL
1
P03
VCL
RX230 Group,
RX231 Group
PLQP0064KB-C
(64-pin LFQFP)
(Top view)
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (64-Pin LFQFP/HWQFN)”.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
Figure 1.7
Pin Assignments of the 64-Pin LFQFP
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 21 of 170
PA4
VSS
PB0
VCC
PB1
PB3
PB5
30
29
28
27
26
25
PA3
PA6
PA1
33
31
PE4
34
PE2
37
24
PC4
PE1
38
23
PC5
VREFL
39
22
PC6
P46
40
21
PC7
VREFH
41
20
VSS_USB/PH0*1
P42
42
19
USB0_DP/PH1*1
P41
43
18
USB0_DM/PH2*1
VREFL0
44
17
VCC_USB/PH3*1
16
P14
15
P15
RX230 Group,
RX231 Group
PLQP0048KB-B
(48-pin LFQFP)
(Top view)
12
P26
11
10
P30
P27
9
P31
P35
8
7
VCC
MD
6
P17
P36/EXTAL
13
5
48
VSS
P16
AVSS0
4
14
P37/XTAL
47
3
AVCC0
RES#
46
2
VREFH0
1
P40
45
VCL
Note:
32
PE3
35
1. Overview
36
RX230 Group, RX231 Group
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (48-Pin LFQFP/HWQFN)”.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
25 PB5
26 PB3
27 PB1
28 VCC
29 PB0
30 VSS
31 PA6
32 PA4
33 PA3
34 PA1
PE2 37
24 PC4
PE1 38
23 PC5
VREFL 39
22 PC6
RX230 Group,
RX231 Group
PWQN0048KB-A
(48-pin HWQFN)
(Top view)
P46 40
VREFH 41
P42 42
P41 43
VREFL0 44
P40 45
VREFH0 46
21 PC7
20 VSS_USB/PH0*1
19 USB0_DP/PH1*1
18 USB0_DM/PH2*1
17 VCC_USB/PH3*1
16 P14
15 P15
P26 12
P27 11
P30 10
P31 9
P35
8
VCC 7
P36/EXTAL 6
VSS 5
13 P17
P37/XTAL 4
14 P16
AVSS0 48
RES# 3
AVCC0 47
VCL 1
Note:
Note:
35 PE4
36 PE3
Pin Assignments of the 48-Pin LFQFP
MD 2
Figure 1.8
It is recommended to connect an exposed die pad to VSS.
This figure indicates the power supply pins and I/O port pins.
For the pin configuration, see the table “List of Pins and Pin Functions (48-Pin LFQFP/HWQFN)”.
Note 1. RX230: PH0, PH1, PH2, PH3
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
Figure 1.9
Pin Assignments of the 48-Pin HWQFN
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 22 of 170
RX230 Group, RX231 Group
Table 1.6
Pin
No.
A2
I/O Port
External Bus
Timers
(MTU, TPU, TMR, RTC,
CMT, POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN,
USB, SSI)
Memory
Interface
(SDHI)
Touch
sensing
Others
P05
DA1
P07
ADTRG0#
VREFH
A3
A4
List of Pins and Pin Functions (100-Pin TFLGA) (1/3)
Power Supply,
Clock, System
Control
A1
1. Overview
VREFL0
A5
P43
A6
PD0
D0[A0/D0]
A7
PD4
D4[A4/D4]
A8
PE0
D8[A8/D8]
A9
PE1
D9[A9/D9]
A10
PE2
D10[A10/D10]
B1
AN003
IRQ0/AN024
POE3#
IRQ4/AN028
SCK12
AN016
MTIOC4C
TXD12/TXDX12/SIOX12/
SMOSI12/SSDA12
AN017/
CMPB0
MTIOC4A
RXD12/RXDX12/
SMISO12/SSCL12
IRQ7/AN018/
CVREFB0
P03
DA0
B4
P40
AN000
B5
P44
B6
PD1
D1[A1/D1]
MTIOC4B
IRQ1/AN025
B7
PD3
D3[A3/D3]
POE8#
IRQ3/AN027
B8
PD6
D6[A6/D6]
MTIC5V/POE1#
IRQ6/AN030
B9
PD7
D7[A7/D7]
MTIC5U/POE0#
IRQ7/AN031
B10
PE3
D11[A11/D11]
MTIOC4B/POE8#
CTS12#/RTS12#/SS12#/
AUDIO_MCLK
MTIOC3C
CTS6#/RTS6#/SS6#
B2
AVSS0
B3
AVCC0
C1
VCL
C2
VREFL
C3
C4
AN004
PJ3
AN019/
CLKOUT
VREFH0
C5
P42
C6
P47
C7
PD2
D2[A2/D2]
MTIOC4D
IRQ2/AN026
C8
PD5
D5[A5/D5]
MTIC5W/POE2#
IRQ5/AN029
C9
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B
IRQ5/AN021/
CMPOB0
C10
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A
AN020/
CMPA2/
CLKOUT
D1
XCIN
D2
XCOUT
D3
MD
D4
VBATT
AN002
AN007
FINED
D5
P45
D6
P46
D7
PE6
D14[A14/D14]
D8
PE7
D15[A15/D15]
D9
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0
SCK5/SSLA2/SSISCK0
PA0
A0/BC0#
MTIOC4A/TIOCA0
SSLA1
MTIOC0A/TMCI3/POE2#
SCK6
D10
E1
XTAL
E2
VSS
E3
RES#
AN005
AN006
IRQ6/AN022
IRQ7/AN023
CACREF
P37
E4
P34
E5
P41
E6
PA2
A2
E7
PA6
A6
TS0
IRQ4
AN001
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
RXD5/SMISO5/SSCL5/
SSLA3/IRRXD5
MTIC5V/MTCLKB/TMCI3/
POE2#/TIOCA2
CTS5#/RTS5#/SS5#/
MOSIA/SSIWS0
Page 23 of 170
RX230 Group, RX231 Group
Table 1.6
Pin
No.
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (2/3)
Power Supply,
Clock, System
Control
E8
I/O Port
External Bus
PA4
A4
Timers
(MTU, TPU, TMR, RTC,
CMT, POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN,
USB, SSI)
MTIC5U/MTCLKA/TMRI0/
TIOCA1
TXD5/SMOSI5/SSDA5/
SSLA0/SSITXD0/IRTXD5
E9
PA5
A5
TIOCB1
RSPCKA
E10
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB
RXD5/SMISO5/SSCL5/
SSIRXD0/IRRXD5
MTIOC0C/TMO3/TIOCC0/
RTCOUT/RTCIC2
TXD6/SMOSI6/SSDA6/
USB0_VBUSEN
TMCI1
SCL
F1
EXTAL
F2
VCC
F3
UPSEL
F4
Others
IRQ5 /
CVREFB1
IRQ6 /CMPB1
P35
NMI
F5
P12
F6
PB3
A11
MTIOC0A/MTIOC4A/TMO0/ SCK6
POE3#/TIOCD3/TCLKD
F7
PB2
A10
TIOCC3/TCLKC
CTS6#/RTS6#/SS6#
F8
PB0
A8
MTIC5W/TIOCA3
RXD6/SMISO6/SSCL6/
RSPCKA
PA7
A7
TIOCB2
MISOA
F10
Touch
sensing
P36
P32
F9
Memory
Interface
(SDHI)
IRQ2
IRQ2
SDHI_W
P
SDHI_C
MD
VSS
G1
P33
MTIOC0D/TMRI3/POE3#/
TIOCD0
RXD6/SMISO6/SSCL6
G2
P31
MTIOC4D/TMCI2/RTCIC1
CTS1#/RTS1#/SS1#/
SSISCK0
IRQ1
G3
P30
MTIOC4B/TMRI3/POE8#/
RTCIC0
RXD1/SMISO1/SSCL1/
AUDIO_MCLK
IRQ0/
CMPOB3
MTIOC2B/TMCI3
SCK1/ SSIWS0
G4
G5
P27
BCLK
CS3#
TS1
TS2
P53
P52
RD#
G7
PB5
A13
TS18
MTIOC2A/MTIOC1B/
TMRI1/POE1#/TIOCB4
SCK9/USB0_VBUS
SDHI_CD
G8
PB4
A12
TIOCA4
CTS9#/RTS9#/SS9#
G9
PB1
A9
MTIOC0C/MTIOC4C/
TMCI0/TIOCB3
TXD6/SMOSI6/SSDA6
H1
P26
CS2#
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1/
SSIRXD0
H2
P25
CS1#
MTIOC4C/MTCLKB/
TIOCA4
H3
P16
MTIOC3C/MTIOC3D/
TMO2/TIOCB1/TCLKC/
RTCOUT
TXD1/SMOSI1/SSDA1/
MOSIA/SCL/
USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
H4
P15
MTIOC0B/MTCLKB/TMCI2/
TIOCB2/TCLKB
RXD1/SMISO1/SSCL1/
CRXD0
TS12
H5
P55
WAIT#
MTIOC4D/TMO3
CRXD0
TS15
H6
P54
ALE
MTIOC4B/TMCI1
CTXD0
TS16
PC7
A23/CS0#
MTIOC3A/MTCLKB/TMO2
TXD8/SMOSI8/SSDA8/
MISOA
H8
PC6
A22/CS1#
MTIOC3C/MTCLKA/TMCI2
RXD8/SMISO8/SSCL8/
MOSIA
H9
PB6
A14
MTIOC3D/TIOCA5
RXD9/SMISO9/SSCL9
SDHI_D1
H10
PB7
A15
MTIOC3B/TIOCB5
TXD9/SMOSI9/SSDA9
SDHI_D2
J1
P24
CS0#
MTIOC4A/MTCLKA/TMRI1/
TIOCB4
USB0_VBUSEN
TS5
J2
P21
MTIOC1B/TMCI0/TIOCA3
RXD0/SMISO0/SSCL0/
USB0_EXICEN/SSIWS0
TS8
J3
P17
MTIOC3A/MTIOC3B/TMO1/ SCK1/MISOA/SDA/
POE8#/TIOCB0/TCLKD
SSITXD0
P13
MTIOC0B/TMO3/TIOCA5
H7
SDHI_CL
K
IRQ4/
CMPOB1
VCC
UB
J4
J5
CVREFB3
TS17
G6
G10
IRQ3
VSS_USB*1
PH0*1
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
SDA
TS3
CMPB3
TS4
ADTRG0#
IRQ6/
ADTRG0#
IRQ5/CMPB2
CACREF
TS22
IRQ7/
CMPOB2
IRQ3
CACREF*1
Page 24 of 170
RX230 Group, RX231 Group
Table 1.6
1. Overview
List of Pins and Pin Functions (100-Pin TFLGA) (3/3)
Pin
No.
Power Supply,
Clock, System
Control
I/O Port
J6
VCC_USB*1
PH3*1
External Bus
Timers
(MTU, TPU, TMR, RTC,
CMT, POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN,
USB, SSI)
Memory
Interface
(SDHI)
Touch
sensing
Others
TMCI0*1
J7
P50
WR0#/WR#
J8
PC4
A20/CS3#
MTIOC3D/MTCLKC/TMCI1/ SCK5/CTS8#/RTS8#/
POE0#
SS8#/SSLA0
TS20
J9
PC0
A16
MTIOC3C/TCLKC
CTS5#/RTS5#/SS5#/
SSLA1
TS35
J10
PC1
A17
MTIOC3A/TCLKD
SCK5/SSLA2
TS33
K1
P23
MTIOC3D/MTCLKD/
TIOCD3
CTS0#/RTS0#/SS0#/
SSISCK0
TS6
K2
P22
MTIOC3B/MTCLKC/TMO0/
TIOCC3
SCK0/ USB0_OVRCURB/
AUDIO_MCLK
TS7
K3
P20
MTIOC1A/TMRI0/TIOCB3
TXD0/SMOSI0/SSDA0/
USB0_ID/SSIRXD0
TS9
K4
P14
MTIOC3A/MTCLKA/TMRI2/
TIOCB5/TCLKA
CTS1#/RTS1#/SS1#/
CTXD0/USB0_OVRCURA
TS13
K5
PH2*1
TMRI0*1
USB0_DM*1
IRQ1*1
K6
PH1*1
TMO0*1
USB0_DP*1
IRQ0*1
K7
P51
WR1#/BC1#/
WAIT#
K8
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/TMRI2
SCK8/RSPCKA
K9
PC3
A19
MTIOC4D/TCLKB
TXD5/SMOSI5/SSDA5/
IRTXD5
SDHI_D0
TS27
K10
PC2
A18
MTIOC4B/TCLKA
RXD5/SMISO5/SSCL5/
SSLA3/ IRRXD5
SDHI_D3
TS30
SDHI_D1
TSCAP
IRQ4/
CVREFB2
TS19
TS23
Note 1. RX230: PH0/CACREF, PH1/IRQ0/TMO0, PH2/IRQ1/TMRI0, PH3/TMCI0
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 25 of 170
RX230 Group, RX231 Group
Table 1.7
List of Pins and Pin Functions (100-Pin LFQFP) (1/3)
Pin
No.
Power Supply,
Clock, System
Control
1
VREFH
2
3
1. Overview
I/O Port
External Bus
Timers
(MTU, TPU, TMR, RTC,
CMT, POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN,
USB, SSI)
Memory
Interface
(SDHI)
Touch
sensing
P03
Others
DA0
VREFL
4
PJ3
5
VCL
6
VBATT
7
MD
8
XCIN
9
XCOUT
10
RES#
11
XTAL
12
VSS
13
EXTAL
14
VCC
15
UPSEL
MTIOC3C
CTS6#/RTS6#/SS6#
FINED
P37
P36
P35
NMI
16
P34
MTIOC0A/TMCI3/POE2#
SCK6
TS0
IRQ4
17
P33
MTIOC0D/TMRI3/POE3#/
TIOCD0
RXD6/SMISO6/SSCL6
TS1
IRQ3
18
P32
MTIOC0C/TMO3/TIOCC0/
RTCOUT/RTCIC2
TXD6/SMOSI6/SSDA6/
USB0_VBUSEN
IRQ2
19
P31
MTIOC4D/TMCI2/RTCIC1
CTS1#/RTS1#/SS1#/
SSISCK0
IRQ1
20
P30
MTIOC4B/TMRI3/POE8#/
RTCIC0
RXD1/SMISO1/SSCL1/
AUDIO_MCLK
IRQ0/
CMPOB3
21
P27
CS3#
MTIOC2B/TMCI3
SCK1/ SSIWS0
TS2
CVREFB3
22
P26
CS2#
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1/
SSIRXD0
TS3
CMPB3
23
P25
CS1#
MTIOC4C/MTCLKB/
TIOCA4
TS4
ADTRG0#
24
P24
CS0#
MTIOC4A/MTCLKA/TMRI1/
TIOCB4
USB0_VBUSEN
TS5
25
P23
MTIOC3D/MTCLKD/
TIOCD3
CTS0#/RTS0#/SS0#/
SSISCK0
TS6
26
P22
MTIOC3B/MTCLKC/TMO0/
TIOCC3
SCK0/ USB0_OVRCURB/
AUDIO_MCLK
TS7
27
P21
MTIOC1B/TMCI0/TIOCA3
RXD0/SMISO0/SSCL0/
USB0_EXICEN/SSIWS0
TS8
28
P20
MTIOC1A/TMRI0/TIOCB3
TXD0/SMOSI0/SSDA0/
USB0_ID/SSIRXD0
TS9
29
P17
MTIOC3A/MTIOC3B/TMO1/ SCK1/MISOA/SDA/
POE8#/TIOCB0/TCLKD
SSITXD0
IRQ7/
CMPOB2
30
P16
MTIOC3C/MTIOC3D/
TMO2/TIOCB1/TCLKC/
RTCOUT
TXD1/SMOSI1/SSDA1/
MOSIA/SCL/USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6/
ADTRG0#
31
P15
MTIOC0B/MTCLKB/TMCI2/
TIOCB2/TCLKB
RXD1/SMISO1/SSCL1/
CRXD0
TS12
IRQ5/CMPB2
32
P14
MTIOC3A/MTCLKA/TMRI2/
TIOCB5/TCLKA
CTS1#/RTS1#/SS1#/
CTXD0/USB0_OVRCURA
TS13
IRQ4/
CVREFB2
33
P13
MTIOC0B/TMO3/TIOCA5
SDA
IRQ3
34
P12
TMCI1
SCL
IRQ2
PH3*1
TMCI0*1
36
PH2*1
TMRI0*1
USB0_DM*1
IRQ1*1
37
PH1*1
TMO0*1
USB0_DP*1
IRQ0*1
35
38
VCC_USB*1
VSS_USB*1
PH0*1
CACREF*1
39
P55
WAIT#
MTIOC4D/TMO3
CRXD0
TS15
40
P54
ALE
MTIOC4B/TMCI1
CTXD0
TS16
41
BCLK
P53
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
TS17
Page 26 of 170
RX230 Group, RX231 Group
Table 1.7
Pin
No.
1. Overview
List of Pins and Pin Functions (100-Pin LFQFP) (2/3)
Power Supply,
Clock, System
Control
Timers
(MTU, TPU, TMR, RTC,
CMT, POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN,
USB, SSI)
Memory
Interface
(SDHI)
Touch
sensing
I/O Port
External Bus
42
P52
RD#
TS18
43
P51
WR1#/BC1#/
WAIT#
TS19
44
P50
WR0#/WR#
PC7
A23/CS0#
MTIOC3A/MTCLKB/TMO2
TXD8/SMOSI8/SSDA8/
MISOA
46
PC6
A22/CS1#
MTIOC3C/MTCLKA/TMCI2
RXD8/SMISO8/SSCL8/
MOSIA
TS22
47
PC5
A21/CS2#/
WAIT#
MTIOC3B/MTCLKD/TMRI2
SCK8/RSPCKA
TS23
48
PC4
A20/CS3#
MTIOC3D/MTCLKC/TMCI1/ SCK5/CTS8#/RTS8#/
POE0#
SS8#/SSLA0
SDHI_D1
TSCAP
49
PC3
A19
MTIOC4D/TCLKB
TXD5/SMOSI5/SSDA5/
IRTXD5
SDHI_D0
TS27
50
PC2
A18
MTIOC4B/TCLKA
RXD5/SMISO5/SSCL5/
SSLA3/ IRRXD5
SDHI_D3
TS30
51
PC1
A17
MTIOC3A/TCLKD
SCK5/SSLA2
TS33
52
PC0
A16
MTIOC3C/TCLKC
CTS5#/RTS5#/SS5#/
SSLA1
TS35
53
PB7
A15
MTIOC3B/TIOCB5
TXD9/SMOSI9/SSDA9
54
PB6
A14
MTIOC3D/TIOCA5
RXD9/SMISO9/SSCL9
SDHI_D1
55
PB5
A13
MTIOC2A/MTIOC1B/
TMRI1/POE1#/TIOCB4
SCK9/USB0_VBUS
SDHI_CD
56
PB4
A12
TIOCA4
CTS9#/RTS9#/SS9#
57
PB3
A11
MTIOC0A/MTIOC4A/TMO0/ SCK6
POE3#/TIOCD3/TCLKD
45
UB
TS20
CACREF
SDHI_D2
SDHI_W
P
58
PB2
A10
TIOCC3/TCLKC
CTS6#/RTS6#/SS6#
59
PB1
A9
MTIOC0C/MTIOC4C/
TMCI0/TIOCB3
TXD6/SMOSI6/SSDA6
SDHI_CL
K
PB0
A8
MTIC5W/TIOCA3
RXD6/SMISO6/SSCL6/
RSPCKA
SDHI_C
MD
60
IRQ4/
CMPOB1
VCC
61
62
Others
VSS
63
PA7
A7
TIOCB2
MISOA
64
PA6
A6
MTIC5V/MTCLKB/TMCI3/
POE2#/TIOCA2
CTS5#/RTS5#/SS5#/
MOSIA/SSIWS0
65
PA5
A5
TIOCB1
RSPCKA
66
PA4
A4
MTIC5U/MTCLKA/TMRI0/
TIOCA1
TXD5/SMOSI5/SSDA5/
SSLA0/SSITXD0/IRTXD5
IRQ5 /
CVREFB1
67
PA3
A3
MTIOC0D/MTCLKD/
TIOCD0/TCLKB
RXD5/SMISO5/SSCL5/
SSIRXD0/IRRXD5
IRQ6 /CMPB1
68
PA2
A2
69
PA1
A1
MTIOC0B/MTCLKC/
TIOCB0
SCK5/SSLA2/SSISCK0
70
PA0
A0/BC0#
MTIOC4A/TIOCA0
SSLA1
71
PE7
D15[A15/D15]
72
PE6
D14[A14/D14]
73
PE5
D13[A13/D13]
MTIOC4C/MTIOC2B
IRQ5/AN021/
CMPOB0
74
PE4
D12[A12/D12]
MTIOC4D/MTIOC1A
AN020/
CMPA2/
CLKOUT
75
PE3
D11[A11/D11]
MTIOC4B/POE8#
CTS12#/RTS12#/SS12#/
AUDIO_MCLK
AN019/
CLKOUT
76
PE2
D10[A10/D10]
MTIOC4A
RXD12/RXDX12/
SMISO12/SSCL12
IRQ7/AN018/
CVREFB0
77
PE1
D9[A9/D9]
MTIOC4C
TXD12/TXDX12/SIOX12/
SMOSI12/SSDA12
AN017/
CMPB0
78
PE0
D8[A8/D8]
SCK12
AN016
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
RXD5/SMISO5/SSCL5/
SSLA3/IRRXD5
CACREF
IRQ7/AN023
IRQ6/AN022
Page 27 of 170
RX230 Group, RX231 Group
Table 1.7
1. Overview
List of Pins and Pin Functions (100-Pin LFQFP) (3/3)
I/O Port
External Bus
Timers
(MTU, TPU, TMR, RTC,
CMT, POE, CAC)
79
PD7
D7[A7/D7]
MTIC5U/POE0#
IRQ7/AN031
80
PD6
D6[A6/D6]
MTIC5V/POE1#
IRQ6/AN030
81
PD5
D5[A5/D5]
MTIC5W/POE2#
IRQ5/AN029
82
PD4
D4[A4/D4]
POE3#
IRQ4/AN028
83
PD3
D3[A3/D3]
POE8#
IRQ3/AN027
84
PD2
D2[A2/D2]
MTIOC4D
IRQ2/AN026
85
PD1
D1[A1/D1]
MTIOC4B
IRQ1/AN025
86
PD0
D0[A0/D0]
87
P47
AN007
88
P46
AN006
89
P45
AN005
90
P44
AN004
91
P43
AN003
92
P42
AN002
93
P41
AN001
P40
AN000
P07
ADTRG0#
P05
DA1
Pin
No.
94
Power Supply,
Clock, System
Control
96
VREFH0
97
AVCC0
98
100
Memory
Interface
(SDHI)
Touch
sensing
Others
IRQ0/AN024
VREFL0
95
99
Communications
(SCI, RSPI, RIIC, RSCAN,
USB, SSI)
AVSS0
Note 1. RX230: PH0/CACREF, PH1/IRQ0/TMO0, PH2/IRQ1/TMRI0, PH3/TMCI0
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 28 of 170
RX230 Group, RX231 Group
Table 1.8
Pin
No.
List of Pins and Pin Functions (64-Pin WFLGA) (1/2)
Power Supply,
Clock, System
Control
A1
1. Overview
I/O Port
Timers
(MTU, TPU, TMR, RTC, CMT,
POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN, USB,
SSI)
Memory
Interface
(SDHI)
Touch
sensing
P05
A2
AVCC0
A3
VREFH0
A4
VREFL0
A5
VREFH
A6
VREFL
Others
DA1
A7
PE2
MTIOC4A
RXD12/RXDX12/SMISO12/
SSCL12
IRQ7/AN018/
CVREFB0
A8
PE3
MTIOC4B/POE8#
CTS12#/RTS12#/SS12#/
AUDIO_MCLK
AN019/CLKOUT
B1
VCL
B2
AVSS0
B3
P40
AN000
B4
P42
AN002
B5
P44
AN004
B6
P46
B7
PE1
MTIOC4C
B8
PE4
MTIOC4D/MTIOC1A
C1
XCIN
C2
MD
AN006
TXD12/TXDX12/SIOX12/
SMOSI12/SSDA12
AN017/CMPB0
AN020/CMPA2/
CLKOUT
FINED
C3
P03
DA0
C4
P41
AN001
C5
P43
C6
PE0
C7
PE5
MTIOC4C/MTIOC2B
PA0
MTIOC4A/TIOCA0
SSLA1
C8
D1
XCOUT
D2
RES#
AN003
SCK12
AN016
IRQ5/AN021/
CMPOB0
CACREF
D3
P27
MTIOC2B/TMCI3
SCK1/ SSIWS0
TS2
CVREFB3
D4
P14
MTIOC3A/MTCLKA/TMRI2/
TIOCB5/TCLKA
CTS1#/RTS1#/SS1#/CTXD0/
USB0_OVRCURA
TS13
IRQ4/CVREFB2
D5
PA6
MTIC5V/MTCLKB/TMCI3/POE2#/
TIOCA2
CTS5#/RTS5#/SS5#/MOSIA/
SSIWS0
D6
PA4
MTIC5U/MTCLKA/TMRI0/TIOCA1
TXD5/SMOSI5/SSDA5/SSLA0/
SSITXD0/IRTXD5
IRQ5 /CVREFB1
D7
PA1
MTIOC0B/MTCLKC/TIOCB0
SCK5/SSLA2/SSISCK0
D8
PA3
MTIOC0D/MTCLKD/TIOCD0/
TCLKB
RXD5/SMISO5/SSCL5/SSIRXD0/
IRRXD5
IRQ6 /CMPB1
E3
P30
MTIOC4B/TMRI3/POE8#/RTCIC0
RXD1/SMISO1/SSCL1/
AUDIO_MCLK
IRQ0/CMPOB3
E4
P16
MTIOC3C/MTIOC3D/TMO2/
TIOCB1/TCLKC/RTCOUT
TXD1/SMOSI1/SSDA1/MOSIA/
SCL/USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6/ADTRG0#
E5
PC4
MTIOC3D/MTCLKC/TMCI1/
POE0#
SCK5/CTS8#/RTS8#/SS8#/
SSLA0
SDHI_D1
PB0
MTIC5W/TIOCA3
RXD6/SMISO6/SSCL6/RSPCKA
SDHI_C
MD
MTIOC4D/TMCI2/RTCIC1
CTS1#/RTS1#/SS1#/SSISCK0
E1
VSS
E2
VBATT
E6
VCC
E7
VSS
E8
F1
VCC
F2
UPSEL
F3
P35
P31
TSCAP
NMI
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
IRQ1
Page 29 of 170
RX230 Group, RX231 Group
Table 1.8
1. Overview
List of Pins and Pin Functions (64-Pin WFLGA) (2/2)
I/O Port
Timers
(MTU, TPU, TMR, RTC, CMT,
POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN, USB,
SSI)
F4
PC5
MTIOC3B/MTCLKD/TMRI2
SCK8/RSPCKA/USB0_ID
F5
P15
MTIOC0B/MTCLKB/TMCI2/
TIOCB2/TCLKB
RXD1/SMISO1/SSCL1/CRXD0
F6
PB1
MTIOC0C/MTIOC4C/TMCI0/
TIOCB3
TXD6/SMOSI6/SSDA6
SDHI_CL
K
F7
PB5
MTIOC2A/MTIOC1B/TMRI1/
POE1#/TIOCB4
SCK9/USB0_VBUS
SDHI_CD
F8
PB3
MTIOC0A/MTIOC4A/TMO0/
POE3#/TIOCD3/TCLKD
SCK6
SDHI_W
P
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1/
USB0_VBUSEN/SSIRXD0
TMCI0*1
Pin
No.
G1
Power Supply,
Clock, System
Control
EXTAL
G2
Memory
Interface
(SDHI)
Touch
sensing
Others
TS12
IRQ5/CMPB2
TS23
IRQ4/ CMPOB1
P36
G3
VCC_USB*1
PH3*1
G4
VSS_USB*1
PH0*1
G5
UB
TS3
CMPB3
CACREF*1
PC7
MTIOC3A/MTCLKB/TMO2
TXD8/SMOSI8/SSDA8/MISOA
G6
PC6
MTIOC3C/MTCLKA/TMCI2
RXD8/SMISO8/SSCL8/MOSIA/
USB0_EXICEN
G7
PC3
MTIOC4D/TCLKB
TXD5/SMOSI5/SSDA5/IRTXD5
SDHI_D0
G8
PB6/PC0
MTIOC3D/TIOCA5
RXD9/SMISO9/SSCL9
SDHI_D1
P17
MTIOC3A/MTIOC3B/TMO1/
POE8#/TIOCB0/TCLKD
SCK1/MISOA/SDA/SSITXD0
IRQ7/ CMPOB2
IRQ1*1
H1
H2
XTAL
CACREF
TS22
TS27
P37
H3
PH2*1
TMRI0*1
USB0_DM*1
H4
PH1*1
TMO0*1
USB0_DP*1
H5
P55
MTIOC4D/TMO3
CRXD0
H6
P54
MTIOC4B/TMCI1
CTXD0
H7
PC2
MTIOC4B/TCLKA
RXD5/SMISO5/SSCL5/SSLA3/
IRRXD5
SDHI_D3
H8
PB7/PC1
MTIOC3B/TIOCB5
TXD9/SMOSI9/SSDA9
SDHI_D2
IRQ0*1
TS15
TS16
TS30
Note 1. RX230: PH0/CACREF, PH1/IRQ0/TMO0, PH2/IRQ1/TMRI0, PH3/TMCI0
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 30 of 170
RX230 Group, RX231 Group
Table 1.9
Pin
No.
1. Overview
List of Pins and Pin Functions (64-Pin LFQFP/HWQFN) (1/2)
Power Supply,
Clock, System
Control
1
I/O Port
Timers
(MTU, TPU, TMR, RTC, CMT,
POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN, USB,
SSI)
Memory
Interface
(SDHI)
Touch
sensing
P03
2
VCL
3
MD
4
XCIN
5
XCOUT
6
RES#
7
XTAL
8
VSS
9
EXTAL
10
VCC
11
UPSEL
12
VBATT
Others
DA0
FINED
P37
P36
P35
NMI
13
P31
MTIOC4D/TMCI2/RTCIC1
CTS1#/RTS1#/SS1#/SSISCK0
IRQ1
14
P30
MTIOC4B/TMRI3/POE8#/RTCIC0
RXD1/SMISO1/SSCL1/
AUDIO_MCLK
IRQ0/CMPOB3
15
P27
MTIOC2B/TMCI3
SCK1/SSIWS0
TS2
CVREFB3
16
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1/
USB0_VBUSEN/SSIRXD0
TS3
CMPB3
17
P17
MTIOC3A/MTIOC3B/TMO1/
POE8#/TIOCB0/TCLKD
SCK1/MISOA/SDA/SSITXD0
IRQ7/ CMPOB2
18
P16
MTIOC3C/MTIOC3D/TMO2/
TIOCB1/TCLKC/RTCOUT
TXD1/SMOSI1/SSDA1/MOSIA/
SCL/USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6/ADTRG0#
19
P15
MTIOC0B/MTCLKB/TMCI2/
TIOCB2/TCLKB
RXD1/SMISO1/SSCL1/CRXD0
TS12
IRQ5/CMPB2
20
P14
MTIOC3A/MTCLKA/TMRI2/
TIOCB5/TCLKA
CTS1#/RTS1#/SS1#/CTXD0/
USB0_OVRCURA
TS13
IRQ4/CVREFB2
PH3*1
TMCI0*1
22
PH2*1
TMRI0*1
USB0_DM*1
IRQ1*1
23
PH1*1
TMO0*1
USB0_DP*1
IRQ0*1
MTIOC4D/TMO3
CRXD0
TS15
TS16
21
24
VCC_USB*1
VSS_USB*1
25
P55
26
27
PH0*1
UB
28
CACREF*1
P54
MTIOC4B/TMCI1
CTXD0
PC7
MTIOC3A/MTCLKB/TMO2
TXD8/SMOSI8/SSDA8/MISOA
PC6
MTIOC3C/MTCLKA/TMCI2
RXD8/SMISO8/SSCL8/MOSIA/
USB0_EXICEN
CACREF
TS22
29
PC5
MTIOC3B/MTCLKD/TMRI2
SCK8/RSPCKA/USB0_ID
30
PC4
MTIOC3D/MTCLKC/TMCI1/
POE0#
SCK5/CTS8#/RTS8#/SS8#/
SSLA0
SDHI_D1
TS23
31
PC3
MTIOC4D/TCLKB
TXD5/SMOSI5/SSDA5/ IRTXD5
SDHI_D0
TS27
32
PC2
MTIOC4B/TCLKA
RXD5/SMISO5/SSCL5/SSLA3/
IRRXD5
SDHI_D3
TS30
SDHI_D2
33
PB7/PC1
MTIOC3B/TIOCB5
TXD9/SMOSI9/SSDA9
34
PB6/PC0
MTIOC3D/TIOCA5
RXD9/SMISO9/SSCL9
SDHI_D1
35
PB5
MTIOC2A/MTIOC1B/TMRI1/
POE1#/TIOCB4
SCK9/USB0_VBUS
SDHI_CD
36
PB3
MTIOC0A/MTIOC4A/TMO0/
POE3#/TIOCD3/TCLKD
SCK6
SDHI_W
P
37
PB1
MTIOC0C/MTIOC4C/TMCI0/
TIOCB3
TXD6/SMOSI6/SSDA6
SDHI_CL
K
PB0
MTIC5W/TIOCA3
RXD6/SMISO6/SSCL6/RSPCKA
SDHI_C
MD
PA6
MTIC5V/MTCLKB/TMCI3/POE2#/
TIOCA2
CTS5#/RTS5#/SS5#/MOSIA/
SSIWS0
38
41
IRQ4/ CMPOB1
VCC
39
40
TSCAP
VSS
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 31 of 170
RX230 Group, RX231 Group
Table 1.9
1. Overview
List of Pins and Pin Functions (64-Pin LFQFP/HWQFN) (2/2)
I/O Port
Timers
(MTU, TPU, TMR, RTC, CMT,
POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN, USB,
SSI)
42
PA4
MTIC5U/MTCLKA/TMRI0/TIOCA1
TXD5/SMOSI5/SSDA5/SSLA0/
SSITXD0/IRTXD5
IRQ5 /CVREFB1
43
PA3
MTIOC0D/MTCLKD/TIOCD0/
TCLKB
RXD5/SMISO5/SSCL5/SSIRXD0/
IRRXD5
IRQ6 /CMPB1
Pin
No.
Power Supply,
Clock, System
Control
Memory
Interface
(SDHI)
Touch
sensing
Others
44
PA1
MTIOC0B/MTCLKC/TIOCB0
SCK5/SSLA2/SSISCK0
45
PA0
MTIOC4A/TIOCA0
SSLA1
46
PE5
MTIOC4C/MTIOC2B
IRQ5/AN021/
CMPOB0
47
PE4
MTIOC4D/MTIOC1A
AN020/CMPA2/
CLKOUT
48
PE3
MTIOC4B/POE8#
CTS12#/RTS12#/SS12#/
AUDIO_MCLK
AN019/CLKOUT
49
PE2
MTIOC4A
RXD12/RXDX12/SMISO12/
SSCL12
IRQ7/AN018/
CVREFB0
50
PE1
MTIOC4C
TXD12/TXDX12/SIOX12/
SMOSI12/SSDA12
AN017/CMPB0
SCK12
AN016
51
52
PE0
VREFL
53
54
CACREF
P46
AN006
AN004
VREFH
55
P44
56
P43
AN003
57
P42
AN002
P41
AN001
P40
AN000
P05
DA1
58
59
VREFL0
60
61
VREFH0
62
AVCC0
63
64
AVSS0
Note 1. RX230: PH0/CACREF, PH1/IRQ0/TMO0, PH2/IRQ1/TMRI0, PH3/TMCI0
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 32 of 170
RX230 Group, RX231 Group
Table 1.10
1. Overview
List of Pins and Pin Functions (48-Pin LFQFP/HWQFN) (1/2)
Pin
No.
Power Supply,
Clock, System
Control
1
VCL
2
MD
3
RES#
4
XTAL
5
VSS
6
EXTAL
7
VCC
8
UPSEL
I/O Port
Timers
(MTU, TPU, TMR, RTC, CMT,
POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN, USB,
SSI)
Memory
Interface
(SDHI)
Touch
sensing
Others
FINED
P37
P36
P35
NMI
9
P31
MTIOC4D/TMCI2
CTS1#/RTS1#/SS1#/SSISCK0
IRQ1
10
P30
MTIOC4B/TMRI3/POE8#
RXD1/SMISO1/SSCL1/
AUDIO_MCLK
IRQ0/CMPOB3
11
P27
MTIOC2B/TMCI3
SCK1/SSIWS0
TS2
CVREFB3
12
P26
MTIOC2A/TMO1
TXD1/SMOSI1/SSDA1/
USB0_VBUSEN/SSIRXD0
TS3
CMPB3
13
P17
MTIOC3A/MTIOC3B/TMO1/
POE8#/TIOCB0/TCLKD
SCK1/MISOA/SDA/ SSITXD0
IRQ7/ CMPOB2
14
P16
MTIOC3C/MTIOC3D/TMO2/
TIOCB1/TCLKC
TXD1/SMOSI1/SSDA1/MOSIA/
SCL/USB0_VBUS/
USB0_VBUSEN/
USB0_OVRCURB
IRQ6/ADTRG0#
15
P15
MTIOC0B/MTCLKB/TMCI2/
TIOCB2/TCLKB
RXD1/SMISO1/SSCL1/CRXD0
TS12
IRQ5/CMPB2
16
P14
MTIOC3A/MTCLKA/TMRI2/
TIOCB5/TCLKA
CTS1#/RTS1#/SS1#/CTXD0/
USB0_OVRCURA
TS13
IRQ4/CVREFB2
PH3*1
TMCI0*1
18
PH2*1
TMRI0*1
USB0_DM*1
IRQ1*1
19
PH1*1
TMO0*1
USB0_DP*1
IRQ0*1
CACREF
17
VCC_USB*1
20
VSS_USB*1
PH0*1
21
UB
PC7
MTIOC3A/MTCLKB/TMO2
TXD8/SMOSI8/SSDA8/MISOA
PC6
MTIOC3C/MTCLKA/TMCI2
RXD8/SMISO8/SSCL8/MOSIA/
USB0_EXICEN
TS22
22
CACREF*1
23
PC5
MTIOC3B/MTCLKD/TMRI2
SCK8/RSPCKA/USB0_ID
TS23
24
PC4
MTIOC3D/MTCLKC/TMCI1/
POE0#
SCK5/CTS8#/RTS8#/SS8#/
SSLA0
TSCAP
25
PB5/PC3
MTIOC2A/MTIOC1B/TMRI1/
POE1#/TIOCB4
USB0_VBUS
26
PB3/PC2
MTIOC0A/MTIOC4A/TMO0/
POE3#/TIOCD3/TCLKD
SCK6
27
PB1/PC1
MTIOC0C/MTIOC4C/TMCI0/
TIOCB3
TXD6/SMOSI6/SSDA6
PB0/PC0
MTIC5W/TIOCA3
RXD6/SMISO6/SSCL6/RSPCKA
31
PA6
MTIC5V/MTCLKB/TMCI3/POE2#/
TIOCA2
CTS5#/RTS5#/SS5#/MOSIA/
SSIWS0
32
PA4
MTIC5U/MTCLKA/TMRI0/TIOCA1
TXD5/SMOSI5/SSDA5/SSLA0/
SSITXD0/IRTXD5
IRQ5 /CVREFB1
33
PA3
MTIOC0D/MTCLKD/TIOCD0/
TCLKB
RXD5/SMISO5/SSCL5/SSIRXD0/
IRRXD5
IRQ6 /CMPB1
SCK5/SSLA2/SSISCK0
28
VCC
29
30
IRQ4/ CMPOB1
VSS
34
PA1
MTIOC0B/MTCLKC/TIOCB0
35
PE4
MTIOC4D/MTIOC1A
AN020/CMPA2/
CLKOUT
36
PE3
MTIOC4B/POE8#
CTS12#/RTS12#/AUDIO_MCLK
AN019/CLKOUT
37
PE2
MTIOC4A
RXD12/RXDX12/SSCL12
IRQ7/AN018/
CVREFB0
PE1
MTIOC4C
TXD12/TXDX12/SIOX12/SSDA12
AN017/CMPB0
38
39
VREFL
40
41
P46
AN006
VREFH
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 33 of 170
RX230 Group, RX231 Group
Table 1.10
Pin
No.
43
44
List of Pins and Pin Functions (48-Pin LFQFP/HWQFN) (2/2)
Power Supply,
Clock, System
Control
42
1. Overview
I/O Port
Timers
(MTU, TPU, TMR, RTC, CMT,
POE, CAC)
Communications
(SCI, RSPI, RIIC, RSCAN, USB,
SSI)
Memory
Interface
(SDHI)
Touch
sensing
Others
P42
AN002
P41
AN001
P40
AN000
VREFL0
45
46
VREFH0
47
AVCC0
48
AVSS0
Note 1. RX230: PH0/CACREF, PH1/IRQ0/TMO0, PH2/IRQ1/TMRI0, PH3/TMCI0
RX231: VSS_USB, USB0_DP, USB0_DM, VCC_USB
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 34 of 170
RX230 Group, RX231 Group
2.
2. CPU
CPU
Figure 2.1 shows register set of the CPU.
Control register
General-purpose register
b31
b0
b31
*1
b0
R0 (SP)
ISP (Interrupt stack pointer)
R1
USP (User stack pointer)
R2
INTB (Interrupt table register)
R3
R4
PC (Program counter)
R5
PSW (Processor status word)
R6
R7
BPC (Backup PC)
R8
BPSW (Backup PSW)
R9
R10
FINTV (Fast interrupt vector register)
R11
FPSW (Floating-point status word)
R12
R13
EXTB (Exception table register)
R14
R15
DSP instruction register
b71
b0
ACC0 (Accumulator 0)
ACC1 (Accumulator 1)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to
the value of the U bit in the PSW.
Figure 2.1
Register Set of the CPU
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 35 of 170
RX230 Group, RX231 Group
2.1
2. CPU
General-Purpose Registers (R0 to R15)
This CPU has sixteen 32-bit general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address
registers.
R0, a general-purpose register, also functions as the stack pointer (SP).
The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the
stack pointer select bit (U) in the processor status word (PSW).
2.2
Control Registers
(1)
Interrupt stack pointer (ISP) and user stack pointer (USP)
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and
instructions entailing stack manipulation.
(2)
Exception table register (EXTB)
The exception table register (EXTB) specifies the address where the exception vector table starts.
Set the EXTB to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions
entailing stack manipulation.
(3)
Interrupt table register (INTB)
The interrupt table register (INTB) specifies the address where the interrupt vector table starts.
Set the INTB to a multiple of 4 to reduce the number of cycles required to execute interrupt sequences and instructions
entailing stack manipulation.
(4)
Program counter (PC)
The program counter (PC) indicates the address of the instruction being executed.
(5)
Processor status word (PSW)
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
(6)
Backup PC (BPC)
The backup PC (BPC) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register.
(7)
Backup PSW (BPSW)
The backup PSW (BPSW) is provided to speed up response to interrupts.
After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The
allocation of bits in the BPSW corresponds to that in the PSW.
(8)
Fast interrupt vector register (FINTV)
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 36 of 170
RX230 Group, RX231 Group
(9)
2. CPU
Floating-point status word (FPSW)
The floating-point status word (FPSW) indicates the results of floating-point operations.
When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified
by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the
occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has
been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V).
2.3
Accumulator
The accumulator (ACC0 or ACC1) is a 72-bit register used for DSP instructions. The accumulator is handled as a 96-bit
register for reading and writing. At this time, when bits 95 to 72 of the accumulator are read, the value where the value of
bit 71 is sign extended is read. Writing to bits 95 to 72 of the accumulator is ignored. ACC0 is also used for the multiply
and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in
ACC0 is modified by execution of the instruction.
Use the MVTACGU, MVTACHI, and MVTACLO instructions for writing to the accumulator. The MVTACGU,
MVTACHI, and MVTACLO instructions write data to bits 95 to 64, the higher-order 32 bits (bits 63 to 32), and the
lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions for reading data from the accumulator. The
MVFACGU, MVFACHI, MVFACMI, and MVFACLO instructions read data from the guard bits (bits 95 to 64), higherorder 32 bits (bits 63 to 32), the middle 32 bits (bits 47 to 16), and the lower-order 32 bits (bits 31 to 0), respectively.
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 37 of 170
RX230 Group, RX231 Group
3.
Address Space
3.1
Address Space
3. Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the
operating mode and states of control bits.
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 38 of 170
RX230 Group, RX231 Group
3. Address Space
On-chip ROM disabled
extended mode
On-chip ROM enabled
extended mode
Single-chip mode*1
0000 0000h
RAM*2
0000 0000h
RAM*2
0000 0000h
RAM*2
0001 0000h
Reserved area*3
0001 0000h
Reserved area*3
0001 0000h
Reserved area*3
0008 0000h
0008 0000h
0008 0000h
Peripheral I/O registers
0010 0000h
On-chip ROM (E2DataFlash)
0010 2000h
Peripheral I/O registers
Peripheral I/O registers
0010 0000h
On-chip ROM (E2DataFlash)
0010 0000h
0010 2000h
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
007F FC00h
0080 0000h
Peripheral I/O registers
Reserved area
*3
Reserved area*3
007F C000h
007F C500h
Peripheral I/O registers
007F FC00h
Peripheral I/O registers
Reserved area
Reserved area*3
*3
0080 0000h
Reserved area*3
0500 0000h
0500 0000h
External address space
(CS area)
External address space
(CS area)
0800 0000h
0800 0000h
Reserved area*3
Reserved area*3
Reserved area*3
FF00 0000h
External address space
FFF8 0000h
FFFF FFFFh
On-chip ROM (program ROM)
(read only)*2
FFF8 0000h
FFFF FFFFh
On-chip ROM (program ROM)
(read only)*2
FFFF FFFFh
Note 1. The address space in boot mode and USB boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
ROM (bytes)
RAM (bytes)
Capacity
Address
Capacity
Address
512 Kbytes
FFF8 0000h to FFFF FFFFh
64 Kbytes
0000 0000h to 0000 FFFFh
384 Kbytes
FFFA 0000h to FFFF FFFFh
32 Kbytes
0000 0000h to 0000 7FFFh
256 Kbytes
FFFC 0000h to FFFF FFFFh
128 Kbytes
FFFE 0000h to FFFF FFFFh
Note: See Table 1.3 and Table 1.4 List of Products, for the product type name.
Note 3. Reserved areas should not be accessed.
Figure 3.1
Memory Map in Each Operating Mode
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 39 of 170
RX230 Group, RX231 Group
3.2
3. Address Space
External Address Space
The external address space is divided into up to four CS areas (CS0 to CS3), each corresponding to the CSn# signal
output from a CSn# (n = 0 to 3) pin. Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0
to CS3) in on-chip ROM disabled extended mode.
0000 0000h
RAM
0001 0000h
Reserved area*1
0008 0000h
Peripheral I/O registers
0010 0000h
Reserved area*1
0500 0000h
CS3 (16 Mbytes)
0500 0000h
05FF FFFFh
0600 0000h
External address space
(CS area)
CS2 (16 Mbytes)
06FF FFFFh
0700 0000h
0800 0000h
CS1 (16 Mbytes)
07FF FFFFh
Reserved area*1
FF00 0000h
FF00 0000h
External address space*
(CS area)
FFFF FFFFh
2
CS0 (16 Mbytes)
FFFF FFFFh
Note 1. Reserved areas should not be accessed.
Note 2. The CS0 area is disabled in on-chip ROM enabled extended mode.
In this mode, the address space for addresses above 1000 0000h is as shown in figure on this
section, Memory Map in Each Operating Mode.
Figure 3.2
Correspondence between External Address Spaces and CS Areas
(In On-Chip ROM Disabled Extended Mode)
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 40 of 170
RX230 Group, RX231 Group
4.
4. I/O Registers
I/O Registers
This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as
shown below. Notes on writing to registers are also given below.
(1)
I/O register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified according to module symbols.
• Numbers of cycles for access indicate numbers of cycles of the given base clock.
• Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses
must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and
subsequent operations cannot be guaranteed.
(2)
Notes on writing to I/O registers
When writing to an I/O register, the CPU starts executing the subsequent instruction before completing I/O register write.
This may cause the subsequent instruction to be executed before the post-update I/O register value is reflected on the
operation.
As described in the following examples, special care is required for the cases in which the subsequent instruction must be
executed after the post-update I/O register value is actually reflected.
[Examples of cases requiring special care]
• The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the
ICU (interrupt request enable bit) cleared to 0.
• A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power
consumption state.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
(a)
(b)
(c)
(d)
Write to an I/O register.
Read the value from the I/O register to a general register.
Execute the operation using the value read.
Execute the subsequent instruction.
[Instruction examples]
• Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
• Word-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 41 of 170
RX230 Group, RX231 Group
4. I/O Registers
• Longword-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
(3)
Number of Access Cycles to I/O Registers
For numbers of clock cycles for access to I/O registers, see Table 4.1, List of I/O Registers (Address Order).
The number of access cycles to I/O registers is obtained by following equation.*1
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral bus 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 or registers for the external bus control unit (except
for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK, BCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access cycles shown in Table 4.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
In the external bus control unit, the sum of the number of bus cycles for internal main bus 1 and the number of divided
clock synchronization cycles will be one cycle of BCLK at a maximum. Therefore, one BCLK is added to the number of
access cycles shown in Table 4.1.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction fetching
to the external memory or bus access from the different bus master (DMAC or DTC).
(4)
Restrictions in Relation to RMPA and String-Manipulation Instructions
The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited, and
operation is not guaranteed if this restriction is not observed.
(5)
Notes on Sleep Mode and Mode Transitions
During sleep mode or mode transitions, do not write to the system control related registers (indicated by 'SYSTEM' in the
Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).
R01DS0261EJ0120 Rev.1.20
Sep 28, 2018
Page 42 of 170
RX230 Group, RX231 Group
4.1
4. I/O Registers
I/O Register Addresses (Address Order)
Table 4.1
List of I/O Registers (Address Order) (1/33)
Address
Module
Symbol
Register Name
Register
Symbol
0008 0000h
SYSTEM
Mode Monitor Register
0008 0006h
SYSTEM
0008 0008h
SYSTEM
0008 000Ch
Number of Access Cycles
Number
of Bits
Access
Size
MDMONR
16
16
3 ICLK
System Control Register 0
SYSCR0
16
16
3 ICLK
System Control Register 1
SYSCR1
16
16
3 ICLK
SYSTEM
Standby Control Register
SBYCR
16
16
3 ICLK
0008 0010h
SYSTEM
Module Stop Control Register A
MSTPCRA
32
32
3 ICLK
0008 0014h
SYSTEM
Module Stop Control Register B
MSTPCRB
32
32
3 ICLK
ICLK ≥ PCLK
ICLK
工商网监
湘ICP备2023018690号
