Datasheet
R01DS0385EJ0110
Rev.1.10
Feb 26, 2021
RA2L1 Group
Renesas Microcontrollers
Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 256-KB code flash memory, 32 KB SRAM, Capacitive Sensing Unit
(CTSU2), 12-bit A/D Converter, 12-bit D/A Converter, Security and Safety features.
Features
■ Arm Cortex-M23 Core
●
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Armv8-M architecture
Maximum operating frequency: 48 MHz
Arm Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: DWT, FPB, CoreSight™ MTB-M23
CoreSight Debug Port: SW-DP
■ Memory
●
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Up to 256-KB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
32 KB SRAM
Memory protection units
128-bit unique ID
■ Connectivity
● Serial Communications Interface (SCI) × 5
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Simple IIC
– Simple SPI
– Smart card interface
● Serial Peripheral Interface (SPI) × 2
● I2C bus interface (IIC) × 2
● CAN module (CAN)
●
●
●
●
●
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
Clock trim function for HOCO/MOCO/LOCO
IWDT-dedicated on-chip oscillator (15 kHz)
Clock out support
■ Up to 85 pins for general I/O ports
● 5-V tolerance, open drain, input pull-up
■ Operating Voltage
● VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
● Ta = -40℃ to +85℃
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
– 48-pin LQFP (7 mm × 7 mm, 0.50 mm pitch)
– 48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
● Ta = -40℃ to +105℃
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 80-pin LQFP (12 mm × 12 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
– 48-pin LQFP (7 mm × 7 mm, 0.50 mm pitch)
– 48-pin HWQFN (7 mm × 7 mm, 0.50 mm pitch)
■ Analog
●
●
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12-bit A/D Converter (ADC12)
12-bit D/A Converter (DAC12)
Low-Power Analog Comparator (ACMPLP) × 2
Temperature Sensor (TSN)
■ Timers
●
●
●
●
General PWM Timer 32-bit (GPT32) × 4
General PWM Timer 16-bit (GPT16) × 6
Low Power Asynchronous General Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ Safety
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●
●
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●
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ECC in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
■ Security and Encryption
● AES128/256
● True Random Number Generator (TRNG)
■ System and Power Management
●
●
●
●
●
●
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●
Low power modes
Switching regulator
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Human Machine Interface (HMI)
● Capacitive Sensing Unit (CTSU2)
■ Multiple Clock Sources
● Main clock oscillator (MOSC) （1 to 20 MHz）
● Sub-clock oscillator (SOSC) (32.768 kHz)
● High-speed on-chip oscillator (HOCO) (24/32/48/64 MHz)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 1 of 111
RA2L1 Datasheet
1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability.
The MCU in this series incorporates an energy-efficient Arm Cortex®-M23 32-bit core, that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
● Up to 256-KB code flash memory
● 32-KB SRAM
● 12-bit A/D Converter (ADC12)
● 12-bit D/A Converter (DAC12)
● Security features
1.1
Table 1.1
Function Outline
Arm core
Feature
Functional description
Arm Cortex-M23 core
Table 1.2
● Maximum operating frequency: up to 48 MHz
● Arm Cortex-M23 core:
– Revision: r1p0-00rel0
– Armv8-M architecture profile
– Single-cycle integer multiplier
– 19-cycle integer divider
● Arm Memory Protection Unit (Arm MPU):
– Armv8 Protected Memory System Architecture
– 8 protect regions
● SysTick timer:
– Driven by SYSTICCLK (LOCO) or ICLK
Memory
Feature
Functional description
Code flash memory
Maximum 256 KB of code flash memory.
Data flash memory
8 KB of data flash memory.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset.
SRAM
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3
System (1 of 2)
Feature
Functional description
Operating modes
Two operating modes:
● Single-chip mode
● SCI boot mode
Resets
The MCU provides 13 resets. lists the reset names and sources.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
See section x, Low Voltage Detection (LVD).
Clocks
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
●
●
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Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator (IWDTLOCO)
Clock out support
Page 2 of 111
RA2L1 Datasheet
Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.When measurement is
complete or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also
controls non-maskable interrupts.
Key Interrupt Function (KINT)
The key interrupt function (KINT) generates the key interrupt by detecting rising or falling edge
on the key interrupt input pins.
Low power modes
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Register write protection
The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
Memory Protection Unit (MPU)
The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function
are provided.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt or watchdog timer reset.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the
MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.
Table 1.4
Event link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
Table 1.6
Timers (1 of 2)
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, downcounter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
Port Output Enable for GPT (POEG)
The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
Low power Asynchronous General
Purpose Timer (AGT)
The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
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Feb 26, 2021
Page 3 of 111
RA2L1 Datasheet
Table 1.6
1. Overview
Timers (2 of 2)
Feature
Functional description
Realtime Clock (RTC)
The RTC has two operation modes, normal operation mode and low-consumption clock mode. In
each of the operation mode, the RTC has two counting modes, calendar count mode and binary
count mode, that are used by switching register settings. For calendar count mode, the RTC has
a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For
binary count mode, the RTC counts seconds and retains the information as a serial value. Binary
count mode can be used for calendars other than the Gregorian (Western) calendar.
Table 1.7
Communication interfaces
Feature
Functional description
Serial Communications Interface (SCI)
The Serial Communications Interface (SCI) × 5 channels have asynchronous and synchronous
serial interfaces:
● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
● 8-bit clock synchronous interface
● Simple IIC (master-only)
● Simple SPI
● Smart card interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol. SCIn (n = 0) has FIFO buffers to enable continuous and full-duplex
communication, and the data transfer speed can be configured independently using an on-chip
baud rate generator.
I2C bus interface (IIC)
The I2C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset
of the NXP I2C (Inter-Integrated Circuit) bus interface functions.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial
communications with multiple processors and peripheral devices.
Control Area Network (CAN)
The Controller Area Network (CAN) module uses a message-based protocol to receive and
transmit data between multiple slaves and masters in electromagnetically noisy applications. The
module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32
mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO
modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN
module requires an additional external CAN transceiver.
Table 1.8
Analog
Feature
Functional description
12-bit A/D Converter (ADC12)
A 12-bit successive approximation A/D converter is provided. Up to 19 analog input channels are
selectable. Temperature sensor output and internal reference voltage are selectable for
conversion.
12-bit D/A Converter (DAC12)
A 12-bit D/A converter (DAC12) is provided.
Temperature Sensor (TSN)
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.
Low-Power Analog Comparator
(ACMPLP)
The Low-Power Analog Comparator (ACMPLP) compares a reference input voltage with an
analog input voltage. Comparator channels ACMPLP0 and ACMPLP1 are independent of each
other.
The comparison result of the reference input voltage and analog input voltage can be read by
software. The comparison result can also be output externally. The reference input voltage can
be selected from either an input to the CMPREFi (i = 0, 1) pin or from the internal reference
voltage (Vref) generated internally in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed mode
decreases the response delay time, but increases current consumption. Setting low-speed mode
increases the response delay time, but decreases current consumption.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 4 of 111
RA2L1 Datasheet
Table 1.9
1. Overview
Human machine interfaces
Feature
Functional description
Capacitive Sensing Unit (CTSU2)
The Capacitive Sensing Unit (CTSU2) measures the electrostatic capacitance of the sensor.
Changes in the electrostatic capacitance are determined by software that enables the CTSU to
detect whether a finger is in contact with the sensor. The electrode surface of the sensor is
usually enclosed with a dielectric film so that a finger does not come into direct contact with the
electrode.
Table 1.10
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generation polynomials are available. The snoop
function allows to monitor the access to specific addresses. This function is useful in applications
that require CRC code to be generated automatically in certain events, such as monitoring writes
to the serial transmit buffer and reads from the serial receive buffer.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected
condition applies, 16-bit data is compared and an interrupt can be generated.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 5 of 111
RA2L1 Datasheet
1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Memory
256-KB code flash
Bus
Arm Cortex-M23
MPU
MPU
System
POR/LVD
MOSC/SOSC
8-KB data flash
Reset
NVIC
32-KB SRAM
Mode control
System timer
Test and DBG Interface
DTC
Timers
(H/M/L) OCO
Power control
DMA
GPT32 × 4
GPT16 × 6
Clocks
Communication interfaces
ICU
CAC
KINT
Register write
protection
Human machine interfaces
CTSU
SCI × 5
AGT × 2
IIC × 2
RTC
SPI × 2
CAN × 1
WDT/IWDT
Event link
Data processing
Analogs
ELC
CRC
ADC12
TSN
Security
DOC
DAC12 × 1
ACMPLP × 2
AES + TRNG
Figure 1.1
1.3
Block diagram
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a
list of products.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 6 of 111
RA2L1 Datasheet
1. Overview
R 7 F A2 L 1 AB 3 C F P
Package type
FP: LQFP 100 pins 0.5 mm pitch
FN: LQFP 80 pins 0.5 mm pitch
FM: LQFP 64 pins 0.5 mm pitch
FL: LQFP 48 pins 0.5 mm pitch
NE: HWQFN 48 pins 0.5 mm pitch
Quality ID
C: Industrial applications
D: Consumer applications
Operating temperature
2: -40°C to +85°C
3: -40°C to +105°C
Code flash memory size
B: 256 KB
9: 128 KB
Feature set
A: Standard and security
Group name
L1: Low Power group
Core
2: Arm Cortex-M23
RA Family (Renesas Advanced)
Flash memory
Renesas microcontroller unit
Renesas
Figure 1.2
Part numbering scheme
Table 1.11
Product list (1 of 2)
Product part number
Package code
Code flash
Data
flash
SRAM
Operating
temperature
R7FA2L1AB3CFP
PLQP0100KB-B
256 KB
8 KB
32 KB
-40 to +105°C
R7FA2L1AB3CFN
PLQP0080KB-B
R7FA2L1AB3CFM
PLQP0064KB-C
R7FA2L1AB3CFL
PLQP0048KB-B
R7FA2L1AB3CNE
PWQN0048KC-A
R7FA2L1AB2DFP
PLQP0100KB-B
R7FA2L1AB2DFN
PLQP0080KB-B
R7FA2L1AB2DFM
PLQP0064KB-C
R7FA2L1AB2DFL
PLQP0048KB-B
R7FA2L1AB2DNE
PWQN0048KC-A
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
-40 to +85°C
Page 7 of 111
RA2L1 Datasheet
Table 1.11
1. Overview
Product list (2 of 2)
Product part number
Package code
Code flash
Data
flash
SRAM
Operating
temperature
R7FA2L1A93CFP
PLQP0100KB-B
128 KB
8 KB
32 KB
-40 to +105°C
R7FA2L1A93CFN
PLQP0080KB-B
R7FA2L1A93CFM
PLQP0064KB-C
R7FA2L1A93CFL
PLQP0048KB-B
R7FA2L1A93CNE
PWQN0048KC-A
R7FA2L1A92DFP
PLQP0100KB-B
R7FA2L1A92DFN
PLQP0080KB-B
R7FA2L1A92DFM
PLQP0064KB-C
R7FA2L1A92DFL
PLQP0048KB-B
R7FA2L1A92DNE
PWQN0048KC-A
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
-40 to +85°C
Page 8 of 111
RA2L1 Datasheet
1.4
1. Overview
Function Comparison
Table 1.12
Function Comparison
R7FA2L1A
B3CFP
Parts number
Pin count
R7FA2L1A
93CFP
R7FA2L1A
B3CFN
100
Package
Code flash memory
R7FA2L1A
93CFN
R7FA2L1A
B3CFM
80
64
LQFP
LQFP
LQFP
LQFP
LQFP
256 KB
128 KB
256 KB
128 KB
256 KB
128 KB
8 KB
SRAM
32 KB
Parity
16 KB
ECC
16 KB
CPU clock
48 MHz
Sub-clock
oscillator
Yes
ICU
Yes
KINT
Yes
DMA
DTC
Yes
Timers
GPT32
128 KB
6
3
AGT
2
RTC
Yes
WDT/IWDT
Yes
Communicatio SCI
n
IIC
5
SPI
2
CAN
Yes
2
19
17
13
DAC12
1
ACMPLP
2
TSN
Yes
HMI
CTSU
Data
processing
CRC
Yes
DOC
Yes
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
256 KB
4
GPT16
Security
LQFP/QFN
5
ELC
ADC12
LQFP/QFN
8
Event control
Analog
R7FA2L1A
93CFL
R7FA2L1A
93CNE
48
LQFP
Data flash memory
System
R7FA2L1A
93CFM
R7FA2L1A
B3CFL
R7FA2L1A
B3CNE
32
30
20
AES and TRNG
Page 9 of 111
RA2L1 Datasheet
1.5
1. Overview
Pin Functions
Table 1.13
Pin functions (1 of 3)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. Place the capacitor close to
the pin.
VCL
I/O
Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
VCC_DCDC
Input
Switching regulator power supply pin
VLO
I/O
Switching regulator pin
VSS_DCDC
Input
Switching regulator ground pin. Connect it to the system power
supply (0 V).
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
XCIN
Input
XCOUT
Output
CLKOUT
Output
Clock output pin
Operating mode control
MD
Input
Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC
CACREF
Input
Measurement reference clock input pin
On-chip debug
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ7
Input
Maskable interrupt request pins
GTETRGA, GTETRGB
Input
External trigger input pins
GTIOCnA (n = 0 to 9),
GTIOCnB (n = 0 to 9)
I/O
Input capture, output compare, or PWM output pins
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
AGTEE0, AGTEE1
Input
External event input enable signals
AGTIO0, AGTIO1
I/O
External event input and pulse output pins
AGTO0, AGTO1
Output
Pulse output pins
AGTOA0, AGTOA1
Output
Output compare match A output pins
AGTOB0, AGTOB1
Output
Output compare match B output pins
Clock
Interrupt
GPT
AGT
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
Page 10 of 111
RA2L1 Datasheet
Table 1.13
1. Overview
Pin functions (2 of 3)
Function
Signal
I/O
Description
RTC
RTCOUT
Output
Output pin for 1-Hz or 64-Hz clock
SCI
SCKn (n = 0 to 3, 9)
I/O
Input/output pins for the clock (clock synchronous mode)
RXDn (n = 0 to 3, 9)
Input
Input pins for received data (asynchronous mode/clock synchronous
mode)
TXDn (n = 0 to 3, 9)
Output
Output pins for transmitted data (asynchronous mode/clock
synchronous mode)
CTSn_RTSn (n = 0 to 3,
9)
I/O
Input/output pins for controlling the start of transmission and
reception (asynchronous mode/clock synchronous mode), activelow.
SCLn (n = 0 to 3, 9)
I/O
Input/output pins for the IIC clock (simple IIC mode)
SDAn (n = 0 to 3, 9)
I/O
Input/output pins for the IIC data (simple IIC mode)
SCKn (n = 0 to 3, 9)
I/O
Input/output pins for the clock (simple SPI mode)
MISOn (n = 0 to 3, 9)
I/O
Input/output pins for slave transmission of data (simple SPI mode)
MOSIn (n = 0 to 3, 9)
I/O
Input/output pins for master transmission of data (simple SPI mode)
SSn (n = 0 to 3, 9)
Input
Chip-select input pins (simple SPI mode), active-low
SCLn (n = 0, 1)
I/O
Input/output pins for the clock
SDAn (n = 0, 1)
I/O
Input/output pins for data
RSPCKA, RSPCKB
I/O
Clock input/output pin
MOSIA, MOSIB
I/O
Input or output pins for data output from the master
MISOA, MISOB
I/O
Input or output pins for data output from the slave
SSLA0, SSLB0
I/O
Input or output pin for slave selection
SSLA1 to SSLA3, SSLB1
to SSLB3
Output
Output pins for slave selection
CRX0
Input
Receive data
CTX0
Output
Transmit data
AVCC0
Input
Analog voltage supply pin for the ADC12, DAC12
AVSS0
Input
Analog ground pin for the ADC12, DAC12
VREFH0
Input
Analog reference voltage supply pin for the ADC12. Connect this pin
to AVCC0 when not using the ADC12.
VREFL0
Input
Analog reference ground pin for the ADC12. Connect this pin to
AVSS0 when not using the ADC12.
AN000 to AN014, AN017
to AN020
Input
Input pins for the analog signals to be processed by the A/D
converter.
ADTRG0
Input
Input pin for the external trigger signals that start the A/D
conversion, active-low.
DAC12
DA0
Output
Output pin for the analog signals processed by the D/A converter.
ACMPLP
VCOUT
Output
Comparator output pin
CMPREF0, CMPREF1
Input
Reference voltage input pins
CMPIN0, CMPIN1
Input
Analog voltage input pins
IIC
SPI
CAN
Analog power supply
ADC12
CTSU
KINT
TS00, TS02-CFC, TS04
Input
to TS07, TS08-CFC to
TS16-CFC, TS17, TS18,
TS21 to TS25, TS26-CFC
to TS35-CFC
Capacitive touch detection pins (touch pins)
TSCAP
—
Secondary power supply pin for the touch driver
KR00 to KR07
Input
Key interrupt input pins
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 11 of 111
RA2L1 Datasheet
Table 1.13
1. Overview
Pin functions (3 of 3)
Function
Signal
I/O
Description
I/O ports
P000 to P008, P010 to
P015
I/O
General-purpose input/output pins
P100 to P115
I/O
General-purpose input/output pins
P200
Input
General-purpose input pin
P201 to P208, P212,
P213
I/O
General-purpose input/output pins
P214, P215
Input
General-purpose input pins
P300 to P307
I/O
General-purpose input/output pins
P400 to P415
I/O
General-purpose input/output pins
P500 to P505
I/O
General-purpose input/output pins
P600 to P603, P608 to
P610
I/O
General-purpose input/output pins
P708, P714
I/O
General-purpose input/output pins
P808, P809
I/O
General-purpose input/output pins
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 12 of 111
RA2L1 Datasheet
1.6
1. Overview
Pin Assignments
Figure 1.3
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602
P603
VSS
VCC
P610
P609
P608
P115
P114
P113
P112
P111
P110
P109
P108/SWDIO
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P100
74
75
Figure 1.3 and Figure 1.4 show the pin assignments from the top view.
P500
76
50
P501
77
49
P300/SWCLK
P301
P502
78
48
P302
P503
79
47
P303
P504
80
46
P809
P505
81
45
P808
VCC
82
44
P304
VSS
83
43
P305
P015
84
42
P306
P014
85
41
P307
P013
86
40
P200
P012
87
39
P201/MD
AVCC0
88
38
RES
AVSS0
89
37
VCC
P011/VREFL0
90
36
VSS
P010/VREFH0
91
35
P202
P008
92
34
P203
P007
93
33
P204
P006
94
32
P205
P005
95
31
P206
P004
96
30
P207
P003
97
29
P208
P002
98
28
VCC_DCDC
P001
99
27
VLO
P000
100
26
VSS_DCDC
14
15
16
17
18
19
20
21
22
23
24
25
P212/EXTAL
VCC
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
9
VCL
13
8
P714
P213/XTAL
7
P406
12
6
P405
VSS
5
P404
P214/XCOUT
4
P403
11
3
P402
P215/XCIN
2
10
1
P400
P401
R7FA2L1AB3CFP
Pin assignment for LQFP 100-pin (top view)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 13 of 111
P104
P105
P106
P107
P600
P601
VSS
VCC
P115
P114
P113
P112
P111
P110
P109
P108/SWDIO
56
55
54
53
52
51
49
47
46
45
44
43
42
41
48
P103
57
50
P101
P102
61
40
62
39
P301
P502
63
38
P302
P503
64
37
P303
P504
65
36
P809
P015
66
35
P808
P014
67
34
P304
P013
68
33
P305
P012
69
32
P306
AVCC0
70
31
P200
AVSS0
71
30
P201/MD
P011/VREFL0
72
29
RES
P010/VREFH0
73
28
P204
P006
74
27
P205
P005
75
26
P206
P004
76
25
P207
P003
77
24
P208
P002
78
23
VCC_DCDC
P001
79
22
VLO
P000
80
21
VSS_DCDC
14
15
16
17
18
19
20
P708
P415
P411
P410
P409
P408
P407
P214/XCOUT
13
9
P215/XCIN
12
8
VCC
7
VCL
P212/EXTAL
6
P714
11
5
VSS
4
P403
P406
P213/XTAL
3
P402
10
2
1
P401
R7FA2L1AB3CFN
P400
Figure 1.5
58
P100
P500
P501
P300/SWCLK
P100
P101
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110
P109
P108/SWDIO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Pin assignment for LQFP 80-pin (top view)
P500
49
32
P300/SWCLK
P501
50
31
P301
P502
51
30
P302
P015
52
29
P303
P014
53
28
P304
P013
54
27
P200
P012
55
26
P201/MD
AVCC0
56
25
RES
AVSS0
57
24
P204
P011/VREFL0
58
23
P205
P010/VREFH0
59
22
P206
P004
60
21
P207
P003
61
20
P208
P002
62
19
VCC_DCDC
P001
63
18
VLO
P000
64
17
VSS_DCDC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P401
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
R7FA2L1AB3CFM
P400
Figure 1.4
59
1. Overview
60
RA2L1 Datasheet
Pin assignment for LQFP 64-pin (top view)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 14 of 111
P103
P104
VSS
VCC
P112
P111
P110
P109
P108/SWDIO
32
31
30
29
28
27
26
25
P101
P102
33
37
24
P300/SWCLK
P015
38
23
P301
P014
39
22
P302
P013
40
21
P200
P012
41
20
P201/MD
19
RES
18
P206
P207
AVSS0
42
43
R7FA2L1AB3CFL
10
11
12
P409
P408
P407
P110
27
9
VCC
P111
28
8
P212/EXTAL
P112
7
P213/XTAL
5
6
VSS
P215/XCIN
P214/XCOUT
4
3
VCL
2
P401
1
29
VSS_DCDC
VCC
13
30
48
VSS
VLO
P000
P104
14
P103
47
31
VCC_DCDC
P001
32
15
33
46
P102
P208
P002
34
16
P101
45
P100
P010/VREFH0
36
44
35
P011/VREFL0
17
P400
Figure 1.7
34
P100
P500
AVCC0
26
P109
25 P108/SWDIO
Pin assignment for LQFP 48-pin (top view)
P500
37
24
P300/SWCLK
P015
38
23
P301
P014
39
22
P302
P013
40
21
P200
P012
41
20
P201/MD
AVCC0
42
19
RES
AVSS0
43
18
P206
P011/VREFL0
44
17
P207
P010/VREFH0
45
16
P208
P002
46
15
VCC_DCDC
P001
47
14
VLO
P000
48
13
VSS_DCDC
1
2
3
4
5
6
7
8
9
10
11
12
P401
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
R7FA2L1AB3CNE
P400
Figure 1.6
35
1. Overview
36
RA2L1 Datasheet
Pin assignment for QFN 48-pin (top view)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 15 of 111
RA2L1 Datasheet
Pin Lists
Pin list (1 of 4)
Interrupt
CTSU
DAC12
SPI
ACMPLP
HMI
ADC12
Analogs
IIC
RTC
GPT
AGT
I/O ports
Power, System,
Clock,
Debug, CAC
LQFP48/QFN48
LQFP64
LQFP80
LQFP100
Communication interfaces
GPT_OPS,
POEG
Timers
Num.
SCI
Table 1.14
CAN
1.7
1. Overview
1
1
1
1
CACREF
_C
P400
AGTIO1_
C
—
GTIOC6A
_A
—
—
SCK0_B/
SCK1_B
SCL0_A
—
—
—
—
—
IRQ0_A
2
2
2
2
—
P401
—
GTETRG
A_B
GTIOC6B
_A
—
CTX0_B
CTS0_RT
S0_B/
SS0_B/
TXD1_B/
MOSI1_B/
SDA1_B
SDA0_A
—
—
—
—
—
IRQ5
3
3
3
—
—
P402
AGTIO0_
E/
AGTIO1_
D
—
—
—
CRX0_B
RXD1_B/
MISO1_B/
SCL1_B
—
—
—
—
—
TS18
IRQ4
4
4
4
—
—
P403
AGTIO0_
F/
AGTIO1_
E
—
GTIOC3A
_B
—
—
CTS1_RT
S1_B/
SS1_B
—
—
—
—
—
TS17
—
5
—
—
—
—
P404
—
—
GTIOC3B
_B
—
—
—
—
—
—
—
—
—
—
6
—
—
—
—
P405
—
—
GTIOC1A
_B
—
—
—
—
—
—
—
—
—
—
7
5
—
—
—
P406
—
—
GTIOC1B
_B
—
—
—
—
—
—
—
—
—
—
8
6
—
—
—
P714
—
—
—
—
—
—
—
—
—
—
—
—
—
9
7
5
3
VCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
8
6
4
XCIN
P215
—
—
—
—
—
—
—
—
—
—
—
—
—
11
9
7
5
XCOUT
P214
—
—
—
—
—
—
—
—
—
—
—
—
—
12
10
8
6
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
11
9
7
XTAL
P213
—
GTETRG
A_D
GTIOC0A
_D
—
—
TXD1_A/
MOSI1_A/
SDA1_A
—
—
—
—
—
—
IRQ2_B
14
12
10
8
EXTAL
P212
AGTEE1
GTETRG
B_D
GTIOC0B
_D
—
—
RXD1_A/
MISO1_A/
SCL1_A
—
—
—
—
—
—
IRQ3_B
15
13
11
9
VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
14
—
—
—
P708
—
—
—
—
—
RXD1_D/
MISO1_D
/SCL1_D
—
SSLA3_B
—
—
—
—
—
17
15
—
—
—
P415
—
—
GTIOC0A
_C
—
—
—
—
SSLA2_B
—
—
—
—
—
18
—
—
—
—
P414
—
—
GTIOC0B
_C
—
—
—
—
SSLA1_B
—
—
—
—
—
19
—
—
—
—
P413
—
GTOUUP
_B
—
—
—
CTS0_RT
S0_E/
SS0_E
—
SSLA0_B
—
—
—
—
—
20
—
—
—
—
P412
—
GTOULO
_B
—
—
—
SCK0_E
—
RSPCKA
_B
—
—
—
—
—
21
16
12
—
—
P411
AGTOA1
GTOVUP
_B
GTIOC9A
_A
—
—
TXD0_B/
MOSI0_B/
SDA0_B/
CTS3_RT
S3_A/
SS3_A
—
MOSIA_B
—
—
—
TS07
IRQ4_B
22
17
13
—
—
P410
AGTOB1
GTOVLO
_B
GTIOC9B
_A
—
—
RXD0_B/
MISO0_B/
SCL0_B/
SCK3_A
—
MISOA_B
—
—
—
TS06
IRQ5_B
23
18
14
10
—
P409
—
GTOWUP
_B
GTIOC5A
_B
—
—
TXD3_A/
MOSI3_A/
SDA3_A
—
—
—
—
—
TS05
IRQ6_B
24
19
15
11
—
P408
—
GTOWLO
_B
GTIOC5B
_B
—
—
CTS1_RT
S1_D/
SS1_D/
RXD3_A/
MISO3_A/
SCL3_A
SCL0_C
—
—
—
—
TS04
IRQ7_B
25
20
16
12
—
P407
AGTIO0_
C
—
—
RTCOUT
—
CTS0_RT
S0_D/
SS0_D
SDA0_B
SSLB3_A
ADTRG0_
B
—
—
—
—
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 16 of 111
RA2L1 Datasheet
Pin list (2 of 4)
Interrupt
CTSU
DAC12
ACMPLP
HMI
ADC12
IIC
SCI
RTC
GPT
Analogs
SPI
Communication interfaces
GPT_OPS,
POEG
AGT
I/O ports
Power, System,
Clock,
Debug, CAC
LQFP48/QFN48
LQFP64
Timers
LQFP80
LQFP100
Num.
CAN
Table 1.14
1. Overview
26
21
17
13
VSS_DC
DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27
22
18
14
VLO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28
23
19
15
VCC_DC
DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29
24
20
16
—
P208
AGTOB0_
A
—
—
—
—
—
—
—
—
—
—
—
—
30
25
21
17
—
P207
—
—
—
—
—
—
—
—
—
—
—
—
—
31
26
22
18
—
P206
—
GTIU_A
—
—
—
RXD0_D/
MISO0_D
/SCL0_D
SDA1_A
SSLB1_A
—
—
—
—
IRQ0
32
27
23
—
CLKOUT_
A
P205
AGTO1
GTIV_A
GTIOC4A
_B
—
—
TXD0_D/
MOSI0_D
/SDA0_D/
CTS9_RT
S9_A/
SS9_A
SCL1_A
SSLB0_A
—
—
—
—
IRQ1
33
28
24
—
CACREF
_A
P204
AGTIO1_
A
GTIW_A
GTIOC4B
_B
—
—
SCK0_D/
SCK9_A
SCL0_B
RSPCKB
_A
—
—
—
TS00
—
34
—
—
—
—
P203
—
—
—
—
—
CTS2_RT
S2_A/
SS2_A/
TXD9_A/
MOSI9_A/
SDA9_A
—
MOSIB_A
—
—
—
—
—
35
—
—
—
—
P202
—
—
—
—
—
SCK2_A/
RXD9_A/
MISO9_A/
SCL9_A
—
MISOB_A
—
—
—
—
—
36
—
—
—
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
37
—
—
—
VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
38
29
25
19
RES
—
—
—
—
—
—
—
—
—
—
—
—
—
—
39
30
26
20
MD
P201
—
—
—
—
—
—
—
—
—
—
—
—
—
40
31
27
21
—
P200
—
—
—
—
—
—
—
—
—
—
—
—
NMI
41
—
—
—
—
P307
—
—
—
—
—
—
—
—
—
—
—
—
—
42
32
—
—
—
P306
—
—
—
—
—
—
—
—
—
—
—
—
—
43
33
—
—
—
P305
—
—
—
—
—
—
—
—
—
—
—
—
—
44
34
28
—
—
P304
—
—
GTIOC7A
_A
—
—
—
—
—
—
—
—
—
—
45
35
—
—
—
P808
—
—
—
—
—
—
—
—
—
—
—
—
—
46
36
—
—
—
P809
—
—
—
—
—
—
—
—
—
—
—
—
—
47
37
29
—
—
P303
—
—
GTIOC7B
_A
—
—
—
—
—
—
—
—
TS02CFC
—
48
38
30
22
—
P302
—
GTOUUP
_A
GTIOC4A
_A
—
—
TXD2_A/
MOSI2_A/
SDA2_A
—
SSLB3_B
—
—
—
TS08CFC
IRQ5_A
49
39
31
23
—
P301
AGTIO0_
D
GTOULO
_A
GTIOC4B
_A
—
—
RXD2_A/
MISO2_A/
SCL2_A/
CTS9_RT
S9_D/
SS9_D
—
SSLB2_B
—
—
—
TS09CFC
IRQ6_A
50
40
32
24
SWCLK
P300
—
GTOUUP
_C
GTIOC0A
_A
—
—
—
—
SSLB1_B
—
—
—
—
—
51
41
33
25
SWDIO
P108
—
GTOULO
_C
GTIOC0B
_A
—
—
CTS9_RT
S9_B/
SS9_B
—
SSLB0_B
—
—
—
—
—
52
42
34
26
CLKOUT_
B
P109
—
GTOVUP
_A
GTIOC1A
_A
—
CTX0_A
SCK1_E/
TXD9_B/
MOSI9_B/
SDA9_B
—
MOSIB_B
—
—
—
TS10CFC
—
53
43
35
27
—
P110
—
GTOVLO
_A
GTIOC1B
_A
—
CRX0_A
CTS2_RT
S2_B/
SS2_B/
RXD9_B/
MISO9_B/
SCL9_B
—
MISOB_B
—
—
VCOUT
TS11CFC
IRQ3_A
54
44
36
28
—
P111
AGTOA0
—
GTIOC3A
_A
—
—
SCK2_B/
SCK9_B
—
RSPCKB
_B
—
—
—
TS12CFC
IRQ4_A
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 17 of 111
RA2L1 Datasheet
Pin list (3 of 4)
Analogs
HMI
AGTOB0
—
GTIOC3B
_A
—
—
SCK1_D/
TXD2_B/
MOSI2_B/
SDA2_B
—
SSLB0_C
—
—
—
TSCAP-C
—
56
46
38
—
—
P113
—
—
GTIOC2A
_C
—
—
—
—
—
—
—
—
TS27CFC
—
57
47
—
—
—
P114
—
—
GTIOC2B
_C
—
—
—
—
—
—
—
—
TS29CFC
—
58
48
—
—
—
P115
—
—
GTIOC4A
_C
—
—
—
—
—
—
—
—
TS35CFC
—
59
—
—
—
—
P608
—
—
GTIOC4B
_C
—
—
—
—
—
—
—
—
—
—
60
—
—
—
—
P609
—
—
GTIOC5A
_C
—
—
—
—
—
—
—
—
—
—
61
—
—
—
—
P610
—
—
GTIOC5B
_C
—
—
—
—
—
—
—
—
—
—
62
49
39
30
VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
63
50
40
31
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
64
—
—
—
—
P603
—
—
GTIOC7A
_B
—
—
CTS9_RT
S9_C/
SS9_C
—
—
—
—
—
—
—
65
—
—
—
—
P602
—
—
GTIOC7B
_B
—
—
TXD9_C/
MOSI9_C
/SDA9_C
—
—
—
—
—
—
—
66
51
—
—
—
P601
—
—
GTIOC6A
_C
—
—
RXD9_C/
MISO9_C
/SCL9_C
—
—
—
—
—
—
—
67
52
—
—
—
P600
—
—
GTIOC6B
_C
—
—
SCK9_C
—
—
—
—
—
—
—
68
53
41
—
—
P107
—
—
GTIOC8A
_A
—
—
—
—
—
—
—
—
—
KR07
69
54
42
—
—
P106
—
—
GTIOC8B
_A
—
—
—
—
SSLA3_A
—
—
—
—
KR06
70
55
43
—
—
P105
—
GTETRG
A_C
GTIOC1A
_C
—
—
—
—
SSLA2_A
—
—
—
TS34CFC
KR05/
IRQ0_B
71
56
44
32
—
P104
—
GTETRG
B_B
GTIOC1B
_C
—
—
RXD0_C/
MISO0_C
/SCL0_C
—
SSLA1_A
—
—
—
TS13CFC
KR04/
IRQ1_B
72
57
45
33
—
P103
—
GTOWUP
_A
GTIOC2A
_A
—
CTX0_C
CTS0_RT
S0_A/
SS0_A
—
SSLA0_A
—
—
CMPREF
1
TS14CFC
KR03
73
58
46
34
—
P102
AGTO0
GTOWLO
_A
GTIOC2B
_A
—
CRX0_C
SCK0_A/
TXD2_D/
MOSI2_D
/SDA2_D
—
RSPCKA
_A
ADTRG0_
A
—
CMPIN1
TS15CFC
KR02
74
59
47
35
—
P101
AGTEE0
GTETRG
B_A
GTIOC5A
_A
—
—
TXD0_A/
MOSI0_A/
SDA0_A/
CTS1_RT
S1_A/
SS1_A
SDA1_B
MOSIA_A
—
—
CMPREF
0
TS16CFC
KR01/
IRQ1_A
75
60
48
36
—
P100
AGTIO0_
A
GTETRG
A_A
GTIOC5B
_A
—
—
RXD0_A/
MISO0_A/
SCL0_A/
SCK1_A
SCL1_B
MISOA_A
—
—
CMPIN0
TS26CFC
KR00/
IRQ2_A
76
61
49
37
—
P500
—
GTIU_B
GTIOC2A
_B
—
—
—
—
—
—
—
—
—
—
77
62
50
—
—
P501
—
GTIV_B
GTIOC2B
_B
—
—
TXD1_C/
MOSI1_C
/SDA1_C
—
—
AN017
—
—
—
—
78
63
51
—
—
P502
—
GTIW_B
GTIOC3B
_C
—
—
RXD1_C/
MISO1_C
/SCL1_C
—
—
AN018
—
—
—
—
79
64
—
—
—
P503
—
GTETRG
A_E
—
—
—
SCK1_C
—
—
AN019
—
—
—
—
80
65
—
—
—
P504
—
GTETRG
B_E
—
—
—
CTS1_RT
S1_C/
SS1_C
—
—
AN020
—
—
—
—
81
—
—
—
—
P505
—
—
—
—
—
—
—
—
—
—
—
—
—
82
—
—
—
VCC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
CTSU
SPI
IIC
SCI
RTC
Interrupt
P112
DAC12
—
ADC12
29
CAN
37
GPT
45
LQFP64
55
LQFP80
AGT
GPT_OPS,
POEG
Communication interfaces
I/O ports
Power, System,
Clock,
Debug, CAC
Timers
LQFP48/QFN48
LQFP100
Num.
ACMPLP
Table 1.14
1. Overview
Page 18 of 111
RA2L1 Datasheet
Pin list (4 of 4)
Interrupt
CTSU
DAC12
ACMPLP
HMI
ADC12
IIC
SCI
RTC
GPT
Analogs
SPI
Communication interfaces
GPT_OPS,
POEG
AGT
I/O ports
Power, System,
Clock,
Debug, CAC
LQFP48/QFN48
LQFP64
Timers
LQFP80
LQFP100
Num.
CAN
Table 1.14
1. Overview
83
—
—
—
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
84
66
52
38
—
P015
—
—
—
—
—
—
—
—
AN010
—
—
TS28CFC
IRQ7_A
85
67
53
39
—
P014
—
—
—
—
—
—
—
—
AN009
DA0
—
—
—
86
68
54
40
—
P013
—
—
—
—
—
—
—
—
AN008
—
—
TS33CFC
—
87
69
55
41
—
P012
—
—
—
—
—
—
—
—
AN007
—
—
TS32CFC
—
88
70
56
42
AVCC0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
89
71
57
43
AVSS0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
90
72
58
44
VREFL0
P011
—
—
—
—
—
—
—
—
AN006
—
—
TS31CFC
—
91
73
59
45
VREFH0
P010
—
—
—
—
—
—
—
—
AN005
—
—
TS30CFC
—
92
—
—
—
—
P008
—
—
—
—
—
—
—
—
AN014
—
—
—
—
93
—
—
—
—
P007
—
—
—
—
—
—
—
—
AN013
—
—
—
—
94
74
—
—
—
P006
—
—
—
—
—
—
—
—
AN012
—
—
—
—
95
75
—
—
—
P005
—
—
—
—
—
—
—
—
AN011
—
—
—
—
96
76
60
—
—
P004
—
—
—
—
—
—
—
—
AN004
—
—
TS25
IRQ3
97
77
61
—
—
P003
—
—
—
—
—
—
—
—
AN003
—
—
TS24
—
98
78
62
46
—
P002
—
—
—
—
—
—
—
—
AN002
—
—
TS23
IRQ2
99
79
63
47
—
P001
—
—
—
—
—
—
—
—
AN001
—
—
TS22
IRQ7
100
80
64
48
—
P000
—
—
—
—
—
—
—
—
AN000
—
—
TS21
IRQ6
Note:
Several pin names have the added suffix of _A, _B, _C, _D, _E and _F. The suffix can be ignored when assigning functionality.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 19 of 111
RA2L1 Datasheet
2.
2. Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = VCC_DCDC*2 = 1.6 to 5.5 V, VREFH0 = 1.6 V to VCC
VSS = AVSS0 = VREFL0 = 0 V, Ta = Topr
Note 1. The typical condition is set to VCC = 3.3 V.
Note 2. When VCC_DCDC is used. VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V.
Figure 2.1 shows the timing conditions.
For example, P300
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The measurement conditions of the timing specifications for each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities for each pin to meet the conditions of your system.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin
is mixed, the AC characteristics of each function are not guaranteed.
2.1
Absolute Maximum Ratings
Table 2.1
Absolute maximum ratings (1 of 2)
Parameter
Symbol
Value
Unit
Power supply voltage
VCC
-0.5 to +6.5
V
5V-tolerant ports*1
Vin
-0.3 to +6.5
V
P000 to P008, P010 to P015
Vin
-0.3 to AVCC0 + 0.3
V
Others
Vin
-0.3 to VCC + 0.3
V
Reference power supply voltage
VREFH0
-0.3 to +6.5
V
Analog power supply voltage
AVCC0
-0.5 to +6.5
V
Switching regulator power supply voltage
VCC_DCDC
-0.5 to +6.5
V
Analog input voltage
VAN
-0.3 to AVCC0 + 0.3
V
-0.3 to VCC + 0.3
V
Input voltage
When AN000 to AN014 are
used
When AN017 to AN020 are
used
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 20 of 111
RA2L1 Datasheet
Table 2.1
2. Electrical Characteristics
Absolute maximum ratings (2 of 2)
Parameter
Symbol
Value
Unit
Operating temperature*2 *3 *4
Topr
-40 to +85
-40 to +105
°C
Storage temperature
Tstg
-55 to +125
°C
Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of
such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause
degradation of internal elements.
Note 2. See section 2.2.1. Tj/Ta Definition.
Note 3. Contact Renesas Electronics sales office for information on derating operation under Ta = +85°C to +105°C.
Derating is the systematic reduction of load for improved reliability.
Note 4. The upper limit of the operating temperature is 85°C or 105°C, depending on the product.
Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors with high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, and between the
VREFH0 and VREFL0 pins when VREFH0 is selected as the high potential reference voltage for the
ADC12. Place capacitors of the following value as close as possible to every power supply pin and use
the shortest and heaviest possible traces:
● VCC and VSS: about 0.1 µF
● AVCC0 and AVSS0: about 0.1 µF
● VREFH0 and VREFL0: about 0.1 µF
Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. Connect the VCC_DCDC pin to a VSS_DCDC pin
by a 1.0 µF capacitor. Each capacitor must be placed close to the pin.
Table 2.2
Recommended operating conditions
Parameter
Symbol
Min
Typ
Max
Unit
Power supply voltages
VCC*1 *2
1.6
—
5.5
V
VSS
—
0
—
V
2.4
—
5.5
V
Switching regulator power supply voltage
VCC_DCDC
VCC_DCDC = VCC
Analog power supply voltages
AVCC0*1 *2
1.6
—
5.5
V
AVSS0
—
0
—
V
1.6
—
AVCC0 V
—
0
—
VREFH0
When used as ADC12
Reference
VREFL0
V
Note 1. Use AVCC0 and VCC under the following conditions:
AVCC0 = VCC
Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pins.
When powering off the VCC and AVCC0 pins, power them off at the same time or the AVCC0 pin first and then the VCC pins.
2.2
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
—
125
°C
High-speed mode
Middle-speed mode
Low-speed mode
Subosc-speed mode
105*1
Note:
Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL +
ICCmax × VCC.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 21 of 111
RA2L1 Datasheet
2. Electrical Characteristics
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. If the part number shows the operation
temperature at 85°C, then the maximum value of Tj is 105°C, otherwise it is 125°C.
2.2.2
I/O VIH, VIL
Table 2.4
I/O VIH, VIL
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH
VCC × 0.7
—
5.8
V
—
VIL
—
—
VCC × 0.3
RES, NMI
Other peripheral input pins
excluding IIC
VIH
VCC × 0.8
—
—
VIL
—
—
VCC × 0.2
IIC (SMBus)*2
VIH
2.2
—
—
VCC = 3.6 to
5.5 V
VIH
2.0
—
—
VCC = 2.7 to
3.6 V
VIL
—
—
0.8
VCC = 3.6 to
5.5 V
VIL
—
—
0.5
VCC = 2.7 to
3.6 V
VIH
VCC × 0.8
—
5.8
—
VIL
—
—
VCC × 0.2
VIH
AVCC0 × 0.8
—
—
VIL
—
—
AVCC0 × 0.2
VIH
VCC × 0.8
—
—
VIL
—
—
VCC × 0.2
Parameter
Schmitt trigger
input voltage
Input voltage
(except for
Schmitt trigger
input pin)
IIC (except for SMBus)*1
5V-tolerant ports*3
P000 to P008, P010 to
P015
EXTAL
Input ports pins except for
P000 to P008, P010 to
P015
Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins)
Note 2. SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SCL1_A, SCL1_B, SDA1_A, SDA1_B (total 9 pins)
Note 3. P205, P206, P400, P401, P407 (total 5 pins)
2.2.3
Table 2.5
I/O IOH, IOL
I/O IOH, IOL (1 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output
current (average
value per pin)
Symbol
Min
Typ
Max
Unit
Ports P000 to P008, P010 to P015, P205, IOH
P206, P212, P213, P400, P401, P407
IOL
—
—
-4.0
mA
—
—
8.0
mA
IOH
—
—
-4.0
mA
IOL
—
—
20.0
mA
Ports P000 to P008, P010 to P015, P205, IOH
P206, P212, P213, P400, P401, P407
IOL
—
—
-4.0
mA
—
—
8.0
mA
IOH
—
—
-4.0
mA
IOL
—
—
20.0
mA
Other output pins*1
Permissible output
current (max value
per pin)
Other output pins*1
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Test
conditions
Page 22 of 111
RA2L1 Datasheet
Table 2.5
2. Electrical Characteristics
I/O IOH, IOL (2 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output
current (max value
total pins)*2
Total of ports P000 to P008, P010 to
P015
Min
Typ
Max
Unit
ΣIOH (max)
—
—
-30
mA
AVCC0 = 2.7
to 5.5 V
—
—
-8
mA
AVCC0 = 1.8
to 2.7 V
—
—
-4
mA
AVCC0 = 1.6
to 1.8 V
—
—
50
mA
AVCC0 = 2.7
to 5.5 V
—
—
4
mA
AVCC0 = 1.8
to 2.7 V
—
—
2
mA
AVCC0 = 1.6
to 1.8 V
—
—
-8.0
mA
VCC = 2.7 to
5.5 V
—
—
-2
mA
VCC = 1.8 to
2.7 V
—
—
-1
mA
VCC = 1.6 to
1.8 V
—
—
16.0
mA
VCC = 2.7 to
5.5 V
—
—
1.2
mA
VCC = 1.8 to
2.7 V
—
—
0.6
mA
VCC = 1.6 to
1.8 V
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
ΣIOL (max)
Total of ports P212, P213
ΣIOH
ΣIOL
Total of ports P400 to
P415, P708, P714
100 pin products
ΣIOH (max)
ΣIOL (max)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Test
conditions
Symbol
Page 23 of 111
RA2L1 Datasheet
Table 2.5
2. Electrical Characteristics
I/O IOH, IOL (3 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output
current (max value
total pins)*2
Total of ports P201 to
P208, P303 to P307,
P808, P809
100 pin products
Min
Typ
Max
Unit
ΣIOH (max)
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
ΣIOL (max)
Total of ports P108 to
P115, P300 to P302,
P600 to P603, P608
to P610
100 pin products
ΣIOH (max)
ΣIOL (max)
Total of ports P100 to
P107, P500 to P505
100 pin products
ΣIOH (max)
ΣIOL (max)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Test
conditions
Symbol
Page 24 of 111
RA2L1 Datasheet
Table 2.5
2. Electrical Characteristics
I/O IOH, IOL (4 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output
current (max value
total pins)*2
Total of all output pin
Total of ports P204 to
P208, P400 to P403,
P406 to P411, P415,
P708, P714
100 pin products
80 pin products
Min
Typ
Max
Unit
ΣIOH (max)
—
—
-100
mA
ΣIOL (max)
—
—
100
mA
ΣIOH (max)
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
ΣIOH (max)
—
—
-60
mA
ΣIOL (max)
—
—
100
mA
ΣIOL (max)
Total of ports P100 to
P115, P201, P300 to
P306, P500 to P504,
P600, P601, P808,
P809
80 pin products
ΣIOH (max)
ΣIOL (max)
Total of all output pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
80 pin products
Test
conditions
Symbol
Page 25 of 111
RA2L1 Datasheet
Table 2.5
2. Electrical Characteristics
I/O IOH, IOL (5 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output
current (max value
total pins)*2
Total of ports P204 to
P208, P400 to P403,
P407 to P411
64 pin products
Min
Typ
Max
Unit
ΣIOH (max)
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
ΣIOH (max)
—
—
-60
mA
ΣIOL (max)
—
—
100
mA
ΣIOL (max)
Total of ports P100 to
P113, P201, P300 to
P304, P500 to P502
64 pin products
ΣIOH (max)
ΣIOL (max)
Total of all output pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
64 pin products
Test
conditions
Symbol
Page 26 of 111
RA2L1 Datasheet
Table 2.5
2. Electrical Characteristics
I/O IOH, IOL (6 of 6)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Permissible output
current (max value
total pins)*2
Total of ports P206 to
P208, P400, P401,
P407 to P409
48 pin products
Min
Typ
Max
Unit
ΣIOH (max)
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
—
—
-30
mA
VCC = 2.7 to
5.5 V
—
—
-8
mA
VCC = 1.8 to
2.7 V
—
—
-4
mA
VCC = 1.6 to
1.8 V
—
—
50
mA
VCC = 2.7 to
5.5 V
—
—
4
mA
VCC = 1.8 to
2.7 V
—
—
2
mA
VCC = 1.6 to
1.8 V
ΣIOH (max)
—
—
-60
mA
ΣIOL (max)
—
—
100
mA
ΣIOL (max)
Total of ports P100 to
P104, P108 to
P112,P201, P300 to
P302, P500
48 pin products
ΣIOH (max)
ΣIOL (max)
Total of all output pin
48 pin products
Test
conditions
Symbol
Note 1. Except for Ports P200, P214, and P215, which are input ports.
Note 2. Specification under conditions where the duty factor ≤ 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
Where n = 80% and IOH = −30.0 mA
Total output current of pins = (−30.0 × 0.7)/(80 × 0.01) ≅ −26.2 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in Table 2.5.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 27 of 111
RA2L1 Datasheet
2.2.4
Table 2.6
2. Electrical Characteristics
I/O VOH, VOL, and Other Characteristics
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = 4.0 to 5.5 V
Parameter
Output
voltage
Symbol
Min
Typ
Max
Unit
Test conditions
Ports P000 to P008, P010 to P015
VOH
AVCC0 - 0.8
—
—
V
IOH = -4.0 mA
Output pins except for P000 to P008 and
P010 to P015*1
VOH
VCC - 0.8
—
—
IOH = -4.0 mA
Ports P000 to P008, P010 to P015
VOL
—
—
0.8
IOL = 8.0 mA
Ports P205, P206, P212, P213, P400,
P401, P407
VOL
—
—
0.8
IOL = 8.0 mA
Output pins except for P000 to P008, P010
to P015, P205, P206, P212, P213, P400,
P401, and P407*1
VOL
—
—
1.2
IOL = 20.0 mA
Symbol
Min
Typ
Max
Unit
Test conditions
Ports P000 to P008, P010 to P015
VOH
AVCC0 - 0.8
—
—
V
IOH = -4.0 mA
Output pins except for P000 to P008 and
P010 to P015*1
VOH
VCC - 0.8
—
—
IOH = -4.0 mA
Ports P000 to P008, P010 to P015
VOL
—
—
0.8
IOL = 8.0 mA
Output pins except for P000 to P008 and
P010 to P015*1
VOL
—
—
0.8
IOL = 8.0 mA
Note 1. Except for Ports P200, P214, and P215, which are input ports.
Table 2.7
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = 2.7 to 4.0 V
Parameter
Output
voltage
Note 1. Except for Ports P200, P214, and P215, which are input ports.
Table 2.8
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = 1.6 to 2.7 V
Parameter
Output
voltage
Ports P000 to P008, P010 to P015
Output pins except for P000 to P008
and P010 to P015*1
Ports P000 to P008, P010 to P015
Output pins except for P000 to P008
and P010 to P015*1
Symbol
Min
Typ
Max
Unit
Test conditions
VOH
AVCC0 - 0.5
—
—
V
IOH = -1.0 mA
AVCC0 = 1.8 to 2.7 V
AVCC0 - 0.5
—
—
IOH = -0.5 mA
AVCC0 = 1.6 to 1.8 V
VCC - 0.5
—
—
IOH = -1.0 mA
VCC = 1.8 to 2.7 V
VCC - 0.5
—
—
IOH = -0.5 mA
VCC = 1.6 to 1.8 V
—
—
0.4
IOL = 0.6 mA
AVCC0 = 1.8 to 2.7 V
—
—
0.4
IOL = 0.3 mA
AVCC0 = 1.6 to 1.8 V
—
—
0.4
IOL = 0.6 mA
VCC = 1.8 to 2.7 V
—
—
0.4
IOL = 0.3 mA
VCC = 1.6 to 1.8 V
VOH
VOL
VOL
Note 1. Except for Ports P200, P214, and P215, which are input ports.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 28 of 111
RA2L1 Datasheet
Table 2.9
2. Electrical Characteristics
I/O other characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
RES, ports P200, P214, P215
| Iin |
—
—
1.0
µA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
5V-tolerant ports*1
| ITSI |
—
—
1.0
µA
Vin = 0 V
Vin = 5.8 V
—
—
1.0
10
20
100
kΩ
Vin = 0 V
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
Other ports
(except for P200, P214, P215, and
5V-tolerant ports)
Input pull-up resistor
Input capacitance
All ports
(except for P200, P214, P215)
RU
P200
Cin
Other input pins
—
—
30
—
—
15
Vin = 0 V
Vin = VCC
Note 1. P205, P206, P400, P401, and P407 (total 5 pins)
2.2.5
Table 2.10
Operating and Standby Current
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
LDO mode
DCDC
mode*12
Symbol
Typ*10 Max
Typ*10 Max
Unit
Test
Conditions
ICC
5.50
—
3.05
—
mA
*7 *11
ICLK = 32 MHz
3.65
—
2.20
—
ICLK = 16 MHz
2.20
—
1.35
—
ICLK = 8 MHz
1.45
—
0.90
—
All peripheral
clocks enabled,
code executing
from flash*5
ICLK = 48 MHz
—
14.5
—
12.5
*9 *11
All peripheral
clocks disabled*5
ICLK = 48 MHz
1.05
—
0.65
—
*7
ICLK = 32 MHz
0.85
—
0.55
—
*7
ICLK = 16 MHz
0.70
—
0.45
—
ICLK = 8 MHz
0.60
—
0.35
—
ICLK = 48 MHz
4.85
—
2.95
—
*9
ICLK = 32 MHz
4.68
—
2.85
—
*8
ICLK = 16 MHz
2.55
—
1.55
—
ICLK = 8 MHz
1.50
—
0.95
—
2.1
—
1.95
—
Parameter
Supply
current*1
Highspeed
mode*2
Normal
mode
Sleep
mode
All peripheral
clocks disabled,
CoreMark code
executing from
flash*5
All peripheral
clocks enabled*5
Increase during BGO
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
ICLK = 48 MHz
operation*6
*7
—
Page 29 of 111
RA2L1 Datasheet
Table 2.10
2. Electrical Characteristics
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
LDO mode
DCDC
mode*12
Symbol
Typ*10 Max
Typ*10 Max
Unit
Test
Conditions
ICC
2.80
—
1.65
—
mA
*7
ICLK = 4 MHz
0.90
—
0.55
—
All peripheral
clocks enabled,
code executing
from flash*5
ICLK = 24 MHz
—
10.0
—
8.8
*8
All peripheral
clocks disabled*5
ICLK = 24 MHz
0.70
—
0.45
—
*7
ICLK = 4 MHz
0.55
—
0.35
—
All peripheral
clocks enabled*5
ICLK = 24 MHz
3.50
—
2.10
—
ICLK = 4 MHz
0.95
—
0.60
—
2.00
—
1.65
—
0.33
—
—
—
Parameter
Supply
current*1
Middlespeed
mode*2
Normal
mode
Sleep
mode
All peripheral
clocks disabled,
CoreMark code
executing from
flash*5
Increase during BGO
Supply
current*1
Lowspeed
mode*3
Normal
mode
Sleep
mode
Subosc- Normal
speed
mode
mode*4
Sleep
mode
ICLK = 24 MHz
operation*6
ICC
*8
—
All peripheral
clocks disabled,
CoreMark code
executing from
flash*5
ICLK = 2 MHz
All peripheral
clocks enabled,
code executing
from flash*5
ICLK = 2 MHz
—
3.1
—
—
*8
All peripheral
clocks disabled*5
ICLK = 2 MHz
0.13
—
—
—
*7
All peripheral
clocks enabled*5
ICLK = 2 MHz
0.35
—
—
—
*8
All peripheral
clocks enabled,
code executing
from flash*5
ICLK = 32.768
kHz
—
540
—
—
All peripheral
clocks disabled*5
ICLK = 32.768
kHz
2.00
—
—
—
*8
All peripheral
clocks enabled*5
ICLK = 32.768
kHz
5.85
—
—
—
*8
ICC
mA
µA
*7
*8
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
In LDO mode, the supply current is total current flowing into VCC.
In DCDC mode, the supply current is total current flowing into VCC and VCC_DCDC.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO and A/D operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. PCLKB and PCLKD are set to divided by 64.
Note 8. PCLKB and PCLKD are the same frequency as that of ICLK.
Note 9. PCLKB are set to be divided by 2 and PCLKD is the same frequency as that of ICLK.
Note 10. VCC = 3.3 V.
Note 11. The prefetch is operating.
Note 12. VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 30 of 111
RA2L1 Datasheet
Table 2.11
2. Electrical Characteristics
Operating and standby current (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Symbol
Typ*3
Max
Unit
Test conditions
ICC
0.30
2.2
µA
—
Ta = 55°C
0.65
5.3
Ta = 85°C
2.0
20
Ta = 105°C
4.0
70
0.25
2.2
0.6
5.3
Ta = 85°C
1.8
20
Ta = 105°C
3.65
70
Increment for RTC operation with low-speed onchip oscillator*4
0.30
—
—
Increment for RTC operation in normal operation
mode with sub-clock oscillator*4
0.20
—
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
RCR4.ROPSEL is 0 (RTC
operation in normal operation
mode)
0.95
—
SOMCR.SODRV[1:0] are 00b
(normal mode)
RCR4.ROPSEL is 0 (RTC
operation in normal operation
mode)
0.11
—
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
RCR4.ROPSEL is 1 (RTC
operation in low-consumption
clock mode)
0.90
—
SOMCR.SODRV[1:0] are 00b
(normal mode)
RCR4.ROPSEL is 1 (RTC
operation in low-consumption
clock mode)
Parameter
Supply
Software
current*1 Standby
mode*2
All
SRAMs(0x2000_00
00 to
0x2000_7FFF) are
on
Ta = 25°C
Only 8KB SRAM
Ta = 25°C
(0x2000_4000 to
0x2000_5FFF) is on Ta = 55°C
Increment for RTC operation in low-consumption
clock mode with sub-clock oscillator*4
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOS
transistors are in the off state. The supply current is total current flowing into VCC.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the low-speed on-chip oscillator or sub-oscillation circuit current.
Table 2.12
Operating and standby current (3) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Analog power
supply current
Reference
power supply
current
Symbol
Min
Typ
Max
Unit
Test conditions
IAVCC0
—
—
1.44
mA
—
During 12-bit A/D conversion (at low-power
A/D conversion mode)
—
—
0.78
mA
—
During 12-bit D/A conversion*1
—
—
0.8
mA
—
Waiting for 12-bit A/D and 12-bit D/A
conversion (all units)*2
—
—
1.0
µA
—
—
—
120
µA
—
—
—
60
nA
—
—
95
—
µA
—
During 12-bit A/D conversion (at high-speed
A/D conversion mode)
During 12-bit A/D conversion
IREFH0
Waiting for 12-bit A/D conversion
Temperature Sensor (TSN) operating current
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
ITNS
Page 31 of 111
RA2L1 Datasheet
Table 2.12
2. Electrical Characteristics
Operating and standby current (3) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Low-power
Analog
Comparator
(ACMPLP)
operating
current
Symbol
Min
Typ
Max
Unit
Test conditions
ICMPLP
—
12
—
µA
—
Comparator (high-speed mode)
—
6.4
—
µA
—
Comparator (low-speed mode)
—
1.8
—
µA
—
Window comparator (high-speed mode)
Note 1. The reference power supply current is included in the power supply current value for D/A conversion.
Note 2. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC120 module-stop bit) is in the module-stop state.
2.2.6
VCC Rise and Fall Gradient and Ripple Frequency
Table 2.13
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = 0 to 5.5 V
Parameter
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup
Symbol
Min
Typ
Max
Unit
Test conditions
SrVCC
0.02
—
2
ms/V
—
Voltage monitor 0 reset enabled at startup*1 *2
—
SCI boot mode*2
2
Note 1. When OFS1.LVDAS = 0.
Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 2.14
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6
V).
When the VCC change exceeds VCC ± 10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple frequency
fr(VCC)
—
—
10
kHz
Figure 2.2
Vr (VCC) ≤ VCC × 0.2
—
—
1
MHz
Figure 2.2
Vr (VCC) ≤ VCC × 0.08
—
—
10
MHz
Figure 2.2
Vr (VCC) ≤ VCC × 0.06
1.0
—
—
ms/V
When VCC change exceeds VCC ± 10%
Allowable voltage change rising and
falling gradient
dt/dVCC
1 / fr(VCC)
VCC
Figure 2.2
2.3
Vr(VCC)
Ripple waveform
AC Characteristics
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 32 of 111
RA2L1 Datasheet
2.3.1
Table 2.15
2. Electrical Characteristics
Frequency
Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
System clock
1.8 to 5.5 V
(ICLK)*1*2
Max*4
Unit
0.032768 —
48
MHz
Symbol
Min
f
Typ
Peripheral module clock (PCLKB)
1.8 to 5.5 V
—
—
32
Peripheral module clock (PCLKD)*3
1.8 to 5.5 V
—
—
64
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or
erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as
1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.
Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.
Table 2.16
Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Max*4
Unit
0.032768 —
24
MHz
1.6 to 1.8 V
0.032768 —
4
1.8 to 5.5 V
—
—
24
1.6 to 1.8 V
—
—
4
1.8 to 5.5 V
—
—
24
1.6 to 1.8 V
—
—
4
Parameter
Operation
frequency
1.8 to 5.5 V
System clock (ICLK)*1*2
Peripheral module clock (PCLKB)
Peripheral module clock
(PCLKD)*3
Symbol
Min
f
Typ
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or
erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as
1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.
Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.
Table 2.17
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Max*4
Unit
0.032768 —
2
MHz
1.6 to 5.5 V
—
—
2
1.6 to 5.5 V
—
—
2
Parameter
Operation
frequency
System clock
1.6 to 5.5 V
(ICLK)*1*2
Peripheral module clock (PCLKB)
Peripheral module clock
(PCLKD)*3
Symbol
Min
f
Typ
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ± 1.0% while programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC12 is in use.
Note 4. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.19.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 33 of 111
RA2L1 Datasheet
Table 2.18
2. Electrical Characteristics
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Operation
frequency
System clock
1.6 to 5.5 V
(ICLK)*1
Symbol
Min
Typ
Max
Unit
f
27.8528
32.768
37.6832
kHz
Peripheral module clock (PCLKB)
1.6 to 5.5 V
—
—
37.6832
Peripheral module clock (PCLKD)*2
1.6 to 5.5 V
—
—
37.6832
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The ADC12 cannot be used.
2.3.2
Table 2.19
Clock Timing
Clock timing
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
EXTAL external clock input cycle time
tXcyc
50
—
—
ns
Figure 2.3
EXTAL external clock input high pulse width
tXH
20
—
—
ns
EXTAL external clock input low pulse width
tXL
20
—
—
ns
EXTAL external clock rising time
tXr
—
—
5
ns
EXTAL external clock falling time
tXf
—
—
5
ns
EXTAL external clock input wait time*1
tEXWT
0.3
—
—
µs
—
EXTAL external clock input frequency
fEXTAL
—
—
20
MHz
1.8 ≤ VCC ≤ 5.5
—
—
4
1
—
20
1
—
4
Main clock oscillator oscillation frequency
fMAIN
1.6 ≤ VCC < 1.8
MHz
1.8 ≤ VCC ≤ 5.5
1.6 ≤ VCC < 1.8
LOCO clock oscillation frequency
fLOCO
27.8528
32.768
37.6832
kHz
—
LOCO clock oscillation stabilization time
tLOCO
—
—
100
µs
Figure 2.4
IWDT-dedicated clock oscillation frequency
fILOCO
12.75
15
17.25
kHz
—
MOCO clock oscillation frequency
fMOCO
6.8
8
9.2
MHz
—
MOCO clock oscillation stabilization time
tMOCO
—
—
1
µs
—
HOCO clock oscillation frequency*5
fHOCO24
23.76
24
24.24
MHz
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
fHOCO32
31.68
32
32.32
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
fHOCO48
47.52
48
48.48
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
fHOCO64
63.36
64
64.64
Ta = -40 to 105°C
1.6 ≤ VCC ≤ 5.5
HOCO clock oscillation stabilization time*3 *4
tHOCO24
tHOCO32
tHOCO48
tHOCO64
—
1.9
—
µs
Figure 2.5
Sub-clock oscillator oscillation frequency
fSUB
—
32.768
—
kHz
—
tSUBOSC
—
0.5
—
s
Figure 2.6
Sub-clock oscillation stabilization
time*2
Note 1. Time until the clock can be used after the Main Clock Oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock oscillator
after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the oscillator
manufacturer.
Note 3. This is a characteristic when the HOCOCR.HCSTP bit is set to 0 (oscillation) in the MOCO stop state. When the HOCOCR.HCSTP
bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 µs.
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RA2L1 Datasheet
2. Electrical Characteristics
Note 4. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
Note 5. Accuracy at production test.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
Figure 2.3
tXf
EXTAL external clock input timing
LOCOCR.LCSTP
tLOCO
LOCO clock oscillator output
Figure 2.4
LOCO clock oscillation start timing
HOCOCR.HCSTP
tHOCOx*1
HOCO clock
Note:
Figure 2.5
x = 24, 32, 48, 64
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 2.6
Sub-clock oscillation start timing
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Page 35 of 111
RA2L1 Datasheet
2.3.3
Table 2.20
2. Electrical Characteristics
Reset Timing
Reset timing
Symbol
Min
Typ
Max
Unit
Test
conditions
At power-on
tRESWP
10
—
—
ms
Figure 2.7
Not at power-on
tRESW
30
—
—
µs
Figure 2.8
tRESWT
—
0.9
—
ms
Figure 2.7
—
0.2
—
—
0.9
—
ms
Figure 2.8
—
0.2
—
—
0.9
—
ms
Figure 2.9
—
0.15
—
Parameter
RES pulse width
Wait time after RES cancellation (at
power-on)
LVD0
enabled*1
LVD0 disabled*2
Wait time after RES cancellation (during LVD0 enabled*1
powered-on state)
LVD0 disabled*2
tRESWT2
Wait time after internal reset
cancellation (Watchdog timer reset,
SRAM parity error reset, SRAM ECC
error reset, bus master MPU error
reset, bus slave MPU error reset, stack
pointer error reset, software reset)
tRESWT3
LVD0
enabled*1
LVD0 disabled*2
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 2.7
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Figure 2.8
Reset input timing (1)
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RA2L1 Datasheet
2. Electrical Characteristics
tRESWIW, tRESWIR
Independent watchdog timer reset
Software reset
Internal reset
tRESWT3
Figure 2.9
2.3.4
Table 2.21
Reset input timing (2)
Wakeup Time
Timing of recovery from low power modes (1)
Parameter
Recovery
time from
Software
Standby
mode*1
Highspeed
mode
Symbol
Min
Typ
Max
Unit
Crystal
resonator
connected to
main clock
oscillator
System clock
source is main
clock oscillator (20
MHz)*2
tSBYMC
—
2
3
ms
External clock
input to main
clock
oscillator
System clock
source is main
clock oscillator (20
MHz)*3
tSBYEX
—
2.4
3.1
µs
System clock source is HOCO
(HOCO clock is 32 MHz)
tSBYHO
—
4.9
6.2
µs
System clock source is HOCO
(HOCO clock is 48 MHz)
tSBYHO
—
4.8
6
µs
System clock source is HOCO
(HOCO clock is 64 MHz)
tSBYHO
—
4.9
6.2
µs
System clock source is MOCO (8
MHz)
tSBYMO
—
4
5
µs
Test conditions
Figure 2.10
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.
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RA2L1 Datasheet
Table 2.22
2. Electrical Characteristics
Timing of recovery from low power modes (2)
Parameter
Recovery
time from
Software
Standby
mode*1
Middlespeed
mode
Symbol
Min
Typ
Max
Unit
Crystal
resonator
connected to
main clock
oscillator
System clock
source is main
clock oscillator (20
MHz)*2
tSBYMC
—
2
3
ms
External clock
input to main
clock
oscillator
System clock
source is main
clock oscillator (20
MHz)*3
VCC = 1.8 V to 5.5
V
tSBYEX
—
2.4
3.1
µs
—
11.7
13
—
5.2
6.5
—
13.2
15
—
4
5
—
7.2
9
System clock
source is main
clock oscillator (20
MHz)*3
VCC = 1.6 V to 1.8
V
System clock
source is
HOCO*4
VCC = 1.8 V to 5.5
V
tSBYHO
VCC = 1.6 V to 1.8
V
System clock
source is
MOCO (8
MHz)
VCC = 1.8 V to 5.5
V
tSBYMO
VCC = 1.6 V to 1.8
V
Test conditions
Figure 2.10
µs
µs
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.
Note 4. The system clock is 24 MHz.
Table 2.23
Timing of recovery from low power modes (3)
Parameter
Recovery
time from
Software
Standby
mode*1
Symbol
Min
Typ
Max
Unit
Test conditions
System clock
source is main
clock oscillator (2
MHz)*2
tSBYMC
—
2
3
ms
Figure 2.10
System clock
source is main
clock oscillator (2
MHz)*3
tSBYEX
—
14.5
16
µs
System clock source is MOCO (2
MHz)
tSBYMO
—
12
15
µs
Low-speed Crystal
mode
resonator
connected to
main clock
oscillator
External clock
input to main
clock
oscillator
Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is
determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.
Table 2.24
Timing of recovery from low power modes (4)
Parameter
Recovery time
from Software
Standby mode*1
Subosc-speed mode
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Symbol
Min
Typ
Max
Unit
Test conditions
System clock source is
sub-clock oscillator
(32.768 kHz)
tSBYSC
—
0.85
1
ms
Figure 2.10
System clock source is
LOCO (32.768 kHz)
tSBYLO
—
0.85
1.2
ms
Page 38 of 111
RA2L1 Datasheet
2. Electrical Characteristics
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode.
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 2.10
Software Standby mode cancellation timing
Table 2.25
Timing of recovery from low power modes (5)
Parameter
Recovery time from Software
Standby mode to Snooze
mode
Symbol
Min
Typ
Max
Unit
Test conditions
High-speed mode
System clock source is
HOCO
tSNZ
—
4.1
5.2
µs
Figure 2.11
Middle-speed mode
System clock source is
HOCO (24 MHz)
VCC = 1.8 V to 5.5 V
tSNZ
—
4.2
5.3
µs
Middle-speed mode
System clock source is
HOCO (24 MHz)
VCC = 1.6 V to 1.8 V
tSNZ
—
8.3
10
µs
Low-speed mode
System clock source is
MOCO (2 MHz)
tSNZ
—
6.7
8.0
µs
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RA2L1 Datasheet
2. Electrical Characteristics
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.11
2.3.5
Recovery timing from Software Standby mode to Snooze mode
NMI and IRQ Noise Filter
Table 2.26
NMI and IRQ noise filter
Parameter
Symbol
Min
NMI pulse
width
tNMIW
200
IRQ pulse
width
Note:
Note:
Note 1.
Note 2.
Note 3.
Typ
Max
Unit
Test conditions
—
—
ns
NMI digital filter disabled
—
—
200
—
—
tNMICK ×
3.5*2
—
—
200
—
—
tPcyc × 2*1
—
—
200
—
—
tIRQCK ×
3.5*3
—
—
tPcyc ×
tIRQW
2*1
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
NMI digital filter enabled
tNMICK × 3 ≤ 200 ns
tNMICK × 3 > 200 ns
ns
IRQ digital filter disabled
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
IRQ digital filter enabled
tIRQCK × 3 ≤ 200 ns
tIRQCK × 3 > 200 ns
200 ns minimum in Software Standby mode.
If the clock source is being switched it is needed to add 4 clock cycle of switched source.
tPcyc indicates the PCLKB cycle.
tNMICK indicates the cycle of the NMI digital filter sampling clock.
tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
tNMIW
Figure 2.12
NMI interrupt input timing
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RA2L1 Datasheet
2. Electrical Characteristics
IRQ
tIRQW
Figure 2.13
2.3.6
Table 2.27
IRQ interrupt input timing
I/O Ports, POEG, GPT, AGT, KINT, and ADC12 Trigger Timing
I/O Ports, POEG, GPT, AGT, KINT, and ADC12 trigger timing
Parameter
I/O Ports
Input data pulse width
POEG
POEG input trigger pulse width
GPT
Input capture pulse width
2.7 V ≤ VCC ≤ 5.5 V
Symbol
Min
Max
Unit
Test
conditions
tPRW
2
—
tPcyc
Figure 2.14
2.4 V ≤ VCC < 2.7 V
3
1.6 V ≤ VCC < 2.4 V
4
tPOEW
3
—
tPcyc
Figure 2.15
tGTICW
1.5
—
tPDcyc
Figure 2.16
2.5
—
250
—
ns
Figure 2.17
2000
—
ns
100
—
ns
800
—
ns
62.5
—
ns
2.4 V ≤ VCC < 2.7 V
125
—
ns
1.8 V ≤ VCC < 2.4 V
250
—
ns
Single edge
Dual edge
AGT
AGTIO, AGTEE input cycle
1.8 V ≤ VCC ≤ 5.5 V
tACYC*1
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTEE input high-level
width, low-level width
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
tACKWH,
tACKWL
AGTIO, AGTO, AGTOA,
AGTOB output cycle
2.7 V ≤ VCC ≤ 5.5 V
tACYC2
1.6 V ≤ VCC < 1.8 V
Figure 2.17
500
—
ns
ADC12
12-bit A/D converter trigger input pulse width
tTRGW
1.5
—
tPcyc
Figure 2.18
KINT
KRn (n = 00 to 07) pulse width
tKR
250
—
ns
Figure 2.19
Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.
Port
tPRW
Figure 2.14
I/O ports input timing
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RA2L1 Datasheet
2. Electrical Characteristics
POEG input trigger
tPOEW
Figure 2.15
POEG input trigger timing
Input capture
tGTICW
Figure 2.16
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.17
AGT I/O timing
ADTRG0
tTRGW
Figure 2.18
ADC12 trigger input timing
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Page 42 of 111
RA2L1 Datasheet
2. Electrical Characteristics
KRn
tKR
Note:
n = 00 to 07
Figure 2.19
2.3.7
Table 2.28
Key interrupt input timing
CAC Timing
CAC timing
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
CAC
CACREF input pulse
width
tPcyc*1 ≤ tCAC*2
tPcyc*1 > tCAC*2
Symbol
Min
Typ
Max
Unit
Test conditions
tCACREF
4.5 × tCAC + 3 × tPcyc
—
—
ns
—
5 × tCAC + 6.5 × tPcyc
—
—
ns
Note 1. tPcyc: PCLKB cycle.
Note 2. tCAC: CAC count clock source cycle.
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Page 43 of 111
RA2L1 Datasheet
2.3.8
2. Electrical Characteristics
SCI Timing
Table 2.29
SCI timing (1)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Symbol
Min
Max
Unit
Test
conditions
tScyc
125
—
ns
Figure 2.20
2.4 V ≤ VCC < 2.7 V
250
—
1.8 V ≤ VCC < 2.4 V
500
—
1.6 V ≤ VCC < 1.8 V
1000
—
2.7 V ≤ VCC ≤ 5.5 V
187.5
—
2.4 V ≤ VCC < 2.7 V
375
—
1.8 V ≤ VCC < 2.4 V
750
—
1.6 V ≤ VCC < 1.8 V
1500
—
Parameter
SCI
Input clock cycle
Asynchronous
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
20
ns
Input clock fall time
tSCKf
—
20
ns
tScyc
187.5
—
ns
2.4 V ≤ VCC < 2.7 V
375
—
1.8 V ≤ VCC < 2.4 V
750
—
1.6 V ≤ VCC < 1.8 V
1500
—
2.7 V ≤ VCC ≤ 5.5 V
125
—
2.4 V ≤ VCC < 2.7 V
250
—
1.8 V ≤ VCC < 2.4 V
500
—
1.6 V ≤ VCC < 1.8 V
1000
—
tSCKW
0.4
0.6
tScyc
tSCKr
—
20
ns
—
30
—
20
—
30
Output clock cycle
Asynchronous
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V
Output clock pulse width
Output clock rise time
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
Output clock fall time
1.8 V ≤ VCC ≤ 5.5 V
tSCKf
1.6 V ≤ VCC < 1.8 V
Transmit data delay
time (master)
Clock
synchronous
1.8 V ≤ VCC ≤ 5.5 V
—
40
1.6 V ≤ VCC < 1.8 V
—
45
Transmit data delay
time (slave)
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V
—
55
2.4 V ≤ VCC < 2.7 V
—
60
1.8 V ≤ VCC < 2.4 V
—
100
1.6 V ≤ VCC < 1.8 V
—
125
45
—
2.4 V ≤ VCC < 2.7 V
55
—
1.8 V ≤ VCC < 2.4 V
90
—
1.6 V ≤ VCC < 1.8 V
110
—
2.7 V ≤ VCC ≤ 5.5 V
40
—
1.6 V ≤ VCC < 2.7 V
45
—
Receive data setup
time (master)
Clock
synchronous
2.7 V ≤ VCC ≤ 5.5 V
tTXD
tRXS
ns
ns
ns
ns
Receive data setup
time (slave)
Clock
synchronous
Receive data hold
time (master)
Clock synchronous
tRXH
5
—
ns
Receive data hold
time (slave)
Clock synchronous
tRXH
40
—
ns
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Feb 26, 2021
Figure 2.21
ns
Page 44 of 111
RA2L1 Datasheet
2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
tScyc
Note:
n = 0 to 3, 9
Figure 2.20
SCK clock input timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
Note:
n = 0 to 3, 9
Figure 2.21
SCI input/output timing in clock synchronous mode
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Page 45 of 111
RA2L1 Datasheet
Table 2.30
2. Electrical Characteristics
SCI timing (2) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Symbol
Min
Max
Unit*1
Test
conditions
tSPcyc
125
—
ns
Figure 2.22
2.4 V ≤ VCC < 2.7 V
250
—
1.8 V ≤ VCC < 2.4 V
500
—
1.6 V ≤ VCC < 1.8 V
1000
—
2.7 V ≤ VCC ≤ 5.5 V
187.5
—
2.4 V ≤ VCC < 2.7 V
375
—
1.8 V ≤ VCC < 2.4 V
750
—
1.6 V ≤ VCC < 1.8 V
1500
—
Parameter
Simple
SPI
SCK clock cycle output
(master)
SCK clock cycle input
(slave)
2.7 V ≤ VCC ≤ 5.5 V
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
—
20
ns
1.6 V ≤ VCC < 1.8 V
tSPCKr,
tSPCKf
—
30
2.7 V ≤ VCC ≤ 5.5 V
tSU
45
—
2.4 V ≤ VCC < 2.7 V
55
—
1.8 V ≤ VCC < 2.4 V
80
—
1.6 V ≤ VCC < 1.8 V
110
—
2.7 V ≤ VCC ≤ 5.5 V
40
—
1.6 V ≤ VCC < 2.7 V
45
—
33.3
—
SCK clock rise and fall
time
Data input
setup time
Master
Slave
Data input
hold time
1.8 V ≤ VCC ≤ 5.5 V
Master
tH
40
—
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
tOD
—
40
ns
1.6 V ≤ VCC < 1.8 V
—
50
2.4 V ≤ VCC ≤ 5.5 V
—
65
1.8 V ≤ VCC < 2.4 V
—
100
1.6 V ≤ VCC < 1.8 V
—
125
-10
—
2.4 V ≤ VCC < 2.7 V
-20
—
1.8 V ≤ VCC < 2.4 V
-30
—
1.6 V ≤ VCC < 1.8 V
-40
—
-10
—
—
20
1.6 V ≤ VCC < 1.8 V
—
30
1.8 V ≤ VCC ≤ 5.5 V
—
20
1.6 V ≤ VCC < 1.8 V
—
30
Master
Slave
Data output
hold time
Master
1.8 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
tOH
Slave
Data rise and
fall time
Master
Slave
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
1.8 V ≤ VCC ≤ 5.5 V
tDr, tDf
Figure 2.23 to
Figure 2.26
ns
SS input setup time
Data output
delay time
Slave
ns
ns
ns
Page 46 of 111
RA2L1 Datasheet
Table 2.30
2. Electrical Characteristics
SCI timing (2) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Symbol
Min
Max
Unit*1
Test
conditions
tSA
—
6
tPcyc
Figure 2.26
24 MHz ≤ PCLKB ≤
32 MHz
—
7
PCLKB < 24 MHz
—
6
—
6
—
6
24 MHz ≤ PCLKB ≤
32 MHz
—
7
PCLKB < 24 MHz
—
6
—
6
Parameter
Simple
SPI
Slave access time
2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Slave output release time 2.4 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.4 V
tREL
1.6 V ≤ VCC < 1.8 V
tPcyc
Note 1. tPcyc: PCLKB cycle.
tSPCKr
tSPCKWH
SCKn
master select
output
VOH
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
SCKn
slave select input
VIH
VIL
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = 0 to 3, 9
Figure 2.22
SCI simple SPI mode clock timing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 47 of 111
RA2L1 Datasheet
2. Electrical Characteristics
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
MISOn
input
tH
MSB IN
DATA
tDr, tDf
MOSIn
output
Note:
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = 0 to 3, 9
Figure 2.23
SCI simple SPI mode timing (master, CKPH = 1)
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
MISOn
input
tH
MSB IN
tOH
MOSIn
output
Note:
DATA
LSB IN
tDr, tDf
tOD
MSB OUT
MSB IN
DATA
LSB OUT
IDLE
MSB OUT
n = 0 to 3, 9
Figure 2.24
SCI simple SPI mode timing (master, CKPH = 0)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 48 of 111
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tOH
tSA
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tOD
DATA
tREL
LSB OUT
MSB IN
MSB OUT
tDr, tDf
tH
MSB IN
DATA
LSB IN
MSB IN
n = 0 to 3, 9
Figure 2.25
SCI simple SPI mode timing (slave, CKPH = 1)
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tREL
DATA
MSB OUT
tDr, tDf
tH
MSB IN
LSB OUT
DATA
LSB IN
MSB IN
n = 0 to 3, 9
Figure 2.26
SCI simple SPI mode timing (slave, CKPH = 0)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 49 of 111
RA2L1 Datasheet
Table 2.31
2. Electrical Characteristics
SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Simple IIC
(Standard mode)
Simple IIC (Fast
mode)
Symbol
Min
Max
Unit
Test conditions
SDA input rise time
tSr
—
1000
ns
Figure 2.27
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc*1
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*2
—
400
pF
SDA input rise time
tSr
—
300
ns
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc*1
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*2
—
400
pF
Figure 2.27
Note 1. tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Note 2. Cb indicates the total capacity of the bus line.
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
P*1
P*1
Sr*1
S*1
tSDAH
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note:
n = 0 to 3, 9
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.27
SCI simple IIC mode timing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 50 of 111
RA2L1 Datasheet
2.3.9
Table 2.32
2. Electrical Characteristics
SPI Timing
SPI timing (1 of 3)
Symbol
Min
Max
Unit*1
tSPcyc
62.5
—
ns
2.4 V ≤ VCC < 2.7 V
125
—
1.8 V ≤ VCC < 2.4 V
250
—
1.6 V ≤ VCC < 1.8 V
500
—
2.7 V ≤ VCC ≤ 5.5 V
187.5
—
2.4 V ≤ VCC < 2.7 V
375
—
1.8 V ≤ VCC < 2.4 V
750
—
1.6 V ≤ VCC < 1.8 V
1500
—
(tSPcyc tSPCKr tSPCKf) / 2 3
—
3 × tPcyc
—
(tSPcyc tSPCKr tSPCKf) / 2 3
—
3 × tPcyc
—
—
10
—
15
1.8 V ≤ VCC ≤ 2.4 V
—
20
1.6 V ≤ VCC < 1.8 V
—
30
—
1
Parameter
SPI RSPCK
clock cycle
Master
Slave
RSPCK
clock high
pulse width
2.7 V ≤ VCC ≤ 5.5 V
Master
tSPCKWH
Slave
RSPCK
clock low
pulse width
Master
tSPCKWL
Slave
RSPCK
clock rise
and fall time
Output
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
Input
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
tSPCKr,
tSPCKf
Test
conditions
Figure 2.28
C = 30 pF
ns
ns
ns
µs
Page 51 of 111
RA2L1 Datasheet
Table 2.32
2. Electrical Characteristics
SPI timing (2 of 3)
Symbol
Min
Max
Unit*1
tSU
10
—
ns
30
—
10
—
55
—
8 MHz < PCLKB ≤ 16
MHz
30
—
PCLKB ≤ 8 MHz
10
—
1.6 V ≤ VCC < 1.8 V
10
—
2.4 V ≤ VCC ≤ 5.5 V
10
—
1.8 V ≤ VCC < 2.4 V
15
—
1.6 V ≤ VCC < 1.8 V
20
—
Parameter
SPI Data input
setup time
Master
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V 16 MHz < PCLKB ≤ 32
MHz
PCLKB ≤ 16 MHz
1.8 V ≤ VCC < 2.4 V 16 MHz < PCLKB ≤ 32
MHz
Slave
Data input
hold time
SPI SSL setup
time
Master
(RSPCK is PCLKB/2)
tHF
0
—
Master
(RSPCK is not PCLKB/2)
tH
tPcyc
—
Slave
tH
20
—
tLEAD
-30 + N ×
tSPcyc*2
—
-50 + N ×
tSPcyc*2
—
6 × tPcyc
—
ns
-30 + N ×
tSPcyc*3
—
ns
6 × tPcyc
—
ns
—
14
ns
2.4 V ≤ VCC < 2.7 V
—
20
1.8 V ≤ VCC < 2.4 V
—
25
1.6 V ≤ VCC < 1.8 V
—
30
2.7 V ≤ VCC ≤ 5.5 V
—
50
2.4 V ≤ VCC < 2.7 V
—
60
1.8 V ≤ VCC < 2.4 V
—
85
1.6 V ≤ VCC < 1.8 V
—
110
0
—
0
—
tSPcyc + 2 ×
tPcyc
8 × tSPcyc +
2 × tPcyc
6 × tPcyc
—
Master
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
Slave
SSL hold
time
Master
tLAG
Slave
Data output
delay time
Master
Slave
Data output
hold time
2.7 V ≤ VCC ≤ 5.5 V
Master
tOD
tOH
Slave
Successive Master
transmission
delay time
Slave
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
tTD
Test
conditions
Figure 2.29
to Figure
2.34
C = 30 pF
ns
ns
ns
ns
Page 52 of 111
RA2L1 Datasheet
Table 2.32
2. Electrical Characteristics
SPI timing (3 of 3)
Symbol
Min
Max
Unit*1
tDr, tDf
—
10
ns
2.4 V ≤ VCC < 2.7 V
—
15
1.8 V ≤ VCC < 2.4 V
—
20
1.6 V ≤ VCC < 1.8 V
—
30
—
1
µs
—
10
ns
—
15
1.8 V ≤ VCC < 2.4 V
—
20
1.6 V ≤ VCC < 1.8 V
—
30
—
1
µs
—
2 × tPcyc +
100
ns
1.8 V ≤ VCC < 2.4 V
—
2 × tPcyc +
140
1.6 V ≤ VCC < 1.8 V
—
2 × tPcyc +
180
—
2 × tPcyc +
100
1.8 V ≤ VCC < 2.4 V
—
2 × tPcyc +
140
1.6 V ≤ VCC < 1.8 V
—
2 × tPcyc +
180
Parameter
SPI MOSI and
MISO rise
and fall time
Output
2.7 V ≤ VCC ≤ 5.5 V
Input
SSL rise and Output
fall time
2.7 V ≤ VCC ≤ 5.5 V
tSSLr,
tSSLf
2.4 V ≤ VCC < 2.7 V
Input
Slave access time
Slave output release
time
2.4 V ≤ VCC ≤ 5.5 V
tSA
2.4 V ≤ VCC ≤ 5.5 V
tREL
Test
conditions
Figure 2.29
to Figure
2.34
C = 30 pF
Figure 2.33
and Figure
2.34
C = 30 pF
ns
Note 1. tPcyc: PCLKB cycle.
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKWH
RSPCKn
master select
output
VOH
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
RSPCKn
slave select input
VIH
VIL
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = A or B
Figure 2.28
SPI clock timing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 53 of 111
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSLni
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
DATA
tDr, tDf
MOSIn
output
Note:
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
i = 0, 1
Figure 2.29
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLni
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
MSB IN
tDr, tDf
MOSIn
output
Note:
tHF
tOH
MSB OUT
LSB IN
DATA
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
i = 0, 1
Figure 2.30
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 54 of 111
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSLni
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tOH
LSB IN
MSB OUT
MSB IN
tDr, tDf
tOD
MOSIn
output
Note:
DATA
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
i = 0, 1
Figure 2.31
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLni
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
MSB IN
tOH
MOSIn
output
Note:
tH
DATA
LSB IN
tDr, tDf
tOD
MSB OUT
MSB IN
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
i = 0, 1
Figure 2.32
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 55 of 111
RA2L1 Datasheet
2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tOD
DATA
tREL
LSB OUT
MSB IN
MSB OUT
tDr, tDf
tH
MSB IN
DATA
LSB IN
MSB IN
n = A or B
Figure 2.33
SPI timing (slave, CPHA = 0)
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tREL
DATA
MSB OUT
tDr, tDf
tH
MSB IN
LSB OUT
DATA
LSB IN
MSB IN
n = A or B
Figure 2.34
SPI timing (slave, CPHA = 1)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 56 of 111
RA2L1 Datasheet
2.3.10
Table 2.33
2. Electrical Characteristics
IIC Timing
IIC timing (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Symbol
Min*1
Max
Unit Test conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
—
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
1000
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time (when
wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
—
ns
SDA input bus free time (when
wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 ×
tPcyc + 300
—
ns
START condition input hold time
tSTAH
(when wakeup function is disabled)
tIICcyc + 300
—
ns
START condition input hold time
(when wakeup function is enabled)
tSTAH
1 (5) × tIICcyc + tPcyc +
300
—
ns
Repeated START condition input
setup time
tSTAS
1000
—
ns
STOP condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Parameter
IIC (standard mode,
SMBus)
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Figure 2.35
Page 57 of 111
RA2L1 Datasheet
Table 2.33
2. Electrical Characteristics
IIC timing (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Symbol
Min*1
Max
Unit Test conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc + 600
—
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA input rise time
tSr
—
300
ns
SCL, SDA input fall time
tSf
—
300
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time (When
wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
—
ns
SDA input bus free time (When
wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 ×
tPcyc+ 300
—
ns
START condition input hold time
(When wakeup function is
disabled)
tSTAH
tIICcyc + 300
—
ns
START condition input hold time
tSTAH
(When wakeup function is enabled)
1 (5) × tIICcyc + tPcyc +
300
—
ns
Repeated START condition input
setup time
tSTAS
300
—
ns
STOP condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Parameter
IIC (Fast mode)
Figure 2.35
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
VIH
SDAn
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCLn
P*1
tSf
P*1
Sr*1
S*1
tSCLL
tSr
tSCL
tSDAS
tSDAH
Note:
n = 0, 1
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.35
I2C bus interface input/output timing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 58 of 111
RA2L1 Datasheet
2.3.11
Table 2.34
2. Electrical Characteristics
CLKOUT Timing
CLKOUT timing
Parameter
CLKOUT
CLKOUT pin output cycle*1
CLKOUT pin high pulse
width*2
CLKOUT pin low pulse
width*2
Symbol
Min
Max
Unit
Test conditions
tCcyc
62.5
—
ns
Figure 2.36
1.8 V ≤ VCC < 2.7 V
125
—
1.6 V ≤ VCC < 1.8 V
250
—
15
—
1.8 V ≤ VCC < 2.7 V
30
—
1.6 V ≤ VCC < 1.8 V
150
—
15
—
30
—
150
—
—
12
1.8 V ≤ VCC < 2.7 V
—
25
1.6 V ≤ VCC < 1.8 V
—
50
—
12
1.8 V ≤ VCC < 2.7 V
—
25
1.6 V ≤ VCC < 1.8 V
—
50
2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
tCH
2.7 V ≤ VCC ≤ 5.5 V
tCL
1.8 V ≤ VCC < 2.7 V
1.6 V ≤ VCC < 1.8 V
CLKOUT pin output rise time
CLKOUT pin output fall time
2.7 V ≤ VCC ≤ 5.5 V
tCr
2.7 V ≤ VCC ≤ 5.5 V
tCf
ns
ns
ns
ns
Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the
CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, specifications in Table 2.34 should be satisfied with 45% to 55% of
input duty cycle.
Note 2. When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio to
be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
tCcyc
tCH
tCf
CLKOUT
tCL
tCr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 2.36
CLKOUT output timing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 59 of 111
RA2L1 Datasheet
2.4
2. Electrical Characteristics
ADC12 Characteristics
VREFH0
VREFH0
5.5
5.5
A/D Conversion
Characteristics (1)
5.0
A/D Conversion
Characteristics (2)
4.0
3.0
2.7
2.4
A/D Conversion
Characteristics (3)
2.0
5.0
A/D Conversion
Characteristics (4)
4.0
3.0
2.7
2.4
A/D Conversion
Characteristics (5)
A/D Conversion
Characteristics (6)
2.0
1.8
1.6
1.0
A/D Conversion
Characteristics (7)
1.0
2.4 2.7
1.0
2.0
3.0
5.5
4.0
1.8
AVCC0
5.0
1.0
2.4 2.7
1.6 2.0
ADCSR.ADHSC = 0
3.0
5.5
4.0
AVCC0
5.0
ADCSR.ADHSC = 1
Figure 2.37
VCC to VREFH0 voltage range
Table 2.35
A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 4.5 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
PCLKD (ADCLK) frequency
1
—
64
MHz
ADACSR.ADSAC = 0
48
MHz
ADACSR.ADSAC = 1
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
1.3*3
kΩ
High-precision channel
—
—
5.0*3
kΩ
Normal-precision channel
0
—
VREFH0
V
—
—
—
12
Bit
—
Permissible
signal
source
impedance
Max. = 0.3
kΩ
0.70
(0.211)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0D
ADACSR.ADSAC = 0
1.34
(0.852)*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x36
ADACSR.ADSAC = 0
Permissible
signal
source
impedance
Max. = 0.3
kΩ
0.67
(0.219)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
1.29
(0.844)*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x28
ADACSR.ADSAC = 1
—
±1.0
±4.5
LSB
High-precision channel
±6.0
LSB
Other than specified
±4.5
LSB
High-precision channel
±6.0
LSB
Other than specified
Rs
Ain
Resolution
Conversion time*1
(Operation at PCLKD = 64
MHz)
Conversion time*1
(Operation at PCLKD = 48
MHz)
Offset error
Full-scale error
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RA2L1 Datasheet
Table 2.35
2. Electrical Characteristics
A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 4.5 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±2.5
±5.0
LSB
High-precision channel
±8.0
LSB
Other than specified
DNL differential nonlinearity error
—
±1.0
—
LSB
—
INL integral nonlinearity error
—
±1.5
±3.0
LSB
—
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.36
A/D conversion characteristics (2) in high-speed A/D conversion mode
Conditions: VCC = AVCC0 = VREFH0 = 2.7 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
PCLKD (ADCLK) frequency
1
—
48
MHz
—
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
1.9*3
kΩ
High-precision channel
—
—
6.0*3
kΩ
Normal-precision channel
0
—
VREFH0
V
—
—
—
12
Bit
—
0.67
(0.219)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
1.29
(0.844)*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x28
ADACSR.ADSAC = 1
—
±1.0
±5.5
LSB
High-precision channel
±7.0
LSB
Other than specified
±5.5
LSB
High-precision channel
±7.0
LSB
Other than specified
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Resolution
Conversion time*1
(Operation at PCLKD = 48
MHz)
Permissible
signal
source
impedance
Max. = 0.3
kΩ
Offset error
Full-scale error
—
±1.0
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±2.5
±6.0
LSB
High-precision channel
±9.0
LSB
Other than specified
DNL differential nonlinearity error
—
±1.0
—
LSB
—
INL integral nonlinearity error
—
±1.5
±3.0
LSB
—
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Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
2. Electrical Characteristics
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.37
A/D conversion characteristics (3) in high-speed A/D conversion mode
Conditions: VCC = AVCC0 = VREFH0 = 2.4 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
PCLKD (ADCLK) frequency
Analog input
capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Resolution
time*1
Conversion
(Operation at PCLKD = 32
MHz)
Permissible
signal
source
impedance
Max. = 1.3
kΩ
Offset error
Full-scale error
Max
Unit
Test conditions
1
—
32
MHz
—
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
2.2*3
kΩ
High-precision channel
—
—
7.0*3
kΩ
Normal-precision channel
0
—
VREFH0
V
—
—
—
12
Bit
—
1.00
(0.328)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
1.94
(1.266)*4
—
—
µs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0x28
ADACSR.ADSAC = 1
—
±1.0
±5.5
LSB
High-precision channel
±7.0
LSB
Other than specified
±5.5
LSB
High-precision channel
±7.0
LSB
Other than specified
—
±1.0
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±2.50
±6.0
LSB
High-precision channel
±9.0
LSB
Other than specified
DNL differential nonlinearity error
—
±1.0
—
LSB
—
INL integral nonlinearity error
—
±1.5
±3.0
LSB
—
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
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Table 2.38
2. Electrical Characteristics
A/D conversion characteristics (4) in low-power A/D conversion mode
Conditions: VCC = AVCC0 = VREFH0 = 2.7 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
PCLKD (ADCLK) frequency
1
—
24
MHz
—
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
1.9*3
kΩ
High-precision channel
—
—
6*3
kΩ
Normal-precision channel
0
—
VREFH0
V
—
—
—
12
Bit
—
1.58
(0.438)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
2.0 (0.854)*4 —
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
—
±6.0
LSB
High-precision channel
±7.5
LSB
Other than specified
±6.0
LSB
High-precision channel
±7.5
LSB
Other than specified
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Resolution
Conversion time*1
(Operation at PCLKD = 24
MHz)
Permissible
signal
source
impedance
Max. = 1.1
kΩ
Offset error
Full-scale error
—
±1.25
±1.25
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±3.25
±7.0
LSB
High-precision channel
±10.0
LSB
Other than specified
DNL differential nonlinearity error
—
±1.5
—
LSB
—
INL integral nonlinearity error
—
±1.75
±4.0
LSB
—
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.39
A/D conversion characteristics (5) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 2.4 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
PCLKD (ADCLK) frequency
1
—
16
MHz
—
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
2.2*3
kΩ
High-precision channel
—
—
7*3
kΩ
Normal-precision channel
Analog input capacitance*2
Analog input resistance
Cs
Rs
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Table 2.39
2. Electrical Characteristics
A/D conversion characteristics (5) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 2.4 to 5.5 V*5, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Analog input voltage range
Ain
Resolution
Conversion time*1
(Operation at PCLKD = 16
MHz)
Permissible
signal
source
impedance
Max. = 2.2
kΩ
Offset error
Full-scale error
Min
Typ
Max
Unit
Test conditions
0
—
VREFH0
V
—
—
—
12
Bit
—
2.38
(0.656)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
3.0 (1.281)*4 —
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
—
±6.0
LSB
High-precision channel
±7.5
LSB
Other than specified
±6.0
LSB
High-precision channel
±7.5
LSB
Other than specified
—
±1.25
±1.25
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±3.25
±7.0
LSB
High-precision channel
±10.0
LSB
Other than specified
DNL differential nonlinearity error
—
±1.5
—
LSB
—
INL integral nonlinearity error
—
±1.75
±4.0
LSB
—
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.40
A/D conversion characteristics (6) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 1.8 to 5.5 V*5 (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
PCLKD (ADCLK) frequency
1
—
8
MHz
—
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
6*3
kΩ
High-precision channel
—
—
14*3
kΩ
Normal-precision channel
0
—
VREFH0
V
—
—
—
12
Bit
—
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Resolution
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Table 2.40
2. Electrical Characteristics
A/D conversion characteristics (6) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 1.8 to 5.5 V*5 (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Conversion time*1
(Operation at PCLKD = 8
MHz)
Permissible
signal
source
impedance
Max. = 5 kΩ
Offset error
Full-scale error
Min
Typ
Max
Unit
Test conditions
4.75
(1.313)*4
—
—
µs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
6.0 (2.563)*4 —
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
—
±7.5
LSB
High-precision channel
±10.0
LSB
Other than specified
±7.5
LSB
High-precision channel
±10.0
LSB
Other than specified
—
±1.25
±1.5
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±3.75
±9.5
LSB
High-precision channel
±13.5
LSB
Other than specified
DNL differential nonlinearity error
—
±2.0
—
LSB
—
INL integral nonlinearity error
—
±2.25
±4.5
LSB
—
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Table 2.41
A/D conversion characteristics (7) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 1.6 to 5.5 V*5 (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
PCLKD (ADCLK) frequency
1
—
4
MHz
—
—
—
9*3
pF
High-precision channel
—
—
10*3
pF
Normal-precision channel
—
—
12*3
kΩ
High-precision channel
—
—
28*3
kΩ
Normal-precision channel
0
—
VREFH0
V
—
—
—
12
Bit
—
9.5 (2.625)*4 —
—
µs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x0A
ADACSR.ADSAC = 1
12.0
(5.125)*4
—
µs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0x14
ADACSR.ADSAC = 1
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Resolution
Conversion time*1
(Operation at PCLKD = 4
MHz)
Permissible
signal
source
impedance
Max. = 9.9
kΩ
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RA2L1 Datasheet
Table 2.41
2. Electrical Characteristics
A/D conversion characteristics (7) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = VREFH0 = 1.6 to 5.5 V*5 (AVCC0 = VCC when VCC < 2.0 V), VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Offset error
—
±1.25
±7.5
LSB
High-precision channel
±10.0
LSB
Other than specified
±7.5
LSB
High-precision channel
±10.0
LSB
Other than specified
Full-scale error
—
±1.5
Quantization error
—
±0.5
—
LSB
—
Absolute accuracy
—
±3.75
±9.5
LSB
High-precision channel
±13.5
LSB
Other than specified
DNL differential nonlinearity error
—
±2.0
—
LSB
—
INL integral nonlinearity error
—
±2.25
±4.5
LSB
—
Note:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The characteristics apply when no pin functions other than 12-bit A/D converter input are used. Absolute accuracy does not include
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include
quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the
test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4. I/O VOH, VOL, and Other Characteristics.
Reference data.
( ) lists sampling time.
When VREFH0 < VCC, the MAX. values are as follows.
Absolute accuracy/Offset error/Full-scale error:
For voltage difference between VCC and VREFH0, it should be added ±0.75 LSB/V to the Max spec.
INL integral non-linearity error:
For voltage difference between VCC and VREFH0, it should be added ±0.2 LSB/V to the Max spec.
Figure 2.38 shows the equivalent circuit for analog input.
MCU
Analog input
ANn
Rs
ADC12
Vi
Cin
Note:
Cs
Terminal leakage current is not shown in this figure.
Figure 2.38
Equivalent circuit for analog input
Table 2.42
12-bit A/D converter channel classification
Classification
Channel
Conditions
Remarks
High-precision channel
AN000 to AN014
VCC = 1.6 to 5.5 V
Normal-precision channel
AN017 to AN020
Pins AN000 to AN014 cannot
be used as general I/O, TS
transmission, when the A/D
converter is in use.
Internal reference voltage input channel
Internal reference voltage
VCC = 1.8 to 5.5 V
—
Temperature sensor input channel
Temperature sensor output
VCC = 1.8 to 5.5 V
—
Input channel from CTSU
CTSU TSCAP voltage
VCC = 1.6 to 5.5 V
—
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RA2L1 Datasheet
Table 2.43
2. Electrical Characteristics
A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = VREFH0 = 1.8 to 5.5 V*1
Parameter
Min
Typ
Max
Unit
Test conditions
Internal reference voltage input channel*2
1.42
1.48
1.54
V
—
PCLKD (ADCLK) frequency*3
1
—
2
MHz
—
Sampling time*4
5.0
—
—
µs
—
Note 1. The internal reference voltage cannot be selected for input channels when VCC < 1.8 V.
Note 2. The 12-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 12-bit A/D
converter.
Note 3. When the internal reference voltage is selected as the high-potential reference voltage.
Note 4. When the internal reference voltage is converted.
0xFFF
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
Offset error
0x000
0
Figure 2.39
Analog input voltage
VREFH0
(full-scale)
Illustration of 12-bit A/D converter characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
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RA2L1 Datasheet
2. Electrical Characteristics
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion result
is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical A/D conversion
characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and
the width of the actual output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
2.5
DAC12 Characteristics
Table 2.44
12-bit D/A conversion characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = AVCC0 or AVSS0 selected
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
—
—
12
bit
—
Resistive load
30
—
—
kΩ
—
Capacitive load
—
—
50
pF
—
Output voltage range
0.35
—
AVCC0-0.47
V
—
DNL differential nonlinearity error
—
±0.5
±2.0
LSB
—
INL integral nonlinearity error
—
±2.0
±8.0
LSB
—
Offset error
—
—
±30
mV
—
Full-scale error
—
—
±30
mV
—
Output impedance
—
5
—
Ω
—
Conversion time
—
—
30
µs
—
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RA2L1 Datasheet
2. Electrical Characteristics
Gain error
Full-scale error
Upper output limit
Integral nonlinearity error (INL)
Offset error
Output analog voltage
1-LSB width for ideal D/A conversion
characteristic
Ideal output voltage
Differential nonlinearity error
(DNL)
*1
Lower output limit
Actual D/A conversion characteristic
Offset error
Ideal output voltage
0x000
0xFFF
D/A converter input code
Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed.
Figure 2.40
Illustration of D/A converter characteristic terms
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion
characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion
characteristics and the width of the actual output voltage.
Offset error
Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal
output voltage based on the input code.
Full-scale error
Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal
output voltage based on the input code.
2.6
TSN Characteristics
Table 2.45
TSN characteristics (1 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Relative accuracy
—
—
± 1.5
—
°C
2.4 V or above
—
± 2.0
—
°C
Below 2.4 V
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RA2L1 Datasheet
Table 2.45
2. Electrical Characteristics
TSN characteristics (2 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Temperature slope
—
—
-3.3
—
mV/°C
—
Output voltage (at 25°C)
—
—
1.05
—
V
VCC = 3.3 V
Temperature sensor start time
tSTART
—
—
5
µs
—
Sampling time
—
5
—
—
µs
2.7
OSC Stop Detect Characteristics
Table 2.46
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Detection time
tdr
—
—
1
ms
Figure 2.41
Main clock
OSTDSR.OSTDF
tdr
MOCO clock
ICLK
Figure 2.41
2.8
Oscillation stop detection timing
POR and LVD Characteristics
Table 2.47
Power-on reset circuit and voltage detection circuit characteristics (1) (1 of 2)
Parameter
Voltage detection
level*1
Power-on reset
(POR)
Voltage detection
circuit (LVD0)*2
Symbol
Min
Typ
Max
Unit
Test Conditions
When power supply rise
VPOR
1.47
1.51
1.55
V
Figure 2.42
When power supply fall
VPDR
1.46
1.50
1.54
When power supply rise
Vdet0_0
3.74
3.91
4.06
3.68
3.85
4.00
2.73
2.9
3.01
2.68
2.85
2.96
2.44
2.59
2.70
2.38
2.53
2.64
1.83
1.95
2.07
1.78
1.90
2.02
1.66
1.75
1.88
1.60
1.69
1.82
When power supply fall
When power supply rise
Vdet0_1
When power supply fall
When power supply rise
Vdet0_2
When power supply fall
When power supply rise
Vdet0_3
When power supply fall
When power supply rise
When power supply fall
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Vdet0_4
Figure 2.43
V
Figure 2.44
At falling edge
VCC
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RA2L1 Datasheet
Table 2.47
2. Electrical Characteristics
Power-on reset circuit and voltage detection circuit characteristics (1) (2 of 2)
Parameter
Voltage detection
level*1
Voltage detection
circuit (LVD1)*3
When power supply rise
Symbol
Min
Typ
Max
Unit
Test Conditions
Vdet1_0
4.23
4.39
4.55
V
4.13
4.29
4.45
Figure 2.45
At falling edge
VCC
4.07
4.25
4.39
3.98
4.16
4.30
3.97
4.14
4.29
3.86
4.03
4.18
3.74
3.92
4.06
3.68
3.86
4.00
3.05
3.17
3.29
2.98
3.10
3.22
2.95
3.06
3.17
2.89
3.00
3.11
2.86
2.97
3.08
2.79
2.90
3.01
2.74
2.85
2.96
2.68
2.79
2.90
2.63
2.75
2.85
V
2.58
2.68
2.78
Figure 2.45
At falling edge
VCC
2.54
2.64
2.75
2.48
2.58
2.68
2.43
2.53
2.63
2.38
2.48
2.58
2.16
2.26
2.36
2.10
2.20
2.30
1.88
2
2.09
1.84
1.96
2.05
1.78
1.9
1.99
1.74
1.86
1.95
1.67
1.79
1.88
1.63
1.75
1.84
1.65
1.7
1.78
1.60
1.65
1.73
4.20
4.40
4.57
V
4.11
4.31
4.48
Figure 2.46
At falling edge
VCC
4.05
4.25
4.42
3.97
4.17
4.34
3.91
4.11
4.28
3.83
4.03
4.20
3.71
3.91
4.08
3.64
3.84
4.01
When power supply fall
When power supply rise
Vdet1_1
When power supply fall
When power supply rise
Vdet1_2
When power supply fall
When power supply rise
Vdet1_3
When power supply fall
When power supply rise
Vdet1_4
When power supply fall
When power supply rise
Vdet1_5
When power supply fall
When power supply rise
Vdet1_6
When power supply fall
When power supply rise
Vdet1_7
When power supply fall
Voltage detection
level*1
Voltage detection
circuit (LVD1)*3
When power supply rise
Vdet1_8
When power supply fall
When power supply rise
Vdet1_9
When power supply fall
When power supply rise
Vdet1_A
When power supply fall
When power supply rise
Vdet1_B
When power supply fall
When power supply rise
Vdet1_C
When power supply fall
When power supply rise
Vdet1_D
When power supply fall
When power supply rise
Vdet1_E
When power supply fall
When power supply rise
Vdet1_F
When power supply fall
Voltage detection
level*1
Voltage detection
circuit (LVD2)*4
When power supply rise
Vdet2_0
When power supply fall
When power supply rise
Vdet2_1
When power supply fall
When power supply rise
Vdet2_2
When power supply fall
When power supply rise
When power supply fall
Vdet2_3
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection.
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2. Electrical Characteristics
Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
Table 2.48
Power-on reset circuit and voltage detection circuit characteristics (2)
Parameter
Wait time after power-on
reset cancellation
Wait time after voltage
monitor 0, 1, 2 reset
cancellation
Symbol
Min
Typ
Max
Unit
Test Conditions
LVD0: enable
tPOR
—
4.3
—
ms
—
LVD0: disable
tPOR
—
3.7
—
ms
—
tLVD0,1,2
—
1.4
—
ms
—
tLVD1,2
—
0.7
—
ms
—
LVD0:
enable*1
LVD0: disable*2
tdet
—
—
500
µs
Figure 2.42, Figure 2.43
time*3
tdet
—
—
500
µs
Figure 2.44
LVD1 response delay time*3
tdet
—
—
350
µs
Figure 2.45
LVD2 response delay time*3
tdet
—
—
600
µs
Figure 2.46
Minimum VCC down time
tVOFF
500
—
—
µs
Figure 2.42, VCC = 1.0 V or
above
Power-on reset enable time
tW (POR)
1
—
—
ms
Figure 2.43, VCC = below 1.0
V
LVD1 operation stabilization time (after LVD1 is
enabled)
Td (E-A)
—
—
300
µs
Figure 2.45
LVD2 operation stabilization time (after LVD2 is
enabled)
Td (E-A)
—
—
1200
µs
Figure 2.46
Hysteresis width (POR)
VPORH
—
10
—
mV
—
Hysteresis width (LVD0, LVD1 and LVD2)
VLVH
—
60
—
mV
LVD0 selected
—
110
—
Vdet1_0 to Vdet1_2 selected
—
70
—
Vdet1_3 to Vdet1_9 selected
—
60
—
Vdet1_A to Vdet1_B selected
—
50
—
Vdet1_C to Vdet1_F selected
—
90
—
LVD2 selected
Power-on reset response delay time*3
LVD0 response delay
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for the POR/LVD.
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2. Electrical Characteristics
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
Figure 2.42
tdet
tPOR
Voltage detection reset timing
VPOR
VCC
1.0 V
tw(POR)
Internal reset signal
(active-low)
*1
tdet
tPOR
Note 1. tw(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the
valid voltage (1.0 V).
When VCC turns on, maintain tw(POR) for 1.0 ms or more.
Figure 2.43
Power-on reset timing
tVOFF
VCC
VLVH
Vdet0
Internal reset signal
(active-low)
tdet
Figure 2.44
tdet
tLVD0
Voltage detection circuit timing (Vdet0)
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2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tdet
tLVD1
When LVD1CR0.RN = 1
tLVD1
Figure 2.45
Voltage detection circuit timing (Vdet1)
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2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVCMPCR.LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.46
2.9
Voltage detection circuit timing (Vdet2)
CTSU Characteristics
Table 2.49
CTSU characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
—
2.10
Table 2.50
Comparator Characteristics
ACMPLP characteristics (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Reference voltage range
VREF
0
—
VCC-1.4
V
—
Input voltage range
VI
0
—
VCC
V
—
Internal reference voltage*1
—
1.34
1.44
1.54
V
—
Output delay time
Td
—
—
1.2
µs
VCC = 3.0 V
Low-speed mode
—
—
9
µs
Window mode
—
—
2
µs
High-speed mode
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Table 2.50
2. Electrical Characteristics
ACMPLP characteristics (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Offset voltage
Symbol
Min
Typ
Max
Unit
Test conditions
High-speed mode
—
—
—
50
mV
—
Low-speed mode
—
—
—
40
mV
—
Window mode
—
—
—
60
mV
—
VRFH
—
0.76 × VCC —
V
—
VRFL
—
0.24 × VCC —
V
—
Tcmp
100
—
—
µs
—
200
—
—
Internal reference voltage for window mode
Operation
stabilization wait
time
High-speed mode
Low-speed mode
Note 1. The internal reference voltage can be selected as ACMPLP reference voltage only when 2.94 V ≤ VCC ≤ 5.50 V.
Output voltage
Td
Td
+100 mV
Reference voltage
Input voltage
-100 mV
Figure 2.47
2.11
Output delay time
Flash Memory Characteristics
2.11.1
Table 2.51
Code Flash Memory Characteristics
Code flash characteristics (1)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Reprogramming/erasure cycle*1
NPEC
1000
—
—
Times
—
Data hold time After 1000 times NPEC
tDRP
20*2 *3
—
—
Year
Ta = +85°C
Ta = +105°C
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),
erasing can be performed n times for each block. For instance, when 4-byte programming is performed 512 times for different
addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address for several times as one erasure is not enabled (overwriting is prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. This result is target spec, may changed after reliability testing.
Table 2.52
Code flash characteristics (2) (1 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 1 MHz
Parameter
ICLK = 48 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
4-byte
tP4
—
86
732
—
34
321
µs
Erasure time
2-KB
tE2K
—
12.5
355
—
5.6
215
ms
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RA2L1 Datasheet
Table 2.52
2. Electrical Characteristics
Code flash characteristics (2) (2 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 1 MHz
Parameter
ICLK = 48 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
4-byte
tBC4
—
—
46.5
—
—
8.3
µs
2-KB
tBC2K
—
—
3681
—
—
240
µs
Erase suspended time
tSED
—
—
22.3
—
—
10.5
µs
Access window information program
Start-up area selection and security
setting time
tAWSSAS —
21.2
570
—
11.4
423
ms
OCD/serial programmer ID setting
time*1
tOSIS
—
84.7
2280
—
45.3
1690
ms
Flash memory mode transition wait
time 1
tDIS
2
—
—
2
—
—
µs
Flash memory mode transition wait
time 2
tMS
15
—
—
15
—
—
µs
Blank check time
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note:
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 1. Total time of four commands.
Table 2.53
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
ICLK = 8 MHz*2
ICLK = 1 MHz
Parameter
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
4-byte
tP4
—
86
732
—
39
356
µs
Erasure time
2-KB
tE2K
—
12.5
355
—
6.2
227
ms
Blank check time
4-byte
tBC4
—
—
46.5
—
—
11.3
µs
2-KB
tBC2K
—
—
3681
—
—
534
µs
Erase suspended time
tSED
—
—
22.3
—
—
11.7
µs
Access window information program
Start-up area selection and security
setting time
tAWSSAS —
21.2
570
—
12.2
435
ms
OCD/serial programmer ID setting
time*1
tOSIS
—
84.7
2280
—
48.7
1740
ms
Flash memory mode transition wait
time 1
tDIS
2
—
—
2
—
—
µs
Flash memory mode transition wait
time 2
tMS
15
—
—
15
—
—
µs
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note:
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 1. Total time of four commands.
Note 2. When 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V
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Table 2.54
2. Electrical Characteristics
Code flash characteristics (4)
Low-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
ICLK = 1 MHz
Parameter
ICLK = 2 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
4-byte
tP4
—
86
732
—
57
502
µs
Erasure time
2-KB
tE2K
—
12.5
355
—
8.8
280
ms
Blank check time
4-byte
tBC4
—
—
46.5
—
—
23.3
µs
2-KB
tBC2K
—
—
3681
—
—
1841
µs
Erase suspended time
tSED
—
—
22.3
—
—
16.2
µs
Access window information program
Start-up area selection and security
setting time
tAWSSAS —
21.2
570
—
15.9
491
ms
OCD/serial programmer ID setting
time*1
tOSIS
—
84.7
2280
—
63.5
1964
ms
Flash memory mode transition wait
time 1
tDIS
2
—
—
2
—
—
µs
Flash memory mode transition wait
time 2
tMS
15
—
—
15
—
—
µs
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz or 2 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note:
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 1. Total time of four commands.
2.11.2
Table 2.55
Data Flash Memory Characteristics
Data flash characteristics (1)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Reprogramming/erasure cycle*1
NDPEC
100000
1000000
—
Times
—
Data hold time
tDDRP
20*2 *3
—
—
Year
After 100000 times of NDPEC
5*2 *3
—
—
Year
Ta = +85°C
Ta = +105°C
After 1000000 times of NDPEC
—
1*2 *3
—
Year
After 10000 times of NDPEC
Ta = +25°C
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,024 times for different
addresses in 1-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address for several times as one erasure is not enabled. (overwriting is prohibited.)
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
Note 3. These results are target spec, may changed after reliability testing.
Table 2.56
Data flash characteristics (2) (1 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 4 MHz
Parameter
ICLK = 48 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
—
45
404
—
34
321
µs
Erasure time
1-KB
tDE1K
—
8.8
280
—
6.1
224
ms
Blank check time
1-byte
tDBC1
—
—
15.2
—
—
8.3
µs
1-KB
tDBC1K
—
—
1832
—
—
466
µs
tDSED
—
—
13.2
—
—
10.5
µs
Suspended time during erasing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 78 of 111
RA2L1 Datasheet
Table 2.56
2. Electrical Characteristics
Data flash characteristics (2) (2 of 2)
High-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
ICLK = 4 MHz
ICLK = 48 MHz
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Data flash STOP recovery time
tDSTOP
250
—
—
250
—
—
ns
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Table 2.57
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
ICLK = 8 MHz*1
ICLK = 4 MHz
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
—
45
404
—
39
356
µs
Erasure time
1-KB
tDE1K
—
8.8
280
—
7.3
248
ms
Blank check time
1-byte
tDBC1
—
—
15.2
—
—
11.3
µs
1-KB
tDBC1K
—
—
1.84
—
—
1.06
ms
Suspended time during erasing
tDSED
—
—
13.2
—
—
11.7
µs
Data flash STOP recovery time
tDSTOP
250
—
—
250
—
—
ns
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the
frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note:
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
Note 1. When 1.8 V ≤ VCC = AVCC0 ≤ 5.5 V
Table 2.58
Data flash characteristics (4)
Low-speed operating mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, Ta = -40 to +85°C
ICLK = 1 MHz
Parameter
ICLK = 2 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
—
86
732
—
57
502
µs
Erasure time
1-KB
tDE1K
—
19.7
504
—
12.4
354
ms
Blank check time
1-byte
tDBC1
—
—
46.5
—
—
23.3
µs
1-KB
tDBC1K
—
—
7.3
—
—
3.66
ms
Suspended time during erasing
tDSED
—
—
22.3
—
—
16.2
µs
Data flash STOP recovery time
tDSTOP
250
—
—
250
—
—
ns
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 2 MHz, the
frequency can be set to 1 MHz or 2 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of ICLK must be ± 1.0% during programming or erasing the flash memory. Confirm the frequency accuracy
of the clock source.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 79 of 111
RA2L1 Datasheet
2.11.3
Table 2.59
2. Electrical Characteristics
Serial Wire Debug (SWD)
SWD characteristics (1)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
80
—
—
ns
Figure 2.48
SWCLK clock high pulse width
tSWCKH
35
—
—
ns
SWCLK clock low pulse width
tSWCKL
35
—
—
ns
SWCLK clock rise time
tSWCKr
—
—
5
ns
SWCLK clock fall time
tSWCKf
—
—
5
ns
SWDIO setup time
tSWDS
16
—
—
ns
SWDIO hold time
tSWDH
16
—
—
ns
SWDIO data delay time
tSWDD
2
—
70
ns
Table 2.60
Figure 2.49
SWD characteristics (2)
Conditions: VCC = AVCC0 = 1.6 to 2.4 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
250
—
—
ns
Figure 2.48
SWCLK clock high pulse width
tSWCKH
120
—
—
ns
SWCLK clock low pulse width
tSWCKL
120
—
—
ns
SWCLK clock rise time
tSWCKr
—
—
5
ns
SWCLK clock fall time
tSWCKf
—
—
5
ns
SWDIO setup time
tSWDS
50
—
—
ns
SWDIO hold time
tSWDH
50
—
—
ns
SWDIO data delay time
tSWDD
2
—
170
ns
Figure 2.49
tSWCKcyc
tSWCKH
tSWCKf
SWCLK
tSWCKL
Figure 2.48
tSWCKr
SWD SWCLK timing
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 80 of 111
RA2L1 Datasheet
2. Electrical Characteristics
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 2.49
2.12
Table 2.61
SWD input/output timing
DCDC Characteristics
DCDC characteristics
Conditions: VCC = AVCC0 = VCC_DCDC = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
DCDC output Voltage
—
1.42
1.50
1.58
V
—
Power switching stabilization time
—
—
—
22
µs
Switch from LDO power to DCDC
power
—
—
—
60
µs
Switch from DCDC power to LDO
power
—
—
—
60
µs
Switch from DCDC power to LDO
power in the LC boost mode
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 81 of 111
RA2L1 Datasheet
Appendix 1.
Table 1.1
Appendix 1. Port States in each Processing Mode
Port States in each Processing Mode
Port states in each processing mode (1 of 4)
Port name
Reset
Software Standby Mode
P000/AN000/TS21/IRQ6
Hi-Z
Keep-O*1
P001/AN001/TS22/IRQ7
Hi-Z
Keep-O*1
P002/AN002/TS23/IRQ2
Hi-Z
Keep-O*1
P003/AN003/TS24
Hi-Z
Keep-O
P004/AN004/TS25/IRQ3
Hi-Z
Keep-O*1
P005/AN011
Hi-Z
Keep-O
P006/AN012
Hi-Z
Keep-O
P007/AN013
Hi-Z
Keep-O
P008/AN014
Hi-Z
Keep-O
P010/AN005/TS30-CFC
Hi-Z
Keep-O
P011/AN006/TS31-CFC
Hi-Z
Keep-O
P012/AN007/TS32-CFC
Hi-Z
Keep-O
P013/AN008/TS33-CFC
Hi-Z
Keep-O
P014/AN009/DA0
Hi-Z
[DA0 output (DACE0 = 1)]
DA0 output retained
[Other than the above (DACE0 = 0)]
Keep-O
P015/AN010/TS28-CFC/IRQ7_A
Hi-Z
Keep-O*1
P100/CMPIN0/TS26-CFC/AGTIO0_A/GTETRGA_A/GTIOC5B_A/RXD0_A/
MISO0_A/SCL0_A/SCK1_A/SCL1_B/MISOA_A/KRM00/IRQ2_A
Hi-Z
[AGTIO0_A output selected]
AGTIO0_A output*2
[Other than the above]
Keep-O*1
P101/CMPREF0/TS16-CFC/AGTEE0/GTETRGB_A/GTIOC5A_A/TXD0_A/
MOSI0_A/SDA0_A/CTS1_RTS1_A/SDA1_B/MOSIA_A/KRM01/IRQ1_A
Hi-Z
Keep-O*1
P102/CMPIN1/ADTRG0_A/TS15-CFC/AGTO0/GTOWLO_A/GTIOC2B_A/
CRX0_C /SCK0_A/TXD2_D/MOSI2_D/SDA2_D/RSPCKA_A/KRM02
Hi-Z
[AGTO0 selected]
AGTO0 output*2
[Other than the above]
Keep-O*1
P103/CMPREF1/TS14-CFC/GTOWUP_A/GTIOC2A_A/CTX0_C/
CTS0_RTS0_A/SSLA0_A/KRM03
Hi-Z
Keep-O*1
P104/TS13-CFC/GTETRGB_B/GTIOC1B_C/RXD0_C/MISO0_C/SCL0_C/
SSLA1_A/KRM04/IRQ1_B
Hi-Z
Keep-O*1
P105/TS34-CFC/GTETRGA_C/GTIOC1A_C/SSLA2_A/KRM05/IRQ0_B
Hi-Z
Keep-O*1
P106/GTIOC8B_A/SSLA3_A/KRM06
Hi-Z
Keep-O*1
P107/GTIOC8A_A/KRM07
Hi-Z
Keep-O*1
P108/SWDIO/GTOULO_C/GTIOC0B_A/CTS9_RTS9_B/SSLB0_B
Pull-up
Keep-O
P109/TS10-CFC/GTOVUP_A/GTIOC1A_A/CTX0_A//SCK1_E/TXD9_B/
MOSI9_B/SDA9_B/MOSIB_B/CLKOUT_B
Hi-Z
[CLKOUT selected]
CLKOUT output
[Other than the above]
Keep-O
P110/TS11-CFC/GTOVLO_A/GTIOC1B_A/CRX0_A/CTS2_RTS2_B/RXD9_B/
MISO9_B/SCL9_B/MISOB_B/IRQ3_A/VCOUT
Hi-Z
[ACMPLP selected]
VCOUT output
[Other than the above]
Keep-O*1
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 82 of 111
RA2L1 Datasheet
Table 1.1
Appendix 1. Port States in each Processing Mode
Port states in each processing mode (2 of 4)
Port name
Reset
Software Standby Mode
P111/TS12-CFC/AGTOA0/GTIOC3A_A/SCK2_B/SCK9_B/RSPCKB_B/
IRQ4_A
Hi-Z
[AGTOA0 selected]
AGTOA0 output*2
[Other than the above]
Keep-O*1
P112/TSCAP_C/AGTOB0/GTIOC3B_A/TXD2_B/MOSI2_B/SDA2_B/SCK1_D/
SSLB0_C
Hi-Z
[AGTOB0 selected]
AGTOB0 output*2
[Other than the above]
Keep-O
P113/TS27-CFC/GTIOC2A_C
Hi-Z
Keep-O
P114/TS29-CFC/GTIOC2B_C
Hi-Z
Keep-O
P115/TS35-CFC/GTIOC4A_C
Hi-Z
Keep-O
P200/NMI
Hi-Z
Hi-Z
P201/MD
Pull-up
Keep-O
P202/SCK2_A/RXD9_A/MISO9_A/SCL9_A/MISOB_A
Hi-Z
Keep-O
P203/CTS2_RTS2_A/TXD9_A/MOSI9_A/SDA9_A/MOSIB_A
Hi-Z
Keep-O
P204/CACREF_A/TS0/AGTIO1_A/GTIW_A/GTIOC4B_B/SCK0_D/SCK9_A/
SCL0_B/RSPCKB_A
Hi-Z
[AGTIO1_A output selected]
AGTIO1_A output*2
[Other than the above]
Keep-O*1
P205/AGTO1/GTIV_A/GTIOC4A_B/TXD0_D/MOSI0_D/SDA0_D/
CTS9_RTS9_A/ SCL1_A/SSLB0_A/IRQ1/CLKOUT_A
Hi-Z
[AGTO1 selected]
AGTO1 output*2
[CLKOUT selected]
CLKOUT output
[Other than the above]
Keep-O*1
P206/GTIU_A/RXD0_D/MISO0_D/SCL0_D/SDA1_A/SSLB1_A/IRQ0
Hi-Z
Keep-O*1
P207
Hi-Z
Keep-O
P208/AGTOB0_A
Hi-Z
[AGTOB0_A selected]
AGTOB0_A output*2
[Other than the above]
Keep-O
P212/EXTAL /AGTEE1/GTETRGB_D/GTIOC0B_D/RXD1_A/MISO1_A/
SCL1_A/IRQ3_B
Hi-Z
Keep-O*1
P213/XTAL /GTETRGA_D/GTIOC0A_D/TXD1_A/MOSI1_A/SDA1_A/IRQ2_B
Hi-Z
Keep-O*1
P214/XCOUT, P215/XCIN
Hi-Z
[Sub-clock Oscillator selected]
Sub-clock Oscillator is operating
[Other than the above]
Hi-Z
P300/SWCLK/GTOUUP_C/GTIOC0A_A/SSLB1_B
Pull-up
Keep-O
P301/TS9-CFC/AGTIO0_D/GTOULO_A/GTIOC4B_A/RXD2_A/MISO2_A/
SCL2_A/CTS9_RTS9_D/SSLB2_B/IRQ6_A
Hi-Z
[AGTIO0_D output selected]
AGTIO0_D output*2
[Other than the above]
Keep-O*1
P302/TS8-CFC/GTOUUP_A/GTIOC4A_A/TXD2_A/MOSI2_A/SDA2_A/
SSLB3_B/IRQ5_A
Hi-Z
Keep-O*1
P303/TS2-CFC/GTIOC7B_A
Hi-Z
Keep-O
P304/GTIOC7A_A
Hi-Z
Keep-O
P305, P306, P307
Hi-Z
Keep-O
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 83 of 111
RA2L1 Datasheet
Table 1.1
Appendix 1. Port States in each Processing Mode
Port states in each processing mode (3 of 4)
Port name
Reset
Software Standby Mode
P400/CACREF_C/AGTIO1_C/GTIOC6A_A/SCK0_B/SCK1_B/SCL0_A/
IRQ0_A
Hi-Z
[AGTIO1_C output selected]
AGTIO1_C output*2
[Other than the above]
Keep-O*1
P401/GTETRGA_B/GTIOC6B_A/CTX0_B/CTS0_RTS0_B/TXD1_B/MOSI1_B/ Hi-Z
SDA1_B/SDA0_A/IRQ5
Keep-O*1
P402/TS18/AGTIO0_E/AGTIO1_D/CRX0_B/RXD1_B/MISO1_B/SCL1_B/
IRQ4
Hi-Z
[AGTIO0_E, AGTIO1_D output
selected]
AGTIO0_E, AGTIO1_D output*2
[Other than the above]
Keep-O*1
P403/TS17/AGTIO0_F/AGTIO1_E/GTIOC3A_B/CTS1_RTS1_B
Hi-Z
[AGTIO0_F, AGTIO1_E output
selected]
AGTIO0_F, AGTIO1_E output*2
[Other than the above]
Keep-O*1
P404/GTIOC3B_B,
P405/GTIOC1A_B,
P406/GTIOC1B_B
Hi-Z
Keep-O
P407/ADTRG0_B/AGTIO0_C/RTCOUT/CTS0_RTS0_D/SDA0_B/SSLB3_A
Hi-Z
[AGTIO0_C output selected]
AGTIO0_C output*2
[RTCOUT selected]
RTCOUT output
[Other than the above]
Keep-O*1
P408/TS4/GTOWLO_B/GTIOC5B_B/CTS1_RTS1_D/RXD3_A/MISO3_A/
SCL3_A/SCL0_C/IRQ7_B
Hi-Z
Keep-O*1
P409/TS5/GTOWUP_B/GTIOC5A_B/TXD3_A/MOSI3_A/SDA3_A/IRQ6_B
Hi-Z
Keep-O*1
P410/TS6/AGTOB1/GTOVLO_B/GTIOC9B_A/RXD0_B/MISO0_B/SCL0_B/
SCK3_A/MISOA_B/IRQ5_B
Hi-Z
[AGTOB1 selected]
AGTOB1 output*2
[Other than the above]
Keep-O*1
P411/TS7/AGTOA1/GTOVUP_B/GTIOC9A_A/TXD0_B/MOSI0_B/SDA0_B/
CTS3_RTS3_A/MOSIA_B/IRQ4_B
Hi-Z
[AGTOA1 selected]
AGTOA1 output*2
[Other than the above]
Keep-O*1
P412/GTOULO_B/SCK0_E/RSPCKA_B
Hi-Z
Keep-O
P413/GTOUUP_B/CTS0_RTS0_E/SSLA0_B
Hi-Z
Keep-O
P414/GTIOC0B_C/SSLA1_B
Hi-Z
Keep-O
P415/GTIOC0A_C/SSLA2_B
Hi-Z
Keep-O
P500/GTIU_B/GTIOC2A_B
Hi-Z
Keep-O
P501/AN017/GTIV_B/GTIOC2B_B/TXD1_C/MOSI1_C/SDA1_C
Hi-Z
Keep-O
P502/AN018/GTIW_B/GTIOC3B_C/RXD1_C/MISO1_C/SCL1_C
Hi-Z
Keep-O
P503/AN019/GTETRGA_E/SCK1_C
Hi-Z
Keep-O
P504/AN020/GTETRGB_E/CTS1_RTS1_C
Hi-Z
Keep-O
P505
Hi-Z
Keep-O
P600/GTIOC6B_C/SCK9_C
Hi-Z
Keep-O
P601/GTIOC6A_C/RXD9_C/MISO9_C/SCL9_C
Hi-Z
Keep-O
P602/GTIOC7B_B/TXD9_C/MOSI9_C/SDA9_C
Hi-Z
Keep-O
P603/GTIOC7A_B/CTS9_RTS9_C
Hi-Z
Keep-O
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 84 of 111
RA2L1 Datasheet
Table 1.1
Appendix 1. Port States in each Processing Mode
Port states in each processing mode (4 of 4)
Port name
Reset
Software Standby Mode
P608/GTIOC4B_C
Hi-Z
Keep-O
P609/GTIOC5A_C
Hi-Z
Keep-O
P610/GTIOC5B_C
Hi-Z
Keep-O
P708/RXD1_D/MISO1_D/SCL1_D/SSLA3_B
Hi-Z
Keep-O
P714
Hi-Z
Keep-O
P808, P809
Hi-Z
Keep-O
Note:
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins become high-impedance.
Note 1. Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.
Note 2. AGTIO output is enabled while LOCO or SOSC is selected as a count source.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 85 of 111
RA2L1 Datasheet
Appendix 2.
Appendix 2. Package Dimensions
Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
0.6
HD
Unit: mm
*1 D
75
51
*2
100
HE
50
E
76
26
1
25
NOTE 4
Index area
NOTE 3
F
S
*3
A1
c
0.25
A2
A
e
y S
Lp
L1
Detail F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
bp
M
Min
Nom
Max
D
13.9
14.0
14.1
E
13.9
14.0
14.1
A2
1.4
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.1
LQFP 100-pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 86 of 111
RA2L1 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP80-12x12-0.50
PLQP0080KB-B
—
0.5
HD
Unit: mm
*1 D
41
40
80
21
*2
E
61
1
20
HE
60
NOTE 4
Index area
NOTE 3
F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
S
y
S
*3
0.25
A1
c
A2
A
e
Lp
L1
bp
M
Min
Nom
Max
D
11.9
12.0
12.1
12.1
E
11.9
12.0
A2
1.4
HD
13.8
14.0
14.2
HE
13.8
14.0
14.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
Detail F
© 2017 Renesas Electronics Corporation. All rights reserved.
Figure 2.2
LQFP 80-pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 87 of 111
RA2L1 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.3
LQFP 64-pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 88 of 111
RA2L1 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP48-7x7-0.50
PLQP0048KB-B
—
0.2
HD
Unit: mm
*1 D
36
25
*2
48
13
1
12
Index area
NOTE 4
NOTE 3
F
S
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
y S
*3
bp
0.25
A2
A1
A
M
c
e
Lp
L1
Detail F
Figure 2.4
HE
24
E
37
LQFP 48-pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Min
Nom
Max
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
1.4
HD
8.8
9.0
9.2
HE
8.8
9.0
9.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Page 89 of 111
RA2L1 Datasheet
Appendix 2. Package Dimensions
JEITA Package code
RENESAS code
MASS(TYP.)[g]
P-HWQFN048-7x7-0.50
PWQN0048KC-A
0.13 g
2X
aaa C
36
25
37
24
D
INDEX AREA
(D/2 X E/2)
48
2X
aaa C
13
1
12
B
A
E
ccc C
C
SEATING PLANE
A (A3) A1
b(48X)
e
48X
bbb
ddd
eee C
E2
1
fff
fff
C A B
12
EXPOSED
13
DIE PAD
48
C A B
C A B
C
Reference
Symbol
Dimension in Millimeters
Min.
A
－
－
0.80
0.00
0.02
0.05
0.203 REF.
A3
0.20
D
24
37
36
25
L(48X)
Figure 2.5
K(48X)
Max.
A1
b
D2
Nom.
0.25
0.30
7.00 BSC
E
7.00 BSC
e
0.50 BSC
L
0.30
0.40
0.50
K
0.20
－
－
D2
5.25
5.30
5.35
E2
5.25
5.30
5.35
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
HWQFN 48-pin
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 90 of 111
RA2L1 Datasheet
Appendix 3.
Appendix 3. I/O Registers
I/O Registers
This appendix describes I/O register addresses, access cycles, and reset values by function.
3.1
Peripheral Base Addresses
This section provides the base addresses for peripherals described in this manual.
Table 3.1 shows the name, description, and the base address of each peripheral.
Table 3.1
Peripheral base address (1 of 2)
Name
Description
Base address
MPU
Memory Protection Unit
0x4000_0000
SRAM
SRAM Control
0x4000_2000
BUS
BUS Control
0x4000_3000
DTC
Data Transfer Controller
0x4000_5400
ICU
Interrupt Controller
0x4000_6000
DBG
Debug Function
0x4001_B000
SYSC
System Control
0x4001_E000
PORT0
Port 0 Control Registers
0x4004_0000
PORT1
Port 1 Control Registers
0x4004_0020
PORT2
Port 2 Control Registers
0x4004_0040
PORT3
Port 3 Control Registers
0x4004_0060
PORT4
Port 4 Control Registers
0x4004_0080
PORT5
Port 5 Control Registers
0x4004_00A0
PORT6
Port 6 Control Registers
0x4004_00C0
PORT7
Port 7 Control Registers
0x4004_00E0
PORT8
Port 8 Control Registers
0x4004_0100
PFS
Pmn Pin Function Control Register
0x4004_0800
ELC
Event Link Controller
0x4004_1000
POEG
Port Output Enable Module for GPT
0x4004_2000
RTC
Realtime Clock
0x4004_4000
WDT
Watchdog Timer
0x4004_4200
IWDT
Independent Watchdog Timer
0x4004_4400
CAC
Clock Frequency Accuracy Measurement Circuit
0x4004_4600
MSTP
Module Stop Control B, C, D
0x4004_7000
CAN0
CAN0 Module
0x4005_0000
IIC0
Inter-Integrated Circuit 0
0x4005_3000
IIC0WU
Inter-Integrated Circuit 0 Wakeup Unit
0x4005_3014
IIC1
Inter-Integrated Circuit 1
0x4005_3100
DOC
Data Operation Circuit
0x4005_4100
ADC12
12-bit A/D Converter
0x4005_C000
DAC12
12-bit D/A Converter
0x4005_E000
SCI0
Serial Communication Interface 0
0x4007_0000
SCI1
Serial Communication Interface 1
0x4007_0020
SCI2
Serial Communication Interface 2
0x4007_0040
SCI3
Serial Communication Interface 3
0x4007_0060
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 91 of 111
RA2L1 Datasheet
Table 3.1
Appendix 3. I/O Registers
Peripheral base address (2 of 2)
Name
Description
Base address
SCI9
Serial Communication Interface 9
0x4007_0120
SPI0
Serial Peripheral Interface 0
0x4007_2000
SPI1
Serial Peripheral Interface 1
0x4007_2100
CRC
CRC Calculator
0x4007_4000
GPT320
General PWM Timer 0 (32-bit)
0x4007_8000
GPT321
General PWM Timer 1 (32-bit)
0x4007_8100
GPT322
General PWM Timer 2 (32-bit)
0x4007_8200
GPT323
General PWM Timer 3 (32-bit)
0x4007_8300
GPT164
General PWM Timer 4 (16-bit)
0x4007_8400
GPT165
General PWM Timer 5 (16-bit)
0x4007_8500
GPT166
General PWM Timer 6 (16-bit)
0x4007_8600
GPT167
General PWM Timer 7 (16-bit)
0x4007_8700
GPT168
General PWM Timer 8 (16-bit)
0x4007_8800
GPT169
General PWM Timer 9 (16-bit)
0x4007_8900
GPT_OPS
Output Phase Switching Controller
0x4007_8FF0
KINT
Key Interrupt Function
0x4008_0000
CTSU
Capacitive Sensing Unit
0x4008_2000
AGT0
Low Power Asynchronous General Purpose Timer 0
0x4008_4000
AGT1
Low Power Asynchronous General Purpose Timer 1
0x4008_4100
ACMPLP
Low-Power Analog Comparator
0x4008_5E00
FLCN
Flash I/O Registers
0x407E_C000
Note:
3.2
Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral
Access Cycles
This section provides access cycle information for the I/O registers described in this manual.
The following information applies to Table 3.2:
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
Note:
This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus master such as DTC.
Table 3.2 shows the register access cycles for non-GPT modules.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 92 of 111
RA2L1 Datasheet
Table 3.2
Appendix 3. I/O Registers
Access cycles for non-GPT modules
Number of access cycles
Address
ICLK = PCLK
ICLK > PCLK*1
Read
Read
Cycle
unit
Peripherals
From
To
MPU, SRAM, BUS,
DTC, ICU, DBG
0x4000_2000
0x4001_BFFF
3
ICLK
Memory Protection Unit, SRAM,
Buses, Data Transfer Controller,
Interrupt Controller, CPU, Flash
Memory
SYSC
0x4001_E000
0x4001_E6FF
4
ICLK
Low Power Modes, Resets, Low
Voltage Detection, Clock
Generation Circuit, Register
Write Protection
PORTn, PFS, ELC,
POEG, RTC, WDT,
IWDT, CAC, MSTP
0x4004_0000
0x4004_7FFF
3
2 to 3
PCLKB
I/O Ports, Event Link Controller,
Port Output Enable for GPT,
Realtime Clock, Watchdog Timer,
Independent Watchdog Timer,
Clock Frequency Accuracy
Measurement Circuit, Module
Stop Control
CAN0,IICn (n = 0,
1),IIC0WU, DOC,
ADC12, DAC12
0x4005_0000
0x4005_EFFF
3
2 to 3
PCLKB
Controller Area Network Module,
I2C Bus Interface, Data
Operation Circuit, 12-bit A/D
Converter
SCIn (n = 0*2 to 2, 9)
0x4007_0000
0x4007_0EFF
5
2 to 3
PCLKB
Serial Communications Interface
0x4007_2000
0x4007_2FFF
5
2 to 3
PCLKB
Serial Peripheral Interface
CRC
0x4007_4000
0x4007_4FFF
3
2 to 3
PCLKB
CRC Calculator
GPT32n (n = 0 to 3),
GPT16n (n = 4 to 9),
GPT_OPS
0x4007_8000
0x4007_BFFF
PCLKB
General PWM Timer
KINT, CTSU
0x4008_0000
0x4008_2FFF
3
2 to 3
PCLKB
Key interrupt Function,
Capacitive Sensing Unit
AGTn
0x4008_4000
0x4008_4FFF
3
2 to 3
PCLKB
Low Power Asynchronous
General Purpose Timer
ACMPLP
0x4008_5000
0x4008_6FFF
3
2 to 3
PCLKB
Low-Power Analog Comparator
FLCN
0x407E_C000 0x407E_FFFF
7
7
ICLK
Data Flash, Temperature Sensor,
Capacitive Sensing Unit, Flash
Control
SPIn (n = 0,
1)*3
Write
Write
See Table 3.3.
Related function
Note 1. If the number of PCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the maximum
value is rounded up to the decimal point. For example, 1.5 to 2.5 is 1 to 3.
Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in
Table 3.2. When accessing an 8-bit register (FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in Table 3.2.
Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit
register (SPDR_HA), the access cycles are as shown in Table 3.2.
Table 3.3 shows register access cycles for GPT modules.
Table 3.3
Access cycles for GPT modules (1 of 2)
Frequency ratio between ICLK
and PCLK
Number of access cycles
Read
Write
Cycle unit
ICLK > PCLKD = PCLKB
5 to 6
3 to 4
PCLKB
ICLK > PCLKD > PCLKB
3 to 4
2 to 3
PCLKB
PCLKD = ICLK = PCLKB
6
4
PCLKB
PCLKD = ICLK > PCLKB
2 to 3
1 to 2
PCLKB
PCLKD > ICLK = PCLKB
4
3
PCLKB
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 93 of 111
RA2L1 Datasheet
Table 3.3
Appendix 3. I/O Registers
Access cycles for GPT modules (2 of 2)
Frequency ratio between ICLK
and PCLK
Number of access cycles
Read
PCLKD > ICLK > PCLKB
3.3
Write
2 to 3
Cycle unit
1 to 2
PCLKB
Register Descriptions
This section provides information associated with registers described in this manual.
Table 3.4 shows a list of registers including address offsets, address sizes, access rights, and reset values.
Table 3.4
Register description (1 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
MPU
—
—
—
MMPUCTLA
Bus Master MPU Control Register
0x000
16
R/W
0x0000
0xFFFF
MPU
—
—
—
MMPUPTA
Group A Protection of Register
0x102
16
R/W
0x0000
0xFFFF
MPU
4
0x010
0-3
MMPUACA%s
Group A Region %s access control
register
0x200
16
R/W
0x0000
0xFFFF
MPU
4
0x010
0-3
MMPUSA%s
Group A Region %s Start Address
Register
0x204
32
R/W
0x00000000
0x00000003
MPU
4
0x010
0-3
MMPUEA%s
Group A Region %s End Address Register
0x208
32
R/W
0x00000003
0x00000003
MPU
—
—
—
SMPUCTL
Slave MPU Control Register
0xC00
16
R/W
0x0000
0xFFFF
MPU
—
—
—
SMPUMBIU
Access Control Register for Memory Bus 1
0xC10
16
R/W
0x0000
0xFFFF
MPU
—
—
—
SMPUFBIU
Access Control Register for Internal
Peripheral Bus 9
0xC14
16
R/W
0x0000
0xFFFF
MPU
—
—
—
SMPUSRAM0
Access Control Register for Memory Bus 4
0xC18
16
R/W
0x0000
0xFFFF
MPU
—
—
—
SMPUP0BIU
Access Control Register for Internal
Peripheral Bus 1
0xC20
16
R/W
0x0000
0xFFFF
MPU
—
—
—
SMPUP2BIU
Access Control Register for Internal
Peripheral Bus 3
0xC24
16
R/W
0x0000
0xFFFF
MPU
—
—
—
SMPUP6BIU
Access Control Register for Internal
Peripheral Bus 7
0xC28
16
R/W
0x0000
0xFFFF
MPU
—
—
—
MSPMPUOAD
Stack Pointer Monitor Operation After
Detection Register
0xD00
16
R/W
0x0000
0xFFFF
MPU
—
—
—
MSPMPUCTL
Stack Pointer Monitor Access Control
Register
0xD04
16
R/W
0x0000
0xFEFF
MPU
—
—
—
MSPMPUPT
Stack Pointer Monitor Protection Register
0xD06
16
R/W
0x0000
0xFFFF
MPU
—
—
—
MSPMPUSA
Main Stack Pointer (MSP) Monitor Start
Address Register
0xD08
32
R/W
0x00000000
0x00000000
MPU
—
—
—
MSPMPUEA
Main Stack Pointer (MSP) Monitor End
Address Register
0xD0C
32
R/W
0x00000000
0x00000000
MPU
—
—
—
PSPMPUOAD
Stack Pointer Monitor Operation After
Detection Register
0xD10
16
R/W
0x0000
0xFFFF
MPU
—
—
—
PSPMPUCTL
Stack Pointer Monitor Access Control
Register
0xD14
16
R/W
0x0000
0xFEFF
MPU
—
—
—
PSPMPUPT
Stack Pointer Monitor Protection Register
0xD16
16
R/W
0x0000
0xFFFF
MPU
—
—
—
PSPMPUSA
Process Stack Pointer (PSP) Monitor Start
Address Register
0xD18
32
R/W
0x00000000
0x00000000
MPU
—
—
—
PSPMPUEA
Process Stack Pointer (PSP) Monitor End
Address Register
0xD1C
32
R/W
0x00000000
0x00000000
SRAM
—
—
—
PARIOAD
SRAM Parity Error Operation After
Detection Register
0x00
8
R/W
0x00
0xFF
SRAM
—
—
—
SRAMPRCR
SRAM Protection Register
0x04
8
R/W
0x00
0xFF
SRAM
—
—
—
ECCMODE
ECC Operating Mode Control Register
0xC0
8
R/W
0x00
0xFF
SRAM
—
—
—
ECC2STS
ECC 2-Bit Error Status Register
0xC1
8
R/W
0x00
0xFF
SRAM
—
—
—
ECC1STSEN
ECC 1-Bit Error Information Update
Enable Register
0xC2
8
R/W
0x00
0xFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 94 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (2 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
SRAM
—
—
—
ECC1STS
ECC 1-Bit Error Status Register
0xC3
8
R/W
0x00
0xFF
SRAM
—
—
—
ECCETST
ECC Test Control Register
0xC4
8
R/W
0x00
0xFF
SRAM
—
—
—
ECCPRCR
ECC Protection Register
0xC4
8
R/W
0x00
0xFF
SRAM
—
—
—
ECCPRCR2
ECC Protection Register 2
0xD0
8
R/W
0x00
0xFF
SRAM
—
—
—
ECCOAD
SRAM ECC Error Operation After
Detection Register
0xD8
8
R/W
0x00
0xFF
BUS
—
—
—
BUSMCNTSYS
Master Bus Control Register SYS
0x1008
16
R/W
0x0000
0xFFFF
BUS
—
—
—
BUSMCNTDMA
Master Bus Control Register DMA
0x100C
16
R/W
0x0000
0xFFFF
BUS
—
—
—
BUS3ERRADD
Bus Error Address Register 3
0x1820
32
R
0x00000000
0x00000000
BUS
—
—
—
BUS3ERRSTAT
BUS Error Status Register 3
0x1824
8
R
0x00
0xFE
BUS
—
—
—
BUS4ERRADD
Bus Error Address Register 4
0x1830
32
R
0x00000000
0x00000000
BUS
—
—
—
BUS4ERRSTAT
BUS Error Status Register 4
0x1834
8
R
0x00
0xFE
DTC
—
—
—
DTCCR
DTC Control Register
0x00
8
R/W
0x08
0xFF
DTC
—
—
—
DTCVBR
DTC Vector Base Register
0x04
32
R/W
0x00000000
0xFFFFFFFF
DTC
—
—
—
DTCST
DTC Module Start Register
0x0C
8
R/W
0x00
0xFF
DTC
—
—
—
DTCSTS
DTC Status Register
0x0E
16
R
0x0000
0xFFFF
ICU
8
0x1
0-7
IRQCR%s
IRQ Control Register
0x000
8
R/W
0x00
0xFF
ICU
—
—
—
NMICR
NMI Pin Interrupt Control Register
0x100
8
R/W
0x00
0xFF
ICU
—
—
—
NMIER
Non-Maskable Interrupt Enable Register
0x120
16
R/W
0x0000
0xFFFF
ICU
—
—
—
NMICLR
Non-Maskable Interrupt Status Clear
Register
0x130
16
R/W
0x0000
0xFFFF
ICU
—
—
—
NMISR
Non-Maskable Interrupt Status Register
0x140
16
R
0x0000
0xFFFF
ICU
—
—
—
WUPEN
Wake Up Interrupt Enable Register
0x1A0
32
R/W
0x00000000
0xFFFFFFFF
ICU
—
—
—
IELEN
ICU event Enable Register
0x1C0
8
R/W
0x00
0xFF
ICU
—
—
—
SELSR0
SYS Event Link Setting Register
0x200
16
R/W
0x0000
0xFFFF
ICU
32
0x4
0-31
IELSR%s
ICU Event Link Setting Register %s
0x300
32
R/W
0x00000000
0xFFFFFFFF
DBG
—
—
—
DBGSTR
Debug Status Register
0x00
32
R
0x00000000
0xFFFFFFFF
DBG
—
—
—
DBGSTOPCR
Debug Stop Control Register
0x10
32
R/W
0x00000003
0xFFFFFFFF
SYSC
—
—
—
SBYCR
Standby Control Register
0x00C
16
R/W
0x0000
0xFFFF
SYSC
—
—
—
MSTPCRA
Module Stop Control Register A
0x01C
32
R/W
0xFFBFFFFF
0xFFFFFFFF
SYSC
—
—
—
SCKDIVCR
System Clock Division Control Register
0x020
32
R/W
0x04000404
0xFFFFFFFF
SYSC
—
—
—
SCKSCR
System Clock Source Control Register
0x026
8
R/W
0x01
0xFF
SYSC
—
—
—
MEMWAIT
Memory Wait Cycle Control Register for
Code Flash
0x031
8
R/W
0x00
0xFF
SYSC
—
—
—
MOSCCR
Main Clock Oscillator Control Register
0x032
8
R/W
0x01
0xFF
SYSC
—
—
—
HOCOCR
High-Speed On-Chip Oscillator Control
Register
0x036
8
R/W
0x00
0xFE
SYSC
—
—
—
MOCOCR
Middle-Speed On-Chip Oscillator Control
Register
0x038
8
R/W
0x00
0xFF
SYSC
—
—
—
OSCSF
Oscillation Stabilization Flag Register
0x03C
8
R
0x00
0xFE
SYSC
—
—
—
CKOCR
Clock Out Control Register
0x03E
8
R/W
0x00
0xFF
SYSC
—
—
—
OSTDCR
Oscillation Stop Detection Control Register
0x040
8
R/W
0x00
0xFF
SYSC
—
—
—
OSTDSR
Oscillation Stop Detection Status Register
0x041
8
R/W
0x00
0xFF
SYSC
—
—
—
LPOPT
Lower Power Operation Control Register
0x04C
8
R/W
0x00
0xFF
SYSC
—
—
—
MOCOUTCR
MOCO User Trimming Control Register
0x061
8
R/W
0x00
0xFF
SYSC
—
—
—
HOCOUTCR
HOCO User Trimming Control Register
0x062
8
R/W
0x00
0xFF
SYSC
—
—
—
SNZCR
Snooze Control Register
0x092
8
R/W
0x00
0xFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 95 of 111
RA2L1 Datasheet
Table 3.4
Peripheral
name
Appendix 3. I/O Registers
Register description (3 of 15)
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
SYSC
—
—
—
SNZEDCR0
Snooze End Control Register
0x094
8
R/W
0x00
0xFF
SYSC
—
—
—
SNZREQCR
Snooze Request Control Register
0x098
32
R/W
0x00000000
0xFFFFFFFF
SYSC
—
—
—
PSMCR
Power Save Memory Control Register
0x09F
8
R/W
0x00
0xFF
SYSC
—
—
—
OPCCR
Operating Power Control Register
0x0A0
8
R/W
0x01
0xFF
SYSC
—
—
—
MOSCWTCR
Main Clock Oscillator Wait Control
Register
0x0A2
8
R/W
0x05
0xFF
SYSC
—
—
—
SOPCCR
Sub Operating Power Control Register
0x0AA
8
R/W
0x00
0xFF
SYSC
—
—
—
RSTSR1
Reset Status Register 1
0x0C0
16
R/W
0x0000
0xE0F8
SYSC
—
—
—
LVD1CR1
Voltage Monitor 1 Circuit Control Register
0x0E0
8
R/W
0x01
0xFF
SYSC
—
—
—
LVD1SR
Voltage Monitor 1 Circuit Status Register
0x0E1
8
R/W
0x02
0xFF
SYSC
—
—
—
LVD2CR1
Voltage Monitor 2 Circuit Control Register
1
0x0E2
8
R/W
0x01
0xFF
SYSC
—
—
—
LVD2SR
Voltage Monitor 2 Circuit Status Register
0x0E3
8
R/W
0x02
0xFF
SYSC
—
—
—
PRCR
Protect Register
0x3FE
16
R/W
0x0000
0xFFFF
SYSC
—
—
—
SYOCDCR
System Control OCD Control Register
0x040E
8
R/W
0x00
0xFF
SYSC
—
—
—
RSTSR0
Reset Status Register 0
0x410
8
R/W
0x00
0xF0
SYSC
—
—
—
RSTSR2
Reset Status Register 2
0x411
8
R/W
0x00
0xFE
SYSC
—
—
—
MOMCR
Main Clock Oscillator Mode Oscillation
Control Register
0x413
8
R/W
0x00
0xFF
SYSC
—
—
—
LVCMPCR
Voltage Monitor Circuit Control Register
0x417
8
R/W
0x00
0xFF
SYSC
—
—
—
LVDLVLR
Voltage Detection Level Select Register
0x418
8
R/W
0x07
0xFF
SYSC
—
—
—
LVD1CR0
Voltage Monitor 1 Circuit Control Register
0
0x41A
8
R/W
0x80
0xF7
SYSC
—
—
—
LVD2CR0
Voltage Monitor 2 Circuit Control Register
0
0x41B
8
R/W
0x80
0xF7
SYSC
—
—
—
DCDCCTL
DCDC/LDO Control Register
0x440
8
R/W
0xC0
0xFF
SYSC
—
—
—
VCCSEL
Voltage Level Selection Control Register
0x441
8
R/W
0x00
0xFF
SYSC
—
—
—
SOSCCR
Sub-Clock Oscillator Control Register
0x480
8
R/W
0x01
0xFF
SYSC
—
—
—
SOMCR
Sub-Clock Oscillator Mode Control
Register
0x481
8
R/W
0x00
0xFF
SYSC
—
—
—
SOMRG
Sub-Clock Oscillator Margin Check
Register
0x482
8
R/W
0x00
0xFF
SYSC
—
—
—
LOCOCR
Low-Speed On-Chip Oscillator Control
Register
0x490
8
R/W
0x00
0xFF
SYSC
—
—
—
LOCOUTCR
LOCO User Trimming Control Register
0x492
8
R/W
0x00
0xFF
PORT0,3-8
—
—
—
PCNTR1
Port Control Register 1
0x000
32
R/W
0x00000000
0xFFFFFFFF
PORT0,3-8
—
—
—
PODR
Port Control Register 1
0x000
16
R/W
0x0000
0xFFFF
PORT0,3-8
—
—
—
PDR
Port Control Register 1
0x002
16
R/W
0x0000
0xFFFF
PORT0,3-8
—
—
—
PCNTR2
Port Control Register 2
0x004
32
R
0x00000000
0xFFFF0000
PORT0,3-8
—
—
—
PIDR
Port Control Register 2
0x006
16
R
0x0000
0x0000
PORT0,3-8
—
—
—
PCNTR3
Port Control Register 3
0x008
32
W
0x00000000
0xFFFFFFFF
PORT0,3-8
—
—
—
PORR
Port Control Register 3
0x008
16
W
0x0000
0xFFFF
PORT0,3-8
—
—
—
POSR
Port Control Register 3
0x00A
16
W
0x0000
0xFFFF
PORT1-2
—
—
—
PCNTR1
Port Control Register 1
0x000
32
R/W
0x00000000
0xFFFFFFFF
PORT1-2
—
—
—
PODR
Port Control Register 1
0x000
16
R/W
0x0000
0xFFFF
PORT1-2
—
—
—
PDR
Port Control Register 1
0x002
16
R/W
0x0000
0xFFFF
PORT1-2
—
—
—
PCNTR2
Port Control Register 2
0x004
32
R
0x00000000
0xFFFF0000
PORT1-2
—
—
—
EIDR
Port Control Register 2
0x004
16
R
0x0000
0xFFFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 96 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (4 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
PORT1-2
—
—
—
PIDR
Port Control Register 2
0x006
16
R
0x0000
0x0000
PORT1-2
—
—
—
PCNTR3
Port Control Register 3
0x008
32
W
0x00000000
0xFFFFFFFF
PORT1-2
—
—
—
PORR
Port Control Register 3
0x008
16
W
0x0000
0xFFFF
PORT1-2
—
—
—
POSR
Port Control Register 3
0x00A
16
W
0x0000
0xFFFF
PORT1-2
—
—
—
PCNTR4
Port Control Register 4
0x00C
32
R/W
0x00000000
0xFFFFFFFF
PORT1-2
—
—
—
EORR
Port Control Register 4
0x00C
16
R/W
0x0000
0xFFFF
PORT1-2
—
—
—
EOSR
Port Control Register 4
0x00E
16
R/W
0x0000
0xFFFF
PFS
9
0x4
0-8
P00%sPFS
Port 00%s Pin Function Select Register
0x000
32
R/W
0x00000000
0xFFFFFFFD
PFS
9
0x4
0-8
P00%sPFS_HA
Port 00%s Pin Function Select Register
0x002
16
R/W
0x0000
0xFFFD
PFS
9
0x4
0-8
P00%sPFS_BY
Port 00%s Pin Function Select Register
0x003
8
R/W
0x00
0xFD
PFS
6
0x4
10-15
P0%sPFS
Port 0%s Pin Function Select Register
0x028
32
R/W
0x00000000
0xFFFFFFFD
PFS
6
0x4
10-15
P0%sPFS_HA
Port 0%s Pin Function Select Register
0x02A
16
R/W
0x0000
0xFFFD
PFS
6
0x4
10-15
P0%sPFS_BY
Port 0%s Pin Function Select Register
0x02B
8
R/W
0x00
0xFD
PFS
8
0x4
0-7
P10%sPFS
Port 10%s Pin Function Select Register
0x040
32
R/W
0x00000000
0xFFFFFFFD
PFS
8
0x4
0-7
P10%sPFS_HA
Port 10%s Pin Function Select Register
0x042
16
R/W
0x0000
0xFFFD
PFS
8
0x4
0-7
P10%sPFS_BY
Port 10%s Pin Function Select Register
0x043
8
R/W
0x00
0xFD
PFS
—
—
—
P108PFS
Port 108 Pin Function Select Register
0x060
32
R/W
0x00010010
0xFFFFFFFD
PFS
—
—
—
P108PFS_HA
Port 108 Pin Function Select Register
0x062
16
R/W
0x0010
0xFFFD
PFS
—
—
—
P108PFS_BY
Port 108 Pin Function Select Register
0x063
8
R/W
0x10
0xFD
PFS
—
—
—
P109PFS
Port 109 Pin Function Select Register
0x064
32
R/W
0x00000000
0xFFFFFFFD
PFS
—
—
—
P109PFS_HA
Port 109 Pin Function Select Register
0x066
16
R/W
0x0000
0xFFFD
PFS
—
—
—
P109PFS_BY
Port 109 Pin Function Select Register
0x067
8
R/W
0x00
0xFD
PFS
6
0x4
10-15
P1%sPFS
Port 1%s Pin Function Select Register
0x068
32
R/W
0x00000000
0xFFFFFFFD
PFS
6
0x4
10-15
P1%sPFS_HA
Port 1%s Pin Function Select Register
0x06A
16
R/W
0x0000
0xFFFD
PFS
6
0x4
10-15
P1%sPFS_BY
Port 1%s Pin Function Select Register
0x06B
8
R/W
0x00
0xFD
PFS
—
—
—
P200PFS
Port 200 Pin Function Select Register
0x080
32
R/W
0x00000000
0xFFFFFFFD
PFS
—
—
—
P200PFS_HA
Port 200 Pin Function Select Register
0x082
16
R/W
0x0000
0xFFFD
PFS
—
—
—
P200PFS_BY
Port 200 Pin Function Select Register
0x083
8
R/W
0x00
0xFD
PFS
—
—
—
P201PFS
Port 201 Pin Function Select Register
0x084
32
R/W
0x00000010
0xFFFFFFFD
PFS
—
—
—
P201PFS_HA
Port 201 Pin Function Select Register
0x086
16
R/W
0x0010
0xFFFD
PFS
—
—
—
P201PFS_BY
Port 201 Pin Function Select Register
0x087
8
R/W
0x10
0xFD
PFS
7
0x4
2-8
P20%sPFS
Port 20%s Pin Function Select Register
0x088
32
R/W
0x00000000
0xFFFFFFFD
PFS
7
0x4
2-8
P20%sPFS_HA
Port 20%s Pin Function Select Register
0x08A
16
R/W
0x0000
0xFFFD
PFS
7
0x4
2-8
P20%sPFS_BY
Port 20%s Pin Function Select Register
0x08B
8
R/W
0x00
0xFD
PFS
4
0x4
12-15
P2%sPFS
Port 2%s Pin Function Select Register
0x0B0
32
R/W
0x00000000
0xFFFFFFFD
PFS
4
0x4
12-15
P2%sPFS_HA
Port 2%s Pin Function Select Register
0x0B2
16
R/W
0x0000
0xFFFD
PFS
4
0x4
12-15
P2%sPFS_BY
Port 2%s Pin Function Select Register
0x0B3
8
R/W
0x00
0xFD
PFS
—
—
—
P300PFS
Port 300 Pin Function Select Register
0x0C0
32
R/W
0x00010000
0xFFFFFFFD
PFS
—
—
—
P300PFS_HA
Port 300 Pin Function Select Register
0x0C2
16
R/W
0x0000
0xFFFD
PFS
—
—
—
P300PFS_BY
Port 300 Pin Function Select Register
0x0C3
8
R/W
0x00
0xFD
PFS
7
0x4
1-7
P30%sPFS
Port 30%s Pin Function Select Register
0x0C4
32
R/W
0x00000000
0xFFFFFFFD
PFS
7
0x4
1-7
P30%sPFS_HA
Port 30%s Pin Function Select Register
0x0C6
16
R/W
0x0000
0xFFFD
PFS
7
0x4
1-7
P30%sPFS_BY
Port 30%s Pin Function Select Register
0x0C7
8
R/W
0x00
0xFD
PFS
10
0x4
0-9
P40%sPFS
Port 40%s Pin Function Select Register
0x100
32
R/W
0x00000000
0xFFFFFFFD
PFS
10
0x4
0-9
P40%sPFS_HA
Port 40%s Pin Function Select Register
0x102
16
R/W
0x0000
0xFFFD
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 97 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (5 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
PFS
10
0x4
0-9
P40%sPFS_BY
Port 40%s Pin Function Select Register
0x103
8
R/W
0x00
0xFD
PFS
6
0x4
10-15
P4%sPFS
Port 4%s Pin Function Select Register
0x128
32
R/W
0x00000000
0xFFFFFFFD
PFS
6
0x4
10-15
P4%sPFS_HA
Port 4%s Pin Function Select Register
0x12A
16
R/W
0x0000
0xFFFD
PFS
6
0x4
10-15
P4%sPFS_BY
Port 4%s Pin Function Select Register
0x12B
8
R/W
0x00
0xFD
PFS
6
0x4
0-5
P50%sPFS
Port 50%s Pin Function Select Register
0x140
32
R/W
0x00000000
0xFFFFFFFD
PFS
6
0x4
0-5
P50%sPFS_HA
Port 50%s Pin Function Select Register
0x142
16
R/W
0x0000
0xFFFD
PFS
6
0x4
0-5
P50%sPFS_BY
Port 50%s Pin Function Select Register
0x143
8
R/W
0x00
0xFD
PFS
4
0x4
0-3
P60%sPFS
Port 60%s Pin Function Select Register
0x180
32
R/W
0x00000000
0xFFFFFFFD
PFS
4
0x4
0-3
P60%sPFS_HA
Port 60%s Pin Function Select Register
0x182
16
R/W
0x0000
0xFFFD
PFS
4
0x4
0-3
P60%sPFS_BY
Port 60%s Pin Function Select Register
0x183
8
R/W
0x00
0xFD
PFS
2
0x4
8-9
P60%sPFS
Port 60%s Pin Function Select Register
0x1A0
32
R/W
0x00000000
0xFFFFFFFD
PFS
2
0x4
8-9
P60%sPFS_HA
Port 60%s Pin Function Select Register
0x1A2
16
R/W
0x0000
0xFFFD
PFS
2
0x4
8-9
P60%sPFS_BY
Port 60%s Pin Function Select Register
0x1A3
8
R/W
0x00
0xFD
PFS
—
—
—
P610PFS
Port 610 Pin Function Select Register
0x1A8
32
R/W
0x00000000
0xFFFFFFFD
PFS
—
—
—
P610PFS_HA
Port 610 Pin Function Select Register
0x1AA
16
R/W
0x0000
0xFFFD
PFS
—
—
—
P610PFS_BY
Port 610 Pin Function Select Register
0x1AB
8
R/W
0x00
0xFD
PFS
—
—
—
P708PFS
Port 708 Pin Function Select Register
0x1E0
32
R/W
0x00000000
0xFFFFFFFD
PFS
—
—
—
P708PFS_HA
Port 708 Pin Function Select Register
0x1E2
16
R/W
0x0000
0xFFFD
PFS
—
—
—
P708PFS_BY
Port 708 Pin Function Select Register
0x1E3
8
R/W
0x00
0xFD
PFS
—
—
—
P714PFS
Port 714 Pin Function Select Register
0x1F8
32
R/W
0x00000000
0xFFFFFFFD
PFS
—
—
—
P714PFS_HA
Port 714 Pin Function Select Register
0x1FA
16
R/W
0x0000
0xFFFD
PFS
—
—
—
P714PFS_BY
Port 714 Pin Function Select Register
0x1FB
8
R/W
0x00
0xFD
PFS
2
0x4
8-9
P80%sPFS
Port 80%s Pin Function Select Register
0x220
32
R/W
0x00000000
0xFFFFFFFD
PFS
2
0x4
8-9
P80%sPFS_HA
Port 80%s Pin Function Select Register
0x222
16
R/W
0x0000
0xFFFD
PFS
2
0x4
8-9
P80%sPFS_BY
Port 80%s Pin Function Select Register
0x223
8
R/W
0x00
0xFD
PFS
—
—
—
PWPR
Write-Protect Register
0x503
8
R/W
0x80
0xFF
PFS
—
—
—
PRWCNTR
Port Read Wait Control Register
0x50F
8
R/W
0x01
0xFF
ELC
—
—
—
ELCR
Event Link Controller Register
0x00
8
R/W
0x00
0xFF
ELC
2
0x02
0-1
ELSEGR%s
Event Link Software Event Generation
Register %s
0x02
8
R/W
0x80
0xFF
ELC
4
0x04
0-3
ELSR%s
Event Link Setting Register %s
0x10
16
R/W
0x0000
0xFFFF
ELC
2
0x04
8-9
ELSR%s
Event Link Setting Register %s
0x30
16
R/W
0x0000
0xFFFF
ELC
—
—
—
ELSR12
Event Link Setting Register 12
0x40
16
R/W
0x0000
0xFFFF
ELC
2
0x04
14-15
ELSR%s
Event Link Setting Register %s
0x48
16
R/W
0x0000
0xFFFF
ELC
—
—
—
ELSR18
Event Link Setting Register 18
0x58
16
R/W
0x0000
0xFFFF
POEG
—
—
—
POEGGA
POEG Group A Setting Register
0x000
32
R/W
0x00000000
0xFFFFFFFF
POEG
—
—
—
POEGGB
POEG Group B Setting Register
0x100
32
R/W
0x00000000
0xFFFFFFFF
RTC
—
—
—
R64CNT
64-Hz Counter
0x00
8
R
0x00
0x00
RTC
4
0x02
0-3
BCNT%s
Binary Counter %s
0x02
8
R/W
0x00
0x00
RTC
—
—
—
RSECCNT
Second Counter (in Calendar Count Mode)
0x02
8
R/W
0x00
0x00
RTC
—
—
—
RMINCNT
Minute Counter (in Calendar Count Mode)
0x04
8
R/W
0x00
0x00
RTC
—
—
—
RHRCNT
Hour Counter (in Calendar Count Mode)
0x06
8
R/W
0x00
0x00
RTC
—
—
—
RWKCNT
Day-of-Week Counter (in Calendar Count
Mode)
0x08
8
R/W
0x00
0x00
RTC
—
—
—
RDAYCNT
Day Counter
0x0A
8
R/W
0x00
0xC0
RTC
—
—
—
RMONCNT
Month Counter
0x0C
8
R/W
0x00
0xE0
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 98 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (6 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
RTC
—
—
—
RYRCNT
Year Counter
0x0E
16
R/W
0x0000
0xFF00
RTC
4
0x02
0-3
BCNT%sAR
Binary Counter %s Alarm Register
0x10
8
R/W
0x00
0x00
RTC
—
—
—
RSECAR
Second Alarm Register (in Calendar Count
Mode)
0x10
8
R/W
0x00
0x00
RTC
—
—
—
RMINAR
Minute Alarm Register (in Calendar Count
Mode)
0x12
8
R/W
0x00
0x00
RTC
—
—
—
RHRAR
Hour Alarm Register (in Calendar Count
Mode)
0x14
8
R/W
0x00
0x00
RTC
—
—
—
RWKAR
Day-of-Week Alarm Register (in Calendar
Count Mode)
0x16
8
R/W
0x00
0x00
RTC
2
0x02
0-1
BCNT%sAER
Binary Counter %s Alarm Enable Register
0x18
8
R/W
0x00
0x00
RTC
—
—
—
RDAYAR
Date Alarm Register (in Calendar Count
Mode)
0x18
8
R/W
0x00
0x00
RTC
—
—
—
RMONAR
Month Alarm Register (in Calendar Count
Mode)
0x1A
8
R/W
0x00
0x00
RTC
—
—
—
BCNT2AER
Binary Counter 2 Alarm Enable Register
0x1C
16
R/W
0x0000
0xFF00
RTC
—
—
—
RYRAR
Year Alarm Register (in Calendar Count
Mode)
0x1C
16
R/W
0x0000
0xFF00
RTC
—
—
—
BCNT3AER
Binary Counter 3 Alarm Enable Register
0x1E
8
R/W
0x00
0x00
RTC
—
—
—
RYRAREN
Year Alarm Enable Register (in Calendar
Count Mode)
0x1E
8
R/W
0x00
0x00
RTC
—
—
—
RCR1
RTC Control Register 1
0x22
8
R/W
0x00
0x0A
RTC
—
—
—
RCR2
RTC Control Register 2 (in Calendar Count 0x24
Mode)
8
R/W
0x00
0x0E
RTC
—
—
—
RCR2
RTC Control Register 2 (in Binary Count
Mode)
0x24
8
R/W
0x00
0x0E
RTC
—
—
—
RCR4
RTC Control Register 4
0x28
8
R/W
0x00
0x7E
RTC
—
—
—
RFRH
Frequency Register H
0x2A
16
R/W
0x0000
0xFFFE
RTC
—
—
—
RFRL
Frequency Register L
0x2C
16
R/W
0x0000
0x0000
RTC
—
—
—
RADJ
Time Error Adjustment Register
0x2E
8
R/W
0x00
0x00
WDT
—
—
—
WDTRR
WDT Refresh Register
0x00
8
R/W
0xFF
0xFF
WDT
—
—
—
WDTCR
WDT Control Register
0x02
16
R/W
0x0000
0xFFFF
WDT
—
—
—
WDTSR
WDT Status Register
0x04
16
R/W
0x0000
0xFFFF
WDT
—
—
—
WDTRCR
WDT Reset Control Register
0x06
8
R/W
0x80
0xFF
WDT
—
—
—
WDTCSTPR
WDT Count Stop Control Register
0x08
8
R/W
0x80
0xFF
IWDT
—
—
—
IWDTRR
IWDT Refresh Register
0x00
8
R/W
0xFF
0xFF
IWDT
—
—
—
IWDTSR
IWDT Status Register
0x04
16
R/W
0x0000
0xFFFF
CAC
—
—
—
CACR0
CAC Control Register 0
0x00
8
R/W
0x00
0xFF
CAC
—
—
—
CACR1
CAC Control Register 1
0x01
8
R/W
0x00
0xFF
CAC
—
—
—
CACR2
CAC Control Register 2
0x02
8
R/W
0x00
0xFF
CAC
—
—
—
CAICR
CAC Interrupt Control Register
0x03
8
R/W
0x00
0xFF
CAC
—
—
—
CASTR
CAC Status Register
0x04
8
R
0x00
0xFF
CAC
—
—
—
CAULVR
CAC Upper-Limit Value Setting Register
0x06
16
R/W
0x0000
0xFFFF
CAC
—
—
—
CALLVR
CAC Lower-Limit Value Setting Register
0x08
16
R/W
0x0000
0xFFFF
CAC
—
—
—
CACNTBR
CAC Counter Buffer Register
0x0A
16
R
0x0000
0xFFFF
MSTP
—
—
—
MSTPCRB
Module Stop Control Register B
0x000
32
R/W
0xFFFFFFFF
0xFFFFFFFF
MSTP
—
—
—
MSTPCRC
Module Stop Control Register C
0x004
32
R/W
0xFFFFFFFF
0xFFFFFFFF
MSTP
—
—
—
MSTPCRD
Module Stop Control Register D
0x008
32
R/W
0xFFFFFFFF
0xFFFFFFFF
MSTP
—
—
—
LSMRWDIS
Low Speed Module R/W Disable Control
Register
0x00C
16
R/W
0x0000
0xFFFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 99 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (7 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
CAN0
32
0x10
0-31
MB%s_ID
Mailbox ID Register %s
0x200
32
R/W
0x00000000
0x00000001
CAN0
32
0x10
0-31
MB%s_DL
Mailbox Data Length Register %s
0x204
16
R/W
0x0000
0x0000
CAN0
32
0x10
0-31
MB%s_D0
Mailbox Data Register %s
0x206
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D1
Mailbox Data Register %s
0x207
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D2
Mailbox Data Register %s
0x208
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D3
Mailbox Data Register %s
0x209
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D4
Mailbox Data Register %s
0x20A
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D5
Mailbox Data Register %s
0x20B
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D6
Mailbox Data Register %s
0x20C
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_D7
Mailbox Data Register %s
0x20D
8
R/W
0x00
0x00
CAN0
32
0x10
0-31
MB%s_TS
Mailbox Time Stamp Register %s
0x20E
16
R/W
0x0000
0x0000
CAN0
8
0x04
—
MKR[%s]
Mask Register %s
0x400
32
R/W
0x00000000
0x00000000
CAN0
2
0x04
0-1
FIDCR%s
FIFO Received ID Compare Register %s
0x420
32
R/W
0x00000000
0x00000000
CAN0
—
—
—
MKIVLR
Mask Invalid Register
0x428
32
R/W
0x00000000
0x00000000
CAN0
—
—
—
MIER
Mailbox Interrupt Enable Register
0x42C
32
R/W
0x00000000
0x00000000
CAN0
—
—
—
MIER_FIFO
Mailbox Interrupt Enable Register for FIFO
Mailbox Mode
0x42C
32
R/W
0x00000000
0x00000000
CAN0
32
0x01
—
MCTL_RX[%s]
Message Control Register for Receive
0x820
8
R/W
0x00
0xFF
CAN0
32
0x01
—
MCTL_TX[%s]
Message Control Register for Transmit
0x820
8
R/W
0x00
0xFF
CAN0
—
—
—
CTLR
Control Register
0x840
16
R/W
0x0500
0xFFFF
CAN0
—
—
—
STR
Status Register
0x842
16
R
0x0500
0xFFFF
CAN0
—
—
—
BCR
Bit Configuration Register
0x844
32
R/W
0x00000000
0xFFFFFFFF
CAN0
—
—
—
RFCR
Receive FIFO Control Register
0x848
8
R/W
0x80
0xFF
CAN0
—
—
—
RFPCR
Receive FIFO Pointer Control Register
0x849
8
W
0x00
0x00
CAN0
—
—
—
TFCR
Transmit FIFO Control Register
0x84A
8
R/W
0x80
0xFF
CAN0
—
—
—
TFPCR
Transmit FIFO Pointer Control Register
0x84B
8
W
0x00
0x00
CAN0
—
—
—
EIER
Error Interrupt Enable Register
0x84C
8
R/W
0x00
0xFF
CAN0
—
—
—
EIFR
Error Interrupt Factor Judge Register
0x84D
8
R/W
0x00
0xFF
CAN0
—
—
—
RECR
Receive Error Count Register
0x84E
8
R
0x00
0xFF
CAN0
—
—
—
TECR
Transmit Error Count Register
0x84F
8
R
0x00
0xFF
CAN0
—
—
—
ECSR
Error Code Store Register
0x850
8
R/W
0x00
0xFF
CAN0
—
—
—
CSSR
Channel Search Support Register
0x851
8
R/W
0x00
0x00
CAN0
—
—
—
MSSR
Mailbox Search Status Register
0x852
8
R
0x80
0xFF
CAN0
—
—
—
MSMR
Mailbox Search Mode Register
0x853
8
R/W
0x00
0xFF
CAN0
—
—
—
TSR
Time Stamp Register
0x854
16
R
0x0000
0xFFFF
CAN0
—
—
—
AFSR
Acceptance Filter Support Register
0x856
16
R/W
0x0000
0x0000
CAN0
—
—
—
TCR
Test Control Register
0x858
8
R/W
0x00
0xFF
IIC0-1
—
—
—
ICCR1
I2C Bus Control Register 1
0x00
8
R/W
0x1F
0xFF
IIC0-1
—
—
—
ICCR2
I2C Bus Control Register 2
0x01
8
R/W
0x00
0xFF
IIC0-1
—
—
—
ICMR1
I2C Bus Mode Register 1
0x02
8
R/W
0x08
0xFF
IIC0-1
—
—
—
ICMR2
I2C Bus Mode Register 2
0x03
8
R/W
0x06
0xFF
IIC0-1
—
—
—
ICMR3
I2C Bus Mode Register 3
0x04
8
R/W
0x00
0xFF
IIC0-1
—
—
—
ICFER
I2C Bus Function Enable Register
0x05
8
R/W
0x72
0xFF
IIC0-1
—
—
—
ICSER
I2C Bus Status Enable Register
0x06
8
R/W
0x09
0xFF
IIC0-1
—
—
—
ICIER
I2C Bus Interrupt Enable Register
0x07
8
R/W
0x00
0xFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 100 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (8 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
IIC0-1
—
—
—
ICSR1
I2C Bus Status Register 1
0x08
8
R/W
0x00
0xFF
IIC0-1
—
—
—
ICSR2
I2C Bus Status Register 2
0x09
8
R/W
0x00
0xFF
IIC0-1
3
0x02
0-2
SARL%s
Slave Address Register Ly
0x0A
8
R/W
0x00
0xFF
IIC0-1
3
0x02
0-2
SARU%s
Slave Address Register Uy
0x0B
8
R/W
0x00
0xFF
IIC0-1
—
—
—
ICBRL
I2C Bus Bit Rate Low-Level Register
0x10
8
R/W
0xFF
0xFF
IIC0-1
—
—
—
ICBRH
I2C Bus Bit Rate High-Level Register
0x11
8
R/W
0xFF
0xFF
IIC0-1
—
—
—
ICDRT
I2C Bus Transmit Data Register
0x12
8
R/W
0xFF
0xFF
IIC0-1
—
—
—
ICDRR
I2C Bus Receive Data Register
0x13
8
R
0x00
0xFF
IIC0WU
—
—
—
ICWUR
I2C Bus Wakeup Unit Register
0x02
8
R/W
0x10
0xFF
IIC0WU
—
—
—
ICWUR2
I2C Bus Wakeup Unit Register 2
0x03
8
R/W
0xFD
0xFF
DOC
—
—
—
DOCR
DOC Control Register
0x00
8
R/W
0x00
0xFF
DOC
—
—
—
DODIR
DOC Data Input Register
0x02
16
R/W
0x0000
0xFFFF
DOC
—
—
—
DODSR
DOC Data Setting Register
0x04
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCSR
A/D Control Register
0x000
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADANSA0
A/D Channel Select Register A0
0x004
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADANSA1
A/D Channel Select Register A1
0x006
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADADS0
A/D-Converted Value Addition/Average
Channel Select Register 0
0x008
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADADS1
A/D-Converted Value Addition/Average
Channel Select Register 1
0x00A
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADADC
A/D-Converted Value Addition/Average
Count Select Register
0x00C
8
R/W
0x00
0xFF
ADC12
—
—
—
ADCER
A/D Control Extended Register
0x00E
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADSTRGR
A/D Conversion Start Trigger Select
Register
0x010
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADEXICR
A/D Conversion Extended Input Control
Registers
0x012
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADANSB0
A/D Channel Select Register B0
0x014
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADANSB1
A/D Channel Select Register B1
0x016
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADDBLDR
A/D Data Duplexing Register
0x018
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADTSDR
A/D Temperature Sensor Data Register
0x01A
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADOCDR
A/D Internal Reference Voltage Data
Register
0x01C
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADRD
A/D Self-Diagnosis Data Register
0x01E
16
R
0x0000
0xFFFF
ADC12
15
0x2
0-14
ADDR%s
A/D Data Registers %s
0x020
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADCTDR
A/D CTSU TSCAP Voltage Data Register
0x040
16
R
0x0000
0xFFFF
ADC12
4
0x2
17-20
ADDR%s
A/D Data Registers %s
0x042
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADDISCR
A/D Disconnection Detection Control
Register
0x07A
8
R/W
0x00
0xFF
ADC12
—
—
—
ADACSR
A/D Conversion Operation Mode Select
Register
0x07E
8
R/W
0x00
0xFF
ADC12
—
—
—
ADGSPCR
A/D Group Scan Priority Control Register
0x080
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADDBLDRA
A/D Data Duplexing Register A
0x084
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADDBLDRB
A/D Data Duplexing Register B
0x086
16
R
0x0000
0xFFFF
ADC12
—
—
—
ADHVREFCNT
A/D High-Potential/Low-Potential
Reference Voltage Control Register
0x08A
8
R/W
0x00
0xFF
ADC12
—
—
—
ADWINMON
A/D Compare Function Window A/B Status
Monitor Register
0x08C
8
R
0x00
0xFF
ADC12
—
—
—
ADCMPCR
A/D Compare Function Control Register
0x090
16
R/W
0x0000
0xFFFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 101 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (9 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Address
offset
Size R/W
Reset value
Reset mask
ADC12
—
—
—
ADCMPANSER
A/D Compare Function Window A
Extended Input Select Register
0x092
8
R/W
0x00
0xFF
ADC12
—
—
—
ADCMPLER
A/D Compare Function Window A
Extended Input Comparison Condition
Setting Register
0x093
8
R/W
0x00
0xFF
ADC12
—
—
—
ADCMPANSR0
A/D Compare Function Window A Channel
Select Register 0
0x094
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPANSR1
A/D Compare Function Window A Channel
Select Register 1
0x096
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPLR0
A/D Compare Function Window A
Comparison Condition Setting Register 0
0x098
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPLR1
A/D Compare Function Window A
Comparison Condition Setting Register 1
0x09A
16
R/W
0x0000
0xFFFF
ADC12
2
0x2
0-1
ADCMPDR%s
A/D Compare Function Window A LowerSide/Upper-Side Level Setting Register
0x09C
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPSR0
A/D Compare Function Window A Channel
Status Register 0
0x0A0
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPSR1
A/D Compare Function Window A Channel
Status Register1
0x0A2
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPSER
A/D Compare Function Window A
Extended Input Channel Status Register
0x0A4
8
R/W
0x00
0xFF
ADC12
—
—
—
ADCMPBNSR
A/D Compare Function Window B Channel
Select Register
0x0A6
8
R/W
0x00
0xFF
ADC12
—
—
—
ADWINLLB
A/D Compare Function Window B LowerSide/Upper-Side Level Setting Register
0x0A8
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADWINULB
A/D Compare Function Window B LowerSide/Upper-Side Level Setting Register
0x0AA
16
R/W
0x0000
0xFFFF
ADC12
—
—
—
ADCMPBSR
A/D Compare Function Window B Status
Register
0x0AC
8
R/W
0x00
0xFF
ADC12
—
—
—
ADSSTRL
A/D Sampling State Register
0x0DD
8
R/W
0x0D
0xFF
ADC12
—
—
—
ADSSTRT
A/D Sampling State Register
0x0DE
8
R/W
0x0D
0xFF
ADC12
—
—
—
ADSSTRO
A/D Sampling State Register
0x0DF
8
R/W
0x0D
0xFF
ADC12
15
0x1
0-14
ADSSTR%s
A/D Sampling State Register
0x0E0
8
R/W
0x0D
0xFF
DAC12
—
—
—
DADR0
D/A Data Register 0
0x00
16
R/W
0x0000
0xFFFF
DAC12
—
—
—
DACR
D/A Control Register
0x04
8
R/W
0x1F
0xFF
DAC12
—
—
—
DADPR
DADR0 Format Select Register
0x05
8
R/W
0x00
0xFF
DAC12
—
—
—
DAADSCR
D/A A/D Synchronous Start Control
Register
0x06
8
R/W
0x00
0xFF
DAC12
—
—
—
DAVREFCR
D/A VREF Control Register
0x07
8
R/W
0x00
0xFF
SCI0
—
—
—
SMR
Serial Mode Register for Non-Smart Card
Interface Mode (SCMR.SMIF = 0)
0x00
8
R/W
0x00
0xFF
SCI0
—
—
—
SMR_SMCI
Serial Mode Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x00
8
R/W
0x00
0xFF
SCI0
—
—
—
BRR
Bit Rate Register
0x01
8
R/W
0xFF
0xFF
SCI0
—
—
—
SCR
Serial Control Register for Non-Smart Card 0x02
Interface Mode (SCMR.SMIF = 0)
8
R/W
0x00
0xFF
SCI0
—
—
—
SCR_SMCI
Serial Control Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x02
8
R/W
0x00
0xFF
SCI0
—
—
—
TDR
Transmit Data Register
0x03
8
R/W
0xFF
0xFF
SCI0
—
—
—
SSR
Serial Status Register for Non-Smart Card
Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
0x04
8
R/W
0x84
0xFF
SCI0
—
—
—
SSR_FIFO
Serial Status Register for Non-Smart Card 0x04
Interface and FIFO Mode (SCMR.SMIF = 0
and FCR.FM = 1)
8
R/W
0x80
0xFD
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Description
Page 102 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (10 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Address
offset
Size R/W
Reset value
Reset mask
SCI0
—
—
—
SSR_SMCI
Serial Status Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x04
8
R/W
0x84
0xFF
SCI0
—
—
—
RDR
Receive Data Register
0x05
8
R/W
0x00
0xFF
SCI0
—
—
SCI0
—
—
—
SCMR
Smart Card Mode Register
0x06
8
R/W
0xF2
0xFF
—
SEMR
Serial Extended Mode Register
0x07
8
R/W
0x00
0xFF
SCI0
—
—
—
SNFR
Noise Filter Setting Register
0x08
8
R/W
0x00
0xFF
SCI0
SCI0
—
—
—
SIMR1
IIC Mode Register 1
0x09
8
R/W
0x00
0xFF
—
—
—
SIMR2
IIC Mode Register 2
0x0A
8
R/W
0x00
0xFF
SCI0
—
—
—
SIMR3
IIC Mode Register 3
0x0B
8
R/W
0x00
0xFF
SCI0
—
—
—
SISR
IIC Status Register
0x0C
8
R
0x00
0xCB
SCI0
—
—
—
SPMR
SPI Mode Register
0x0D
8
R/W
0x00
0xFF
SCI0
—
—
—
TDRHL
Transmit Data Register
0x0E
16
R/W
0xFFFF
0xFFFF
SCI0
—
—
—
FRDRHL
Receive FIFO Data Register
0x10
16
R
0x0000
0xFFFF
SCI0
—
—
—
FTDRHL
Transmit FIFO Data Register
0x0E
16
W
0xFFFF
0xFFFF
SCI0
—
—
—
RDRHL
Receive Data Register
0x10
16
R
0x0000
0xFFFF
SCI0
—
—
—
FRDRH
Receive FIFO Data Register
0x10
8
R
0x00
0xFF
SCI0
—
—
—
FTDRH
Transmit FIFO Data Register
0x0E
8
W
0xFF
0xFF
SCI0
—
—
—
FRDRL
Receive FIFO Data Register
0x11
8
R
0x00
0xFF
SCI0
—
—
—
FTDRL
Transmit FIFO Data Register
0x0F
8
W
0xFF
0xFF
SCI0
—
—
—
MDDR
Modulation Duty Register
0x12
8
R/W
0xFF
0xFF
SCI0
—
—
—
DCCR
Data Compare Match Control Register
0x13
8
R/W
0x40
0xFF
SCI0
—
—
—
FCR
FIFO Control Register
0x14
16
R/W
0xF800
0xFFFF
SCI0
—
—
—
FDR
FIFO Data Count Register
0x16
16
R
0x0000
0xFFFF
SCI0
—
—
—
LSR
Line Status Register
0x18
16
R
0x0000
0xFFFF
SCI0
—
—
—
CDR
Compare Match Data Register
0x1A
16
R/W
0x0000
0xFFFF
SCI0
—
—
—
SPTR
Serial Port Register
0x1C
8
R/W
0x03
0xFF
SCI1-3,9
—
—
—
SMR
Serial Mode Register for Non-Smart Card
Interface Mode (SCMR.SMIF = 0)
0x00
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SMR_SMCI
Serial Mode Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x00
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
BRR
Bit Rate Register
0x01
8
R/W
0xFF
0xFF
SCI1-3,9
—
—
—
SCR
Serial Control Register for Non-Smart Card 0x02
Interface Mode (SCMR.SMIF = 0)
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SCR_SMCI
Serial Control Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x02
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
TDR
Transmit Data Register
0x03
8
R/W
0xFF
0xFF
SCI1-3,9
—
—
—
SSR
Serial Status Register for Non-Smart Card
Interface and Non-FIFO Mode
(SCMR.SMIF = 0 and FCR.FM = 0)
0x04
8
R/W
0x84
0xFF
SCI1-3,9
—
—
—
SSR_SMCI
Serial Status Register for Smart Card
Interface Mode (SCMR.SMIF = 1)
0x04
8
R/W
0x84
0xFF
SCI1-3,9
—
—
—
RDR
Receive Data Register
0x05
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SCMR
Smart Card Mode Register
0x06
8
R/W
0xF2
0xFF
SCI1-3,9
—
—
—
SEMR
Serial Extended Mode Register
0x07
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SNFR
Noise Filter Setting Register
0x08
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SIMR1
IIC Mode Register 1
0x09
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SIMR2
IIC Mode Register 2
0x0A
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
SIMR3
IIC Mode Register 3
0x0B
8
R/W
0x00
0xFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Description
Page 103 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (11 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
SCI1-3,9
—
—
—
SISR
IIC Status Register
0x0C
8
R
0x00
0xCB
SCI1-3,9
—
—
—
SPMR
SPI Mode Register
0x0D
8
R/W
0x00
0xFF
SCI1-3,9
—
—
—
TDRHL
Transmit Data Register
0x0E
16
R/W
0xFFFF
0xFFFF
SCI1-3,9
—
—
—
RDRHL
Receive Data Register
0x10
16
R
0x0000
0xFFFF
SCI1-3,9
—
—
—
MDDR
Modulation Duty Register
0x12
8
R/W
0xFF
0xFF
SCI1-3,9
—
—
—
DCCR
Data Compare Match Control Register
0x13
8
R/W
0x40
0xFF
SCI1-3,9
—
—
—
CDR
Compare Match Data Register
0x1A
16
R/W
0x0000
0xFFFF
SCI1-3,9
—
—
—
SPTR
Serial Port Register
0x1C
8
R/W
0x03
0xFF
SPI0-1
—
—
—
SPCR
SPI Control Register
0x00
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SSLP
SPI Slave Select Polarity Register
0x01
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SPPCR
SPI Pin Control Register
0x02
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SPSR
SPI Status Register
0x03
8
R/W
0x20
0xFF
SPI0-1
—
—
—
SPDR
SPI Data Register
0x04
32
R/W
0x00000000
0xFFFFFFFF
SPI0-1
—
—
—
SPDR_HA
SPI Data Register
0x04
16
R/W
0x0000
0xFFFF
SPI0-1
—
—
—
SPBR
SPI Bit Rate Register
0x0A
8
R/W
0xFF
0xFF
SPI0-1
—
—
—
SPDCR
SPI Data Control Register
0x0B
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SPCKD
SPI Clock Delay Register
0x0C
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SSLND
SPI Slave Select Negation Delay Register
0x0D
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SPND
SPI Next-Access Delay Register
0x0E
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SPCR2
SPI Control Register 2
0x0F
8
R/W
0x00
0xFF
SPI0-1
—
—
—
SPCMD0
SPI Command Register 0
0x10
16
R/W
0x070D
0xFFFF
CRC
—
—
—
CRCCR0
CRC Control Register 0
0x00
8
R/W
0x00
0xFF
CRC
—
—
—
CRCCR1
CRC Control Register 1
0x01
8
R/W
0x00
0xFF
CRC
—
—
—
CRCDIR
CRC Data Input Register
0x04
32
R/W
0x00000000
0xFFFFFFFF
CRC
—
—
—
CRCDIR_BY
CRC Data Input Register
0x04
8
R/W
0x00
0xFF
CRC
—
—
—
CRCDOR
CRC Data Output Register
0x08
32
R/W
0x00000000
0xFFFFFFFF
CRC
—
—
—
CRCDOR_HA
CRC Data Output Register
0x08
16
R/W
0x0000
0xFFFF
CRC
—
—
—
CRCDOR_BY
CRC Data Output Register
0x08
8
R/W
0x00
0xFF
CRC
—
—
—
CRCSAR
Snoop Address Register
0x0C
16
R/W
0x0000
0xFFFF
GPT320-3
—
—
—
GTWP
General PWM Timer Write-Protection
Register
0x00
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTSTR
General PWM Timer Software Start
Register
0x04
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTSTP
General PWM Timer Software Stop
Register
0x08
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTCLR
General PWM Timer Software Clear
Register
0x0C
32
W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTSSR
General PWM Timer Start Source Select
Register
0x10
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTPSR
General PWM Timer Stop Source Select
Register
0x14
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTCSR
General PWM Timer Clear Source Select
Register
0x18
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTUPSR
General PWM Timer Up Count Source
Select Register
0x1C
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTDNSR
General PWM Timer Down Count Source
Select Register
0x20
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTICASR
General PWM Timer Input Capture Source
Select Register A
0x24
32
R/W
0x00000000
0xFFFFFFFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 104 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (12 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Address
offset
Size R/W
Reset value
Reset mask
GPT320-3
—
—
—
GTICBSR
General PWM Timer Input Capture Source
Select Register B
0x28
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTCR
General PWM Timer Control Register
0x2C
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTUDDTYC
General PWM Timer Count Direction and
Duty Setting Register
0x30
32
R/W
0x00000001
0xFFFFFFFF
GPT320-3
—
GPT320-3
—
—
—
GTIOR
General PWM Timer I/O Control Register
0x34
32
R/W
0x00000000
0xFFFFFFFF
—
—
GTINTAD
General PWM Timer Interrupt Output
Setting Register
0x38
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
GPT320-3
—
—
—
GTST
General PWM Timer Status Register
0x3C
32
R/W
0x00008000
0xFFFFFFFF
—
—
—
GTBER
General PWM Timer Buffer Enable
Register
0x40
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTCNT
General PWM Timer Counter
0x48
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTCCRA
General PWM Timer Compare Capture
Register A
0x4C
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTCCRB
General PWM Timer Compare Capture
Register B
0x50
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTCCRC
General PWM Timer Compare Capture
Register C
0x54
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTCCRE
General PWM Timer Compare Capture
Register E
0x58
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTCCRD
General PWM Timer Compare Capture
Register D
0x5C
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTCCRF
General PWM Timer Compare Capture
Register F
0x60
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTPR
General PWM Timer Cycle Setting
Register
0x64
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTPBR
General PWM Timer Cycle Setting Buffer
Register
0x68
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT320-3
—
—
—
GTDTCR
General PWM Timer Dead Time Control
Register
0x88
32
R/W
0x00000000
0xFFFFFFFF
GPT320-3
—
—
—
GTDVU
General PWM Timer Dead Time Value
Register U
0x8C
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTWP
General PWM Timer Write-Protection
Register
0x00
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTSTR
General PWM Timer Software Start
Register
0x04
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTSTP
General PWM Timer Software Stop
Register
0x08
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTCLR
General PWM Timer Software Clear
Register
0x0C
32
W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTSSR
General PWM Timer Start Source Select
Register
0x10
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTPSR
General PWM Timer Stop Source Select
Register
0x14
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTCSR
General PWM Timer Clear Source Select
Register
0x18
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTUPSR
General PWM Timer Up Count Source
Select Register
0x1C
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTDNSR
General PWM Timer Down Count Source
Select Register
0x20
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTICASR
General PWM Timer Input Capture Source
Select Register A
0x24
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTICBSR
General PWM Timer Input Capture Source
Select Register B
0x28
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTCR
General PWM Timer Control Register
0x2C
32
R/W
0x00000000
0xFFFFFFFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Description
Page 105 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (13 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Address
offset
Size R/W
Reset value
Reset mask
GPT164-9
—
—
—
GTUDDTYC
General PWM Timer Count Direction and
Duty Setting Register
0x30
32
R/W
0x00000001
0xFFFFFFFF
GPT164-9
—
—
—
GTIOR
General PWM Timer I/O Control Register
0x34
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTINTAD
General PWM Timer Interrupt Output
Setting Register
0x38
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
GPT164-9
—
—
—
GTST
General PWM Timer Status Register
0x3C
32
R/W
0x00008000
0xFFFFFFFF
—
—
GTBER
General PWM Timer Buffer Enable
Register
0x40
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
GPT164-9
—
—
—
GTCNT
General PWM Timer Counter
0x48
32
R/W
0x00000000
0xFFFFFFFF
—
—
—
GTCCRA
General PWM Timer Compare Capture
Register A
0x4C
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTCCRB
General PWM Timer Compare Capture
Register B
0x50
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTCCRC
General PWM Timer Compare Capture
Register C
0x54
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTCCRE
General PWM Timer Compare Capture
Register E
0x58
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTCCRD
General PWM Timer Compare Capture
Register D
0x5C
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTCCRF
General PWM Timer Compare Capture
Register F
0x60
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTPR
General PWM Timer Cycle Setting
Register
0x64
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTPBR
General PWM Timer Cycle Setting Buffer
Register
0x68
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT164-9
—
—
—
GTDTCR
General PWM Timer Dead Time Control
Register
0x88
32
R/W
0x00000000
0xFFFFFFFF
GPT164-9
—
—
—
GTDVU
General PWM Timer Dead Time Value
Register U
0x8C
32
R/W
0xFFFFFFFF
0xFFFFFFFF
GPT_OPS
—
—
—
OPSCR
Output Phase Switching Control Register
0x00
32
R/W
0x00000000
0xFFFFFFFF
KINT
—
—
—
KRCTL
Key Return Control Register
0x00
8
R/W
0x00
0xFF
KINT
—
—
—
KRF
Key Return Flag Register
0x04
8
R/W
0x00
0xFF
KINT
—
—
—
KRM
Key Return Mode Register
0x08
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCRA
CTSU Control Register A
0x00
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUCRAL
CTSU Control Register A
0x00
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCR0
CTSU Control Register A
0x00
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCR1
CTSU Control Register A
0x01
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCR2
CTSU Control Register A
0x02
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCR3
CTSU Control Register A
0x03
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCRB
CTSU Control Register B
0x04
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUCRBL
CTSU Control Register B
0x04
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSDPRS
CTSU Control Register B
0x04
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUSST
CTSU Control Register B
0x05
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCRBH
CTSU Control Register B
0x06
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUDCLKC
CTSU Control Register B
0x07
8
R/W
0x00
0xFF
Description
CTSU
—
—
—
CTSUMCH
CTSU Measurement Channel Register
0x08
32
R/W
0x00003F3F
0xFFFFFFFF
CTSU
—
—
—
CTSUMCHL
CTSU Measurement Channel Register
0x08
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUMCH0
CTSU Measurement Channel Register
0x08
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUMCH1
CTSU Measurement Channel Register
0x09
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUMCHH
CTSU Measurement Channel Register
0x0A
16
R/W
0x3F3F
0xFFFF
CTSU
—
—
—
CTSUMFAF
CTSU Measurement Channel Register
0x0A
8
R/W
0x3F
0xFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 106 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (14 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Description
Address
offset
Size R/W
Reset value
Reset mask
CTSU
—
—
—
CTSUCHACA
CTSU Channel Enable Control Register A
0x0C
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUCHACAL
CTSU Channel Enable Control Register A
0x0C
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCHAC0
CTSU Channel Enable Control Register A
0x0C
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHAC1
CTSU Channel Enable Control Register A
0x0D
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHACAH
CTSU Channel Enable Control Register A
0x0E
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCHAC2
CTSU Channel Enable Control Register A
0x0E
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHAC3
CTSU Channel Enable Control Register A
0x0F
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHACB
CTSU Channel Enable Control Register B
0x10
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUCHACBL
CTSU Channel Enable Control Register B
0x10
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCHAC4
CTSU Channel Enable Control Register B
0x10
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHTRCA
CTSU Channel Transmit/Receive Control
Register A
0x14
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUCHTRCAL
CTSU Channel Transmit/Receive Control
Register A
0x14
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCHTRC0
CTSU Channel Transmit/Receive Control
Register A
0x14
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHTRC1
CTSU Channel Transmit/Receive Control
Register A
0x15
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHTRCAH
CTSU Channel Transmit/Receive Control
Register A
0x16
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCHTRC2
CTSU Channel Transmit/Receive Control
Register A
0x16
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHTRC3
CTSU Channel Transmit/Receive Control
Register A
0x17
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUCHTRCB
CTSU Channel Transmit/Receive Control
Register B
0x18
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUCHTRCBL
CTSU Channel Transmit/Receive Control
Register B
0x18
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUCHTRC4
CTSU Channel Transmit/Receive Control
Register B
0x18
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUSR
CTSU Status Register
0x1C
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUSRL
CTSU Status Register
0x1C
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSR0
CTSU Status Register
0x1C
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUST
CTSU Status Register
0x1D
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUSRH
CTSU Status Register
0x1E
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSR2
CTSU Status Register
0x1E
8
R/W
0x00
0xFF
CTSU
—
—
—
CTSUSO
CTSU Sensor Offset Register
0x20
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUSO0
CTSU Sensor Offset Register
0x20
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSO1
CTSU Sensor Offset Register
0x22
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSCNT
CTSU Sensor Counter Register
0x24
32
R
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUSC
CTSU Sensor Counter Register
0x24
16
R
0x0000
0xFFFF
CTSU
—
—
—
CTSUCALIB
CTSU Calibration Register
0x28
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUDBGR0
CTSU Calibration Register
0x28
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUDBGR1
CTSU Calibration Register
0x2A
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSUCLKA
CTSU Sensor Unit Clock Control Register
A
0x2C
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUSUCLK0
CTSU Sensor Unit Clock Control Register
A
0x2C
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSUCLK1
CTSU Sensor Unit Clock Control Register
A
0x2E
16
R/W
0x0000
0xFFFF
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 107 of 111
RA2L1 Datasheet
Table 3.4
Appendix 3. I/O Registers
Register description (15 of 15)
Peripheral
name
Dim
Dim
inc.
Dim
index
Register
name
Address
offset
Size R/W
Reset value
Reset mask
CTSU
—
—
—
CTSUSUCLKB
CTSU Sensor Unit Clock Control Register
B
0x30
32
R/W
0x00000000
0xFFFFFFFF
CTSU
—
—
—
CTSUSUCLK2
CTSU Sensor Unit Clock Control Register
B
0x30
16
R/W
0x0000
0xFFFF
CTSU
—
—
—
CTSUSUCLK3
CTSU Sensor Unit Clock Control Register
B
0x32
16
R/W
0x0000
0xFFFF
CTSU
—
CTSU
—
—
—
CTSUCFCCNT
CTSU CFC Counter Register
0x34
32
R
0x00000000
0xFFFFFFFF
—
—
CTSUCFCCNTL
CTSU CFC Counter Register
0x34
16
R
0x0000
0xFFFF
AGT0-1
AGT0-1
—
—
—
AGT
AGT Counter Register
0x00
16
R/W
0xFFFF
0xFFFF
—
—
—
AGTCMB
AGT Compare Match B Register
0x00
16
R/W
0xFFFF
0xFFFF
AGT0-1
—
—
—
AGTCMA
AGT Compare Match A Register
0x02
16
R/W
0xFFFF
0xFFFF
AGT0-1
—
—
—
AGTCR
AGT Control Register
0x08
8
R/W
0x00
0xFF
AGT0-1
—
—
—
AGTMR1
AGT Mode Register 1
0x09
8
R/W
0x00
0xFF
AGT0-1
—
—
—
AGTMR2
AGT Mode Register 2
0x0A
8
R/W
0x00
0xFF
AGT0-1
—
—
—
AGTIOC
AGT I/O Control Register
0x0C
8
R/W
0x00
0xFF
AGT0-1
—
—
—
AGTISR
AGT Event Pin Select Register
0x0D
8
R/W
0x00
0xFF
AGT0-1
—
—
—
AGTCMSR
AGT Compare Match Function Select
Register
0x0E
8
R/W
0x00
0xFF
AGT0-1
—
—
—
AGTIOSEL
AGT Pin Select Register
0x00F
8
R/W
0x00
0xFF
ACMPLP
—
—
—
COMPMDR
ACMPLP Mode Setting Register
0x00
8
R/W
0x00
0xFF
ACMPLP
—
—
—
COMPFIR
ACMPLP Filter Control Register
0x01
8
R/W
0x00
0xFF
ACMPLP
—
—
—
COMPOCR
ACMPLP Output Control Register
0x02
8
R/W
0x00
0xFF
FLCN
—
—
—
DFLCTL
Data Flash Enable Register
0x0090
8
R/W
0x00
0xFF
FLCN
—
—
—
TSCDR
Temperature Sensor Calibration Data
Register
0x0228
16
R
0x00
0x00
FLCN
—
—
—
CTSUTRIMA
CTSU Trimming Register A
0x03A4
32
R/W
0x00000000
0x00000000
FLCN
—
—
—
FLDWAITR
Memory Wait Cycle Control Register for
Data Flash
0x3FC4
8
R/W
0x00
0xFF
FLCN
—
—
—
PFBER
Prefetch Buffer Enable Register
0x3FC8
8
R/W
0x00
0xFF
Note:
Description
Peripheral name = Name of peripheral
Dim = Number of elements in an array of registers
Dim inc. = Address increment between two simultaneous registers of a register array in the address map
Dim index = Sub string that replaces the %s placeholder within the register name
Register name = Name of register
Description = Register description
Address offset = Address of the register relative to the base address defined by the peripheral of the register
Size = Bit width of the register
Reset value = Default reset value of a register
Reset mask = Identifies which register bits have a defined reset value
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 108 of 111
RA2L1 Datasheet
Revision History
Revision History
Revision 1.00 — Aug 06, 2020
First edition, issued
Revision 1.10 — Feb 26, 2021
Features:
● Changed from LFQFP to LQFP.
Overview:
● Changed LFQFP to LQFP in the Figure 1.2 Part numbering scheme.
● Added PWQN0048KC-A on the Table 1.12 Product list.
● Changed from MISO0_A to MISO9_A for P202 on Table 1.15 Pin list.
Electrical Characteristics:
● Added Note 5 on the table Table 2.19 Clock timing.
Appendix 2. Package Dimensions:
● Added Figure 2.5 HWQFN 48-pin.
R01DS0385EJ0110 Rev.1.10
Feb 26, 2021
Page 109 of 111
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products
and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your
product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use
of these circuits, software, or information.
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No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics
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(Note1)
(Note2)
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subsidiaries.
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
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