Datasheet
R01DS0368EJ0120
Rev.1.20
Dec 2, 2020
RA4M3 Group
Renesas Microcontrollers
Leading-performance 100 MHz Arm Cortex-M33 core, up to 1 MB code flash memory with background and SWAP operation,
8 KB Data flash memory, and 128 KB SRAM with Parity/ECC. High-integration with USB 2.0 Full-Speed, SDHI, Quad SPI,
and advanced analog. Integrated Secure Crypto Engine with cryptography accelerators, key management support, tamper
detection and power analysis resistance in concert with Arm TrustZone for integrated secure element functionality.
Features
■ Arm® Cortex®-M33 Core
● Armv8-M architecture with the main extension
● Maximum operating frequency: 100 MHz
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by LOCO or system clock
● CoreSight™ ETM-M33
■ Memory
● Up to 1-MB code flash memory
● 8-KB data flash memory (100,000 program/erase (P/E) cycles)
● 128-KB SRAM
■ Connectivity
● Serial Communications Interface (SCI) × 6
– Asynchronous interfaces
– 8-bit clock synchronous interface
– Smart card interface
– Simple IIC
– Simple SPI
– Manchester coding (SCI3, SCI4)
● I2C bus interface (IIC) × 2
● Serial Peripheral Interface (SPI)
● Quad Serial Peripheral Interface (QSPI)
● USB 2.0 Full-Speed Module (USBFS)
● Control Area Network module (CAN) × 2
● SD/MMC Host Interface (SDHI)
● Serial Sound Interface Enhanced (SSIE)
● Independent Watchdog Timer (IWDT)
■ Human Machine Interface (HMI)
● Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
●
●
●
●
●
●
●
●
●
Main clock oscillator (MOSC) (8 to 24 MHz)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
PLL/PLL2
Clock out support
■ General-Purpose I/O Ports
● 5-V tolerance, open drain, input pull-up, switchable driving ability
■ Operating Voltage
● VCC: 2.7 to 3.6 V
■ Operating Temperature and Packages
● Ta = -40℃ to +105℃
– 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
– 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
– 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
■ Analog
● 12-bit A/D Converter (ADC12) × 2
● 12-bit D/A Converter (DAC12) × 2
● Temperature Sensor (TSN)
■ Timers
● General PWM Timer 32-bit (GPT32) × 4
● General PWM Timer 16-bit (GPT16) × 4
● Low Power Asynchronous General Purpose Timer (AGT) × 6
■ Security and Encryption
● Secure Crypto Engine 9
– Symmetric algorithms: AES
– Asymmetric algorithms: RSA, ECC, and DSA
– Hash-value generation: SHA224, SHA256, GHASH
– 128-bit unique ID
● Arm® TrustZone®
– Up to three regions for the code flash
– Up to two regions for the data flash
– Up to three regions for the SRAM
– Individual secure or non-secure security attribution for each
peripheral
● Device lifecyle management
● Pin function
– Up to three tamper pins
– Secure pin multiplexing
■ System and Power Management
●
●
●
●
●
●
●
●
●
Low power modes
Battery backup function (VBATT)
Realtime Clock (RTC) with calendar and VBATT support
Event Link Controller (ELC)
Data Transfer Controller (DTC)
DMA Controller (DMAC) × 8
Power-on reset
Low Voltage Detection (LVD) with voltage settings
Watchdog Timer (WDT)
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RA4M3 Datasheet
1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set of
Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to 100 MHz with the following
features:
● Up to 1 MB code flash memory
● 128 KB SRAM
● Quad Serial Peripheral Interface (QSPI)
● USBFS, SD/MMC Host Interface
● Capacitive Touch Sensing Unit (CTSU)
● Analog peripherals
● Security and safety features
1.1
Table 1.1
Function Outline
Arm core
Feature
Functional description
Arm Cortex-M33 core
Table 1.2
● Maximum operating frequency: up to 100 MHz
● Arm Cortex-M33 core:
– Armv8-M architecture with security extension
– Revision: r0p4-00rel0
● Arm Memory Protection Unit (Arm MPU)
– Protected Memory System Architecture (PMSAv8)
– Secure MPU (MPU_S): 8 regions
– Non-secure MPU (MPU_NS): 8 regions
● SysTick timer
– Embeds two Systick timers: Secure and Non-secure instance
– Driven by SysTick timer clock (SYSTICCLK) or system clock (ICLK)
● CoreSight™ ETM-M33
Memory
Feature
Functional description
Code flash memory
Maximum 1 MB of code flash memory.
Data flash memory
8 KB of data flash memory.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset.
SRAM
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC).
Table 1.3
System (1 of 2)
Functional description
Operating modes
Two operating modes:
● Single-chip mode
● SCI/USB boot mode
Resets
The MCU provides 14 resets.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The
detection level can be selected by register settings. The LVD module consists of three separate
voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level
input to the VCC pin. LVD registers allow your application to configure detection of VCC changes
at various voltage thresholds.
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RA4M3 Datasheet
Table 1.3
1. Overview
System (2 of 2)
Functional description
Clocks
●
●
●
●
●
●
●
●
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator
PLL/PLL2
Clock out support
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock selected as the
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.When measurement is
complete or the number of pulses within the time generated by the measurement reference clock
is not within the allowable range, an interrupt request is generated.
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector
Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)
modules. The ICU also controls non-maskable interrupts.
Low power modes
Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes.
Battery backup function
A battery backup function is provided for partial powering by a battery. The battery-powered area
includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.
Register write protection
The register write protection function protects important registers from being overwritten due to
software errors. The registers to be protected are set with the Protect Register (PRCR).
Memory Protection Unit (MPU)
The MCU has one Memory Protection Unit (MPU).
Table 1.4
Event link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the event requests generated by various peripheral
modules as source signals to connect them to different modules, allowing direct link between the
modules without CPU intervention.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request.
DMA Controller (DMAC)
The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data
without intervention from the CPU. When a DMA transfer request is generated, the DMAC
transfers data stored at the transfer source address to the transfer destination address.
Table 1.6
External bus interface
Feature
Functional description
External buses
Table 1.7
● QSPI area (EQBIU): Connected to the QSPI (external device interface)
Timers (1 of 2)
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with
GPT16 × 4 channels. PWM waveforms can be generated by controlling the up-counter, downcounter, or the up- and down-counter. In addition, PWM waveforms can be generated for
controlling brushless DC motors. The GPT can also be used as a general-purpose timer.
Port Output Enable for GPT (POEG)
The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins
in the output disable state
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RA4M3 Datasheet
Table 1.7
1. Overview
Timers (2 of 2)
Feature
Functional description
Low power Asynchronous General
Purpose Timer (AGT)
The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used
for pulse output, external pulse width or period measurement, and counting external events. This
timer consists of a reload register and a down counter. The reload register and the down counter
are allocated to the same address, and can be accessed with the AGT register.
Realtime Clock (RTC)
The realtime clock (RTC) has two counting modes, calendar count mode and binary count mode,
that are used by switching register settings. For calendar count mode, the RTC has a 100-year
calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count
mode, the RTC counts seconds and retains the information as a serial value. Binary count mode
can be used for calendars other than the Gregorian (Western) calendar.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow
interrupt.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the
MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer
operates with an independent, dedicated clock source, it is particularly useful in returning the
MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT
can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value
in the registers.
Table 1.8
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface (SCI)
The Serial Communications Interface (SCI) × 6 channels have asynchronous and synchronous
serial interfaces:
● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
● 8-bit clock synchronous interface
● Simple IIC (master-only)
● Simple SPI
● Smart card interface
● Manchester interface
● Extended Serial interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol. SCIn (n = 0, 3, 4, 9) has FIFO buffers to enable continuous and full-duplex
communication, and the data transfer speed can be configured independently using an on-chip
baud rate generator.
I2C bus interface (IIC)
The I2C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset
of the NXP I2C (Inter-Integrated Circuit) bus interface functions.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial
communications with multiple processors and peripheral devices.
Control Area Network (CAN)
The Controller Area Network (CAN) module uses a message-based protocol to receive and
transmit data between multiple slaves and masters in electromagnetically noisy applications. The
module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32
mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO
modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN
module requires an additional external CAN transceiver.
USB 2.0 Full-Speed module (USBFS)
The USB 2.0 Full-Speed module (USBFS) can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0. The USB has
buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned
any endpoint number based on the peripheral devices used for communication or based on your
system.
Quad Serial Peripheral Interface (QSPI)
The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial ROM
(nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has
an SPI-compatible interface.
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RA4M3 Datasheet
Table 1.8
1. Overview
Communication interfaces (2 of 2)
Feature
Functional description
Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting I2S/Monaural/TDM audio data over a serial bus. The SSIE
supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master
receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage
FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data
reception and transmission.
SD/MMC Host Interface (SDHI)
Table 1.9
The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit
buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with the
SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit, 4bit, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451) device
access. This interface also provides backward compatibility and supports high-speed SDR
transfer modes.
Analog
Functional description
12-bit A/D Converter (ADC12)
A 12-bit successive approximation A/D converter is provided. Up to 22 analog input channels are
selectable. Temperature sensor output and internal reference voltage are selectable for
conversion.
12-bit D/A Converter (DAC12)
A 12-bit D/A converter (DAC12) is provided.
Temperature Sensor (TSN)
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is fairly
linear. The output voltage is provided to the ADC12 for conversion and can be further used by
the end application.
Table 1.10
Human machine interfaces
Feature
Functional description
Capacitive Touch Sensing Unit (CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch
sensor. Changes in the electrostatic capacitance are determined by software that enables the
CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the
touch sensor is usually enclosed with an electrical conductor so that a finger does not come into
direct contact with the electrode.
Table 1.11
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generation polynomials are available.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected
condition applies, 16-bit data is compared and an interrupt can be generated.
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RA4M3 Datasheet
1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Memory
Bus
1 MB code flash
MPU
Arm Cortex-M33
DSP
FPU
System
POR/LVD
Clocks
MOSC/SOSC
8 KB data flash
IDAU
Reset
(H/M/L) OCO
128 KB SRAM
MPU
1 KB Standby
SRAM
Mode control
PLL/PLL2
Power control
CAC
ICU
Battery backup
NVIC
DMA
System timer
DTC
Test and DBG interface
Register write
protection
DMAC × 8
Timers
GPT32 x 4
GPT16 x 4
Communication interfaces
SCI × 6
QSPI
IIC × 2
SDHI
SPI
CAN × 2
SSIE
USBFS
Human machine interfaces
CTSU
AGT × 6
RTC
WDT/IWDT
Event link
Data processing
Analog
ELC
CRC
ADC12 × 2
Security
DOC
DAC12 × 2
TSN
SCE9
Note:
Not available on all parts.
Figure 1.1
1.3
Block diagram
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a
list of products.
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RA4M3 Datasheet
1. Overview
R7FA4M3AF3C FB #AA 0
Production identification code
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FB: LQFP 144 pins
FP: LQFP 100 pins
FM: LQFP 64 pins
Quality Grade
Operating temperature
3: -40°C to 105°C
Code flash memory size
D: 512 KB
E: 768 KB
F: 1 MB
Feature set
Group number
Series name
RA family
Flash memory
Renesas microcontroller
Figure 1.2
Part numbering scheme
Table 1.12
Product list
Product part number
Package code
Code flash
Data
flash
SRAM
Operating
temperature
R7FA4M3AF3CFB
PLQP0144KA-B
1 MB
8 KB
128 KB
-40 to +105°C
R7FA4M3AF3CFP
PLQP0100KB-B
R7FA4M3AF3CFM
PLQP0064KB-C
R7FA4M3AE3CFB
PLQP0144KA-B
768 KB
8 KB
128 KB
-40 to +105°C
R7FA4M3AE3CFP
PLQP0100KB-B
R7FA4M3AE3CFM
PLQP0064KB-C
R7FA4M3AD3CFB
PLQP0144KA-B
512 KB
8 KB
128 KB
-40 to +105°C
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RA4M3 Datasheet
1.4
1. Overview
Function Comparison
Table 1.13
Function Comparison
R7FA4M3AF3CFB
R7FA4M3AE3CFB
R7FA4M3AD3CFB
Parts number
Pin count
R7FA4M3AF3CFP
R7FA4M3AE3CFP
144
100
Package
1 MB
768 KB
512 KB
1 MB
768 KB
Data flash memory
8 KB
SRAM
128 KB
Parity
64 KB
ECC
64 KB
Standby SRAM
1 KB
DTC
Yes
DMAC
System
8
CPU clock
100 MHz (max.)
CPU clock sources
MOSC, SOSC, HOCO, MOCO, LOCO, PLL
CAC
Yes
WDT/IWDT
Yes
Backup register
Communication
128 B
SCI
6
IIC
2
SPI
1
CAN
Timers
2
USBFS
Yes
QSPI
Yes
SSIE
Yes
No
SDHI/MMC
Yes
No
GPT32*1
4
GPT16*1
4
AGT*1
6
RTC
Analog
ADC12
Yes
Unit 0: 12
Unit 1: 10
DAC12
Unit 0: 11
Unit 1: 9
Yes
HMI
CTSU
Data processing
CRC
Yes
DOC
Yes
ELC
Yes
Security
Unit 0: 7
Unit 1: 4
2
TSN
Event control
64
LQFP
Code flash memory
DMA
R7FA4M3AF3CFM
R7FA4M3AE3CFM
20
12
7
SCE9, TrustZone, and Lifecycle management
Note 1. Available pins depend on the Pin count, about details see section 1.7. Pin Lists.
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RA4M3 Datasheet
1.5
1. Overview
Pin Functions
Table 1.14
Pin functions (1 of 4)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect
this pin to VSS by a 0.1-µF capacitor. The capacitor should be
placed close to the pin.
VCL/VCL0
I/O
Connect this pin to the VSS pin by the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the
pin.
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
VBATT
Input
Battery Backup power pin
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
XCIN
Input
XCOUT
Output
CLKOUT
Output
Clock output pin
Operating mode control
MD
Input
Pin for setting the operating mode. The signal level on this pin must
not be changed during operation mode transition on release from
the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this
signal goes low.
CAC
CACREF
Input
Measurement reference clock input pin
On-chip emulator
TMS
I/O
On-chip emulator or boundary scan pins
TDI
Input
TCK
Input
TDO
Output
TCLK
Output
Output clock for synchronization with the trace data
TDATA0 to TDATA3
Output
Trace data output
SWO
Output
Serial wire trace output pin
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
NMI
Input
Non-maskable interrupt request pin
Clock
Interrupt
Input/output pins for the sub-clock oscillator. Connect a crystal
resonator between XCOUT and XCIN.
IRQn
Input
Maskable interrupt request pins
IRQn-DS
Input
Maskable interrupt request pins that can also be used in Deep
Software Standby mode
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RA4M3 Datasheet
Table 1.14
1. Overview
Pin functions (2 of 4)
Function
Signal
I/O
Description
GPT
GTETRGA, GTETRGB,
GTETRGC, GTETRGD
Input
External trigger input pins
GTIOCnA, GTIOCnB
I/O
Input capture, output compare, or PWM output pins
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
AGTEEn
Input
External event input enable signals
AGTIOn
I/O
External event input and pulse output pins
AGTOn
Output
Pulse output pins
AGTOAn
Output
Output compare match A output pins
AGTOBn
Output
Output compare match B output pins
RTCOUT
Output
Output pin for 1-Hz or 64-Hz clock
RTCICn
Input
Time capture event input pins
SCKn
I/O
Input/output pins for the clock (clock synchronous mode)
RXDn
Input
Input pins for received data (asynchronous mode/clock synchronous
mode)
TXDn
Output
Output pins for transmitted data (asynchronous mode/clock
synchronous mode)
CTSn_RTSn
I/O
Input/output pins for controlling the start of transmission and
reception (asynchronous mode/clock synchronous mode), activelow.
CTSn
Input
Input for the start of transmission.
SCLn
I/O
Input/output pins for the IIC clock (simple IIC mode)
SDAn
I/O
Input/output pins for the IIC data (simple IIC mode)
SCKn
I/O
Input/output pins for the clock (simple SPI mode)
MISOn
I/O
Input/output pins for slave transmission of data (simple SPI mode)
MOSIn
I/O
Input/output pins for master transmission of data (simple SPI mode)
SSn
Input
Chip-select input pins (simple SPI mode), active-low
RXDXn
Input
Input pins for received data (Extended Serial Mode)
TXDXn
Output
Output pins for transmitted data (Extended Serial Mode)
SIOXn
I/O
Input/output pins for receivde or tramsmitted data (Extended Serial
Mode)
SCLn
I/O
Input/output pins for the clock
SDAn
I/O
Input/output pins for data
AGT
RTC
SCI
IIC
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RA4M3 Datasheet
Table 1.14
1. Overview
Pin functions (3 of 4)
Function
Signal
I/O
Description
SPI
RSPCKA
I/O
Clock input/output pin
MOSIA
I/O
Input or output pins for data output from the master
MISOA
I/O
Input or output pins for data output from the slave
SSLA0
I/O
Input or output pin for slave selection
SSLA1 to SSLA3
Output
Output pins for slave selection
CRXn
Input
Receive data
CTXn
Output
Transmit data
VCC_USB
Input
Power supply pin
VSS_USB
Input
Ground pin
USB_DP
I/O
D+ pin of the USB on-chip transceiver. Connect this pin to the D+
pin of the USB bus.
USB_DM
I/O
D- pin of the USB on-chip transceiver. Connect this pin to the D- pin
of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. Connect this pin to VBUS of the
USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a function controller.
USB_EXICEN
Output
Low-power control signal for external power supply (OTG) chip
USB_VBUSEN
Output
VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA,
USB_OVRCURB
Input
Connect the external overcurrent detection signals to these pins.
Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_OVRCURA-DS,
USB_OVRCURB-DS
Input
Overcurrent pins for USBFS that can also be used in Deep Software
Standby mode.
Connect the external overcurrent detection signals to these pins.
Connect the VBUS comparator signals to these pins when the OTG
power supply chip is connected.
USB_ID
Input
Connect the MicroAB connector ID input signal to this pin during
operation in OTG mode
QSPCLK
Output
QSPI clock output pin
QSSL
Output
QSPI slave output pin
QIO0 to QIO3
I/O
Data0 to Data3
SSIBCK0
I/O
SSIE serial bit clock pins
SSILRCK0/SSIFS0
I/O
LR clock/frame synchronization pins
SSITXD0
Output
Serial data output pin
SSIRXD0
Input
Serial data input pin
SSIDATA0
I/O
Serial data input/output pins
AUDIO_CLK
Input
External clock pin for audio (input oversampling clock)
SD0CLK
Output
SD clock output pins
SD0CMD
I/O
Command output pin and response input signal pins
SD0DAT0 to SD0DAT7
I/O
SD and MMC data bus pins
SD0CD
Input
SD card detection pins
SD0WP
Input
SD write-protect signals
CAN
USBFS
QSPI
SSIE
SDHI/MMC
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 11 of 92
RA4M3 Datasheet
Table 1.14
1. Overview
Pin functions (4 of 4)
Function
Signal
I/O
Description
Analog power supply
AVCC0
Input
Analog voltage supply pin. This is used as the analog power supply
for the respective modules. Supply this pin with the same voltage as
the VCC pin.
AVSS0
Input
Analog ground pin. This is used as the analog ground for the
respective modules. Supply this pin with the same voltage as the
VSS pin.
VREFH0
Input
Analog reference voltage supply pin for the ADC12 (unit 0). Connect
this pin to AVCC0 when not using the ADC12 (unit 0).
VREFL0
Input
Analog reference ground pin for the ADC12. Connect this pin to
AVSS0 when not using the ADC12 (unit 0).
VREFH
Input
Analog reference voltage supply pin for the ADC12 (unit 1) and D/A
Converter. Connect this pin to AVCC0 when not using the ADC12
(unit 1) and D/A Converter.
VREFL
Input
Analog reference ground pin for the ADC12 and D/A Converter.
Connect this pin to AVSS0 when not using the ADC12 (unit 1) and
D/A Converter.
ANmn
Input
Input pins for the analog signals to be processed by the A/D
converter.
(m: ADC unit number, n: pin number)
ADTRGm
Input
Input pins for the external trigger signals that start the A/D
conversion, active-low.
DAC12
DAn
Output
Output pins for the analog signals processed by the D/A converter.
CTSU
TSn
Input
Capacitive touch detection pins (touch pins)
TSCAP
I/O
Secondary power supply pin for the touch driver
Pmn
I/O
General-purpose input/output pins
(m: port number, n: pin number)
P200
Input
General-purpose input pin
ADC12
I/O ports
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 12 of 92
RA4M3 Datasheet
1.6
1. Overview
Pin Assignments
Figure 1.3
VCL
VSS
VCC
P614
P613
P612
P611
P610
P609
P608
VSS
VCC
P115
P114
P113
P112
P111
P110/TDI
P109/TDO
P108/TMS/SWDIO
92
91
90
89
88
87
85
84
83
81
79
77
76
75
74
73
P604
P605
94
78
P602
P603
96
80
P601
97
82
VCC
P600
99
86
VSS
100
93
P107
101
95
P106
102
98
P104
P105
103
104
105
P101
P102
P103
106
P100
107
108
The following figures show the pin assignments from the top view.
P800
109
P801
110
71
P301
VCC
111
70
P302
72
P300/TCK/SWCLK
VSS
112
69
P303
P500
113
68
P501
114
67
VCC
VSS
P502
P503
115
66
P304
116
65
P305
P504
117
64
P306
P505
118
63
P307
P506
119
62
P308
P507
120
61
P309
VCC
121
60
P310
P311
P312
35
36
P409
P408
P407
P701
P702
P406
P700
34
VSS_USB
33
37
32
144
P410
P511
31
USB_DP
USB_DM
30
38
P412
P411
39
143
P413
142
29
VCC_USB
28
40
P414
141
P415
P207
VSS
VCC
P512
27
41
P708
P206
140
26
42
P709
139
25
P205
P001
P000
P710
P204
43
24
44
138
P711
137
P002
23
P003
P712
P202
P203
22
45
VCC
46
136
P713
135
P004
21
P005
P212/EXTAL
VSS
P313
20
47
19
134
18
P006
17
48
VSS
P213/XTAL
VCC
P007
133
XCOUT
P214
49
16
50
132
15
131
XCIN
P211
P009
P008
14
51
13
130
P705
VBATT
VCL0
P210
VREFH0
12
52
P704
129
11
P209
VREFL0
P703
53
10
128
9
P208
AVSS0
8
RES
54
7
55
127
6
126
AVCC0
5
P200
P201/MD
4
56
P404
P405
125
P403
VREFL
VREFH
3
57
P402
124
2
58
P014
1
59
123
P401
122
P400
VSS
P015
Pin assignment for LQFP 144-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 13 of 92
Figure 1.5
P113
P112
P111
P110/TDI
P109/TDO
P108/TMS/SWDIO
55
54
53
52
51
VCC
P114
VSS
62
56
VCL
63
P115
P602
64
57
P601
65
58
P600
66
P610
P107
67
P608
P106
68
P609
P105
69
59
P104
70
60
P103
71
61
P101
P102
72
P100
75
95
31
P206
P004
96
30
P207
P003
97
29
VCC_USB
P002
98
28
USB_DP
P001
99
27
USB_DM
P000
100
26
VSS_USB
25
P205
P005
P407
32
24
94
P408
P214
P006
23
33
P409
P211
93
22
34
P007
P410
P210
92
21
35
P008
P411
P209
VREFH0
20
36
91
P412
P208
VREFL0
19
37
90
18
89
P413
RES
AVSS0
P414
38
17
88
P415
P201/MD
AVCC0
P708
39
16
87
VCC
P200
VREFH
15
40
14
86
P212/EXTAL
P307
VREFL
13
41
P213/XTAL
85
12
P306
P014
VSS
42
11
84
XCOUT
P305
P015
10
43
XCIN
83
9
P304
VSS
VCL0
44
8
82
VBATT
VSS
VCC
7
45
P406
81
6
VCC
P505
5
P303
46
P405
47
80
P404
P302
79
P504
P403
48
P503
4
P502
P402
P300/TCK/SWCLK
P301
3
49
78
1
50
77
2
76
P501
P401
P500
P400
P100
P101
P102
P103
P104
P105
P106
VCL
VSS
VCC
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Pin assignment for LQFP 100-pin
21
P207
P003
61
20
VCC_USB
P002
62
19
USB_DP
P001
63
18
USB_DM
P000
64
17
VSS_USB
16
P206
P004
P407
22
60
15
59
P408
P205
VREFH0
14
23
13
58
P410
P208
VREFL0
P409
RES
24
12
25
57
P411
56
AVSS0
11
AVCC0
VCC
P201/MD
10
26
P212/EXTAL
55
9
P200
VREFH
P213/XTAL
27
8
54
VSS
P304
VREFL
7
28
XCOUT
53
6
P303
P014
XCIN
29
5
52
VCL0
P302
P015
4
30
VBATT
51
3
P301
VSS
P402
P300/TCK/SWCLK
31
2
32
50
P401
49
VCC
1
P500
P400
Figure 1.4
73
1. Overview
74
RA4M3 Datasheet
Pin assignment for LQFP 64-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 14 of 92
RA4M3 Datasheet
1.7
Pin Lists
Pin list (1 of 4)
LPQFP64
LPQFP100
Table 1.15
LPQFP144
1. Overview
Power, System,
Clock, Debug,
CAC
1
1
1
—
P400
IRQ0
SCK4/SCL0_A/AUDIO_CLK
GTIOC6A/AGTIO1
ADTRG1
2
2
2
—
P401
IRQ5-DS
CTS4_RTS4/SS4/SDA0_A/CTX0
GTETRGA/GTIOC6B
—
—
3
3
3
CACREF
P402
IRQ4-DS
CTS4/CRX0/AUDIO_CLK
AGTIO0/AGTIO1/AGTIO2/AGTIO3/
RTCIC0
—
—
4
4
—
—
P403
IRQ14-DS
SSIBCK0_A
GTIOC3A/AGTIO0/AGTIO1/AGTIO2/
AGTIO3/RTCIC1
—
—
5
5
—
—
P404
IRQ15-DS
SSILRCK0/SSIFS0_A
GTIOC3B/AGTIO0/AGTIO1/AGTIO2/
AGTIO3/RTCIC2
—
—
6
6
—
—
P405
—
SSITXD0_A
GTIOC1A
—
—
7
7
—
—
P406
—
SSLA3_C/SSIRXD0_A
GTIOC1B/AGTO5
—
—
8
—
—
—
P700
—
MISOA_C
GTIOC5A/AGTO4
—
—
9
—
—
—
P701
—
MOSIA_C
GTIOC5B/AGTO3
—
—
10
—
—
—
P702
—
RSPCKA_C
GTIOC6A/AGTO2
—
—
11
—
—
—
P703
—
SSLA0_C
GTIOC6B/AGTO1
—
—
12
—
—
—
P704
—
SSLA1_C/CTX0
AGTO0
—
—
13
—
—
—
P705
—
CTS3/SSLA2_C/CRX0
AGTIO0
—
—
14
8
4
VBATT
—
—
—
—
—
—
15
9
5
VCL0
—
—
—
—
—
—
16
10
6
XCIN
—
—
—
—
—
—
17
11
7
XCOUT
—
—
—
—
—
—
18
12
8
VSS
—
—
—
—
—
—
19
13
9
XTAL
P213
IRQ2
TXD1/MOSI1/SDA1/TXDX1/SIOX1
GTETRGC/GTIOC0A/AGTEE2
ADTRG1
—
20
14
10
EXTAL
P212
IRQ3
RXD1/MISO1/SCL1/RXDX1
GTETRGD/GTIOC0B/AGTEE1
—
—
21
15
11
VCC
—
—
—
—
—
—
22
—
—
—
P713
—
—
GTIOC2A/AGTOA0
—
TS17
23
—
—
—
P712
—
—
GTIOC2B/AGTOB0
—
TS16
24
—
—
—
P711
—
CTS1_RTS1/SS1
AGTEE0
—
TS15
25
—
—
—
P710
—
SCK1
—
—
TS14
26
—
—
—
P709
IRQ10
TXD1/MOSI1/SDA1/TXDX1/SIOX1
—
—
TS13
27
16
—
CACREF
P708
IRQ11
RXD1/MISO1/SCL1/RXDX1/AUDIO_CLK
—
—
TS12
28
17
—
—
P415
IRQ8
USB_VBUSEN/SD0CD
GTIOC0A/AGTIO4
—
TS11
29
18
—
—
P414
IRQ9
CTS0/SD0WP
GTIOC0B/AGTIO5
—
TS10
30
19
—
—
P413
—
CTS0_RTS0/SSL0/SD0CLK_A
GTOUUP/AGTEE3
—
TS09
31
20
—
—
P412
—
SCK0/CTS3/SD0CMD_A
GTOULO/AGTEE1
—
TS08
I/O
ports
Ex. Interrupt
SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12
CTSU
—
32
21
12
—
P411
IRQ4
TXD0/MOSI0/SDA0/CTS3_RTS3/SS3/SD0DAT0_A
GTOVUP/AGTOA1
—
TS07
33
22
13
—
P410
IRQ5
RXD0/MISO0/SCL0/SCK3/SD0DAT1_A
GTOVLO/AGTOB1
—
TS06
34
23
14
—
P409
IRQ6
TXD3/MOSI3/SDA3/USB_EXICEN
GTOWUP/AGTOA2
—
TS05
35
24
15
—
P408
IRQ7
CTS4/RXD3/MISO3/SCL3/SCL0_B/USB_ID
GTOWLO/GTIOC6B/AGTOB2
—
TS04
36
25
16
—
P407
—
CTS4_RTS4/SS4/SDA0_B/SSLA3_A/USB_VBUS
GTIOC6A/AGTIO0/RTCOUT
ADTRG0
TS03
37
26
17
VSS_USB
—
—
—
—
—
—
38
27
18
USB_DM
—
—
—
—
—
—
39
28
19
USB_DP
—
—
—
—
—
—
40
29
20
VCC_USB
—
—
—
—
—
—
41
30
21
—
P207
—
TXD4/MOSI4/SDA4/SSLA2_A/QSSL
—
—
TSCAP
42
31
22
—
P206
IRQ0-DS
RXD4/MISO4/SCL4/CTS9/SDA1_B/SSLA1_A/
USB_VBUSEN/SSIDATA0_C/SD0DAT2_A
GTIU
—
TS02
43
32
23
CLKOUT
P205
IRQ1-DS
TXD4/MOSI4/SDA4/CTS9_RTS9/SS9/SCL1_B/SSLA0_A/
USB_OVRCURA-DS/SSILRCK0/SSIFS0_C/SD0DAT3_A
GTIV/GTIOC4A/AGTO1
—
TS01
44
—
—
CACREF
P204
—
SCK4/SCK9/RSPCKA_A/USB_OVRCURB-DS/
SSIBCK0_C/SD0DAT4_A
GTIW/GTIOC4B/AGTIO1
—
TS00
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 15 of 92
RA4M3 Datasheet
Pin list (2 of 4)
LPQFP64
LPQFP100
LPQFP144
Table 1.15
1. Overview
Power, System,
Clock, Debug,
CAC
45
—
—
—
P203
46
—
—
—
P202
IRQ3-DS
SCK2/RXD9/MISO9/SCL9/MISOA_A/CRX0/SD0DAT6_A
GTIOC5B/AGTOB3
—
TS19
47
—
—
—
P313
—
SD0DAT7_A
—
—
—
48
—
—
VSS
—
—
—
—
—
—
49
—
—
VCC
—
—
—
—
—
—
50
33
—
TCLK
P214
—
QSPCLK/SD0CLK_B
GTIU/AGTO5
—
—
51
34
—
TDATA0
P211
—
QIO0/SD0CMD_B
GTIV/AGTOA5
—
—
52
35
—
TDATA1
P210
—
QIO1/SD0CD
GTIW/AGTOB5
—
—
53
36
—
TDATA2
P209
—
QIO2/SD0WP
GTOVUP/AGTEE5
—
—
54
37
24
TDATA3
P208
—
QIO3/SD0DAT0_B
GTOVLO
—
—
55
38
25
RES
—
—
—
—
—
—
56
39
26
MD
P201
—
—
—
—
—
57
40
27
—
P200
NMI
—
—
—
—
58
—
—
—
P312
—
CTS3_RTS3/SS3
AGTOA1
—
—
59
—
—
—
P311
—
SCK3
AGTOB1
—
—
I/O
ports
Ex. Interrupt
SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12
CTSU
IRQ2-DS
CTS2_RTS2/SS2/TXD9/MOSI9/SDA9/MOSIA_A/CTX0/
SD0DAT5_A
GTIOC5A/AGTOA3
—
TS18
60
—
—
—
P310
—
TXD3/MOSI3/SDA3/QIO3
AGTEE1
—
—
61
—
—
—
P309
—
RXD3/MISO3/SCL3/QIO2
AGTOA4
—
—
62
—
—
—
P308
—
CTS3/QIO1
AGTOB4
—
—
63
41
—
—
P307
—
QIO0
GTOUUP_D/AGTEE4
—
—
64
42
—
—
P306
—
QSSL
GTOULO_D/AGTOA2
—
—
65
43
—
—
P305
IRQ8
QSPCLK
GTOWUP/AGTOB2
—
—
66
44
28
—
P304
IRQ9
—
GTOWLO/GTIOC7A/AGTEE2
—
—
67
45
—
VSS
—
—
—
—
—
—
68
46
—
VCC
—
—
—
—
—
—
69
47
29
—
P303
—
CTS9
GTIOC7B
—
—
70
48
30
—
P302
IRQ5
TXD2/MOSI2/SDA2/TXDX2/SIOX2/SSLA3_B
GTOUUP/GTIOC4A
—
—
71
49
31
—
P301
IRQ6
RXD2/MISO2/SCL2/RXDX2/CTS9_RTS9/SS9/SSLA2_B
GTOULO/GTIOC4B/AGTIO0
—
—
72
50
32
TCK/SWCLK
P300
—
SSLA1_B
GTOUUP/GTIOC0A
—
—
73
51
33
TMS/SWDIO
P108
—
CTS9_RTS9/SS9/SSLA0_B
GTOULO/GTIOC0B/AGTOA3
—
—
74
52
34
TDO/SWO/CLKOUT
P109
—
TXD9/MOSI9/SDA9/MOSIA_B/CTX1
GTOVUP/GTIOC1A/AGTOB3
—
—
75
53
35
TDI
P110
IRQ3
CTS2_RTS2/SS2/RXD9/MISO9/SCL9/MISOA_B/CRX1
GTOVLO/GTIOC1B/AGTEE3
—
—
76
54
36
—
P111
IRQ4
SCK2/SCK9/RSPCKA_B
GTIOC3A/AGTOA5
—
—
77
55
37
—
P112
—
TXD2/MOSI2/SDA2/TXDX2/SIOX2/SCK1/SSLA0_B/QSSL/
SSIBCK0_B
GTIOC3B/AGTOB5
—
—
78
56
38
—
P113
—
RXD2/MISO2/SCL2/RXDX2/SSILRCK0/SSIFS0_B
GTIOC2A/AGTEE5
—
—
79
57
—
—
P114
—
CTS9/SSIRXD0_B
GTIOC2B/AGTIO5
—
—
80
58
—
—
P115
—
SSITXD0_B
GTIOC4A
—
—
81
—
—
VCC
—
—
—
—
—
—
82
—
—
VSS
—
—
—
—
—
—
83
59
—
—
P608
—
—
GTIOC4B
—
—
84
60
—
—
P609
—
CTX1
GTIOC5A/AGTO5
—
—
85
61
—
—
P610
—
CRX1
GTIOC5B/AGTO4
—
—
86
—
—
CACREF/CLKOUT
P611
—
—
AGTO3
—
—
87
—
—
—
P612
—
—
AGTO2
—
—
88
—
—
—
P613
—
—
AGTO1
—
—
89
—
—
—
P614
—
—
AGTO0
—
—
90
62
39
VCC
—
—
—
—
—
—
91
63
40
VSS
—
—
—
—
—
—
92
64
41
VCL
—
—
—
—
—
—
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 16 of 92
RA4M3 Datasheet
Pin list (3 of 4)
LPQFP64
LPQFP100
LPQFP144
Table 1.15
1. Overview
Power, System,
Clock, Debug,
CAC
Ex. Interrupt
SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12
CTSU
93
—
—
—
P605
—
—
AGTO4
—
—
94
—
—
—
P604
—
CTS9
AGTEE4
—
—
95
—
—
—
P603
—
CTS9_RTS9/SS9
GTIOC7A/AGTIO4
—
—
96
65
—
—
P602
—
TXD9/MOSI9/SDA9
GTIOC7B/AGTO3
—
—
97
66
—
—
P601
—
RXD9/MISO9/SCL9
GTIOC6A/AGTEE3
—
—
98
67
—
CACREF/CLKOUT
P600
—
SCK9
GTIOC6B/AGTIO3
—
—
99
—
—
VCC
—
—
—
—
—
—
100
—
—
VSS
—
—
—
—
—
—
—
I/O
ports
101
68
—
—
P107
—
—
AGTOA0
—
102
69
42
—
P106
—
—
AGTOB0
—
—
103
70
43
—
P105
IRQ0
—
GTETRGA/GTIOC1A/AGTO2
—
—
—
104
71
44
—
P104
IRQ1
QIO2
GTETRGB/GTIOC1B/AGTEE2
—
105
72
45
—
P103
—
CTS0_RTS0/SS0/CTX0/QIO3
GTOWUP/GTIOC2A/AGTIO2
—
—
106
73
46
—
P102
—
SCK0/CRX0/QIO0
GTOWLO/GTIOC2B/AGTO0
ADTRG0
—
107
74
47
—
P101
IRQ1
TXD0/MOSI0/SDA0/CTS1_RTS1/SS1/QIO1
GTETRGB/GTIOC5A/AGTEE0
—
—
108
75
48
—
P100
IRQ2
RXD0/MISO0/SCL0/SCK1/QSPCLK
GTETRGA/GTIOC5B/AGTIO0
—
—
109
—
—
—
P800
—
CTS0
AGTOA4
—
—
110
—
—
—
P801
—
—
AGTOB4
—
—
111
—
—
VCC
—
—
—
—
—
—
112
—
—
VSS
—
—
—
—
—
—
113
76
49
CACREF
P500
—
USB_VBUSEN/QSPCLK
GTIU/AGTOA0
AN116
—
114
77
—
—
P501
IRQ11
USB_OVRCURA/QSSL
GTIV/AGTOB0
AN117
—
115
78
—
—
P502
IRQ12
USB_OVRCURB/QIO0
GTIW/AGTOA2
AN118
—
116
79
—
—
P503
—
USB_EXICEN/QIO1
GTETRGC/AGTOB2
AN119
—
117
80
—
—
P504
—
USB_ID/QIO2
GTETRGD/AGTOA3
AN120
—
118
81
—
—
P505
IRQ14
QIO3
AGTOB3
AN121
—
119
—
—
—
P506
IRQ15
—
—
AN122
—
120
—
—
—
P507
—
—
—
—
—
121
82
50
VCC
—
—
—
—
—
—
122
83
51
VSS
—
—
—
—
—
—
123
84
52
—
P015
IRQ13
—
—
AN013/DA1
—
124
85
53
—
P014
—
—
—
AN012/DA0
—
125
86
54
VREFL
—
—
—
—
—
—
126
87
55
VREFH
—
—
—
—
—
—
127
88
56
AVCC0
—
—
—
—
—
—
128
89
57
AVSS0
—
—
—
—
—
—
129
90
58
VREFL0
—
—
—
—
—
—
130
91
59
VREFH0
—
—
—
—
—
—
131
—
—
—
P009
IRQ13-DS
—
—
AN009
—
132
92
—
—
P008
IRQ12-DS
—
—
AN008
—
133
93
—
—
P007
—
—
—
AN007
—
134
94
—
—
P006
IRQ11-DS
—
—
AN006
—
135
95
—
—
P005
IRQ10-DS
—
—
AN005
—
136
96
60
—
P004
IRQ9-DS
—
—
AN004
—
137
97
61
—
P003
—
—
—
AN003
—
—
138
98
62
—
P002
IRQ8-DS
—
—
AN002/AN102
139
99
63
—
P001
IRQ7-DS
—
—
AN001/AN101
—
140
100
64
—
P000
IRQ6-DS
—
—
AN000/AN100
—
141
—
—
VSS
—
—
—
—
—
—
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 17 of 92
RA4M3 Datasheet
Pin list (4 of 4)
LPQFP64
LPQFP100
LPQFP144
Table 1.15
1. Overview
Power, System,
Clock, Debug,
CAC
Ex. Interrupt
SCI/IIC/SPI/CAN/USBFS/QSPI/SSIE/SDHI/MMC
GPT/AGT/RTC
ADC12/DAC12
CTSU
142
—
—
VCC
—
—
—
—
—
—
143
—
—
—
P512
IRQ14
TXD4/MOSI4/SDA4/SCL1_A/CTX1
GTIOC0A
—
—
144
—
—
—
P511
IRQ15
RXD4/MISO4/SCL4/SDA1_A/CRX1
GTIOC0B
—
—
Note:
I/O
ports
Several pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 18 of 92
RA4M3 Datasheet
2.
2. Electrical Characteristics
Electrical Characteristics
Supported peripheral functions and pins differ from one product name to another.
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
● VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V
● 2.7 ≤ VREFH0/VREFH ≤ AVCC0
● VSS = AVSS0 = VREFL0/VREFL = VSS_USB = 0 V
● Ta = Topr
Figure 2.1 shows the timing conditions.
For example, P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The recommended measurement conditions for the timing specification of each peripheral provided are for the best
peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.
Absolute Maximum Ratings
2.1
Table 2.1
Absolute maximum ratings
Parameter
Symbol
Value
Unit
Power supply voltage
VCC, VCC_USB*2
–0.3 to +4.0
V
VBATT power supply voltage
VBATT
–0.3 to +4.0
V
Input voltage (except for 5 V-tolerant ports*1)
Vin
–0.3 to VCC + 0.3
V
Input voltage (5 V-tolerant ports*1)
Vin
–0.3 to + VCC + 4.0 (max. 5.8)
V
Reference power supply voltage
VREFH/VREFH0
–0.3 to VCC + 0.3
V
Analog power supply voltage
AVCC0*2
–0.3 to +4.0
V
Analog input voltage
VAN
–0.3 to AVCC0 + 0.3
V
Operating temperature*3 *4
Topr
–40 to +105
°C
Storage temperature
Tstg
–55 to +125
°C
Note 1.
Note 2.
Note 3.
Note 4.
Ports P205, P206, P400, P401, P407 to P415, and P708 to P713 are 5 V tolerant.
Connect AVCC0 and VCC_USB to VCC.
See section 2.2.1. Tj/Ta Definition.
Contact a Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 19 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.
Table 2.2
Recommended operating conditions
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltages
VCC
When USB is not used
2.7
—
3.6
V
When USB is used
3.0
—
3.6
V
VSS
—
0
—
V
VCC_USB
—
VCC
—
V
VSS_USB
—
0
—
V
VBATT power supply voltage
VBATT
1.8
—
3.6
V
Analog power supply voltages
AVCC0*1
—
VCC
—
V
AVSS0
—
0
—
V
USB power supply voltages
Note 1. Connect AVCC0 to VCC. When the A/D converter and the D/A converter are not in use, do not leave the AVCC0, VREFH/VREFH0,
AVSS0, and VREFL/VREFL0 pins open. Connect the AVCC0 and VREFH/VREFH0 pins to VCC, and the AVSS0 and VREFL/
VREFL0 pins to VSS, respectively.
2.2
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
—
125
°C
High-speed mode
Low-speed mode
Subosc-speed mode
Note:
Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL +
ICCmax × VCC.
2.2.2
I/O VIH, VIL
Table 2.4
I/O VIH, VIL (1 of 2)
Parameter
Input voltage
(except for
Schmitt trigger
input pins)
Peripheral
function pin
EXTAL (external clock input), SPI (except RSPCK)
IIC (SMBus)
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Symbol Min
Typ Max
Unit
VIH
VCC ×
0.8
—
—
V
VIL
—
—
VCC × 0.2
VIH
2.1
—
VCC + 3.6
(max 5.8)
VIL
—
—
0.8
Page 20 of 92
RA4M3 Datasheet
Table 2.4
2. Electrical Characteristics
I/O VIH, VIL (2 of 2)
Parameter
Schmitt trigger
input voltage
Peripheral
function pin
IIC (except for SMBus)
5 V-tolerant ports*1 *5
RTCIC0,
RTCIC1,
RTCIC2
When using the
Battery Backup
Function
When VBATT
power supply is
selected
When VCC
power supply is
selected
When not using the Battery Backup
Function
Other input pins*2
Ports
5 V-tolerant ports*3 *5
Other input pins*4
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Symbol Min
Typ Max
Unit
VIH
VCC ×
0.7
—
VCC + 3.6
(max 5.8)
V
VIL
—
—
VCC × 0.3
ΔVT
VCC ×
0.05
—
—
VIH
VCC ×
0.8
—
VCC + 3.6
(max 5.8)
VIL
—
—
VCC × 0.2
ΔVT
VCC ×
0.05
—
—
VIH
VBATT ×
0.8
—
VBATT + 0.3
VIL
—
—
VBATT × 0.2
ΔVT
VBATT ×
0.05
—
—
VIH
VCC ×
0.8
—
Higher
voltage
either
VCC + 0.3 V
or
VBATT + 0.3
V
VIL
—
—
VCC × 0.2
ΔVT
VCC ×
0.05
—
—
VIH
VCC ×
0.8
—
VCC + 0.3
VIL
—
—
VCC × 0.2
ΔVT
VCC ×
0.05
—
—
VIH
VCC ×
0.8
—
—
VIL
—
—
VCC × 0.2
ΔVT
VCC ×
0.05
—
—
VIH
VCC ×
0.8
—
VCC + 3.6
(max 5.8)
VIL
—
—
VCC × 0.2
VIH
VCC ×
0.8
—
—
VIL
—
—
VCC × 0.2
V
RES and peripheral function pins associated with Ports P205, P206, P400, P401, P407 to P415, and P708 to P713 (total 22 pins).
All input pins except for the peripheral function pins already described in the table.
Ports P205, P206, P400, P401, P407 to P415, and P708 to P713 (total 21 pins).
All input pins except for the ports already described in the table.
When VCC is less than 2.7 V, the input voltage of 5 V-tolerant ports should be less than 3.6 V, otherwise breakdown may occur
because 5 V-tolerant ports are electrically controlled so as not to violate the break down voltage.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 21 of 92
RA4M3 Datasheet
2.2.3
Table 2.5
2. Electrical Characteristics
I/O IOH, IOL
I/O IOH, IOL
Parameter
Permissible output current (average value
per pin)
Ports P000 to P009, P014, P015, P201
Ports P205, P206, P407 to P415, P708
to P713 (total 17 pins)
Symbol
Min Typ Max Unit
IOH
—
—
–2.0 mA
IOL
—
—
2.0
IOH
—
—
–2.0 mA
IOL
—
—
2.0
Middle drive*2 IOH
—
—
–4.0 mA
IOL
—
—
4.0
mA
IOH
—
—
–20
mA
IOL
—
—
20
mA
IOH
—
—
–2.0 mA
IOL
—
—
2.0
Middle drive*2 IOH
—
—
–4.0 mA
IOL
—
—
4.0
mA
IOH
—
—
–16
mA
IOL
—
—
16
mA
IOH
—
—
–4.0 mA
IOL
—
—
4.0
IOH
—
—
–4.0 mA
IOL
—
—
4.0
Middle drive*2 IOH
—
—
–8.0 mA
IOL
—
—
8.0
mA
IOH
—
—
–40
mA
IOL
—
—
40
mA
IOH
—
—
–4.0 mA
IOL
—
—
4.0
Middle drive*2 IOH
—
—
–8.0 mA
IOL
—
—
8.0
mA
IOH
—
—
–32
mA
IOL
—
—
32
mA
ΣIOH (max) —
—
–80
mA
ΣIOL (max) —
—
80
mA
—
Low drive*1
High drive*3
Other output pins*4
Low drive*1
High drive*3
Permissible output current (max value per
pin)
Ports P000 to P009, P014, P015, P201
Ports P205, P206, P407 to P415, P708
to P713 (total 17 pins)
—
Low drive*1
High drive*3
Other output pins*4
Low drive*1
High drive*3
Permissible output current (maxvalue of total
of all pins)
Maximum of all output pins
mA
mA
mA
mA
mA
mA
Note 1. This is the value when low driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 3. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. The selected driving
ability is retained in Deep Software Standby mode.
Note 4. Except for P200, which is an input port.
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this table.
The average output current indicates the average value of current measured during 100 µs.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 22 of 92
RA4M3 Datasheet
2.2.4
2. Electrical Characteristics
I/O VOH, VOL, and Other Characteristics
Table 2.6
I/O VOH, VOL, and other characteristics
Parameter
Output voltage
IIC
IIC*1
Ports P205, P206, P407 to P415,
P708 to P713 (total of 17 pins)*2
Other output pins
Input leakage current
RES
Symbol Min
Typ Max Unit Test conditions
VOL
—
—
0.4
VOL
—
—
0.6
IOL = 6.0 mA
VOL
—
—
0.4
IOL = 15.0 mA (ICFER.FMPE = 1)
VOL
—
0.4
—
IOL = 20.0 mA (ICFER.FMPE = 1)
VOH
VCC – 1.0 —
—
IOH = –20 mA
VCC = 3.3 V
VOL
—
1.0
IOL = 20 mA
VCC = 3.3 V
VOH
VCC – 0.5 —
—
IOH = –1.0 mA
VOL
—
—
0.5
IOL = 1.0 mA
|Iin|
—
—
5.0
—
—
1.0
—
—
5.0
—
—
1.0
Port P200
Three-state leakage current 5 V-tolerant ports
(off state)
|ITSI|
Other ports (except for port P200)
—
V
µA
IOL = 3.0 mA
Vin = 0 V
Vin = 5.5 V
Vin = 0 V
Vin = VCC
µA
Vin = 0 V
Vin = 5.5 V
Vin = 0 V
Vin = VCC
Input pull-up MOS current
Ports P0 to P8
Ip
–300
—
–10
µA
VCC = 2.7 to 3.6 V
Vin = 0 V
Input capacitance
USB_DP, USB_DM, and ports
P014, P015, P400, P401, P511,
P512
Cin
—
—
16
pF
—
—
8
Vbias = 0 V
Vamp = 20 mV
f = 1 MHz
Ta = 25°C
Other input pins
Note 1. SCL0_A, SDA0_A (total 2 pins).
Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register.
The selected driving ability is retained in Deep Software Standby mode.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 23 of 92
RA4M3 Datasheet
2.2.5
Table 2.7
2. Electrical Characteristics
Operating and Standby Current
Operating and standby current (1 of 2)
Parameter
Supply
current*1
High-speed
mode
Symbol
Min Typ
Max
Unit Test conditions
ICC*3
—
—
95
mA
CoreMark®*5 *6 *12
—
12
—
Normal mode
All peripheral clocks enabled,
while (1) code executing from
flash*4 *12
—
22
—
All peripheral clocks disabled,
while (1) code executing from
flash*5 *6 *12
—
12
—
—
7*6
47*7
*12
*13
Maximum*2 *13
Sleep mode*5
Increase during
BGO operation
ICLK = 100 MHz
PCLKA = 100
MHz
PCLKB = 50
MHz
PCLKC = 50
MHz
PCLKD = 100
MHz
FCLK = 50 MHz
Data flash P/E
—
6
—
Code flash P/E
—
8
—
—
1.9
—
ICLK = 1 MHz
—
1.7
—
ICLK = 32.768
kHz
SNZCR.RXDREQEN = 1
—
—
34
—
SNZCR.RXDREQEN = 0
—
1.6
—
—
Deep Software Power supplied to Standby SRAM and USB
Standby mode resume detecting unit
—
16.9
131
Low-speed
mode*5 *10
Subosc-speed mode*5 *11
Software Standby mode
µA
—
Power not
supplied to
SRAM or USB
resume
detecting unit
Power-on reset circuit low
power function disabled
—
11.8
31
—
Power-on reset circuit low
power function enabled
—
4.8
21
—
Increase when
the RTC and
AGT are
operating
When the low-speed on-chip
oscillator (LOCO) is in use
—
4.0
—
—
When a crystal oscillator for low
clock loads is in use
—
1.2
—
—
When a crystal oscillator for
standard clock loads is in use
—
1.5
—
—
When a crystal
oscillator for low
clock loads is in use
—
0.9
—
VBATT = 1.8 V,
VCC = 0 V
—
1.3
—
VBATT = 3.3 V,
VCC = 0 V
When a crystal
oscillator for
standard clock loads
is in use
—
1.0
—
VBATT = 1.8 V,
VCC = 0 V
—
1.7
—
VBATT = 3.3 V,
VCC = 0 V
RTC operating while VCC is off (with the
battery backup function, only the RTC and
sub-clock oscillator operate)
Inrush current on returning from deep
software standby mode
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Inrush current*8
IRUSH
—
160
—
mA
Energy of inrush
current*8
ERUSH
—
1.0
—
µC
Page 24 of 92
RA4M3 Datasheet
Table 2.7
2. Electrical Characteristics
Operating and standby current (2 of 2)
Parameter
Symbol
Min Typ
Max
Unit Test conditions
Analog
During 12-bit A/D conversion
power supply
Temperature sensor
current
AICC
—
0.8
1.1
mA
—
—
0.1
0.2
mA
—
Without AMP output
—
0.1
0.2
mA
—
With AMP output
—
0.6
1.1
mA
—
Waiting for A/D, D/A conversion (all units)
—
0.9
1.6
mA
—
ADC12, DAC12 in standby modes (all units)*9
—
2
8
µA
—
—
70
120
µA
—
—
0.07
0.5
µA
—
—
0.07
0.5
µA
—
—
70
120
µA
—
Without AMP output
—
0.1
0.4
mA
—
With AMP ouput
—
0.1
0.4
mA
—
Waiting for 12-bit A/D (unit 1), D/A (all units) conversion
—
0.07
0.8
µA
—
ADC12 unit 1 in standby modes
—
0.07
0.8
µA
—
During D/A conversion (per unit)
Reference
During 12-bit A/D conversion (unit 0)
power supply
Waiting for 12-bit A/D conversion (unit 0)
current
(VREFH0)
ADC12 in standby modes (unit 0)
AIREFH0
Reference
During 12-bit A/D conversion (unit 1)
power supply
During D/A conversion (per unit)
current
(VREFH)
AIREFH
USB
operating
current
Low speed
USB
ICCUSBLS —
3.5
6.5
mA
VCC_USB
Full speed
USB
ICCUSBFS —
4.0
10.0
mA
VCC_USB
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. ICC depends on f (ICLK) as follows.
ICC Max. = 0.53 × f + 42 (max. operation in high-speed mode)
ICC Typ. = 0.09 × f + 3.6 (normal operation in high-speed mode, all peripheral clocks disabled)
ICC Typ. = 0.2 × f + 1.7 (low-speed mode)
ICC Max. = 0.05 × f + 42 (sleep mode)
Note 4. This does not include the BGO operation.
Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (1.563 MHz).
Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz).
Note 8. Reference value
Note 9. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) and
MSTPCRD.MSTPD15 (12-bit A/D converter 1 module stop bit) are in the module-stop state.
Note 10. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).
Note 11. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK.
Note 12. PLL output frequency = 100MHz.
Note 13. PLL output frequency = 200MHz.
Table 2.8
Coremark and normal mode current
Parameter
Supply Current*1
Coremark*2 *3
Normal mode
Symbol
Typ
Unit
Test conditions
ICC
119
µA/MHz
ICLK = 100MHz
PCLKA
= PCLKB
= PCLKC
= PCLKD
= FCLK
= 1.56 MHz
All peripheral
clocks disabled,
cache on, while
(1) code
executing from
flash*2 *3
115
All peripheral
clocks disabled,
cache off, while
(1) code
executing from
flash*2 *3
117
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
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RA4M3 Datasheet
2. Electrical Characteristics
Note 3. PLL output frequency = 100MHz.
100.0
ICC (mA)
10.0
1.0
0.1
-40
-20
0
20
40
60
80
100
Ta (°C)
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.2
Temperature dependency in Software Standby mode (reference data)
1000
ICC (uA)
100
10
1
-40
-20
0
20
40
60
80
100
Ta (°C)
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.3
Temperature dependency in Deep Software Standby mode, power supplied to standby SRAM
and USB resume detecting unit (reference data)
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RA4M3 Datasheet
2. Electrical Characteristics
ICC (uA)
100
10
1
-40
-20
0
20
40
60
80
100
Ta (°C)
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.4
Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or
USB resume detecting unit, power-on reset circuit low power function disabled (reference
data)
ICC (uA)
100
10
1
-40
-20
0
20
40
60
80
100
Ta (°C)
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.5
Temperature dependency in Deep Software Standby mode, power not supplied to SRAM or
USB resume detecting unit, power-on reset circuit low power function enabled (reference data)
R01DS0368EJ0120 Rev.1.20
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RA4M3 Datasheet
2.2.6
Table 2.9
2. Electrical Characteristics
VCC Rise and Fall Gradient and Ripple Frequency
Rise and fall gradient characteristics
Symbol
Min
Typ
Max
Unit
Test
conditions
SrVCC
0.0084
—
20
ms/V
—
Voltage monitor 0 reset enabled at startup
0.0084
—
—
—
SCI/USB boot mode*1
0.0084
—
20
—
0.0084
—
—
Parameter
VCC rising gradient
Voltage monitor 0 reset disabled at startup
SfVCC
VCC falling gradient*2
ms/V
—
Note 1. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit.
Note 2. This applies when VBATT is used.
Table 2.10
Rising and falling gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit (2.7
V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple
frequency
fr (VCC)
—
—
10
kHz
Figure 2.6
Vr (VCC) ≤ VCC × 0.2
—
—
1
MHz
Figure 2.6
Vr (VCC) ≤ VCC × 0.08
—
—
10
MHz
Figure 2.6
Vr (VCC) ≤ VCC × 0.06
1.0
—
—
ms/V
When VCC change
exceeds VCC ±10%
Allowable voltage
change rising and
falling gradient
dt/dVCC
1 / fr(VCC)
VCC
Figure 2.6
2.2.7
Vr(VCC)
Ripple waveform
Thermal Characteristics
Maximum value of junction temperature (Tj) must not exceed the value of “section 2.2.1. Tj/Ta Definition”.
Tj is calculated by either of the following equations.
● Tj = Ta + θja × Total power consumption
● Tj = Tt + Ψjt × Total power consumption
– Tj : Junction Temperature (°C)
– Ta : Ambient Temperature (°C)
– Tt : Top Center Case Temperature (°C)
– θja : Thermal Resistance of “Junction”-to-“Ambient” (°C/W)
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RA4M3 Datasheet
2. Electrical Characteristics
– Ψjt : Thermal Resistance of “Junction”-to-“Top Center Case” (°C/W)
● Total power consumption = Voltage × (Leakage current + Dynamic current)
● Leakage current of IO = Σ (IOL × VOL) /Voltage + Σ (|IOH| × |VCC – VOH|) /Voltage
● Dynamic current of IO = Σ IO (Cin + Cload) × IO switching frequency × Voltage
– Cin: Input capacitance
– Cload: Output capacitance
Regarding θja and Ψjt, refer to Table 2.11.
Table 2.11
Thermal Resistance
Parameter
Package
Symbol
Value*1
Unit
Test conditions
Thermal
Resistance
64-pin LQFP (PLQP0064KB-C)
θja
38.0
°C/W
JESD 51-2 and 51-7
compliant
°C/W
JESD 51-2 and 51-7
compliant
100-pin LQFP (PLQP0100KB-B)
35.0
144-pin LQFP (PLQP0144KA-B)
33.0
64-pin LQFP (PLQP0064KB-C)
Ψjt
0.80
100-pin LQFP (PLQP0100KB-B)
0.76
144-pin LQFP (PLQP0144KA-B)
0.63
Note 1. The values are reference values when the 4-layer board is used. Thermal resistance depends on the number of layers or size of the
board. For details, refer to the JEDEC standards.
2.2.7.1
Calculation guide of ICCmax
Table 2.12 shows the power consumption of each unit.
Table 2.12
Power consumption of each unit (1 of 2)
Dynamic current/
Leakage current
MCU
Domain
Category
Item
Frequency
[MHz]
Current
[uA/MHz]
Current*1
[mA]
Leakage current
Analog
LDO and Leak*2
Ta = 75 °C*3
—
—
21.22
Ta = 85 °C*3
—
—
25.22
Ta = 95 °C*3
—
—
30.22
—
—
37.42
Ta = 105
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
°C*3
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RA4M3 Datasheet
Table 2.12
2. Electrical Characteristics
Power consumption of each unit (2 of 2)
Category
Item
Frequency
[MHz]
Current
[uA/MHz]
Current*1
[mA]
CPU
Operation with
Flash and SRAM
Coremark
100
86.493
8.65
Peripheral Unit
Timer
GPT16 (4ch)*4
100
3.548
0.35
GPT32 (4ch)*4
100
3.946
0.39
POEG (4 Groups)
50
1.378
0.07
(6ch)*4
50
10.095
0.50
RTC
50
5.239
0.26
WDT
50
0.722
0.04
IWDT
50
0.267
0.01
USBFS
50
8.788
0.44
100
18.077
1.81
IIC (2ch)*4
50
3.014
0.15
CAN (2ch)*4
50
3.843
0.19
SPI
100
3.394
0.34
QSPI
100
2.587
0.26
SSIE
50
3.131
0.16
SDHI
50
7.074
0.35
ADC12 (2 Units)*4
100
4.697
0.47
DAC12 (2ch)*4
100
3.543
0.35
TSN
50
0.166
0.01
Human machine
interfaces
CTSU
50
0.678
0.03
Event link
ELC
50
1.016
0.05
Security
SCE9
100
218.100
21.81
Data processing
CRC
100
0.521
0.05
DOC
100
0.358
0.04
System
CAC
50
0.909
0.05
DMA
DMAC
100
5.180
0.52
DTC
100
3.792
0.38
Dynamic current/
Leakage current
MCU
Domain
Dynamic current
AGT
Communication
interfaces
Analog
SCI
(6ch)*4
Note 1. The values are guaranteed by design.
Note 2. LDO and Leak are internal voltage regulator’s current and MCU’s leakage current.
It is selected according to the temperature of Ta.
Note 3. Δ(Tj-Ta) = 20 °C is considered to measure the current.
Note 4. To determine the current consumption per channel, group or unit, divide Current [mA] by the number of channels, groups or units.
Table 2.13 shows the outline of operation for each unit.
Table 2.13
Outline of operation for each unit (1 of 2)
Peripheral
Outline of operation
GPT
Operating modes is set to saw-wave PWM mode.
GPT is operating with PCLKD.
POEG
Only clear module stop bit.
AGT
AGT is operating with PCLKB.
RTC
RTC is operating with LOCO.
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RA4M3 Datasheet
Table 2.13
Outline of operation for each unit (2 of 2)
Peripheral
Outline of operation
WDT
WDT is operating with PCLKB.
IWDT
IWDT is operating with IWDTCLK.
USBFS
Transfer types is set to bulk transfer.
USBFS is operating using Full-speed transfer (12 Mbps).
SCI
SCI is transmitting data in clock synchronous mode.
IIC
Communication format is set to I2C-bus format.
IIC is transmitting data in master mode.
CAN
CAN is transmitting and receiving data in self-test mode 1.
SPI
SPI mode is set to SPI operation (4-wire method).
SPI master/slave mode is set to master mode.
SPI is transmitting 8-bit width data.
QSPI
QSPI is issuing Fast Read Quad I/O Instruction.
SSIE
Communication mode is set to Master.
System word length is set to 32 bits.
Data word length is set to 20 bits.
SSIE is transmitting data using I2S format.
SDHI
Transfer bus mode is set to 4-bit wide bus mode.
SDHI is issuing CMD24 (single-block write).
ADC12
Resolution is set to 12-bit accuracy.
Data registers is set to A/D-converted value addition mode.
ADC12 is converting the analog input in continuous scan mode.
DAC12
DAC12 is outputting the conversion result while updating the value of data register.
TSN
TSN is operating.
CTSU
CTSU is operating in self-capacitance single scan mode.
ELC
Only clear module stop bit.
SCE9
SCE9 is executing built-in self test.
CRC
CRC is generating CRC code using 32-bit CRC32-C polynomial.
DOC
DOC is operating in data addition mode.
CAC
Measurement target clocks is set to PCLKB.
Measurement reference clocks is set to PCLKB.
CAC is measuring the clock frequency accuracy.
DMAC
Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DMAC is transferring data from SRAM0 to SRAM0.
DTC
Bit length of transfer data is set to 32 bits.
Transfer mode is set to block transfer mode.
DTC is transferring data from SRAM0 to SRAM0.
2.2.7.2
2. Electrical Characteristics
Example of Tj calculation
Assumption :
● Package 144-pin LQFP : θja = 33.0 °C/W
● Ta = 100 °C
● ICCmax = 70 mA
● VCC = 3.5 V (VCC = AVCC = VCC_USB)
● IOH = 1 mA, VOH = VCC – 0.5 V, 12 Outputs
● IOL = 20 mA, VOL = 1.0 V, 8 Outputs
● IOL = 1 mA, VOL = 0.5 V, 12 Outputs
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RA4M3 Datasheet
2. Electrical Characteristics
● Cin = 8 pF, 32 pins, Input frequency = 10 MHz
● Cload = 30 pF, 32 pins, Output frequency = 10 MHz
Leakage current of IO = Σ (VOL × IOL) / Voltage + Σ ((VCC - VOH) × IOH) / Voltage
= (20 mA × 1 V) × 8 / 3.5 V + (1 mA × 0.5 V) × 12 / 3.5 V + ((VCC - (VCC - 0.5 V)) × 1 mA) × 12 / 3.5 V
= 45.7 mA + 1.71 mA + 1.71 mA
= 49.1 mA
Dynamic current of IO
= Σ IO (Cin + Cload) × IO switching frequency × Voltage
= ((8 pF × 32) × 10 MHz + (30 pF × 32) × 10 MHz) × 3.5 V
= 42.6 mA
Total power consumption
= Voltage × (Leakage current + Dynamic current)
= (70 mA × 3.5 V) + (49.1 mA + 42.6 mA) × 3.5 V
= 566 mW (0.566 W)
Tj = Ta + θja × Total power consumption
= 100 °C + 33.0 °C/W × 0.566W
= 118.7 °C
2.3
AC Characteristics
2.3.1
Table 2.14
Frequency
Operation frequency value in high-speed mode
Parameter
Operation frequency
Symbol
Min
Typ
Max
Unit
f
—
—
100
MHz
Peripheral module clock (PCLKA)
—
—
100
Peripheral module clock (PCLKB)
—
—
50
Peripheral module clock (PCLKC)
—*2
—
50
Peripheral module clock (PCLKD)
—
—
100
Flash interface clock (FCLK)
—*1
—
50
System clock (ICLK)
Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.
Table 2.15
Operation frequency value in low-speed mode
Parameter
Operation frequency
System clock (ICLK)
Symbol
Min
Typ
Max
Unit
f
—
—
1
MHz
Peripheral module clock (PCLKA)
—
—
1
Peripheral module clock (PCLKB)
—
—
1
Peripheral module clock (PCLKC) *2
—*2
—
1
Peripheral module clock (PCLKD)
—
—
1
—
—
1
Flash interface clock
(FCLK)*1
Note 1. Programming or erasing the flash memory is disabled in low-speed mode.
Note 2. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.
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RA4M3 Datasheet
Table 2.16
2. Electrical Characteristics
Operation frequency value in Subosc-speed mode
Parameter
Operation frequency
Symbol
Min
Typ
Max
Unit
f
29.4
—
36.1
kHz
Peripheral module clock (PCLKA)
—
—
36.1
Peripheral module clock (PCLKB)
—
—
36.1
Peripheral module clock (PCLKC) *2
—
—
36.1
Peripheral module clock (PCLKD)
—
—
36.1
Flash interface clock (FCLK)*1
29.4
—
36.1
System clock (ICLK)
Note 1. Programming or erasing the flash memory is disabled in Subosc-speed mode.
Note 2. The ADC12 cannot be used.
2.3.2
Table 2.17
Clock Timing
Clock timing except for sub-clock oscillator (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit Test conditions
EXTAL external clock input cycle time
tEXcyc
41.66
—
—
ns
EXTAL external clock input high pulse width
tEXH
15.83
—
—
ns
EXTAL external clock input low pulse width
tEXL
15.83
—
—
ns
EXTAL external clock rise time
tEXr
—
—
5.0
ns
EXTAL external clock fall time
tEXf
—
—
5.0
ns
Main clock oscillator frequency
fMAIN
8
—
24
MHz —
Main clock oscillation stabilization wait time (crystal)*1
tMAINOSCWT —
—
—*1
ms
LOCO clock oscillation frequency
fLOCO
29.4912 32.768 36.0448 kHz
—
LOCO clock oscillation stabilization wait time
tLOCOWT
—
—
60.4
µs
Figure 2.9
ILOCO clock oscillation frequency
fILOCO
13.5
15
16.5
kHz
—
MOCO clock oscillation frequency
FMOCO
6.8
8
9.2
MHz —
MOCO clock oscillation stabilization wait time
tMOCOWT
—
—
15.0
µs
HOCO clock oscillator oscillation
frequency
fHOCO16
15.78
16
16.22
MHz –20 ≤ Ta ≤ 105°C
fHOCO18
17.75
18
18.25
fHOCO20
19.72
20
20.28
fHOCO16
15.71
16
16.29
fHOCO18
17.68
18
18.32
fHOCO20
19.64
20
20.36
fHOCO16
15.960
16
16.040
fHOCO18
17.955
18
18.045
fHOCO20
19.950
20
20.050
HOCO clock oscillation stabilization wait time*2
tHOCOWT
—
—
64.7
µs
—
HOCO period jitter
—
—
±85
—
ps
—
FLL stabilization wait time
tFLLWT
—
—
1.8
ms
—
PLL clock frequency
fPLL
100
—
200
MHz —
PLL2 clock frequency
fPLL2
120
—
240
MHz —
PLL/PLL2 clock oscillation stabilization wait time
tPLLWT
—
—
174.9
µs
Without FLL
With FLL
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Figure 2.7
Figure 2.8
—
–40 ≤ Ta ≤ –20°C
–40 ≤ Ta ≤ 105°C
Sub-clock frequency accuracy
is ±50 ppm.
Figure 2.10
Page 33 of 92
RA4M3 Datasheet
Table 2.17
2. Electrical Characteristics
Clock timing except for sub-clock oscillator (2 of 2)
Parameter
Symbol
PLL/PLL2 period jitter
Min
Typ
Max
Unit Test conditions
fPLL, fPLL2 ≥ 120MHz —
—
±100
—
ps
—
fPLL, fPLL2 < 120MHz —
—
±120
—
ps
—
—
—
±300
—
ps
Term: 1µs, 10µs
PLL/PLL2 long term jitter
Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation, and use the results as the
recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended
value.
After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF flag to confirm that
it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range for guaranteed
operation.
Table 2.18
Clock timing for the sub-clock oscillator
Parameter
Symbol
Min
Typ
Max Unit Test conditions
Sub-clock frequency
fSUB
—
32.768
—
kHz
—
Sub-clock oscillation stabilization wait time
tSUBOSCWT
—
—
—*1
s
Figure 2.11
Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time.
After changing the setting in the SOSCCR.SOSTP bit to start sub-clock operation, only start using the sub-clock oscillator after the
sub-clock oscillation stabilization time elapses with an adequate margin. A value that is two times the value shown is recommended.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
Figure 2.7
tXf
EXTAL external clock input timing
MOSCCR.MOSTP
Main clock oscillator output
tMAINOSCWT
Main clock
Figure 2.8
Main clock oscillation start timing
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RA4M3 Datasheet
2. Electrical Characteristics
LOCOCR.LCSTP
On-chip oscillator output
tLOCOWT
LOCO clock
Figure 2.9
LOCO clock oscillation start timing
PLLCR.PLLSTP
PLL2CR.PLL2STP
PLL/PLL2 circuit output
tPLLWT
OSCSF.PLLSF
OSCSF.PLL2SF
PLL/PLL2 clock
Figure 2.10
PLL/PLL2 clock oscillation start timing
SOSCCR.SOSTP
Sub-clock oscillator output
tSUBOSCWT
Sub-clock
Figure 2.11
2.3.3
Table 2.19
Sub-clock oscillation start timing
Reset Timing
Reset timing (1 of 2)
Parameter
RES pulse width
Wait time after RES cancellation
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Symbol Min Typ
Max
Unit Test conditions
Power-on
tRESWP
0.7
—
—
ms
Figure 2.12
Deep Software Standby mode
tRESWD
0.6
—
—
ms
Figure 2.13
Software Standby mode, Subosc-speed
mode
tRESWS
0.3
—
—
ms
All other
tRESW
200 —
—
µs
tRESWT
—
37.3 41.2
µs
Figure 2.12
Page 35 of 92
RA4M3 Datasheet
Table 2.19
2. Electrical Characteristics
Reset timing (2 of 2)
Parameter
Symbol Min Typ
Max
Wait time after internal reset cancellation
(IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error
reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset)
tRESW2
397.7 µs
VCC
—
324
Unit Test conditions
—
VCCmin
RES
tRESWP
Internal reset signal
(low is valid)
tRESWT
Figure 2.12
RES pin input timing under the condition that VCC exceeds VPOR voltage threshold
tRESWD, tRESWS, tRESW
RES
Internal reset signal
(low is valid)
tRESWT
Figure 2.13
2.3.4
Table 2.20
Reset input timing
Wakeup Timing
Timing of recovery from low power modes (1 of 2)
Parameter
Recovery time from
Software Standby
mode*1
Symbol
Crystal resonator
connected to main clock
oscillator
Min Typ
Max
Unit Test conditions
System clock source is
main clock oscillator*2
tSBYMC*13 —
2.1
2.4
ms
System clock source is
PLL with main clock
oscillator*3
tSBYPC*13 —
2.2
2.6
ms
System clock source is
main clock oscillator*4
tSBYEX*13 —
45
125
μs
System clock source is
PLL with main clock
oscillator*5
tSBYPE*13 —
170
255
μs
System clock source is sub-clock oscillator*6 *11
tSBYSC*13 —
0.7
0.8
ms
System clock source is LOCO*7 *11
tSBYLO*13 —
0.7
0.9
ms
System clock source is HOCO clock oscillator*8
tSBYHO*13 —
55
130
µs
System clock source is PLL with HOCO*9
tSBYPH*13 —
175
265
µs
System clock source is MOCO clock oscillator*10
tSBYMO*13 —
35
65
µs
External clock input to
main clock oscillator
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Figure 2.14
The division ratio of all
oscillators is 1.
Page 36 of 92
RA4M3 Datasheet
Table 2.20
2. Electrical Characteristics
Timing of recovery from low power modes (2 of 2)
Parameter
Symbol
Min Typ
Max
Unit Test conditions
DPSBYCR.DEEPCUT[1] = 0 and
DPSWCR.WTSTS[5:0] = 0x0E
tDSBY
—
0.38
0.54
ms
DPSBYCR.DEEPCUT[1] = 1 and
DPSWCR.WTSTS[5:0] = 0x19
tDSBY
—
0.55
0.73
ms
Wait time after cancellation of Deep Software Standby mode
tDSBYWT
56
—
57
tcyc
Recovery time from
Software Standby
mode to Snooze
mode
High-speed mode when system clock source is
HOCO (20 MHz)
tSNZ
—
35*12 70*12 μs
High-speed mode when system clock source is
MOCO (8 MHz)
tSNZ
—
11*12 14*12 μs
Recovery time from
Deep Software
Standby mode
Figure 2.15
Figure 2.16
Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be
determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest tSBYOSCWT in the active oscillators tSBYOSCWT for the system clock + 2 LOCO cycles (when LOCO is operating) + Subosc is oscillating and MSTPC0 = 0 (CAC
module stop))
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the
greatest value of the internal clock division setting is 1.
Note 3. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05) and the greatest
value of the internal clock division setting is 4.
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and
the greatest value of the internal clock division setting is 1.
Note 5. When the frequency of PLL is 200 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00) and the greatest
value of the internal clock division setting is 4.
Note 6. The Sub-clock oscillator frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.
Note 7. The LOCO frequency is 32.768 KHz and the greatest value of the internal clock division setting is 1.
Note 8. The HOCO frequency is 20 MHz and the greatest value of the internal clock division setting is 1.
Note 9. The PLL frequency is 200 MHz and the greatest value of the internal clock division setting is 4.
Note 10. The MOCO frequency is 8 MHz and the greatest value of the internal clock division setting is 1.
Note 11. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 12. When the SNZCR.RXDREQEN bit is set to 0, the following time is added as the power supply recovery time: 16 µs (typical), 48 µs
(maximum).
Note 13. The recovery time can be calcurated with the equation of tSBYOSCWT + tSBYSEQ. And they can be determined with the fol-lowing
value and equation. For n, the greatest value is selected from among the internal clock division settings.
Wakeup time TYP
MAX
Unit
tSBYOSCWT
tSBYSEQ
tSBYOSCWT
tSBYSEQ
tSBYMC
(MSTS[7:0]*32 + 3) /
0.262
35 + 18 / fICLK + 4n / fMAIN
(MSTS[7:0]*32 + 14 /
0.236
62 + 18 / fICLK + 4n / fMAIN
µs
tSBYPC
(MSTS[7:0]*32 + 34) /
0.262
35 + 18 / fICLK + 4n / fPLL
(MSTS[7:0]*32 + 45) /
0.236
62 + 18 / fICLK + 4n / fPLL
µs
tSBYEX
10
35 + 18 / fICLK + 4n / fEXMAIN 62
62 + 18 / fICLK + 4n / fEXMAIN µs
tSBYPE
135
35 + 18 / fICLK + 4n / fPLL
192
62 + 18 / fICLK + 4n / fPLL
µs
tSBYSC
0
35 + 18 / fICLK + 4n / fSUB
0
62 + 18 / fICLK + 4n / fSUB
µs
tSBYLO
0
35 + 18 / fICLK + 4n / fLOCO
0
62 + 18 / fICLK + 4n / fLOCO
µs
tSBYHO
20
35 + 18 / fICLK + 4n / fHOCO
67
62 + 18 / fICLK + 4n / fHOCO
µs
tSBYPH
140
35 + 18 / fICLK + 4n / fPLL
202
62 + 18 / fICLK + 4n / fPLL
µs
tSBYMO
0
35 + 18 / fICLK + 4n / fMOCO
0
62 + 18 / fICLK + 4n / fMOCO
µs
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RA4M3 Datasheet
2. Electrical Characteristics
Oscillator
(system clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(not the system clock)
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower
Oscillator
(system clock)
tSBYOSCWT
tSBYSEQ
Oscillator
(not the system clock)
tSBYOSCWT
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX, tSBYPC, tSBYPE,
tSBYPH, tSBYSC, tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower
Figure 2.14
Software Standby mode cancellation timing
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RA4M3 Datasheet
2. Electrical Characteristics
Oscillator
IRQ
Deep Software Standby
reset
(low is valid)
Internal reset
(low is valid)
Deep Software Standby mode
tDSBY
tDSBYWT
Reset exception handling start
Figure 2.15
Deep Software Standby mode cancellation timing
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.16
2.3.5
Table 2.21
Recovery timing from Software Standby mode to Snooze mode
NMI and IRQ Noise Filter
NMI and IRQ noise filter
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
NMI pulse
width
tNMIW
200
—
—
ns
tPcyc × 2 ≤ 200 ns
tPcyc × 2*1
—
—
NMI digital filter
disabled
200
—
—
tNMICK × 3 ≤ 200 ns
—
—
NMI digital filter
enabled
200
—
—
tPcyc × 2 ≤ 200 ns
tPcyc × 2*1
—
—
IRQ digital filter
disabled
200
—
—
tIRQCK × 3 ≤ 200 ns
tIRQCK × 3.5*3
—
—
IRQ digital filter
enabled
tNMICK ×
IRQ pulse
width
tIRQW
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3.5*2
ns
tPcyc × 2 > 200 ns
tNMICK × 3 > 200 ns
tPcyc × 2 > 200 ns
tIRQCK × 3 > 200 ns
Page 39 of 92
RA4M3 Datasheet
Note:
Note:
Note 1.
Note 2.
Note 3.
2. Electrical Characteristics
200 ns minimum in Software Standby mode.
If the clock source is switched, add 4 clock cycles of the switched source.
tPcyc indicates the PCLKB cycle.
tNMICK indicates the cycle of the NMI digital filter sampling clock.
tIRQCK indicates the cycle of the IRQi digital filter sampling clock.
NMI
tNMIW
Figure 2.17
NMI interrupt input timing
IRQ
tIRQW
Figure 2.18
2.3.6
Table 2.22
IRQ interrupt input timing
I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing
I/O ports, POEG, GPT, AGT, and ADC12 trigger timing
GPT32 Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
Unit
Test conditions
I/O ports
Input data pulse width
tPRW
1.5
—
tPcyc
Figure 2.19
POEG
POEG input trigger pulse width
tPOEW
3
—
tPcyc
Figure 2.20
GPT
Input capture pulse width
tGTICW
1.5
—
tPDcyc
Figure 2.21
2.5
—
—
4
ns
Figure 2.22
Single edge
Dual edge
AGT
ADC12
GTIOCxY output skew
(x = 0 to 3, Y = A or B)
Middle drive buffer
High drive buffer
—
4
GTIOCxY output skew
(x = 4 to 7, Y = A or B)
Middle drive buffer
—
4
High drive buffer
—
4
GTIOCxY output skew
(x = 0 to 7, Y = A or B)
Middle drive buffer
—
6
High drive buffer
—
6
tGTISK*1
OPS output skew
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO
tGTOSK
—
5
ns
Figure 2.23
AGTIO, AGTEE input cycle
tACYC*2
100
—
ns
Figure 2.24
AGTIO, AGTEE input high width, low width
tACKWH, tACKWL
40
—
ns
AGTIO, AGTO, AGTOA, AGTOB output cycle
tACYC2
62.5
—
ns
ADC12 trigger input pulse width
tTRGW
1.5
—
tPcyc
Figure 2.25
Note:
tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.
Note 2. Constraints on input cycle:
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RA4M3 Datasheet
2. Electrical Characteristics
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
When switching the source clock: tPcyc × 6 < tACYC should be satisfied.
Port
tPRW
Figure 2.19
I/O ports input timing
POEG input trigger
tPOEW
Figure 2.20
POEG input trigger timing
Input capture
tGTICW
Figure 2.21
GPT input capture timing
PCLKD
Output delay
GPT output
tGTISK
Figure 2.22
GPT output delay skew
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RA4M3 Datasheet
2. Electrical Characteristics
PCLKD
Output delay
GPT output
tGTOSK
Figure 2.23
GPT output delay skew for OPS
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.24
AGT input/output timing
ADTRG0,
ADTRG1
tTRGW
Figure 2.25
2.3.7
Table 2.23
ADC12 trigger input timing
CAC Timing
CAC timing
Parameter
CAC
CACREF input pulse
width
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
tPBcyc ≤ tcac*1
tPBcyc > tcac*1
Symbol
Min
Typ
Max
Unit
Test conditions
tCACREF
4.5 × tcac + 3 × tPBcyc
—
—
ns
—
5 × tcac + 6.5 × tPBcyc
—
—
ns
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RA4M3 Datasheet
2. Electrical Characteristics
Note:
tPBcyc: PCLKB cycle.
Note 1. tcac: CAC count clock source cycle.
2.3.8
SCI Timing
Table 2.24
SCI timing (1)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
SCI Input clock cycle
Asynchronous
Symbol Min
Max Unit Test conditions
tScyc
4
—
Clock synchronous
6
—
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
5
ns
Input clock fall time
tSCKf
—
5
ns
tScyc
6 (other than SCI1,
SCI2)
8 (SCI1, SCI2)
—
tPcyc
4
—
Output clock cycle
Asynchronous
Clock synchronous
Output clock pulse width
tSCKW
0.4
0.6
tScyc
Output clock rise time
tSCKr
—
5
ns
Output clock fall time
tSCKf
—
5
ns
Clock synchronous master mode (internal
clock)
tTXD
—
5
ns
Clock synchronous slave mode (external
clock)
tTXD
—
25
ns
tRXS
15
—
ns
Clock synchronous slave mode (external
clock)
tRXS
5
—
ns
Clock synchronous
tRXH
5
—
ns
Transmit data delay
Receive data setup time Clock synchronous master mode (internal
clock)
Receive data hold time
Note:
tPcyc Figure 2.26
Figure 2.27
tPcyc: PCLKA cycle.
tSCKW
tSCKr
tSCKf
SCKn
tScyc
Note:
n = 0 to 4, 9
Figure 2.26
SCK clock input/output timing
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RA4M3 Datasheet
2. Electrical Characteristics
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
Note:
n = 0 to 4, 9
Figure 2.27
SCI input/output timing in clock synchronous mode
Table 2.25
SCI timing (2)
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Simple SPI
SCK clock cycle output (master)
Symbol
Min
Max
Unit
Test conditions
tSPcyc
4
65536
tPcyc
Figure 2.28
6
65536
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
SCK clock rise and fall time
tSPCKr, tSPCKf
—
5
ns
tSU
15
—
ns
5
—
ns
Data input setup time
master
slave
Data input hold time
tH
5
—
ns
SS input setup time
tLEAD
1
—
tSPcyc
SS input hold time
tLAG
1
—
tSPcyc
tOD
—
5
ns
—
25
ns
Data output delay
master
slave
Note:
Data output hold time
tOH
-5
—
ns
Data rise and fall time
tDr, tDf
—
5
ns
SS input rise and fall time
tSSLr, tSSLf
—
5
ns
Slave access time
tSA
—
3 × tPcyc + 25
ns
Slave output release time
tREL
—
3 × tPcyc + 25
ns
Figure 2.29 to Figure
2.32
Figure 2.32
tPcyc: PCLKA cycle.
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RA4M3 Datasheet
2. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
SCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
SCKn
slave select input
tSPCKf
VIH
VIL
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n = 0 to 4, 9
Figure 2.28
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
Note:
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = 0 to 4, 9
Figure 2.29
SCI simple SPI mode timing for master when CKPH = 1
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RA4M3 Datasheet
2. Electrical Characteristics
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
MISOn
input
tH
MSB IN
tOH
LSB IN
MSB IN
tDr, tDf
tOD
MOSIn
output
Note:
DATA
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
n = 0 to 4, 9
Figure 2.30
SCI simple SPI mode timing for master when CKPH = 0
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tOD
DATA
tREL
LSB OUT
MSB OUT
tDr, tDf
tH
MSB IN
MSB IN
DATA
LSB IN
MSB IN
n = 0 to 4, 9
Figure 2.31
SCI simple SPI mode timing for slave when CKPH = 1
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RA4M3 Datasheet
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tREL
DATA
LSB OUT
MSB OUT
tDr, tDf
tH
MSB IN
DATA
LSB IN
MSB IN
n = 0 to 4, 9
Figure 2.32
SCI simple SPI mode timing for slave when CKPH = 0
Table 2.26
SCI timing (3)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Simple IIC
(Standard mode)
Simple IIC
(Fast mode)
Symbol
Min
Max
Unit
Test conditions
SDA input rise time
tSr
—
1000
ns
Figure 2.33
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
250
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*1
—
400
pF
SDA input rise time
tSr
—
300
ns
SDA input fall time
tSf
—
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
100
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*1
—
400
pF
Figure 2.33
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle.
Note 1. Cb indicates the total capacity of the bus line.
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2. Electrical Characteristics
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
P*1
P*1
Sr*1
S*1
tSDAH
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note:
n = 0 to 4, 9
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.33
SCI simple IIC mode timing
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RA4M3 Datasheet
2.3.9
2. Electrical Characteristics
SPI Timing
Table 2.27
SPI timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
SPI
RSPCK clock cycle
Master
Symbol
Min
Max
Unit
Test conditions
tSPcyc
2
4096
tPcyc
Figure 2.34
4
4096
(tSPcyc – tSPCKr – tSPCKf) /
2–3
—
ns
0.4
0.6
tSPcyc
(tSPcyc – tSPCKr – tSPCKf) /
2–3
—
ns
0.4
0.6
tSPcyc
—
5
ns
—
1
µs
4
—
ns
5
—
Slave
RSPCK clock high
pulse width
Master
tSPCKWH
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
RSPCK clock rise and Master
fall time
Slave
tSPCKr, tSPCKf
Data input setup time
tSU
Master
Slave
Data input hold time
SSL setup time
Master
(PCLKA
division ratio
set to 1/2)
tHF
0
—
Master
(PCLKA
division ratio
set to a value
other than
1/2)
tH
tPcyc
—
Slave
tH
20
—
Master
tLEAD
N × tSPcyc - 10*1
N × tSPcyc +
100*1
ns
4 × tPcyc
—
ns
N × tSPcyc - 10*2
N × tSPcyc +
100*2
ns
4 × tPcyc
—
ns
tOD1
—
6.3
ns
tOD2
—
6.3
Slave
tOD
—
20
Master
tOH
0
—
0
—
tSPcyc + 2 × tPcyc
8 × tSPcyc + 2
× tPcyc
ns
—
5
ns
—
1
µs
—
5
ns
—
1
µs
ns
Slave
SSL hold time
Master
tLAG
Slave
Data output delay
Data output hold time
Master
Slave
Successive
transmission delay
Master
tTD
Slave
MOSI and MISO rise
and fall time
Output
SSL rise and fall time
Output
ns
ns
4 × tPcyc
tDr, tDf
Input
tSSLr, tSSLf
Input
Slave access time
tSA
—
25
Slave output release time
tREL
—
25
R01DS0368EJ0120 Rev.1.20
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Figure 2.35 to Figure
2.40
Figure 2.39 and
Figure 2.40
Page 49 of 92
RA4M3 Datasheet
2. Electrical Characteristics
Note:
Note:
tPcyc: PCLKA cycle.
Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SPI
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. N is set to an integer from 1 to 8 by the SPCKD register.
Note 2. N is set to an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKWH
VOH
RSPCKn
master select
output
VOH
tSPCKf
VOH
VOL
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCKn
slave select input
tSPCKf
VIH
VIL
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Note:
n=A
Figure 2.34
SPI clock timing
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD2
DATA
LSB OUT
IDLE
MSB OUT
tOD1
Note:
n=A
Figure 2.35
SPI timing for master when CPHA = 0
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2. Electrical Characteristics
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
tHF
MSB IN
tDr, tDf
MOSIn
output
LSB IN
DATA
tOH
MSB OUT
MSB IN
tOD2
DATA
LSB OUT
IDLE
MSB OUT
tOD1
Note:
n=A
Figure 2.36
SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tOH
MOSIn
output
Note:
DATA
LSB IN
tDr, tDf
tOD2
MSB OUT
MSB IN
DATA
LSB OUT
IDLE
MSB OUT
n=A
Figure 2.37
SPI timing for master when CPHA = 1
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2. Electrical Characteristics
SPI
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
MSB IN
tOH
DATA
LSB IN
MSB OUT
MSB IN
tDr, tDf
tOD2
MOSIn
output
Note:
tH
DATA
LSB OUT
IDLE
MSB OUT
n=A
Figure 2.38
RSPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
tOD
DATA
tREL
LSB OUT
MSB OUT
tDr, tDf
tH
MSB IN
MSB IN
DATA
LSB IN
MSB IN
n=A
Figure 2.39
SPI timing for slave when CPHA = 0
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2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
Note:
Table 2.28
DATA
LSB OUT
MSB OUT
tDr, tDf
tH
MSB IN
DATA
LSB IN
MSB IN
n=A
Figure 2.40
2.3.10
tREL
SPI timing for slave when CPHA = 1
QSPI Timing
QSPI timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
QSPI
Symbol
Min
Max
Unit
Test conditions
tQScyc
2
48
tPcyc
Figure 2.41
QSPCK clock high pulse tQSWH
width
tQScyc × 0.4
—
ns
QSPCK clock low pulse
width
tQSWL
tQScyc × 0.4
—
ns
Data input setup time
tSu
10
—
ns
Data input hold time
tIH
0
—
ns
QSSL setup time
tLEAD
(N + 0.5) × tQscyc - 5*1
(N + 0.5) × tQscyc +
100*1
ns
QSSL hold time
tLAG
(N + 0.5) × tQscyc - 5*2
(N + 0.5) × tQscyc +
100*2
ns
Data output delay
tOD
—
4
ns
Data output hold time
tOH
–3.3
—
ns
1
16
tQScyc
QSPCK clock cycle
Successive transmission tTD
delay
Figure 2.42
Note:
tPcyc: PCLKA cycle.
Note 1. N is set to 0 or 1 in SFMSLD.
Note 2. N is set to 0 or 1 in SFMSHD.
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2. Electrical Characteristics
tQSWH
tQSWL
QSPCLK output
tQScyc
Figure 2.41
QSPI clock timing
tTD
QSSL
output
tLEAD
tLAG
QSPCLK
output
tSU
QIO0-3
input
tH
MSB IN
DATA
tOH
QIO0-3
output
Figure 2.42
MSB OUT
LSB IN
tOD
DATA
LSB OUT
IDLE
Transmit and receive timing
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2.3.11
Table 2.29
2. Electrical Characteristics
IIC Timing
IIC timing (1) (1 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Symbol
Min
Max
Unit
Test
conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
—
ns
Figure 2.43
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA rise time
tSr
—
1000
ns
SCL, SDA fall time
tSf
—
300
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc ns
SDA input bus free time when
wakeup function is disabled
tBUF
3 (6) × tIICcyc + 300
—
ns
SDA input bus free time when
wakeup function is enabled
tBUF
3 (6) × tIICcyc + 4 × tPcyc +
300
—
ns
START condition input hold time
when wakeup function is disabled
tSTAH
tIICcyc + 300
—
ns
START condition input hold time
when wakeup function is enabled
tSTAH
1 (5) × tIICcyc + tPcyc + 300
—
ns
Repeated START condition input
setup time
tSTAS
1000
—
ns
STOP condition input setup time
tSTOS
1000
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Parameter
IIC
(Standard mode,
SMBus)
ICFER.FMPE = 0
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Table 2.29
2. Electrical Characteristics
IIC timing (1) (2 of 2)
(1) Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_B,
SCL0_B, SDA1_B, SCL1_B.
(2) The following pins do not require setting: SCL0_A, SDA0_A, SCL1_A, SDA1_A.
(3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the
AC portion of the electrical characteristics is measured for each group.
Symbol
Min
Max
Unit
Test
conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc + 600
—
ns
Figure 2.43
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
—
ns
SCL, SDA rise time
tSr
20 × (external pullup
voltage/5.5V)*1
300
ns
SCL, SDA fall time
tSf
20 × (external pullup
voltage/5.5V)*1
300
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc ns
SDA input bus free time when
wakeup function is disabled
tBUF
3 (6) × tIICcyc + 300
—
ns
SDA input bus free time when
wakeup function is enabled
tBUF
3 (6) × tIICcyc + 4 × tPcyc +
300
—
ns
START condition input hold time
when wakeup function is disabled
tSTAH
tIICcyc + 300
—
ns
START condition input hold time
when wakeup function is enabled
tSTAH
1 (5) × tIICcyc + tPcyc + 300
—
ns
Repeated START condition input
setup time
tSTAS
300
—
ns
STOP condition input setup time
tSTOS
300
—
ns
Data input setup time
tSDAS
tIICcyc + 50
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb
—
400
pF
Parameter
IIC
(Fast mode)
Note:
Note:
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC
interface, the AC portion of the electrical characteristics is measured for each group.
Note 1. Only supported for SCL0_A, SDA0_A, SCL1_A, and SDA1_A.
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Table 2.30
2. Electrical Characteristics
IIC timing (2)
Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.
Parameter
IIC
(Fast-mode+)
ICFER.FMPE = 1
Symbol
Min
Max
Unit
Test conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc +
240
—
ns
Figure 2.43
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 120
—
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 120
—
ns
SCL, SDA rise time
tSr
—
120
ns
SCL, SDA fall time
tSf
20 × (external
pullup voltage/
5.5V)
120
ns
SCL, SDA input spike pulse
removal time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time when
wakeup function is disabled
tBUF
3 (6) × tIICcyc + 120
—
ns
SDA input bus free time when
wakeup function is enabled
tBUF
3 (6) × tIICcyc + 4 ×
tPcyc + 120
—
ns
Start condition input hold time
when wakeup function is disabled
tSTAH
tIICcyc + 120
—
ns
START condition input hold time
when wakeup function is enabled
tSTAH
1 (5) × tIICcyc +
tPcyc + 120
—
ns
Restart condition input setup time
tSTAS
120
—
ns
Stop condition input setup time
tSTOS
120
—
ns
Data input setup time
tSDAS
tIICcyc + 30
—
ns
Data input hold time
tSDAH
0
—
ns
SCL, SDA capacitive load
Cb*1
—
550
pF
Note:
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note:
Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
Note 1. Cb indicates the total capacity of the bus line.
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2. Electrical Characteristics
VIH
SDAn
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCLn
P*1
P*1
Sr*1
S*1
tSCLL
tSf
tSr
tSDAS
tSCL
tSDAH
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.43
2.3.12
Table 2.31
I2C bus interface input/output timing
SSIE Timing
SSIE timing
(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the
AC portion of the electrical characteristics is measured for each group.
Target specification
Parameter
SSIBCK0
Cycle
High level/ low
level
Rising time/
falling time
SSILRCK0/
SSIFS0,
SSITXD0,
SSIRXD0,
SSIDATA0
Min.
Max.
Unit
Comments
Master
tO
80
—
ns
Figure 2.44
Slave
tI
80
—
ns
Master
tHC/tLC
0.35
—
tO
0.35
—
tI
—
0.15
tO / tI
—
0.15
tO / tI
12
—
ns
12
—
ns
8
—
ns
15
—
ns
-10
5
ns
0
20
ns
Figure 2.46,
Figure 2.47
Slave
Master
tRC/tFC
Slave
Input set up
time
Master
Input hold time
Master
tSR
Slave
tHR
Slave
Output delay
time
GTIOC2A,
AUDIO_CLK
Symbol
Master
tDTR
Slave
Figure 2.46,
Figure 2.47
Output delay
Slave
time from
SSILRCK0/
SSIFS0 change
tDTRW
—
20
ns
Figure 2.48*1
Cycle
tEXcyc
20
—
ns
Figure 2.45
High level/ low level
tEXL/tEXH
0.4
0.6
tEXcyc
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RA4M3 Datasheet
2. Electrical Characteristics
Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK0/SSIFS0 pin is used to generate
transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA0 pin.
tHC
tRC
tFC
tLC
SSIBCK0
tO, tI
Figure 2.44
SSIE clock input/output timing
tEXcyc
tEXH
tEXL
GTIOC2A,
AUDIO_CLK
(input)
1/2 VCC
tEXf
Figure 2.45
tEXr
Clock input timing
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)
tSR
tHR
SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)
tDTR
Figure 2.46
SSIE data transmit and receive timing when SSICR.BCKP = 0
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2. Electrical Characteristics
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0 (input),
SSIRXD0,
SSIDATA0 (input)
tSR
tHR
SSILRCK0/SSIFS0 (output),
SSITXD0,
SSIDATA0 (output)
tDTR
Figure 2.47
SSIE data transmit and receive timing when SSICR.BCKP = 1
SSILRCK0/SSIFS0 (input)
SSITXD0,
SSIDATA0 (output)
tDTRW
MSB bit output delay after SSILRCK0/SSIFS0 change for slave
transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR.
Figure 2.48
2.3.13
Table 2.32
SSIE data output delay after SSILRCK0/SSIFS0 change
SD/MMC Host Interface Timing
SD/MMC Host Interface signal timing
Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Clock duty ratio is 50%.
Parameter
Symbol
Min
Max
Unit
Test conditions
SDCLK clock cycle
TSDCYC
20
—
ns
Figure 2.49
SDCLK clock high pulse width
TSDWH
6.5
—
ns
SDCLK clock low pulse width
TSDWL
6.5
—
ns
SDCLK clock rise time
TSDLH
—
3
ns
SDCLK clock fall time
TSDHL
—
3
ns
SDCMD/SDDAT output data delay
TSDODLY
–7
4
ns
SDCMD/SDDAT input data setup
TSDIS
4.5
—
ns
SDCMD/SDDAT input data hold
TSDIH
1.5
—
ns
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Note:
2. Electrical Characteristics
Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the SD/MMC
Host interface, the AC portion of the electrical characteristics is measured for each group.
TSDCYC
TSDWL
SDnCLK
(output)
TSDHL
TSDODLY(max)
TSDWH
TSDLH
TSDODLY(min)
SDnCMD/SDnDATm
(output)
TSDIS
TSDIH
SDnCMD/SDnDATm
(input)
n = 0, 1, m = 0 to 7
Figure 2.49
2.4
SD/MMC Host Interface signal timing
USB Characteristics
2.4.1
USBFS Timing
Table 2.33
USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter
Input
characteristics
Output
characteristics
Pull-up and
pull-down
characteristics
Symbol
Min
Typ
Max
Unit
Test conditions
Input high voltage
VIH
2.0
—
—
V
—
Input low voltage
VIL
—
—
0.8
V
—
Differential input sensitivity
VDI
0.2
—
—
V
| USB_DP - USB_DM |
Differential common-mode range
VCM
0.8
—
2.5
V
—
Output high voltage
VOH
2.8
—
3.6
V
IOH = –200 µA
Output low voltage
VOL
0.0
—
0.3
V
IOL = 2 mA
Cross-over voltage
VCRS
1.3
—
2.0
V
Figure 2.50
Rise time
tLR
75
—
300
ns
Fall time
tLF
75
—
300
ns
Rise/fall time ratio
tLR / tLF
80
—
125
%
tLR/ tLF
USB_DP and USB_DM pull-down
resistance in host controller mode
Rpd
14.25
—
24.80
kΩ
—
USB_DP,
USB_DM
90%
VCRS
90%
10%
tLR
Figure 2.50
10%
tLF
USB_DP and USB_DM output timing in low-speed mode
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2. Electrical Characteristics
Observation
point
USB_DP
200 pF to
600 pF
27
3.6 V
1.5 K
USB_DM
200 pF to
600 pF
Figure 2.51
Test circuit in low-speed mode
Table 2.34
USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter
Input
characteristics
Output
characteristics
Pull-up and
pull-down
characteristics
Symbol
Min
Typ
Max
Unit
Test conditions
Input high voltage
VIH
2.0
—
—
V
—
Input low voltage
VIL
—
—
0.8
V
—
Differential input sensitivity
VDI
0.2
—
—
V
| USB_DP - USB_DM |
Differential common-mode range
VCM
0.8
—
2.5
V
—
Output high voltage
VOH
2.8
—
3.6
V
IOH = –200 µA
Output low voltage
VOL
0.0
—
0.3
V
IOL = 2 mA
Cross-over voltage
VCRS
1.3
—
2.0
V
Figure 2.52
Rise time
tLR
4
—
20
ns
Fall time
tLF
4
—
20
ns
Rise/fall time ratio
tLR / tLF
90
—
111.11
%
tFR/ tFF
Output resistance
ZDRV
28
—
44
Ω
USBFS: Rs = 27 Ω included
DM pull-up resistance in device controller
mode
Rpu
0.900
—
1.575
kΩ
During idle state
1.425
—
3.090
kΩ
During transmission and
reception
USB_DP and USB_DM pull-down
resistance in host controller mode
Rpd
14.25
—
24.80
kΩ
—
USB_DP,
USB_DM
90%
VCRS
90%
10%
tFR
Figure 2.52
10%
tFF
USB_DP and USB_DM output timing in full-speed mode
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2. Electrical Characteristics
Observation
point
USB_DP
50 pF
27
USB_DM
50 pF
Figure 2.53
Test circuit in full-speed mode
Table 2.35
USBFS characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, USBCLK = 48 MHz
Parameter
Battery Charging
Specification
2.5
Symbol
Min
Typ
Max
Unit
Test conditions
D+ sink current
IDP_SINK
25
—
175
µA
—
D- sink current
IDM_SINK
25
—
175
µA
—
DCD source current
IDP_SRC
7
—
13
µA
—
Data detection voltage
VDAT_REF
0.25
—
0.4
V
—
D+ source voltage
VDP_SRC
0.5
—
0.7
V
Outout current = 250 µA
D- source voltage
VDM_SRC
0.5
—
0.7
V
Outout current = 250 µA
ADC12 Characteristics
Table 2.36
A/D conversion characteristics for unit 0 (1 of 2)
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min
Typ
Max Unit Test conditions
Frequency
1
—
50
MHz —
Analog input capacitance
—
—
30
pF
Quantization error
—
±0.5 —
LSB —
—
12
Bits
—
Resolution
High-precision high-speed
channels
(AN000 to AN005)
—
time*1
Conversion
(operation at PCLKC =
50 MHz)
—
Permissible signal
source impedance
Max. = 1 kΩ
0.52
—
—
μs
Sampling in 13
states
Max. = 400 Ω
0.40 (0.14)*2 —
—
μs
Sampling in 7 states
VCC = AVCC0 = 3.0
to 3.6 V
3.0 V ≤ VREFH0 ≤
AVCC0
(0.26)*2
Offset error
—
±1.0 ±2.5 LSB —
Full-scale error
—
±1.0 ±2.5 LSB —
Absolute accuracy
—
±2.0 ±4.5 LSB —
DNL differential nonlinearity error
—
±0.5 ±1.5 LSB —
INL integral nonlinearity error
—
±1.0 ±2.5 LSB —
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Table 2.36
2. Electrical Characteristics
A/D conversion characteristics for unit 0 (2 of 2)
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min
High-precision normal-speed
channels
(AN006 to AN009, AN012,
AN013)
time*1
Conversion
(Operation at PCLKC =
50 MHz)
Permissible signal
source impedance
Max. = 1 kΩ
0.92
(0.66)*2
Typ
Max Unit Test conditions
—
—
μs
Sampling in 33
states
Offset error
—
±1.0 ±2.5 LSB —
Full-scale error
—
±1.0 ±2.5 LSB —
Absolute accuracy
—
±2.0 ±4.5 LSB —
DNL differential nonlinearity error
—
±0.5 ±1.5 LSB —
INL integral nonlinearity error
—
±1.0 ±2.5 LSB —
Note:
These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note:
When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave
function. If selected, values might not fall within the indicated ranges.
● AN100 and AN000 or AN001 or AN002
● AN101 and AN000 or AN001 or AN002 or AN003
● AN102 and AN000 or AN001 or AN002 or AN003 or AN004
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Table 2.37
A/D conversion characteristics for unit 1
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min
Typ
Max Unit Test conditions
Frequency
1
—
50
MHz —
Analog input capacitance
—
—
30
pF
Quantization error
—
±0.5 —
LSB —
—
12
Bits
—
Resolution
High-precision high-speed
channels
(AN100 to AN102)
Normal-precision normalspeed channels
(AN116 to AN122)
—
time*1
Conversion
(Operation at PCLKC =
50 MHz)
—
Permissible signal
source impedance
Max. = 1 kΩ
0.52
—
—
μs
Sampling in 13
states
Max. = 400 Ω
0.40 (0.14)*2 —
—
μs
Sampling in 7 states
VCC = AVCC0 = 3.0
to 3.6 V
3.0 V ≤ VREFH ≤
AVCC0
(0.26)*2
Offset error
—
±1.0 ±2.5 LSB —
Full-scale error
—
±1.0 ±2.5 LSB —
Absolute accuracy
—
±2.0 ±4.5 LSB —
DNL differential nonlinearity error
—
±0.5 ±1.5 LSB —
INL integral nonlinearity error
—
time*1
Conversion
(Operation at PCLKC =
50 MHz)
Permissible signal
source impedance
Max. = 1 kΩ
0.92
±1.0 ±2.5 LSB —
(0.66)*2
—
—
μs
Sampling in 33
states
Offset error
—
±1.0 ±5.5 LSB —
Full-scale error
—
±1.0 ±5.5 LSB —
Absolute accuracy
—
±2.0 ±7.5 LSB —
DNL differential nonlinearity error
—
±0.5 ±4.5 LSB —
INL integral nonlinearity error
—
±1.0 ±5.5 LSB —
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2. Electrical Characteristics
Note:
These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note:
When both unit0 and unit1 are used, do not select the following analog input combinations at the same time except the interleave
function. If selected, values might not fall within the indicated ranges.
● AN100 and AN000 or AN001 or AN002
● AN101 and AN000 or AN001 or AN002 or AN003
● AN102 and AN000 or AN001 or AN002 or AN003 or AN004
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Note 2. Values in parentheses indicate the sampling time.
Table 2.38
A/D conversion characteristics for interleaving
Conditions: PCLKC = 1 to 50 MHz
Parameter
Min Typ
Max Unit Test conditions
Frequency
1
—
50
MHz —
Analog input capacitance
—
—
30
pF
Quantization error
—
±0.5 —
LSB —
—
—
12
Bits
—
High-precision high-speed channels
Max. = 400 Ω 0.22 —
Conversion
(AN000 & AN100, AN001 & AN101, AN002 (operation at PCLKC = 50
& AN102))
MHz)
—
µs
Sampling in 9 states
VCC = AVCC0 = 3.0 to
3.6 V
3.0 V ≤ VREFH0 ≤
AVCC0
Resolution
time*1
—
Offset error
—
±1.0 ±2.5 LSB —
Full-scale error
—
±1.0 ±2.5 LSB —
Absolute accuracy
—
±2.0 ±4.5 LSB —
DNL differential nonlinearity error
—
±0.5 ±3.5 LSB —
INL integral nonlinearity error
—
±1.0 ±3.5 LSB —
Note:
These specification values apply when there is no access to the external memory during A/D conversion. If access occurs during
A/D conversion, values might not fall within the indicated ranges.
The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.
The characteristics apply when AVCC0, AVSS0, VREFH0/VREFH, VREFL0, VREFL, and 12-bit A/D converter input voltage are
stable.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test
conditions.
Table 2.39
A/D internal reference voltage characteristics
Parameter
Min
Typ
Max
Unit
Test conditions
A/D internal reference voltage
1.13
1.18
1.23
V
—
Sampling time
4.15
—
—
µs
—
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2. Electrical Characteristics
0xFFF
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
Offset error
0x000
0
Figure 2.54
Analog input voltage
VREFH0
(full-scale)
Illustration of ADC12 characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then the 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the
analog input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D
conversion result is in the range of 0x003 to 0x00D, though an output code of 0x008 can be expected from the theoretical
A/D conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors
are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
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2. Electrical Characteristics
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
2.6
DAC12 Characteristics
Table 2.40
D/A conversion characteristics
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
—
—
12
Bits
—
Absolute accuracy
—
—
±24
LSB
Resistive load 2 MΩ
INL
—
±2.0
±8.0
LSB
Resistive load 2 MΩ
DNL
—
±1.0
±2.0
LSB
—
Output impedance
—
8.5
—
kΩ
—
Conversion time
—
—
3
µs
Resistive load 2 MΩ, Capacitive load 20 pF
Output voltage range
0
—
VREFH
V
—
INL
—
±2.0
±4.0
LSB
—
DNL
—
±1.0
±2.0
LSB
—
Conversion time
—
—
4.0
µs
—
Resistive load
5
—
—
kΩ
—
Capacitive load
—
—
50
pF
—
Output voltage range
0.2
—
VREFH – 0.2
V
—
Without output amplifier
With output amplifier
2.7
TSN Characteristics
Table 2.41
TSN characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Relative accuracy
—
—
± 1.0
—
°C
—
Temperature slope
—
—
4.0
—
mV/°C
—
Output voltage (at 25 °C)
—
—
1.24
—
V
—
Temperature sensor start time
tSTART
—
—
30
µs
—
Sampling time
—
4.15
—
—
µs
—
2.8
OSC Stop Detect Characteristics
Table 2.42
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Detection time
tdr
—
—
1
ms
Figure 2.55
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2. Electrical Characteristics
Main clock
OSTDSR.OSTDF
tdr
MOCO clock
ICLK
Figure 2.55
2.9
Oscillation stop detection timing
POR and LVD Characteristics
Table 2.43
Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter
Voltage detection
level
Power-on reset
(POR)
DPSBYCR.DEEPCUT[1:0] = 00b or
01b.
Symbol Min
Typ
Max
Un
it
Test conditions
VPOR
2.5
2.6
2.7
V
DPSBYCR.DEEPCUT[1:0] = 11b.
Figure 2.56
1.8
2.25
2.7
Vdet0_1
2.84
2.94
3.04
Vdet0_2
2.77
2.87
2.97
Vdet0_3
2.70
2.80
2.90
Vdet1_1
2.89
2.99
3.09
Vdet1_2
2.82
2.92
3.02
Vdet1_3
2.75
2.85
2.95
Vdet2_1
2.89
2.99
3.09
Vdet2_2
2.82
2.92
3.02
Vdet2_3
2.75
2.85
2.95
Power-on reset time
tPOR
—
4.5
—
ms Figure 2.56
LVD0 reset time
tLVD0
—
0.51
—
Figure 2.57
LVD1 reset time
tLVD1
—
0.38
—
Figure 2.58
LVD2 reset time
tLVD2
—
0.38
—
Figure 2.59
Minimum VCC down time*1
tVOFF
200
—
—
µs
Figure 2.56,
Figure 2.57
Response delay
tdet
—
—
200
µs
Figure 2.57 to
Figure 2.59
LVD operation stabilization time (after LVD is enabled)
td(E-A)
—
—
10
µs
Hysteresis width (LVD1 and LVD2)
VLVH
—
70
—
m
V
Figure 2.58,
Figure 2.59
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Internal reset time
Figure 2.57
Figure 2.58
Figure 2.59
Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for POR and LVD.
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2. Electrical Characteristics
tVOFF
VPOR
VCC
Internal reset signal
(active-low)
tdet
Figure 2.56
tPOR
tdet
tdet
tPOR
Power-on reset timing
tVOFF
VCC
VLVH
Vdet0
Internal reset signal
(active-low)
tdet
Figure 2.57
tdet
tLVD0
Voltage detection circuit timing (Vdet0)
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2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tdet
tLVD1
When LVD1CR0.RN = 1
tLVD1
Figure 2.58
Voltage detection circuit timing (Vdet1)
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2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet2
LVCMPCR.LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.59
2.10
Voltage detection circuit timing (Vdet2)
VBATT Characteristics
Table 2.44
Battery backup function characteristics
Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VBATT = 1.8 to 3.6 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Voltage level for switching to battery backup
VDETBATT
2.50
2.60
2.70
V
Figure 2.60
Lower-limit VBATT voltage for power supply
switching caused by VCC voltage drop
VBATTSW
2.70
—
—
V
VCC-off period for starting power supply
switching
tVOFFBATT
200
—
—
µs
VBATT low voltage detection level
Vbattldet
1.8
1.9
2.0
V
Minimum VBATT down time
tBATTOFF
200
—
—
µs
Response delay
tBATTdet
—
—
200
µs
VBATT monitor operation stabilization time
(after VBATTMNSELR.VBATTMNSEL is
changed to 1)
td(E-A)
—
—
20
µs
—
140
350
nA
VBATT current increase (when
IVBATTSEL
VBATTMNSELR.VBATTMNSEL is 1 compared
to the case that VBATTMNSELR.VBATTMNSEL
is 0)
Note:
Figure 2.61
The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage
level for switching to battery backup (VDETBATT).
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2. Electrical Characteristics
tVOFFBATT
VDETBATT
VCC
VBATT
VBATTSW
Backup power
area
Figure 2.60
VBATT supply
VCC supply
VCC supply
Battery backup function characteristics
tBATTOFF
Vbattldet
VBATT
td(E-A)
VBATTMON
tBATTdet
tBATTdet
VBATTMNSEL
Figure 2.61
2.11
Table 2.45
Battery backup function characteristics
CTSU Characteristics
CTSU characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
—
TS pin capacitive load
Cbase
—
—
50
pF
—
Permissible output high current
ΣIoH
—
—
-40
mA
When the mutual capacitance
method is applied
2.12
2.12.1
Table 2.46
Flash Memory Characteristics
Code Flash Memory Characteristics
Code flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
Symbol Min
Typ*6 Max
Min
Typ*6
Max
Unit
128-byte
tP128
—
0.75
13.2
—
0.34
6.0
ms
8-KB
tP8K
—
49
176
—
22
80
ms
32-KB
tP32K
—
194
704
—
88
320
ms
Parameter
Programming time
NPEC ≤ 100 times
20 MHz ≤ FCLK ≤ 50 MHz
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conditions
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RA4M3 Datasheet
Table 2.46
2. Electrical Characteristics
Code flash memory characteristics (2 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Test
conditions
Symbol Min
Typ*6 Max
Min
Typ*6
Max
Unit
128-byte
tP128
—
0.91
15.8
—
0.41
7.2
ms
8-KB
tP8K
—
60
212
—
27
96
ms
32-KB
tP32K
—
234
848
—
106
384
ms
Erasure time
NPEC ≤ 100 times
8-KB
tE8K
—
78
216
—
43
120
ms
32-KB
tE32K
—
283
864
—
157
480
ms
Erasure time
NPEC > 100 times
8-KB
tE8K
—
94
260
—
52
144
ms
32-KB
tE32K
—
341
1040 —
189
576
ms
NPEC
10000*1
—
—
10000*1
—
—
Times
Suspend delay during programming
tSPD
—
—
264
—
—
120
µs
Programming resume time
tPRT
—
—
110
—
—
50
µs
First suspend delay during erasure in suspend
priority mode
tSESD1
—
—
216
—
—
120
µs
Second suspend delay during erasure in suspend
priority mode
tSESD2
—
—
1.7
—
—
1.7
ms
Suspend delay during erasure in erasure priority
mode
tSEED
—
—
1.7
—
—
1.7
ms
First erasing resume time during erasure in suspend
priority mode*5
tREST1
—
—
1.7
—
—
1.7
ms
Second erasing resume time during erasure in
suspend priority mode
tREST2
—
—
144
—
—
80
µs
Erasing resume time during erasure in erasure
priority mode
tREET
—
—
144
—
—
80
µs
Forced stop command
tFD
—
—
32
—
—
20
µs
Data hold time*2
tDRP
10*2 *3
—
—
10*2 *3
—
—
Years
Parameter
Programming time
NPEC > 100 times
Reprogramming/erasure
cycle*4
Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 10,000),
erasing can be performed n times for each block. For example, when 128-byte programming is performed 64 times for different
addresses in 8-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming
the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3V and room temperature.
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2. Electrical Characteristics
• Suspension during programming
FACI command
Program
Suspend
Resume
tSPD
FSTATR.FRDY
Ready
Not Ready
Ready
tPRT
Programming pulse
Programming
Programming
• Suspension during erasure in suspend priority mode
FACI command
Erase
Suspend
Suspend
Resume
Resume
tSESD1
FSTATR.FRDY
Ready
tSESD2
Ready
Not Ready
Not Ready
Not Ready
Ready
tREST1
Erasure pulse
tREST2
Erasing
Erasing
Erasing
• Suspension during erasure in erasure priority mode
FACI command
Erase
Suspend
Resume
tSEED
FSTATR.FRDY
Ready
Not Ready
Ready
Not Ready
tREET
Erasure pulse
Erasing
Erasing
• Forced Stop
FACI command
Forced Stop
tFD
FSTATR.FRDY
Figure 2.62
2.12.2
Table 2.47
Not Ready
Ready
Suspension and forced stop timing for flash memory programming and erasure
Data Flash Memory Characteristics
Data flash memory characteristics (1 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
Symbol Min
Max Min
Typ*6
Max
Test
Unit conditions
4-byte
tDP4
—
0.36
3.8
—
0.16
1.7
ms
8-byte
tDP8
—
0.38
4.0
—
0.17
1.8
16-byte
tDP16
—
0.42
4.5
—
0.19
2.0
64-byte
tDE64
—
3.1
18
—
1.7
10
128-byte tDE128
—
4.7
27
—
2.6
15
256-byte tDE256
—
8.9
50
—
4.9
28
4-byte
tDBC4
—
—
84
—
—
30
µs
NDPEC
125000*2 —
—
125000*2
—
—
—
tDSPD
—
—
264
—
—
120
µs
8-byte
—
—
264
—
—
120
16-byte
—
—
264
—
—
120
—
—
110
—
—
50
µs
tDSESD1 —
—
216
—
—
120
µs
128-byte
—
—
216
—
—
120
256-byte
—
—
216
—
—
120
Parameter
Programming time
Erasure time
Blank check time
Reprogramming/erasure cycle*1
Suspend delay during programming
4-byte
Programming resume time
First suspend delay during erasure in
suspend priority mode
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20 MHz ≤ FCLK ≤ 50 MHz
Typ*6
tDPRT
64-byte
ms
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RA4M3 Datasheet
Table 2.47
2. Electrical Characteristics
Data flash memory characteristics (2 of 2)
Conditions: Program or erase: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Symbol Min
Typ*6 Max Min
Typ*6
Max
Test
Unit conditions
tDSESD2 —
—
300
—
—
300
µs
128-byte
—
—
390
—
—
390
256-byte
—
—
570
—
—
570
—
—
300
—
—
300
128-byte
—
—
390
—
—
390
256-byte
—
—
570
—
—
570
First erasing resume time during erasure in suspend
priority mode*5
tDREST1 —
—
300
—
—
300
µs
Second erasing resume time during erasure in
suspend priority mode
tDREST2 —
—
126
—
—
70
µs
Erasing resume time during erasure in erasure
priority mode
tDREET
—
—
126
—
—
70
µs
Forced stop command
tFD
—
—
32
—
—
20
µs
Data hold time*3
tDRP
10*3 *4
—
—
10*3 *4
—
—
Year
Parameter
Second suspend delay during erasure in
suspend priority mode
64-byte
Suspend delay during erasing in erasure
priority mode
64-byte
tDSEED
µs
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 125,000),
erasing can be performed n times for each block. For example, when 4-byte programming is performed 16 times for different
addresses in 64-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address several times as one erasure is not enabled. Overwriting is prohibited.
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 3. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 4. This result is obtained from reliability testing.
Note 5. Time for resumption includes time for reapplying the erasing pulse (up to one full pulse) that was cut off at the time of suspension.
Note 6. The reference value at VCC = 3.3 V and room temperature.
2.12.3
Table 2.48
Option Setting Memory Characteristics
Option setting memory characteristics
Conditions: Program: FCLK = 4 to 50 MHz
Read: FCLK ≤ 50 MHz
FCLK = 4 MHz
20 MHz ≤ FCLK ≤ 50 MHz
Parameter
Symbol
Min
Typ*4
Max
Min
Typ*4
Max
Unit
Programming time
NOPC ≤ 100 times
tOP
—
83
309
—
45
162
ms
Programming time
NOPC > 100 times
tOP
—
100
371
—
55
195
ms
Reprogramming cycle
NOPC
20000*1
—
—
20000*1
—
—
Times
Data hold time*2
tDRP
10*2 *3
—
—
10*2 *3
—
—
Years
Test conditions
Note 1. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed range is from 1 to
the minimum value.
Note 2. This indicates the minimum value of the characteristic when reprogramming is performed within the specified range.
Note 3. This result is obtained from reliability testing.
Note 4. The reference value at VCC = 3.3 V and room temperature.
2.13
Boundary Scan
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 75 of 92
RA4M3 Datasheet
Table 2.49
2. Electrical Characteristics
Boundary scan characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
TCK clock cycle time
tTCKcyc
100
—
—
ns
Figure 2.63
TCK clock high pulse width
tTCKH
45
—
—
ns
TCK clock low pulse width
tTCKL
45
—
—
ns
TCK clock rise time
tTCKr
—
—
5
ns
TCK clock fall time
tTCKf
—
—
5
ns
TMS setup time
tTMSS
20
—
—
ns
TMS hold time
tTMSH
20
—
—
ns
TDI setup time
tTDIS
20
—
—
ns
TDI hold time
tTDIH
20
—
—
ns
TDO data delay
tTDOD
—
—
40
ns
Boundary scan circuit startup time*1
TBSSTUP
tRESWP
—
—
—
Figure 2.64
Figure 2.65
Note 1. Boundary scan does not function until the power-on reset becomes negative.
tTCKcyc
tTCKH
tTCKf
TCK
tTCKL
Figure 2.63
tTCKr
Boundary scan TCK timing
TCK
tTMSS
tTMSH
tTDIS
tTDIH
TMS
TDI
tTDOD
TDO
Figure 2.64
Boundary scan input/output timing
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 76 of 92
RA4M3 Datasheet
2. Electrical Characteristics
VCC
RES
tBSSTUP
(= tRESWP)
Figure 2.65
2.14
Boundary scan
execute
Boundary scan circuit startup timing
Joint European Test Action Group (JTAG)
Table 2.50
JTAG
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
TCK clock cycle time
tTCKcyc
40
—
—
ns
Figure 2.66
TCK clock high pulse width
tTCKH
15
—
—
ns
TCK clock low pulse width
tTCKL
15
—
—
ns
TCK clock rise time
tTCKr
—
—
5
ns
TCK clock fall time
tTCKf
—
—
5
ns
TMS setup time
tTMSS
8
—
—
ns
TMS hold time
tTMSH
8
—
—
ns
TDI setup time
tTDIS
8
—
—
ns
TDI hold time
tTDIH
8
—
—
ns
TDO data delay time
tTDOD
—
—
20
ns
Figure 2.67
tTCKcyc
tTCKH
TCK
tTCKf
tTCKr
tTCKL
Figure 2.66
JTAG TCK timing
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 77 of 92
RA4M3 Datasheet
2. Electrical Characteristics
TCK
tTMSS
tTMSH
TMS
tTDIS
tTDIH
TDI
tTDOD
TDO
Figure 2.67
2.15
Table 2.51
JTAG input/output timing
Serial Wire Debug (SWD)
SWD
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
40
—
—
ns
Figure 2.68
SWCLK clock high pulse width
tSWCKH
15
—
—
ns
SWCLK clock low pulse width
tSWCKL
15
—
—
ns
SWCLK clock rise time
tSWCKr
—
—
5
ns
SWCLK clock fall time
tSWCKf
—
—
5
ns
SWDIO setup time
tSWDS
8
—
—
ns
SWDIO hold time
tSWDH
8
—
—
ns
SWDIO data delay time
tSWDD
2
—
28
ns
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Figure 2.69
Page 78 of 92
RA4M3 Datasheet
2. Electrical Characteristics
tSWCKcyc
tSWCKH
SWCLK
tSWCKL
Figure 2.68
SWD SWCLK timing
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 2.69
2.16
SWD input/output timing
Embedded Trace Macro Interface (ETM)
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 79 of 92
RA4M3 Datasheet
Table 2.52
2. Electrical Characteristics
ETM
Conditions: High speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
TCLK clock cycle time
tTCLKcyc
40
—
—
ns
Figure 2.70
TCLK clock high pulse width
tTCLKH
17
—
—
ns
TCLK clock low pulse width
tTCLKL
17
—
—
ns
TCLK clock rise time
tTCLKr
—
—
3
ns
TCLK clock fall time
tTCLKf
—
—
3
ns
TDATA[3:0] output setup time
tTRDS
3.5
—
—
ns
TDATA[3:0] output hold time
tTRDH
2.5
—
—
ns
Figure 2.71
tTCLKcyc
tTCLKH
TCLK
tTCLKf
tTCLKL
Figure 2.70
tTCLKr
ETM TCLK timing
TCLK
tTRDS
tTRDH
tTRDS
tTRDH
TDATA[3:0]
Figure 2.71
ETM output timing
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 80 of 92
RA4M3 Datasheet
Appendix 1.
Appendix 1. Port States in Each Processing Mode
Port States in Each Processing Mode
Function
Pin function
Reset
Software Standby mode
Deep Software
Standby mode
Mode
MD
Pull-up
Keep-O
JTAG
TCK/TMS/TDI
Pull-up
Keep-O
TDO
output
IRQx
IRQx-DS
After Deep Software Standby
mode is canceled (return to
startup mode)
IOKEEP = 0
IOKEEP = 1*1
Keep
Hi-Z
Keep
Keep
Hi-Z
Keep
Keep-O
Keep
TDO output
Keep
Hi-Z
Keep-O*2
Keep
Hi-Z
Keep
Hi-Z
Keep-O*2
Keep*3
Hi-Z
Keep
AGTIOn
Hi-Z
Keep-O*2
Keep
Hi-Z
Keep
AGTIOn (n=1,3)
Hi-Z
Keep-O*2
Keep*3
Hi-Z
Keep
SCI
RXD0
Hi-Z
Keep-O*2
Keep
Hi-Z
Keep
IIC
SCLn/SDAn
Hi-Z
Keep-O*2
Keep
Hi-Z
Keep
USBFS
USB_OVRCURx
Hi-Z
Keep-O*2
Keep
Hi-Z
Keep
USB_OVRCURx-DS/
USB_VBUS
Hi-Z
Keep-O*2
Keep*3
Hi-Z
Keep
USB_DP/USB_DM
Hi-Z
Keep-O*4
Keep*3
Hi-Z
Keep
RTCICx
Hi-Z
Keep-O*2
Keep*3
Hi-Z
Keep
IRQ
AGT
RTC
RTCOUT
Hi-Z
[RTCOUT selected] RTCOUT output
Keep
Hi-Z
Keep
CLKOUT
CLKOUT
Hi-Z
[CLKOUT selected] CLKOUT output
Keep
Hi-Z
Keep
DAC
DAn
Hi-Z
[DAn output (DAOE = 1)] D/A output retained
Keep
Hi-Z
Keep
Others
—
Hi-Z
Keep-O
Keep
Hi-Z
Keep
Note:
Note 1.
Note 2.
Note 3.
Note 4.
H: High-level
L: Low-level
Hi-Z: High-impedance
Keep-O: Output pins retain their previous values. Input pins go to high-impedance.
Keep: Pin states are retained during periods in Software Standby mode.
Retains the I/O port state until the DPSBYCR.IOKEEP bit is cleared to 0.
Input is enabled if the pin is specified as the Software Standby canceling source while it is used as an external interrupt pin.
Input is enabled if the pin is specified as the Deep Software Standby canceling source.
Input is enabled while the pin is used as an input pin.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 81 of 92
RA4M3 Datasheet
Appendix 2.
Appendix 2. Package Dimensions
Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP144-20x20-0.50
PLQP0144KA-B
—
1.2
Unit: mm
HD
*1 D
108
73
*2
E
72
144
HE
109
37
1
36
NOTE 4
Index area
NOTE 3
F
S
*3
bp
0.25
A1
c
y S
A2
A
e
Lp
L1
Detail F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
M
Min
Nom
Max
D
19.9
20.0
20.1
20.1
E
19.9
20.0
A2
1.4
HD
21.8
22.0
22.2
HE
21.8
22.0
22.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2016 Renesas Electronics Corporation. All rights reserved.
Figure 2.1
LQFP 144-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 82 of 92
RA4M3 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
0.6
HD
Unit: mm
*1 D
75
51
*2
E
50
100
HE
76
26
1
25
NOTE 4
Index area
NOTE 3
F
S
0.25
*3
A1
c
A2
A
e
y S
Lp
L1
Detail F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
bp
M
Min
Nom
Max
D
13.9
14.0
14.1
14.1
E
13.9
14.0
A2
1.4
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.2
LQFP 100-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 83 of 92
RA4M3 Datasheet
Appendix 2. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
0
3.5
8
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 2.3
LQFP 64-pin
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 84 of 92
RA4M3 Datasheet
Appendix 3.
Appendix 3. I/O Registers
I/O Registers
This appendix describes I/O register address and access cycles by function.
3.1
Peripheral Base Addresses
This section provides the base addresses for peripherals described in this manual. Table 3.1 shows the name, description,
and the base address of each peripheral.
Table 3.1
Peripheral base address (1 of 3)
Name
Description
Base address
RMPU
Renesas Memory Protection Unit
0x4000_0000
TZF
TrustZone Filter
0x4000_0E00
SRAM
SRAM Control
0x4000_2000
BUS
BUS Control
0x4000_3000
DMAC0
Direct memory access controller 0
0x4000_5000
DMAC1
Direct memory access controller 1
0x4000_5040
DMAC2
Direct memory access controller 2
0x4000_5080
DMAC3
Direct memory access controller 3
0x4000_50C0
DMAC4
Direct memory access controller 4
0x4000_5100
DMAC5
Direct memory access controller 5
0x4000_5140
DMAC6
Direct memory access controller 6
0x4000_5180
DMAC7
Direct memory access controller 7
0x4000_51C0
DMA
DMAC Module Activation
0x4000_5200
DTC
Data Transfer Controller
0x4000_5400
ICU
Interrupt Controller
0x4000_6000
CACHE
CACHE
0x4000_7000
CPSCU
CPU System Security Control Unit
0x4000_8000
DBG
Debug Function
0x400_1B000
FCACHE
Flash Cache
0x400_1C100
SYSC
System Control
0x4001_E000
PORT0
Port 0 Control Registers
0x4008_0000
PORT1
Port 1 Control Registers
0x4008_0020
PORT2
Port 2 Control Registers
0x4008_0040
PORT3
Port 3 Control Registers
0x4008_0060
PORT4
Port 4 Control Registers
0x4008_0080
PORT5
Port 5 Control Registers
0x4008_00A0
PORT6
Port 6 Control Registers
0x4008_00C0
PORT7
Port 7 Control Registers
0x4008_00E0
PORT8
Port 8 Control Registers
0x4008_0100
PFS
Pmn Pin Function Control Register
0x4008_0800
ELC
Event Link Controller
0x4008_2000
RTC
Realtime Clock
0x4008_3000
IWDT
Independent Watchdog Timer
0x4008_3200
WDT
Watchdog Timer
0x4008_3400
CAC
Clock Frequency Accuracy Measurement Circuit
0x4008_3600
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 85 of 92
RA4M3 Datasheet
Table 3.1
Appendix 3. I/O Registers
Peripheral base address (2 of 3)
Name
Description
Base address
MSTP
Module Stop Control A, B, C, D
0x4008_4000
POEG
Port Output Enable Module for GPT
0x4008_A000
USBFS
USB 2.0 FS Module
0x4009_0000
SDHI0
SD Host Interface 0
0x4009_2000
SSIE0
Serial Sound Interface Enhanced (SSIE)
0x4009_D000
IIC0
Inter-Integrated Circuit 0
0x4009_F000
IIC0WU
Inter-Integrated Circuit 0 Wake-up Unit
0x4009_F014
IIC1
Inter-Integrated Circuit 1
0x4009_F100
CAN0
CAN0 Module
0x400A_8000
CAN1
CAN1 Module
0x400A_9000
CTSU
Capacitive Touch Sensing Unit
0x400D_0000
PSCU
Peripheral Security Control Unit
0x400E_0000
AGT0
Low Power Asynchronous General purpose Timer 0
0x400E_8000
AGT1
Low Power Asynchronous General purpose Timer 1
0x400E_8100
AGT2
Low Power Asynchronous General purpose Timer 2
0x400E_8200
AGT3
Low Power Asynchronous General purpose Timer 3
0x400E_8300
AGT4
Low Power Asynchronous General purpose Timer 4
0x400E_8400
AGT5
Low Power Asynchronous General purpose Timer 5
0x400E_8500
TSN
Temperature Sensor
0x400F_3000
CRC
CRC Calculator
0x4010_8000
DOC
Data Operation Circuit
0x4010_9000
SCI0
Serial Communication Interface 0
0x4011_8000
SCI1
Serial Communication Interface 1
0x4011_8100
SCI2
Serial Communication Interface 2
0x4011_8200
SCI3
Serial Communication Interface 3
0x4011_8300
SCI4
Serial Communication Interface 4
0x4011_8400
SCI9
Serial Communication Interface 9
0x4011_8900
SPI0
Serial Peripheral Interface 0
0x4011_A000
SCE9
Secure Cryptographic Engine
0x4016_1000
GPT320
General PWM 32-Bit Timer 0
0x4016_9000
GPT321
General PWM 32-Bit Timer 1
0x4016_9100
GPT322
General PWM 32-Bit Timer 2
0x4016_9200
GPT323
General PWM 32-Bit Timer 3
0x4016_9300
GPT164
General PWM 16-Bit Timer 4
0x4016_9400
GPT165
General PWM 16-Bit Timer 5
0x4016_9500
GPT166
General PWM 16-Bit Timer 6
0x4016_9600
GPT167
General PWM 16-Bit Timer 7
0x4016_9700
GPT_OPS
Output Phase Switching Controller
0x4016_9A00
ADC120
12bit A/D Converter 0
0x4017_0000
ADC121
12bit A/D Converter 1
0x4017_0200
DAC12
12-bit D/A converter
0x4017_1000
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 86 of 92
RA4M3 Datasheet
Table 3.1
Appendix 3. I/O Registers
Peripheral base address (3 of 3)
Name
Description
Base address
FLAD
Data Flash
0x407F_C000
FACI
Flash Application Command Interface
0x407F_E000
QSPI
Quad-SPI
0x6400_0000
Note:
Name = Peripheral name
Description = Peripheral functionality
Base address = Lowest reserved address or address used by the peripheral
3.2
Access Cycles
This section provides access cycle information for the I/O registers described in this manual.
● Registers are grouped by associated module.
● The number of access cycles indicates the number of cycles based on the specified reference clock.
● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations
cannot be guaranteed.
● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization
cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio
between ICLK and PCLK.
● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always
constant.
● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided
clock synchronization cycles.
● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access.
Note:
This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the
external memory or bus access from other bus masters such as DTC or DMAC.
Table 3.2
Access cycles (1 of 3)
Number of access cycles
Address
ICLK > PCLK*1
ICLK = PCLK
Peripherals
From
To
Read
Write
Read
Write
Cycle
Unit
RMPU, TZF,
SRAM, BUS,
DMACn, DMA,
DTC, ICU
0x4000_0000
0x4000_6FFF
4
3
4
3
ICLK
Renesas Memory
Protection Unit,
TrustZone Filter,
SRAM Control, BUS
Control, Direct
memory access
controller n, DMAC
Module Activation,
DTC Control Register,
Interrupt Controller
CACHE
0x4000_7000
0x4000_7FFF
3
5
3
5
ICLK
CACHE
CPSCU, DBG,
FCACHE
0x4000_8000
0x4001_CFFF
4
3
4
3
ICLK
CPU System Security
Control Unit, Debug
Function, Flash Cache
SYSC
0x4001_E000
0x4001_E3FF
5
4
5
4
ICLK
System Control
SYSC
0x4001_E400
0x4001_E5FF
9
8
5 to 8
5 to 8
PCLKB
System Control
PORTn, PFS
0x4008_0000
0x4008_0FFF
5
4
2 to 5
2 to 4
PCLKB
Port n Control
Registers, Pmn Pin
Function Control
Register
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Related function
Page 87 of 92
RA4M3 Datasheet
Table 3.2
Appendix 3. I/O Registers
Access cycles (2 of 3)
Number of access cycles
Address
ICLK > PCLK*1
ICLK = PCLK
Peripherals
From
To
Read
Write
Read
Write
Cycle
Unit
ELC, RTC, IWDT,
WDT, CAC
0x4008_2000
0x4008_3FFF
5
4
3 to 5
2 to 4
PCLKB
Event Link Controller,
Realtime Clock,
Independent
Watchdog Timer,
Watchdog Timer,
Clock Frequency
Accuracy
Measurement Circuit
MSTP
0x4008_4000
0x4008_4FFF
5
4
2 to 5
2 to 4
PCLKB
Module Stop Control
POEG
0x4008_A000
0x4008_AFFF
5
4
3 to 5
2 to 4
PCLKB
Port Output Enable
Module for GPT
USBFS
0x4009_0000
0x4009_3FFF
6
5
3 to 6
3 to 5
PCLKB
USB 2.0 FS Module
USBFS
0x4009_4000
0x4009_4FFF
4
3
1 to 4
1 to 3
PCLKB
USB 2.0 FS Module
SDHI0, SSIE0,
IICn, IIC0WU
0x4009_2000
0x4009_FFFF
5
4
2 to 5
2 to 4
PCLKB
SD Host Interface 0,
Serial Sound Interface
Enhanced, InterIntegrated Circuit n,
Inter-Integrated Circuit
0 Wake-up Unit
CANn
0x400A_8000
0x400A_9FFF
5
4
2 to 5
2 to 4
PCLKB
CANn Module
CTSU
0x400D_0000
0x400D_FFFF
4
3
1 to 4
1 to 3
PCLKB
Capacitive Touch
Sensing Unit
PSCU
0x400E_0000
0x400E_0FFF
5
4
2 to 5
2 to 4
PCLKB
Peripheral Security
Control Unit
AGTn
0x400E_8000
0x400E_8FFF
7
4
5 to 7
2 to 4
PCLKB
Low Power
Asynchronous
General purpose
Timer n
TSN
0x400F_3000
0x400F_3FFF
5
4
2 to 5
2 to 4
PCLKB
Temperature Sensor
CRC, DOC
0x4010_8000
0x4010_9FFF
5
4
2 to 5
2 to 4
PCLKA
CRC Calculator, Data
Operation Circuit
SCIn
0x4011_8000
0x4011_8FFF
5*2
4*2
2 to 5*2
2 to 4*2
PCLKA
Serial Communication
Interface n
SPIn
0x4011_A000
0x4011_AFFF
5*3
4*3
2 to 5*3
2 to 4*3
PCLKA
Serial Peripheral
Interface n
SCE9
0x4016_1000
0x4016_1FFF
6
4
3 to 6
2 to 4
PCLKA
Secure Cryptographic
Engine
GPT32n, GPT16n, 0x4016_9000
GPT_OPS
0x4016_9FFF
7
4
4 to 7
2 to 4
PCLKA
General PWM 32-Bit
Timer n, General
PWM 16-Bit Timer n,
Output Phase
Switching Controller
ADC12n, DAC12
0x4017_0000
0x4017_2FFF
5
4
2 to 5
2 to 4
PCLKA
12bit A/D Converter n,
12-bit D/A converter
QSPI
0x6400_0000
0x6400_000F
5
14 to *4
2 to 5
14 to *4
PCLKA
Quad-SPI
QSPI
0x6400_0010
0x6400_0013
25 to *4
6 to *4
25 to *4
5 to *4
PCLKA
Quad-SPI
QSPI
0x6400_0014
0x6400_0037
5
14 to
PCLKA
Quad-SPI
QSPI
0x6400_0804
0x6400_0807
4
3
PCLKA
Quad-SPI
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
*4
2 to 5
14 to
1 to 4
1 to 3
*4
Related function
Page 88 of 92
RA4M3 Datasheet
Table 3.2
Appendix 3. I/O Registers
Access cycles (3 of 3)
Number of access cycles
Address
ICLK > FCLK*1
ICLK = FCLK
Peripherals
From
To
Read
Write
Read
Write
Cycle
Unit
FLAD, FACI
0x407F_C000
0x407F_EFFF
5
4
2 to 5
2 to 4
FCLK
Related function
Data Flash, Flash
Application Command
Interface
Note 1. If the number of PCLK or FCLK cycles is non-integer (for example 1.5), the minimum value is without the decimal point, and the
maximum value is rounded up to the decimal point. For example, 1.5 to 2. 5 is 1 to 3.
Note 2. When accessing a 16-bit register (FTDRHL, FRDRHL, FCR, FDR, LSR, and CDR), access is 2 cycles more than the value shown in
Table 3.2. When accessing an 8-bit register (including FTDRH, FTDRL, FRDRH, and FRDRL), the access cycles are as shown in
Table 3.2.
Note 3. When accessing the 32-bit register (SPDR), access is 2 cycles more than the value in Table 3.2. When accessing an 8-bit or 16-bit
register (SPDR_HA), the access cycles are as shown in Table 3.2.
Note 4. The access cycles depend on the QSPI bus cycles.
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 89 of 92
RA4M3 Datasheet
Revision History
Revision History
Revision 1.20 — December 2, 2020
First edition, issued
R01DS0368EJ0120 Rev.1.20
Dec 2, 2020
Page 90 of 92
General Precautions in the Handling of Microprocessing Unit and Microcontroller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1.
Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
2.
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
3.
level at which resetting is specified.
Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
4.
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
5.
become possible.
Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
6.
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
7.
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
8.
addresses as the correct operation of the LSI is not guaranteed.
Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product.
Notice
1.
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(Note1)
(Note2)
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subsidiaries.
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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