RD151TS3313ARPH0

RD151TS3313ARP, RD151TS3323ARP Spread Spectrum Clock for EMI Solution REJ03D0794-0100 Rev.1.00 May 11, 2006 Description RD151TS3313ARP and RD151TS3323ARP is a high-performance Spread Spectrum Clock generator. It is suitable for EMI solution of electric systems. Features • Supports 20 MHz to 40 MHz operations. Multiple rate (XIN: SSCOUT) = 1: 1 Input frequency 20 MHz to 40 MHz • Spread spectrum modulation ; RD151TS3313ARP : ±1.5%, ±0.5% (Central spread modulation) RD151TS3323ARP : –3.0%, –1.0% (Down spread modulation) Key Specifications • • • • • Supply voltages: VDD = 3.3 V ±0.3 V Cycle to cycle jitter = ±100 ps typ. Clock output duty cycle = 50 ±5% Output slew rate = 0.7 V/ns typ. Ordering Information Part Name Package Type SOP-8 pin (JEDEC) Package Code (Previous Code) PRSP0008DD-C (FP-8DCV) RP Package Abbreviation Taping Abbreviation (Quantity) H (2,500 pcs / Reel) RD151TS3313ARPH0 RD151TS3323ARPH0 Block Diagram VDD GND NC XIN R = 1 MΩ XOUT OSC 1/M Synthesizer 1/N SSC Modulator SSCOUT SEL R = 350 kΩ R = 350 kΩ Mode Control SSN Rev.1.00 May 11, 2006 page 1 of 8 RD151TS3313ARP, RD151TS3323ARP Pin Arrangement XIN 1 8 VDD XOUT 2 7 SEL NC 3 6 SSCOUT SSN 4 5 GND (Top view) Pin Descriptions Pin name GND VDD NC SSCOUT XIN XOUT SEL SSN No. 5 8 3 6 1 2 7 4 Type Ground Power NC Output Input Output Input Input Description GND pin Power supply pin. Don’t connect any VDD or GND. Spread spectrum modulated clock output. Oscillator input. Oscillator output. SSC% mode select pin. LVCMOS level input. Pull-down by internal resistor (350 kΩ). SSC ON/OFF select pin. LVCMOS level input. Pull–down by internal resistor (350 kΩ). SSC Function Table STB 0 0 1 1 Note: SEL 0 1 0 1 RD151TS3313ARP(Central spread) ±1.5%*1 ±0.5% OFF RD151TS3323ARP(Down spread) –3.0%*1 –1.0% OFF 1. ±1.5% (TS3313ARP) / -3.0%(TS3323ARP) SSC is selected for default by internal pull-down resistors. Clock Frequency Table PRODUCT RD151TS3313ARP RD151TS3323ARP XIN(MHz) 20 to 40 20 to 40 SSCOUT(MHz) 20 to 40 20 to 40 Multiply rate (XIN: SSCOUT) 1:1 1:1 Rev.1.00 May 11, 2006 page 2 of 8 RD151TS3313ARP, RD151TS3323ARP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation Storage temperature Symbol VDD VI VO IIK IOK IO Tstg Ratings –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDD+0.5 –50 –50 ±50 0.7 –65 to +150 Unit V V V mA mA mA W °C Conditions VI < 0 VO < 0 VO = 0 to VDD Ta = 55°C (in still air) Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Supply voltage DC input signal voltage High level input voltage Low level input voltage Input clock duty cycle Operating temperature Symbol VDD VIH VIL Ta Min 3.0 –0.3 0.7×VDD –0.3 45 –20 Typ 3.3 — — — 50 — Max 3.6 VDD+0.3 VDD+0.3 0.3×VDD 55 85 Unit V V V V % °C Conditions DC Electrical Characteristics Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V Item Input current Symbol II Min — — Input capacitance CI — Typ — — 3 Max ±20 ±100 — pF Unit µA Test Conditions VI = 0 V or 3.6 V, VDD = 3.6 V, XIN pin VI = 0 V or 3.6 V, VDD = 3.6 V, SEL, SSN pins SEL, SSN pins DC Electrical Characteristics / SSC Clock Output Ta = –20 to 85 °C, VDD = 3.0 to 3.6 V Item Output voltage Output current Output impedance Symbol VOH VOL IOH IOL Min VDD–0.2 — — — — Typ — — –13 13 40 Max — 200 — — — Unit V mV mA Ω Test Conditions IOH = –1 mA IOL = 1 mA VOH = 1.5 V, VDD = 3.3 V VOL = 1.5 V, VDD = 3.3 V Note: Parameters are target of design. Not 100% tested in production. Rev.1.00 May 11, 2006 page 3 of 8 RD151TS3313ARP, RD151TS3323ARP AC Electrical Characteristics / SSC Clock Output Ta = 25°C, VDD = 3.3 V, CL = 15 pF Item Operating current Cycle to cycle jitter *1 Symbol IDD tCCS Min — — Typ 14 |100| Max 19 — Unit mA ps Test Conditions VDD = 3.3 V, CL = 15 pF, XIN = 40 MHz SEL = 0, CL = 0 pF SSC = ±1.5% (TS3313ARP) SSC = -3.0% (TS3323ARP) VDD = 3.3 V, 0.2 × VDD to 0.8 × VDD Notes Figure 1 Slew rate tSL — 0.7 4.0 V/ns Clock duty cycle 45 50 55 % Stabilization time *2 — — 2 ms Notes: Parameters are target of design. Not 100% tested in production. 1. Cycle to cycle jitter is included spread spectrum modulation. 2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up. SSCOUT tcycle n tcycle n+1 tCCS = (tcycle n) – (tcycle n+1) Figure 1 Cycle to cycle jitter Rev.1.00 May 11, 2006 page 4 of 8 RD151TS3313ARP, RD151TS3323ARP Application Information 1. Recommended Circuit Configuration The power supply circuit of the optimal performance on the application of a system should refer to Figure 2. VDD decoupling is important to both reduce Jitter and EMI radiation. The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. XIN (Crystal or Reference input) XOUT (Crystal or Not connection) NC 1 8 C1 C2 VDD 2 7 SEL R1 GND GND 3 6 SSCOUT SSN 4 5 GND Notes: C1 = High frequency supply decoupling capacitor. (0.1 µF recommended) C2 = Low frequency supply decoupling capacitor. (22 µF recommended) R1 = Match value to line impedance. Figure 2 Recommended circuit configuration Rev.1.00 May 11, 2006 page 5 of 8 RD151TS3313ARP, RD151TS3323ARP 2. Example Board Layout Configuration VDD (+3.3V Supply) P FB 22 µF G 0.1 µF Crystal connection or Reference input Crystal connection or No connection 1 G 2 7 R1 3 6 SSCOUT 4 5 G Note: G Via to GND plane R1 = Match value to line impedance. FB = Ferrite bead. Figure 3 Example Board Layout Rev.1.00 May 11, 2006 page 6 of 8 RD151TS3313ARP, RD151TS3323ARP 3. Example of TS33XX EMI Solution IC’s Application Spread Spectrum Modulated Clock XIN XOUT TS33XXA SSCOUT CPU & ASIC XTAL Memory Graphics System Cont. Ref. Clock 3.3 V CMOS level ref. Clock Figure 4 Ref. Clock Input Example Spread Spectrum Modulated Clock XIN XTAL XOUT TS33XXA SSCOUT CPU & ASIC Memory Graphics System Cont. Figure 5 XTAL Ref. Clock Input Example Rev.1.00 May 11, 2006 page 7 of 8 System BUS System BUS RD151TS3313ARP, RD151TS3323ARP Package Dimensions JEITA Package Code P-SOP8-3.95x4.9-1.27 RENESAS Code PRSP0008DD-C Previous Code FP-8DCV MASS[Typ.] 0.085g *1 D 5 F 8 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E *2 Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z e 4 *3 c Reference Dimension in Millimeters Symbol bp x M L1 θ A1 L y Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 4.90 5.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.10 0.75 0.40 0.60 1.27 1.08 Rev.1.00 May 11, 2006 page 8 of 8 A Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .6.0