RD74LVC1G240WPE

RD74LVC1G240 Bus Buffer Inverted with 3–state Output REJ03D0733–0100 Rev.1.00 Apr 13, 2006 Description The RD74LVC1G240 has bus buffer inverted with 3–state output in a 5-pin package. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • • • • • • The basic gate function is lined up as renesas uni logic series. Supply voltage range: 1.65 to 5.5 V Operating temperature range: –40 to +85°C All inputs: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs: VO (Max.) = 5.5 V (@VCC = 0 V) Output current: ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±24 mA (@VCC = 3.0 V) ±32 mA (@VCC = 4.5 V) • Ordering Information Part Name RD74LVC1G240WPE Package Type WCSP–5 pin Package Code (Previous Code) (Previous SXBG0005LB–A (TBS–5CV) (TBS–5CV) Package Abbreviation WP Taping Abbreviation (Quantity) E (3,000 pcs/reel) Article Indication Marking Year code Month code EHYM Rev.1.00 Apr 13, 2006 page 1 of 7 RD74LVC1G240 Function Table Inputs OE L L H H: High level L: Low level X: Immaterial Z: High impedance A L H X Output Y H L Z Pin Arrangement 0.7 mm Height 0.4 mm 0.4 mm pitch 0.17 mm 5–Ball (WP) GND 3 4 Y A 2 1.1 mm Pin#1 INDEX OE 1 5 VCC (Bottom (Bottom view) (Top view) Logic Diagram OE A 1 2 4 Y Rev.1.00 Apr 13, 2006 page 2 of 7 RD74LVC1G240 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Symbol VCC VI VO IIK IOK IO ICC or IGND θja Tstg Ratings –0.5 to 6.5 –0.5 to 6.5 –0.5 to VCC +0.5 –0.5 to 6.5 –50 –50 ±50 ±100 200 –65 to 150 Unit V V V mA mA mA mA °C/W °C WP Test Conditions Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Package Thermal impedance Storage temperature Notes: Output : H or L VCC: OFF or Output “Z” VI < 0 VO < 0 VO = 0 to VCC The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are ngs output observed. 2. This value is limited to 5.5 V maximum. Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOL Min 1.65 0 0 0 — — — — — IOH — — — — — Input transition rise or fall rate ∆t / ∆v 0 0 0 Operating free-air temperature Ta –40 Note: Unused or floating inputs must be held high or low. Max 5.5 5.5 VCC 5.5 4 8 16 16 24 32 –4 –8 –16 –24 –32 20 10 5 85 °C ns / V VCC = 4.5 V VCC = 1.65 to 1.95 V, 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V mA Unit V V V Output : Z VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V Conditions Rev.1.00 Apr 13, 2006 page 3 of 7 RD74LVC1G240 Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VCC (V) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Output voltage VOH Min to Max 1.65 2.3 3.0 4.5 VOL Min to Max 1.65 1.65 2.3 3.0 4.5 Input current Off state Output current Quiescent supply current IIN IOZ ICC ∆ICC Output leakage current Input capacitance IOFF CIN 0 to 5.5 3.6 1.65 to 5.5 3 to 5.5 0 3.3 Min 1.7 2.0 VCC×0.7 — — — — VCC–0.1 1.2 1.9 2.4 2.3 3.8 — — — — — — — — — — — — Typ — — — — — — — — — — — — — — — — — — — — — — — — — 3.5 Max — — — — VCC×0.35 0.7 0.8 VCC×0.3 — — — — — — 0.1 0.45 0.3 0.4 0.55 0.55 ±5 10 10 500 ±10 — µA pF µA µA µA V IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –16 mA IOH = –24 mA IOH = –32 mA IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA VIN = 5.5 V or GND VO = 5.5 V or GND VIN = VCC or GND, IO = 0 One input at VCC–0.6 V, Other input at VCC or GND VIN or VO = 0 to 5.5 V VIN = VCC or GND Unit V Test condition 1.65 to 1.95 VCC×0.65 Note: Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.1.00 Apr 13, 2006 page 4 of 7 RD74LVC1G240 Switching Characteristics VCC = 1.8±0.15 V Ta = –40 to 85°C Item Propagation delay time Output enable time Output disable time Symbol tPLH tPHL tZH tZL tHZ tLZ Min 3.0 3.8 2.1 Max 8.0 9.4 9.4 Unit ns ns ns Test Conditions CL = 30 pF, RL = 1.0 kΩ A OE OE FROM (Input) Y Y Y TO (Output) VCC = 2.5±0.2 V Ta = –40 to 85°C Item Propagation delay time Output enable time Output disable time Symbol tPLH tPHL tZH tZL tHZ tLZ Min 1.4 2.1 1.0 1.0 Max 5.5 6.5 4.9 Unit ns ns ns Test Conditions CL = 30 pF, RL = 500 Ω A OE OE FROM (Input) Y Y Y TO (Output) VCC = 3.3±0.3 V Ta Ta = –40 to 85°C Item Propagation delay time Output enable time Output disable time Symbol tPLH tPHL tZH tZL tHZ tLZ Min Min 1.1 1.1 1.4 1.4 Max 4.5 5.4 5.2 Unit Unit ns ns ns Test Conditions CL = 50 pF, RL = 500 Ω A OE OE FROM (Input) Y Y Y TO (Output) VCC = 5.0±0.5 V Ta Ta = –40 to 85°C Item Propagation delay time Output enable time Output disable time Symbol Symbol tPLH tPHL tZH tZL tHZ tLZ Min Min 1.0 1.1 1.0 Max 4.0 5.2 4.1 Unit ns ns ns Test Conditions CL = 50 pF, RL = 500 Ω A OE OE FROM (Input) Y Y Y TO (Output) Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCC (V) 1.8 2.5 3.3 5.0 Min — — — — Typ 19 19 20 22 Max — — — — Unit pF Test Conditions f = 10 MHz Rev.1.00 Apr 13, 2006 page 5 of 7 RD74LVC1G240 Test Circuit VTT RL S1 OPEN CL Load circuit INPUTS VCC (V) 1.8±0.15 2.5±0.2 3.3±0.3 5.0±0.5 VI VCC VCC VCC VCC tr / tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns Vref VCC / 2 VCC / 2 1.5 V VCC / 2 VTT 2 × VCC 2 × VCC 6V 2 × VCC CL 30 pF 30 pF 50 pF 50 pF RL 1.0 kΩ 500 Ω 500 Ω 500 Ω RL GND TEST t PLH / tPHL t ZH / t HZ t ZL / t LZ S1 OPEN GND VTT From Output ∆V 0.15 V 0.15 V 0.3 V 0.3 V VI Input A Vref t PHL Vref t PLH 0V V OH Output Y Vref Vref V OL VI Input OE Vref t ZL Vref t LZ 0V VOH Output Y (Waveform – A) Vref VOL + ∆V t ZH t HZ VOH – ∆V V OL V OH Output Y (Waveform – B) Vref VOL Notes: 1. CL includes probe and jig capacitance. 2. Waveform–A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform–B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Zo = 50 Ω. 5. The output are measured one at a time with one transition per measurement. Rev.1.00 Apr 13, 2006 page 6 of 7 RD74LVC1G240 Package Dimensions JEITA Package Code S-XFBGA5-0.7x1.1-0.40 RENESAS Code SXBG0005LB-A Previous Code TBS-5CV MASS[Typ.] 0.001g D ZD e C ZE B E B e A 1 Pin#1 index area y1 C 2 A 5×φb φx M C A B φx M C Reference Symbol Dimension in Millimeters Min Nom Max 0.40 0.110 0.140 (0.235) * 0.15 0.70 1.10 0.40 0.05 0.05 0.19 C Seating plane A1 A2 A A1 A2 b yC *Reference value. A D E e x y y 1 0.20 0.15 0.15 ZD ZE Rev.1.00 Apr 13, 2006 page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's Technology Corp. or a third party. application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas T 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of i improvements publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvement or other reasons. It is distributor for the latest product therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distrib information before purchasing a product listed herein. The The information described here may contain technical inaccuracies or typographical errors. Renesas or Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please Technology Corp. Semiconductor Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Techn home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to and evaluate evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life ci is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a aerospace, nuclear, or undersea repeater product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. materi 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and lic cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Any 8. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .6.0