RD74LVC74BFPEL

RD74LVC74B Dual D-type Flip Flops with Preset and Clear REJ03D0324–0100Z Rev.1.00 Jun. 22, 2004 Description The RD74LVC74B has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features VCC = 1.65 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±12 mA (@VCC = 2.7 V) ±24 mA (@VCC = 3.0 V to 5.5 V) • Ordering Information Part Name RD74LVC74BFPEL RD74LVC74BTELL Package Type SOP–14 pin (JEITA) TSSOP–14 pin Package Code FP–14DAV TTP–14DV FP T Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs / reel) ELL (2,000 pcs / reel) • • • • • Function Table Inputs PR L H L H H H H H H: L: X: ↓: ↑: Q0 : Note: H L L H H H H H CLR X X X ↑ ↑ L H ↓ CK X X X H L X X X D H L H*1 H L Q0 Q0 Q0 Q L H H*1 L H Q0 Q0 Q0 Outputs Q High level Low level Immaterial High to Low transition Low to high transition Level to Q before the indicated steady input conditions were established. 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously. Rev.1.00 Jun. 22, 2004 page 1 of 8 RD74LVC74B Pin Arrangement 1CLR 1 1D 2 1CK 3 1PR 4 1Q 5 1Q 6 GND 7 D CK CK D PR CLR Q Q 14 VCC 13 2CLR 12 2D 11 2CK 10 2PR 9 2Q 8 2Q CLR PR Q Q (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg –0.5 to 7.0 –50 –0.5 to 7.0 –50 50 –0.5 to VCC +0.5 ±50 100 –65 to +150 V mA mA °C Ratings V mA V mA VO = –0.5 V VO = VCC +0.5 V VI = –0.5 V Unit Conditions Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.1.00 Jun. 22, 2004 page 2 of 8 RD74LVC74B Recommended Operating Conditions Item Supply voltage Input / output voltage Operating temperature Output current Symbol VCC VI VO Ta IOH Ratings 1.5 to 5.5 1.65 to 5.5 0 to 5.5 0 to VCC –40 to 85 –4 –8 –12 –24 IOL 4 8 12 24 Input rise / fall time *1 tr, tf 20 10 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. ns/V mA °C mA VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 1.65 V to 2.7 V VCC = 3.0 V to 5.5 V V V Unit Conditions Data retention At operation PR, CLR, CK, D Q, Q Rev.1.00 Jun. 22, 2004 page 3 of 8 RD74LVC74B Electrical Characteristics Ta = –40 to 85°C Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 Output voltage VOH 1.65 to 5.5 1.65 2.3 2.7 3.0 3.0 4.5 VOL 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 Input current IIN 0 to 5.5 2.7 to 3.6 2.7 to 5.5 ∆ICC 2.7 to 3.6 Quiescent supply current ICC 1.7 2.0 VCC×0.7 — — — — VCC –0.2 1.2 1.7 2.2 2.4 2.2 3.8 — — — — — — — — — — Min VCC×0.65 — — — — VCC×0.35 V 0.7 0.8 VCC×0.3 — — — — — — — 0.2 0.45 0.7 0.4 0.55 0.55 ±5.0 ±5.0 5.0 500 µA µA µA VIN = 5.5 V or GND VIN = 3.6 V to 5.5 V VIN = VCC or GND VIN = one input at (VCC –0.6)V, other inputs at VCC or GND V IOL = 100 µA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOH = –24 mA V IOH = –100 µA IOH = –4 mA IOH = –8 mA IOH = –12 mA Max V Unit Test Conditions Rev.1.00 Jun. 22, 2004 page 4 of 8 RD74LVC74B Switching Characteristics Item Maximum clock frequency Symbol fmax VCC (V) 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 1.8±0.15 2.5±0.2 2.7 3.3±0.3 5.0±0.5 3.3 Ta = –40 to 85°C Min Typ Max — — 83 — — 83 — — 150 — — 150 — — 150 1.0 — 13.4 1.0 — 7.1 1.0 — 6.0 1.0 — 5.2 1.0 — 4.1 1.0 — 14.4 1.0 — 7.7 1.0 — 6.0 1.0 — 5.2 1.0 — 4.4 1.0 — 12.9 1.0 — 7.0 1.0 — 6.0 1.0 — 5.4 1.0 — 4.1 3.6 — — 2.3 — — 3.4 — — 3.0 — — 3.0 — — 2.7 — — 1.9 — — 2.2 — — 2.0 — — 2.0 — — 1.0 — — 1.0 — — 1.0 — — 0.0 — — 0.0 — — 4.1 — — 3.3 — — 3.3 — — 3.3 — — 3.3 — — — — — — — — — — — — — 1.0 — — 1.0 — 4.0 — Unit MHz From (Input) To (Output) Propagation delay time tPLH tPHL ns CK Q tPLH tPHL ns CK Q tPLH tPHL ns PR or CLR Q, Q Setup time tsu ns Data tsu ns PR or CLR Hold time th ns Pulse width tw ns CK, PR, CLR Output skew between pins*1 tOSLH tOSHL ns Input capacitance Note: CIN pF 1. This parameter is characterized but not tested. tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn| Rev.1.00 Jun. 22, 2004 page 5 of 8 RD74LVC74B Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol CPD VCC = (V) 1.8 2.5 3.3 5.0 Min — — — — Typ 34 34 36 40 Max — — — — Unit pF Test Conditions f = 10 MHz Test Circuit Input VCC Zout = 50 Ω Input See Function Table Pulse Generator PR D Q CL RL Output Q Pulse Generator Zout = 50 Ω CK CLR Q CL RL Output Q Notes: 1. CL includes probe and jig capacitance. 2. Test is put into the each flip flops. Rev.1.00 Jun. 22, 2004 page 6 of 8 RD74LVC74B Waveforms tf Input CLR 90 % Vref 10 % tw tf 90 % Input PR t su tr Input CK 90 % Vref 10 % tf 90 % Vref 10 % t w (H) Vref t w (L) Vref Vref Vref tr 90 % Vref 10 % 10 % tw t SU VIH Vref GND t h (H) t s (L) t h (L) VIH Vref Vref GND t PHL Vref t PLH VOH Output Q Vref Vref Vref VOL t PLH Output Q Vref t PHL Vref t PLH Vref t PHL VOH Vref VOL INPUTS Vcc (V) Vcc = 1.8±0.15 V Vcc = 2.5±0.2 V Vcc = 2.7 V Vcc = 3.3±0.3 V Vcc = 5.0±0.5 V VIH Vcc Vcc tr / tf Vref CL RL ≤ 2 ns 1/2 Vcc 30 pF 1.0 kΩ ≤ 2 ns 1/2 Vcc 30 pF 500 Ω 1.5 V 1.5 V 50 pF 500 Ω 50 pF 500 Ω VIH GND tr 90 % Vref 10 % VIH GND t s (H) Input D 90 % Vref 10 % tr t PHL 90 % Vref 10 % tf t PLH 2.7 V ≤ 2.5 ns 2.7 V ≤ 2.5 ns Vcc ≤ 2.5 ns 1/2 Vcc 50 pF 500 Ω Notes: 1. Clock pulse Input waveform: PRR = 10 MHz, duty cycle 50%. 2. Data input waveform: PRR = 5 MHz, duty cycle 50%. Rev.1.00 Jun. 22, 2004 page 7 of 8 RD74LVC74B Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 14 8 1 7 5.5 *0.20 ± 0.05 2.20 Max 0.20 7.80 + 0.30 – 1.42 Max 1.15 0˚ – 8˚ 0.70 ± 0.20 1.27 *0.40 ± 0.06 0.12 M Package Code JEDEC JEITA Mass (reference value) FP-14DAV — Conforms 0.23 g *Ni/Pd/Au plating 0.10 ± 0.10 0.15 As of January, 2003 Unit: mm 5.00 5.30 Max 14 8 1 7 0.65 1.0 0.13 M 6.40 ± 0.20 0.83 Max 0˚ – 8˚ 0.50 ± 0.10 *0.20 ± 0.05 4.40 *0.15 ± 0.05 1.10 Max 0.10 0.07 +0.03 –0.04 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-14DV — — 0.05 g Rev.1.00 Jun. 22, 2004 page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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