SH7017

REJ09B0398-0500 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7014, SH7016, SH7017F-ZTAT TM TM Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine family/SH7010 Series SH7014 SH7016 SH7017 HD6417014F28 HD6417014RF28 HD6437016F28 HD64F7017F28 Rev.5.00 Revision date: Sep. 27, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.5.00 Sep. 27, 2007 Page ii of xxxiv REJ09B0398-0500 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.5.00 Sep. 27, 2007 Page iii of xxxiv REJ09B0398-0500 Rev.5.00 Sep. 27, 2007 Page iv of xxxiv REJ09B0398-0500 Preface The SH7014/16/17 CMOS single-chip microprocessors integrate a Renesas Technology-original architecture, high-speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In particular, this LSI has a 1-kbyte on-chip cache, which allows an improvement in CPU performance during external memory access. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. Memory or peripheral LSIs can be connected efficiently with an external memory access support function. This greatly reduces system cost. This LSI has an F-ZTAT™ version with on-chip flash memory and a mask ROM version. These versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. This hardware manual covers the SH7014/16/17/. For a detailed description of instructions, refer to the programming manual. Related Manuals SH7014/16/17 instruction execution: SH-1/SH-2/SH-DSP Software Manual For information on development systems, please contact a Renesas Technology sales representative. Rev.5.00 Sep. 27, 2007 Page v of xxxiv REJ09B0398-0500 Rev.5.00 Sep. 27, 2007 Page vi of xxxiv REJ09B0398-0500 Main Revisions for This Edition Item All Page — Revision (See Manual for Details) Company name and brand names amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. Description of DTC deleted 1.2 Block Diagram Figure 1.1 Block Diagram of the SH7014 6 Figure amended PA15/CK RD WRH WRL CS1 CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3/RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18 PB5/IRQ3/RDWR PB4/IRQ2/CASH PB3/IRQ1/CASL PB2/IRQ0/RAS A17 A16 RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLCAP PLLVSS VCC RAM (3 kB)/ cache (1 kB) PLL PLLVCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS CPU Direct memory access controller Interrupt controller Bus state controller A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Serial communication interface (×2 channels) Compare match timer (×2 channels) Multifunction timer/ pulse unit A/D converter Watchdog timer PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 : Peripheral address bus : Peripheral data bus : Internal address bus : Internal upper data bus : Internal lower data bus Figure 1.2 Block 7 Diagram of the SH7016, SH7017 Note amended Note: * VCC in the SH7016, FWP in the SH7017 (except FWE pin in the programmer mode). Rev.5.00 Sep. 27, 2007 Page vii of xxxiv REJ09B0398-0500 PE15/DACK1 PE14/DACK0/AH PE13 PE12 PE11 PE10 PE9 PE8 PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE3/TIOC0D/DRAK1 PE2/TIOC0C/DREQ1 PE1/TIOC0B/DRAK0 PE0/TIOC0A/DREQ0 Item Figure 1.4 SH7016, SH7017 Pin Arrangement (FP-112 Top View) 5.3.1 Address Error Sources Table 5.5 Bus Cycles and Address Errors Page Revision (See Manual for Details) Note amended Note: * VCC in the SH7016, FWP in the SH7017 (except FWE pin in the programmer mode). 1.3.1 Pin Arrangement 9 64 Title added and table amended Bus Cycle Type Bus Master Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Instruction fetched from external memory space when in single chip mode Address Errors None (normal) Address error occurs None (normal) Address error occurs Address error occurs Instruction CPU fetch 5.4.1 Interrupt Sources 65 Title added and description amended Table 5.6 shows the sources that start up interrupt exception processing. These are divided into NMI, IRQ and on-chip peripheral modules. 6.3.1 Interrupt Priority 82 Registers A to H (IPRA to IPRH) 8.1.3 Pin Configuration 103 Table 8.1 Pin Configuration Description amended IPRA to IPRH are initialized to H'0000 by a power-on reset They are not initialized in standby mode. Table amended Signal WRH WRL I/O O O Description Strobe that indicates a write cycle to the higher byte (D15 to D8) for ordinary space/multiplex I/O. Also output during DRAM access. Strobe that indicates a write cycle to the lower byte (D7 to D0) for ordinary space/multiplex I/O. Also output during DRAM access. . 8.1.5 Address Map Table 8.3 Address Map • In on-chip ROM enabled mode 105 Table amdended Addresss H'00000000 to H'0001FFF* 4 8.2.1 Bus Control Register 1 (BCR1) Bit 0⎯CS0 Space Size Specification (A0SZ) 108 Note added Note: A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode, the CS0 space bus size is specified by the mode pin. Rev.5.00 Sep. 27, 2007 Page viii of xxxiv REJ09B0398-0500 Item Page Revision (See Manual for Details) Description amended DCR is a 16-bit read/write register that selects the number of waits, operation mode, number of address multiplex shifts and the like for DRAM control. After a power-on reset, write the initial values to the bits in DCR and do not change the values afterward. Do not perform any DRAM space accesses before DCR initial settings are completed. 8.2.5 DRAM Area 115 Control Register (DCR) 9.1.1 Features 147 Description amended • Transfer requests: There are three DMAC transfer activation requests, as indicated below. ⎯ External request: From two DREQ pins. DREQ can be detected either by falling edge or by low level. These can be received by all channels. 9.2.3 DMA Transfer 153 Count Registers 0, 1 (DMATCR0, DMATCR1) Description amended … Specifying a H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 65,536 transfers. While DMAC is in operation, the number of transfers to be performed is indicated. The initial value after power-on resets or in software standby mode is undefined. Upper sixteen bits of this register are read as 0 and the write value should always be 0. 9.3.5 Number of Bus 176 Cycle States and DREQ Pin Sample Timing Cycle Steal Mode Operations: Figure 9.12 Cycle Steal, Single Address and Level Detection (Normal Operation) Burst Mode, Single Address, and Edge Detection: 185 Note added Note: With cycle-steal and single address operation, sampling timing is the same whether DREQ detection is by level or by edge. Description amended …During this period, data is undefined, and DACK is not output. Nor is the number of DMAC transfers counted. The actual DMAC transfer begins after one dummy bus cycle output. Thereafter, DMAC transfer continues until the data transfer count set in the DMATCR has ended. ... Rev.5.00 Sep. 27, 2007 Page ix of xxxiv REJ09B0398-0500 Item 9.3.6 DMA Transfer Ending Conditions Conditions for Ending All Channels Simultaneously: Page 187 Revision (See Manual for Details) Description amended When the processing of a one unit transfer is complete. In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and DMATCR values are updated. Description amended In this example, an external request, single address mode transfer with external memory as the transfer source and an external device with DACK as the transfer destination is executed using DMAC channel 1. Description amended ⎯ PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, up to seven-phase PWM output is enabled (with channels 0 to 2 set to PWM mode 2 and channel 0 synchronized with the TGR0A register (channels 0 to 2 phase output: 3, 2, 2)). 9.4.2 Example of DMA 189 Transfer between External RAM and External Device with DACK 10.1.1 Features 191 10.1.4 Register Configuration Table 10.3 Register Configuration 198 Notes amended Notes: Do not access empty addresses. 1. 16-bit registers (TCNT, TGR) cannot be read or written in 8-bit units. 2. Write 0 to clear flags. Description amended This bit is reserved for channel 0. It always reads as 0. The write value should always be 0. 10.2.4 Timer Interrupt 215 Enable Register (TIER) Bit 5—Underflow Interrupt Enable (TCIEU) Bit 3—TGR Interrupt Enable D (TGIED): Bit 2—TGR Interrupt Enable C (TGIEC): 10.2.5 Timer Status Register (TSR) 217 216 Description amended This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0. Description amended This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0. Description amended The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset or by standby mode. Rev.5.00 Sep. 27, 2007 Page x of xxxiv REJ09B0398-0500 Item Buffer Operation Examples⎯when TGR Is an Input Capture Register Page Revision (See Manual for Details) Description amended Figure 10.20 shows an example of TGRA set as an input capture register with the TGRA and TGRC registers set for buffer operation. Figure amended TIOC0A Description amended A period can be set for a register by using the TGR comparematch as a counter clear source. All channels can be independently set to PWM mode. Synchronous operation is also possible. 10.4.4 Buffer Operation 237 238 Figure 10.20 Buffer Operation Example (Input Capture Register) 10.4.6 PWM Mode 240 10.4.7 Phase Counting 250 Mode Phase Counting Mode Application Example: Description amended The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0 TGR0A and TGR0C register compare-match is used as an input capture source, and all of the control period increment and decrement values are stored. This procedure enables the accurate detection of position and speed. Description amended The compare-match signal is generated at the final state of TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR is output to the output compare output pin (the TIOC pin). After TCNT and TGR matching, a compare-match signal is not issued until immediately before the TCNT input clock. Description amended With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT1 count (during a TCNT2 overflow/underflow) in the T2 state of the TCNT2 write cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if there is match with TGR1A and the TCNT1 value, a compare signal is issued. Furthermore, when the TCNT1 count clock is selected as the input capture source of channel 0, TGRA0 to TGRD0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB1, TGRB1 carries out input capture operation. The timing is shown in figure 10.57. 10.6.1 Input/Output Timing Output Compare Output Timing: 254 10.7.10 TCNT2 Write 269 and Overflow/Underflow Contention in Cascade Connection Rev.5.00 Sep. 27, 2007 Page xi of xxxiv REJ09B0398-0500 Item 10.8.1 Operating Modes Page 273 Revision (See Manual for Details) Description amended • • • • Normal mode (channels 0 to 2) PWM mode 1 (channels 0 to 2) PWM mode 2 (channels 0 to 2) Phase counting modes 1 to 4 (channels 1 and 2) 10.8.3 Operation in 273 Case of Re-Setting Due to Error during Operation, Etc. 10.8.4 Overview of 277 Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: (4) Operation when 278 Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: 282 281 Description amended The MTU has four operating modes, as stated above. There are thus 16 mode transition combinations . Possible mode transition combinations are shown in table 10.14. Note deleted Note deleted Note deleted Note deleted Rev.5.00 Sep. 27, 2007 Page xii of xxxiv REJ09B0398-0500 Item 12.2.7 Serial Status Register (SSR) Bit 4—Framing Error (FER): Page 318 Revision (See Manual for Details) Description amended and notes added Bit 4 FER 0 Description Receiving is in progress or has ended normally*1 [Clearing conditions] • • 1 Power-on reset or standby mode When 0 is written to FER after reading FER = 1 A receive framing error occurred*2 [Setting condition] When at the end of an SCI receive operation the final stop bit of the receive data is checked and its value*2 is 0 Notes: 1. The FER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2. When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. In addition, serial transmission cannot continue in clock synchronous mode. Bit 3—Parity Error (PER): Description amended and notes added Bit 3 PER 0 Description Receiving is in progress or has ended normally*1 [Clearing conditions] • • 1 Power-on reset or standby mode When 0 is written to PER after reading PER = 1 A receive parity error occurred*2 [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) Notes: 1. The PER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2. When a parity error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. In addition, serial transmission cannot continue in clock synchronous mode. Rev.5.00 Sep. 27, 2007 Page xiii of xxxiv REJ09B0398-0500 Item 12.5.7 Constraints on DMAC Use Page 366 Revision (See Manual for Details) Description amended • When using an external clock source for the synchronization clock, update the TDR with the DMAC , and then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input in the first four system clocks after the TDR is written, an error may occur (figure 12.22). High-speed conversion ⎯ Minimum conversion time: 2.9 µs per channel (for 28-MHz operation) 1.4 μs per channel during continuous conversion 13.1.1 Features 367 Description amended • 13.4 Operation 378 Description amended • In buffer operation, the previous conversion result is saved in a buffer register at the end of a conversion for the relevant channel. In simultaneous sampling operation, the analog input voltages of two channels are sampled simultaneously then converted in order. Software, a timer conversion start trigger (MTU) can be selected as the conversion start condition. • • 13.4.7 Conversion Start Modes 388 Description amended In the low-power conversion mode, power is applied to the analog circuitry simultaneous to the conversion start (ADST set). When 200 cycles of the reference clock have elapsed, conversion becomes possible for the analog circuit and the first A/D conversion begins. When performing consecutive conversions, the second and later conversions are executed in 20 cycles. Select the basic clock with the CKS bit of the ADCSR. When the A/D conversion ends, ADST is cleared to 0 and the analog circuit power supply is automatically cut off. Because the analog circuit is only active during the A/D conversion operation period in this mode, current consumption can be reduced. Rev.5.00 Sep. 27, 2007 Page xiv of xxxiv REJ09B0398-0500 Item 13.4.8 A/D Conversion Time Table 13.7 A/D Conversion Times Page 392 Revision (See Manual for Details) Note 2 amended 2. Table entries are for when PWR = 1. If 200 states have not elapsed since the ADST bit has been set, no conversions are done until after those 200 states have occurred. When PWR = 0, add 200 states to the first A/D conversion start delay time. When two or more conversions are performed in succession, tcp is 20 cycles when CKS = 0, and 40 cycles when CKS = 1. Note added Note: The indication "⎯" means the setting is not available. Title amended Table 13.8 Operating Frequency and CKS Bit Settings 13.6.5 A/D Conversion 394 Termination (HD6417014R only) 14.1.3 Pin Configuration 399 Description amended The eight analog input pins are divided into two groups, with analog input pins 0 to 3 (AN0 to AN3) comprising group 0, and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVCC and AVSS pins are for the mid-speed speed A/D converter internal analog section power supply. 14.2.1 A/D Data 401 Register A to D (ADDRA to ADDRD) 14.4.2 Scan Mode (SCAN = 1) 409 Description amended A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are four registers: ADDRA to ADDRD. Description amended An example of operation in scan mode when three channels of group 0 (AN0 to AN2) are selected for A/D conversion is shown in figure 14.4. 1. Set the operation mode to scan mode (SCAN = 1), set the scan group to group 0 (CH2 = 0), set the analog channels to AN0 to AN2 (CH1 = 1, CH0 = 0), and then start A/D conversion (ADST = 1). 14.5 Interrupt 414 Description amended The mid-speed A/D converter's interrupt source is summarized in table 14.5. When the DMAC are activated by an ADI interrupt, the ADF flag of ADCSR is cleared to 0 by register access of A/D. 15.4.1 Interrupt Sources 427 Title amended Rev.5.00 Sep. 27, 2007 Page xv of xxxiv REJ09B0398-0500 Item Page Revision (See Manual for Details) Description amended The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1 . Figure 15.5 shows the timing when the CMF bit is cleared by the CPU. Description amended PACRL1 is initialized by external power-on reset to H'4000 in extended mode, and to H'0000 in single chip mode. PACRL2 is initialized by external power-on reset to H'0000. Neither register is initialized by reset by WDT, standby mode, or sleep mode, so the previous data is maintained. Description amended Bit 14 PA15MD Description 0 1 General input/output (PA15) Clock output (CK) (single chip mode initial value) (extended mode initial value) 15.4.3 Compare Match 428 Flag Clear Timing 16.3.2 Port A Control 446 Registers L1, L2 (PACRL1 and PACRL2) Port A Control Register 447 L1 (PACRL1): Bit 14—PA15 Mode (PA15MD): 16.3.3 Port B I/O Register (PBIOR) 452 Description amended The port B I/O register L (PBIOR) is a 16-bit read/write register that selects input or output for the ten pins of port B (eight pins in the SH7014). Bits PB9IOR to PB0IOR correspond to the PB9/IRQ7/A21 pin to PB0/A16 pin. PBIOR is enabled when the port B pins function as input/outputs (PB9 to PB0). For other functions, it is disabled. 17.2.2 Port A Data Register L (PADRL) 477 Description amended PADRL is initialized by an external power-on reset. However, PADRL is not initialized for a reset by WDT, standby mode, or sleep mode. 17.3.2 Port B Data Register (PBDR) 479 Description amended PBDR is initialized by an external power-on reset. However, PBDR is not initialized for a reset by WDT, standby mode, or sleep mode. 17.4.2 Port C Data Register (PCDR) 481 Description amended PCDR is initialized by an external power-on reset. However, PCDR is not initialized for a reset by WDT, standby mode, or sleep mode. 17.5.2 Port D Data Register L (PDDRL) 483 Description amended PDDRL is initialized by an external power-on reset. However, PDDRL is not initialized for a reset by WDT, standby mode, or sleep mode. Rev.5.00 Sep. 27, 2007 Page xvi of xxxiv REJ09B0398-0500 Item 17.6.2 Port E Data Register (PEDR) Page 485 Revision (See Manual for Details) Description amended PEDR is initialized by a external power-on reset. However, PEDR is not initialized for a reset by WDT, standby mode, or sleep mode, so the previous data is retained. 17.7.2 Port F Data Register (PFDR) 487 Description amended PFDR is an 8-bit read-only register that stores data for port F. The bits PF7DR to PF0DR correspond to the PF7/AN7 to PF0/AN0 pins. Any value written into these bits is ignored, and there is no effect on the status of the pins. When any of the bits are read, the pin status rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read out. Table 17.17 shows the read/write operations of the port F data register. PFDR is not initialized by power-on resets, standby mode, or sleep mode (the bits always reflect the pin status). 18.4 Register Configuration Table 18.3 Flash Memory Registers 497 Notes amended Notes: FLMCR1, FLMCR2, and EBR1 are 8-bit registers, and RAMER is a 16-bit register. Only byte accesses are valid for FLMCR1, FLMCR2, and EBR1, the access requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a longword access. When a longword write is performed on RAMER, 0 must always be written to the lower word (address H'FFFF8630). Operation is not guaranteed if any other value is written. 1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1. 2. A read in a mode in which on-chip flash memory is disabled will return H'00. 3. When a low level is input to the FWP pin, the initial value is H'80. 4. When a high level is input to the FWP pin, or if a low level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. Rev.5.00 Sep. 27, 2007 Page xvii of xxxiv REJ09B0398-0500 Item Page Revision (See Manual for Details) Description amended RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'0000 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Figure amended and note 5 added Start Set SWE-bit of FLMCR1 Wait 10 μs Store 32 bytes write data in write data area and rewrite data area n=1 m=0 Successively write 32-byte data in rewrite data area in RAM to flash memory *1 *5 18.5.4 RAM Emulation 503 Register (RAMER) 18.7.2 Program-Verify 512 Mode Figure 18.13 Program/ Program-Verify Flowchart *4 Enable WDT Set PSU bit in FLMCR1(2) Wait 50 μs Set PSU bit in FLMCR1(2) Wait 200 μs Set PSU bit in FLMCR1(2) Wait 10 μs Set PSU bit in FLMCR1(2) Wait 10 μs Disable WDT Set PSU bit in FLMCR1(2) Wait 4 μs Perform dummy-write of H'FF to verify address Wait 2 μs Read verify data Increment address *3 *5 *2 *5 *5 *5 Write start *5 Write end *5 n←n+1 Write data = Verify data? OK Operate rewrite data Transfer rewrite data to rewrite data area 32 byte data verify complete? OK Set PSU bit in FLMCR1(2) Wait 4 μs m = 0? OK Clear SWE bit of FLMCR1 Write end NG m=1 *3 *4 NG *5 NG *5 n ≥ 1000? OK Clear SWE bit of FLMCR1 Write failure NG Note: 5. Set the values of x, y, z, α, β, γ, ε, η, and N to match the characteristics of the memory device. Rev.5.00 Sep. 27, 2007 Page xviii of xxxiv REJ09B0398-0500 Item 18.7.3 Erase Mode Page 517 Revision (See Manual for Details) Description added When erasing flash memory, the erase/erase-verify flowchart shown in figure 18.14 should be followed. To perform data or program erasure, set the 1 bit flash memory area to be erased in erase block register 1 (EBR1) at least 10 µs after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). 18.8.2 Software Protection 525 Description amended Software protection can be implemented by setting the SWE bit in FLMCR1, erase block register 1 (EBR1) and the RAMS bit in the RAM emulation register (RAMER). Description amended 3. The lower 8 bits of the transfer address must be H'00, H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 18.24). Do not perform transfer after the third cycle. 18.11.4 Auto-Program 538 Mode 18.11.6 Status Read Mode Table 18.19 Status Read Mode Return Commands 22.3.3 Bus Timing Table 22.7 Bus Timing 543 Note amended Note: I/O2 and I/O3 are undefined at present. 567 Description amended and notes added Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = – 20 to +75°C Notes: TPC is the set value of the TPC bit in DCR. * The delay time Min values are reference values (typ).) 22.3.4 Direct Memory Access Controller Timing Table 22.8 Direct Memory Access Controller Timing 579 Description amended Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = – 20 to +75°C Rev.5.00 Sep. 27, 2007 Page xix of xxxiv REJ09B0398-0500 Item Page Revision (See Manual for Details) Description amended Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = – 20 to +75°C 22.3.5 Multifunction 581 Timer Pulse Unit Timing Table 22.9 Multifunction Timer Pulse Unit Timing 22.3.6 I/O Port Timing 582 Table 22.10 I/O Port Timing 22.3.7 Watchdog Timer 583 Timing Table 22.11 Watchdog Timer Timing 22.3.8 Serial Communication Interface Timing Table 22.12 Serial Communication Interface Timing A.2 Functions Appendix B. I/O Port Block Diagrams Figure B.5 PAn/TCLKm/ IRQx Block Diagram (SH7014, Mask) C.1 Pin States Table C.1 Pin States in Reset, and Power-Down Modes 706 600 to 681 686 583 Description amended Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ±10%, VSS =AVSS = 0 V, Ta = – 20 to +75°C Description amended Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = – 20 to +75°C Description amended Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, AVCC= VCC ±10%, VSS = AVSS = 0 V, Ta = – 20 to +75°C Newly added Title amended Title and table amended Pin Function Class Data bus SCI Pin Name D0 to D15 SCK0, SCK1 TXD0, TXD1 RXD0, RXD1 All trademarks and registered trademarks are the property of their respective owners. Rev.5.00 Sep. 27, 2007 Page xx of xxxiv REJ09B0398-0500 Contents Section 1 SH7014/16/17 Overview ................................................................................ 1.1 1.2 1.3 1 SH7014/16/17 Overview................................................................................................... 1 1.1.1 SH7014/16/17 Series Features ............................................................................. 1 Block Diagram .................................................................................................................. 6 Pin Arrangement and Pin Functions.................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Arrangement by Mode................................................................................... 10 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...................................................................................................................... 19 2.1 Register Configuration ...................................................................................................... 2.1.1 General Registers (Rn)......................................................................................... 2.1.2 Control Registers ................................................................................................. 2.1.3 System Registers .................................................................................................. 2.1.4 Initial Values of Registers.................................................................................... Data Formats ..................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory....................................................................................... 2.2.3 Immediate Data Format ....................................................................................... Instruction Features........................................................................................................... 2.3.1 RISC-Type Instruction Set................................................................................... 2.3.2 Addressing Modes ............................................................................................... 2.3.3 Instruction Format................................................................................................ Instruction Set by Classification ....................................................................................... Processing States............................................................................................................... 2.5.1 State Transitions................................................................................................... 2.5.2 Power-Down State ............................................................................................... 19 19 20 21 21 22 22 22 22 23 23 26 30 33 46 46 48 2.2 2.3 2.4 2.5 Section 3 Operating Modes............................................................................................... 51 3.1 3.2 3.3 Operating Modes, Types, and Selection............................................................................ 51 Explanation of Operating Modes ...................................................................................... 52 Pin Configuration.............................................................................................................. 52 Section 4 Clock Pulse Generator (CPG) ....................................................................... 53 4.1 4.2 Overview........................................................................................................................... 4.1.1 Block Diagram ..................................................................................................... Oscillator........................................................................................................................... 4.2.1 Connecting a Crystal Oscillator ........................................................................... 53 53 54 54 Rev.5.00 Sep. 27, 2007 Page xxi of xxxiv REJ09B0398-0500 4.3 4.2.2 External Clock Input Method............................................................................... 56 Prescaler............................................................................................................................ 57 Section 5 Exception Processing....................................................................................... 59 5.1 Overview........................................................................................................................... 5.1.1 Types of Exception Processing and Priority ........................................................ 5.1.2 Exception Processing Operations......................................................................... 5.1.3 Exception Processing Vector Table ..................................................................... Resets ................................................................................................................................ 5.2.1 Power-on Reset .................................................................................................... Address Errors .................................................................................................................. 5.3.1 Address Error Sources ......................................................................................... 5.3.2 Address Error Exception Processing.................................................................... Interrupts........................................................................................................................... 5.4.1 Interrupt Sources.................................................................................................. 5.4.2 Interrupt Priority Level ........................................................................................ 5.4.3 Interrupt Exception Processing ............................................................................ Exceptions Triggered by Instructions ............................................................................... 5.5.1 Types of Exceptions Triggered by Instructions ................................................... 5.5.2 Trap Instructions .................................................................................................. 5.5.3 Illegal Slot Instructions ........................................................................................ 5.5.4 General Illegal Instructions.................................................................................. When Exception Sources Are Not Accepted .................................................................... 5.6.1 Immediately after a Delayed Branch Instruction ................................................. 5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ Stack Status after Exception Processing Ends .................................................................. Usage Notes ...................................................................................................................... 5.8.1 Value of Stack Pointer (SP) ................................................................................. 5.8.2 Value of Vector Base Register (VBR) ................................................................. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 59 59 60 61 63 63 64 64 65 65 65 66 66 67 67 67 68 68 69 69 69 70 71 71 71 71 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Section 6 Interrupt Controller (INTC) ........................................................................... 73 6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram..................................................................................................... 6.1.3 Pin Configuration................................................................................................. 6.1.4 Register Configuration......................................................................................... Interrupt Sources............................................................................................................... 6.2.1 NMI Interrupts ..................................................................................................... 6.2.2 IRQ Interrupts ...................................................................................................... 73 73 73 75 75 76 76 76 6.2 Rev.5.00 Sep. 27, 2007 Page xxii of xxxiv REJ09B0398-0500 6.3 6.4 6.5 6.6 6.2.3 On-Chip Peripheral Module Interrupts ................................................................ 6.2.4 Interrupt Exception Vectors and Priority Rankings ............................................. Description of Registers.................................................................................................... 6.3.1 Interrupt Priority Registers A to H (IPRA to IPRH) ............................................ 6.3.2 Interrupt Control Register (ICR).......................................................................... 6.3.3 IRQ Status Register (ISR).................................................................................... Interrupt Operation............................................................................................................ 6.4.1 Interrupt Sequence ............................................................................................... 6.4.2 Stack after Interrupt Exception Processing .......................................................... Interrupt Response Time ................................................................................................... Data Transfer with Interrupt Request Signals ................................................................... 6.6.1 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 6.6.2 Treating CPU Interrupt Sources but Not DMAC Activating Sources.................. 77 77 81 81 82 83 85 85 87 88 90 90 90 Section 7 Cache Memory (CAC) .................................................................................... 91 7.1 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Register Configuration......................................................................................... Register Explanation ......................................................................................................... 7.2.1 Cache Control Register (CCR) ............................................................................ Address Array and Data Array.......................................................................................... 7.3.1 Cache Address Array Read/Write Space ............................................................. 7.3.2 Cache Data Array Read/Write Space................................................................... Usage Notes ...................................................................................................................... 7.4.1 Cache Initialization .............................................................................................. 7.4.2 Forced Access to Address Array and Data Array ................................................ 7.4.3 Cache Miss Penalty and Cache Fill Timing ......................................................... 7.4.4 Cache Hit after Cache Miss ................................................................................. 91 91 92 93 94 94 96 96 97 98 98 98 98 100 7.2 7.3 7.4 Section 8 Bus State Controller (BSC) ........................................................................... 101 8.1 Overview........................................................................................................................... 8.1.1 Features................................................................................................................ 8.1.2 Block Diagram ..................................................................................................... 8.1.3 Pin Configuration................................................................................................. 8.1.4 Register Configuration......................................................................................... 8.1.5 Address Map ........................................................................................................ Description of Registers.................................................................................................... 8.2.1 Bus Control Register 1 (BCR1) ........................................................................... 8.2.2 Bus Control Register 2 (BCR2) ........................................................................... 101 101 102 103 103 104 107 107 109 8.2 Rev.5.00 Sep. 27, 2007 Page xxiii of xxxiv REJ09B0398-0500 8.2.3 Wait Control Register 1 (WCR1)......................................................................... 8.2.4 Wait Control Register 2 (WCR2)......................................................................... 8.2.5 DRAM Area Control Register (DCR) ................................................................. 8.2.6 Refresh Timer Control/Status Register (RTCSR) ................................................ 8.2.7 Refresh Timer Counter (RTCNT)........................................................................ 8.2.8 Refresh Time Constant Register (RTCOR) ......................................................... 8.3 Accessing Ordinary Space ................................................................................................ 8.3.1 Basic Timing........................................................................................................ 8.3.2 Wait State Control ............................................................................................... 8.3.3 CS Assert Period Extension ................................................................................. 8.4 DRAM Access .................................................................................................................. 8.4.1 DRAM Direct Connection ................................................................................... 8.4.2 Basic Timing........................................................................................................ 8.4.3 Wait State Control ............................................................................................... 8.4.4 Burst Operation.................................................................................................... 8.4.5 Refresh Timing .................................................................................................... 8.5 Address/Data Multiplex I/O Space Access ....................................................................... 8.5.1 Basic Timing........................................................................................................ 8.5.2 Wait State Control ............................................................................................... 8.5.3 CS Assertion Extension ....................................................................................... 8.6 Waits between Access Cycles........................................................................................... 8.6.1 Prevention of Data Bus Conflicts......................................................................... 8.6.2 Simplification of Bus Cycle Start Detection ........................................................ 8.7 Bus Arbitration.................................................................................................................. 8.8 Memory Connection Examples......................................................................................... 8.9 On-chip Peripheral I/O Register Access ........................................................................... 8.10 CPU Operation when Program Is in External Memory .................................................... 112 114 115 118 121 122 123 123 124 126 127 127 128 129 133 135 136 136 138 139 140 140 142 143 143 145 146 Section 9 Direct Memory Access Controller (DMAC) ............................................ 147 9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagram..................................................................................................... 9.1.3 Pin Configuration................................................................................................. 9.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 9.2.1 DMA Source Address Registers 0, 1 (SAR0, SAR1) .......................................... 9.2.2 DMA Destination Address Registers 0, 1 (DAR0, DAR1).................................. 9.2.3 DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1)......................... 9.2.4 DMA Channel Control Registers 0, 1 (CHCR0, CHCR1)................................... 9.2.5 DMAC Operation Register (DMAOR) ................................................................ 147 147 148 149 150 151 151 152 153 154 159 9.2 Rev.5.00 Sep. 27, 2007 Page xxiv of xxxiv REJ09B0398-0500 9.3 9.4 9.5 Operation........................................................................................................................... 9.3.1 DMA Transfer Flow ............................................................................................ 9.3.2 DMA Transfer Requests ...................................................................................... 9.3.3 Channel Priority ................................................................................................... 9.3.4 DMA Transfer Types........................................................................................... 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing.............................. 9.3.6 DMA Transfer Ending Conditions....................................................................... 9.3.7 DMAC Access from CPU.................................................................................... Examples of Use ............................................................................................................... 9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory .......... 9.4.2 Example of DMA Transfer between External RAM and External Device with DACK .................................................................................................................. Usage Notes ...................................................................................................................... 161 161 163 165 165 172 187 188 188 188 189 190 Section 10 Multifunction Timer Pulse Unit (MTU) .................................................. 191 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram ..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 MTU Register Descriptions .............................................................................................. 10.2.1 Timer Control Register (TCR) ............................................................................. 10.2.2 Timer Mode Register (TMDR) ............................................................................ 10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 10.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 10.2.5 Timer Status Register (TSR)................................................................................ 10.2.6 Timer Counters (TCNT) ...................................................................................... 10.2.7 Timer General Register (TGR) ............................................................................ 10.2.8 Timer Start Register (TSTR)................................................................................ 10.2.9 Timer Synchro Register (TSYR) ......................................................................... 10.3 Bus Master Interface ......................................................................................................... 10.3.1 16-Bit Registers ................................................................................................... 10.3.2 8-Bit Registers ..................................................................................................... 10.4 Operation........................................................................................................................... 10.4.1 Overview.............................................................................................................. 10.4.2 Basic Functions.................................................................................................... 10.4.3 Synchronous Operation........................................................................................ 10.4.4 Buffer Operation .................................................................................................. 10.4.5 Cascade Connection Mode................................................................................... 10.4.6 PWM Mode.......................................................................................................... 191 191 195 196 197 199 199 203 205 214 217 220 221 221 222 224 224 224 226 226 226 232 235 238 240 Rev.5.00 Sep. 27, 2007 Page xxv of xxxiv REJ09B0398-0500 10.4.7 Phase Counting Mode.......................................................................................... 10.5 Interrupts........................................................................................................................... 10.5.1 Interrupt Sources and Priority Ranking................................................................ 10.5.2 DMAC Activation................................................................................................ 10.5.3 A/D Converter Activation.................................................................................... 10.6 Operation Timing.............................................................................................................. 10.6.1 Input/Output Timing ............................................................................................ 10.6.2 Interrupt Signal Timing........................................................................................ 10.7 Usage Notes ...................................................................................................................... 10.7.1 Input Clock Limitations ....................................................................................... 10.7.2 Note on Cycle Setting .......................................................................................... 10.7.3 Contention between TCNT Write and Clear........................................................ 10.7.4 Contention between TCNT Write and Increment ................................................ 10.7.5 Contention between Buffer Register Write and Compare Match ........................ 10.7.6 Contention between TGR Read and Input Capture.............................................. 10.7.7 Contention between TGR Write and Input Capture............................................. 10.7.8 Contention between Buffer Register Write and Input Capture ............................ 10.7.9 Contention between TGR Write and Compare Match ......................................... 10.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 10.7.11 Contention between Overflow/Underflow and Counter Clearing........................ 10.7.12 Contention between TCNT Write and Overflow/Underflow............................... 10.7.13 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode 1....... 10.8 MTU Output Pin Initialization .......................................................................................... 10.8.1 Operating Modes.................................................................................................. 10.8.2 Reset Start Operation ........................................................................................... 10.8.3 Operation in Case of Re-Setting Due to Error during Operation, Etc.................. 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. .......................................................................................... 244 251 251 252 252 253 253 258 262 262 262 263 264 265 266 267 268 269 269 271 272 272 273 273 273 273 274 Section 11 Watchdog Timer (WDT).............................................................................. 291 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Timer Counter (TCNT)........................................................................................ 11.2.2 Timer Control/Status Register (TCSR)................................................................ 11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 11.2.4 Register Access.................................................................................................... Rev.5.00 Sep. 27, 2007 Page xxvi of xxxiv REJ09B0398-0500 291 291 292 292 293 293 293 294 296 297 11.3 Operation........................................................................................................................... 11.3.1 Watchdog Timer Mode ........................................................................................ 11.3.2 Interval Timer Mode ............................................................................................ 11.3.3 Clearing the Standby Mode.................................................................................. 11.3.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 11.4 Usage Notes ...................................................................................................................... 11.4.1 TCNT Write and Increment Contention............................................................... 11.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 11.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 11.4.4 System Reset with WDTOVF .............................................................................. 11.4.5 Internal Reset with the Watchdog Timer ............................................................. 298 298 300 300 301 301 302 302 302 302 303 303 Section 12 Serial Communication Interface (SCI) .................................................... 305 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Receive Shift Register (RSR) .............................................................................. 12.2.2 Receive Data Register (RDR) .............................................................................. 12.2.3 Transmit Shift Register (TSR) ............................................................................. 12.2.4 Transmit Data Register (TDR)............................................................................. 12.2.5 Serial Mode Register (SMR)................................................................................ 12.2.6 Serial Control Register (SCR).............................................................................. 12.2.7 Serial Status Register (SSR) ................................................................................ 12.2.8 Bit Rate Register (BRR) ...................................................................................... 12.3 Operation........................................................................................................................... 12.3.1 Overview.............................................................................................................. 12.3.2 Operation in Asynchronous Mode ....................................................................... 12.3.3 Multiprocessor Communication........................................................................... 12.3.4 Clock Synchronous Operation ............................................................................. 12.4 SCI Interrupt Sources and the DMAC .............................................................................. 12.5 Usage Notes ...................................................................................................................... 12.5.1 TDR Write and TDRE Flags................................................................................ 12.5.2 Simultaneous Multiple Receive Errors ................................................................ 12.5.3 Break Detection and Processing........................................................................... 12.5.4 Sending a Break Signal........................................................................................ 305 305 306 307 307 308 308 308 308 309 309 312 316 320 331 331 333 343 351 362 363 363 363 364 364 Rev.5.00 Sep. 27, 2007 Page xxvii of xxxiv REJ09B0398-0500 12.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only) ........................................................................ 12.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode .................................................................................................................... 12.5.7 Constraints on DMAC Use .................................................................................. 12.5.8 Cautions for Clock Synchronous External Clock Mode ...................................... 12.5.9 Caution for Clock Synchronous Internal Clock Mode......................................... 364 364 366 366 366 Section 13 High Speed A/D Converter ⎯ SH7014 ⎯............................................. 367 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................. 13.2.2 A/D Control/Status Register (ADCSR) ............................................................... 13.2.3 A/D Control Register (ADCR) ............................................................................ 13.3 Bus Master Interface ......................................................................................................... 13.4 Operation .......................................................................................................................... 13.4.1 Select-Single Mode.............................................................................................. 13.4.2 Select-Scan Mode ................................................................................................ 13.4.3 Group-Single Mode ............................................................................................. 13.4.4 Group-Scan Mode................................................................................................ 13.4.5 Buffer Operation .................................................................................................. 13.4.6 Simultaneous Sampling Operation....................................................................... 13.4.7 Conversion Start Modes....................................................................................... 13.4.8 A/D Conversion Time.......................................................................................... 13.5 Interrupts........................................................................................................................... 13.6 Usage Notes ...................................................................................................................... 13.6.1 Analog Input Voltage Range ............................................................................... 13.6.2 AVCC, AVSS Input Voltages .................................................................................. 13.6.3 Input Ports............................................................................................................ 13.6.4 Conversion Start Modes....................................................................................... 13.6.5 A/D Conversion Termination (HD6417014R only)............................................. 13.6.6 Handling of Analog Input Pins ............................................................................ 367 367 368 368 369 370 370 371 374 376 378 378 379 380 381 383 386 388 391 393 394 394 394 394 394 394 395 Section 14 Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯........................... 397 14.1 Overview........................................................................................................................... 397 14.1.1 Features................................................................................................................ 397 Rev.5.00 Sep. 27, 2007 Page xxviii of xxxiv REJ09B0398-0500 14.2 14.3 14.4 14.5 14.6 14.7 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 14.2.1 A/D Data Register A to D (ADDRA to ADDRD) ............................................... 14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 14.2.3 A/D Control Register (ADCR) ............................................................................ Interface with CPU............................................................................................................ Operation........................................................................................................................... 14.4.1 Single Mode (SCAN = 0)..................................................................................... 14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 14.4.3 Input Sampling and A/D Conversion Time.......................................................... 14.4.4 MTU Trigger Input Timing.................................................................................. Interrupt............................................................................................................................. A/D Conversion Precision Definitions.............................................................................. Usage Notes ...................................................................................................................... 14.7.1 Analog Voltage Settings ...................................................................................... 14.7.2 Handling of Analog Input Pins ............................................................................ 398 399 400 401 401 402 404 405 407 407 409 411 413 414 415 417 417 417 Section 15 Compare Match Timer (CMT) ................................................................... 419 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 15.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 15.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 15.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 15.3 Operation........................................................................................................................... 15.3.1 Period Count Operation ....................................................................................... 15.3.2 CMCNT Count Timing........................................................................................ 15.4 Interrupts ........................................................................................................................... 15.4.1 Interrupt Sources.................................................................................................. 15.4.2 Compare Match Flag Set Timing......................................................................... 15.4.3 Compare Match Flag Clear Timing ..................................................................... 15.5 Usage Notes ...................................................................................................................... 15.5.1 Contention between CMCNT Write and Compare Match ................................... 15.5.2 Contention between CMCNT Word Write and Incrementation........................... 15.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 419 419 419 421 422 422 423 424 425 426 426 426 427 427 427 428 429 429 430 431 Rev.5.00 Sep. 27, 2007 Page xxix of xxxiv REJ09B0398-0500 Section 16 Pin Function Controller (PFC) ................................................................... 433 16.1 Overview........................................................................................................................... 16.2 Register Configuration...................................................................................................... 16.3 Register Descriptions ........................................................................................................ 16.3.1 Port A I/O Register L (PAIORL)......................................................................... 16.3.2 Port A Control Registers L1, L2 (PACRL1 and PACRL2) ................................. 16.3.3 Port B I/O Register (PBIOR) ............................................................................... 16.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 16.3.5 Port C I/O Register (PCIOR) ⎯ SH7016, SH7017 ⎯ ........................................ 16.3.6 Port C Control Register (PCCR) ⎯ SH7016, SH7017 ⎯ ................................... 16.3.7 Port D I/O Register L (PDIORL) ⎯ SH7016, SH7017 ⎯ .................................. 16.3.8 Port D Control Register L (PDCRL) ⎯ SH7016, SH7017 ⎯ ............................. 16.3.9 Port E I/O Register (PEIOR)................................................................................ 16.3.10 Port E Control Registers 1, 2 (PECR1 and PECR2) ............................................ 433 444 445 445 446 452 453 458 459 464 465 470 471 Section 17 I/O Ports (I/O) ................................................................................................. 475 17.1 Overview........................................................................................................................... 17.2 Port A................................................................................................................................ 17.2.1 Register Configuration......................................................................................... 17.2.2 Port A Data Register L (PADRL) ........................................................................ 17.3 Port B ................................................................................................................................ 17.3.1 Register Configuration......................................................................................... 17.3.2 Port B Data Register (PBDR) .............................................................................. 17.4 Port C ⎯ SH7016, SH7017 ⎯ ......................................................................................... 17.4.1 Register Configuration......................................................................................... 17.4.2 Port C Data Register (PCDR) .............................................................................. 17.5 Port D ⎯ SH7016, SH7017 ⎯ ......................................................................................... 17.5.1 Register Configuration......................................................................................... 17.5.2 Port D Data Register L (PDDRL) ........................................................................ 17.6 Port E ................................................................................................................................ 17.6.1 Register Configuration......................................................................................... 17.6.2 Port E Data Register (PEDR)............................................................................... 17.7 Port F................................................................................................................................. 17.7.1 Register Configuration......................................................................................... 17.7.2 Port F Data Register (PFDR) ............................................................................... 475 475 476 477 478 478 479 480 480 481 482 482 483 484 484 485 486 486 487 Section 18 128 kB Flash Memory (F-ZTAT).............................................................. 489 18.1 Features............................................................................................................................. 489 18.2 Overview........................................................................................................................... 490 18.2.1 Block Diagram..................................................................................................... 490 Rev.5.00 Sep. 27, 2007 Page xxx of xxxiv REJ09B0398-0500 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 18.11 18.2.2 Mode Transitions ................................................................................................. 18.2.3 On-Board Programming Modes........................................................................... 18.2.4 Flash Memory Emulation in RAM ...................................................................... 18.2.5 Differences between Boot Mode and User Program Mode.................................. 18.2.6 Block Configuration............................................................................................. Pin Configuration.............................................................................................................. Register Configuration ...................................................................................................... Register Descriptions ........................................................................................................ 18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 18.5.3 Erase Block Register 1 (EBR1)............................................................................ 18.5.4 RAM Emulation Register (RAMER)................................................................... On-Board Programming Modes ........................................................................................ 18.6.1 Boot Mode ........................................................................................................... 18.6.2 User Program Mode............................................................................................. Programming/Erasing Flash Memory ............................................................................... 18.7.1 Program Mode ..................................................................................................... 18.7.2 Program-Verify Mode.......................................................................................... 18.7.3 Erase Mode .......................................................................................................... 18.7.4 Erase-Verify Mode............................................................................................... Protection .......................................................................................................................... 18.8.1 Hardware Protection ............................................................................................ 18.8.2 Software Protection.............................................................................................. 18.8.3 Error Protection.................................................................................................... Flash Memory Emulation in RAM.................................................................................... Note on Flash Memory Programming/Erasing ................................................................. Flash Memory Programmer Mode .................................................................................... 18.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 18.11.2 Programmer Mode Operation .............................................................................. 18.11.3 Memory Read Mode ............................................................................................ 18.11.4 Auto-Program Mode ............................................................................................ 18.11.5 Auto-Erase Mode ................................................................................................. 18.11.6 Status Read Mode ................................................................................................ 18.11.7 Status Polling ....................................................................................................... 18.11.8 Programmer Mode Transition Time..................................................................... 18.11.9 Notes on Memory Programming.......................................................................... 491 492 494 495 496 496 497 498 498 501 502 503 504 505 509 510 510 511 517 518 524 524 525 526 528 530 530 531 533 534 538 540 542 543 544 545 Section 19 Mask ROM ....................................................................................................... 547 19.1 Overview........................................................................................................................... 547 Rev.5.00 Sep. 27, 2007 Page xxxi of xxxiv REJ09B0398-0500 Section 20 RAM .................................................................................................................. 549 20.1 Overview........................................................................................................................... 549 Section 21 Power-Down State ......................................................................................... 551 21.1 Overview........................................................................................................................... 21.1.1 Power-Down States.............................................................................................. 21.1.2 Related Register ................................................................................................... 21.2 Standby Control Register (SBYCR) ................................................................................. 21.3 Sleep Mode ....................................................................................................................... 21.3.1 Transition to Sleep Mode..................................................................................... 21.3.2 Canceling Sleep Mode ......................................................................................... 21.4 Standby Mode ................................................................................................................... 21.4.1 Transition to Standby Mode................................................................................. 21.4.2 Canceling the Standby Mode ............................................................................... 21.4.3 Standby Mode Application Example ................................................................... 551 551 552 553 554 554 554 554 554 556 557 Section 22 Electrical Characteristics (5 V 28.7 MHz).............................................. 559 22.1 Absolute Maximum Ratings ............................................................................................. 22.2 DC Characteristics ............................................................................................................ 22.3 AC Characteristics ............................................................................................................ 22.3.1 Clock Timing ....................................................................................................... 22.3.2 Control Signal Timing ......................................................................................... 22.3.3 Bus Timing .......................................................................................................... 22.3.4 Direct Memory Access Controller Timing .......................................................... 22.3.5 Multifunction Timer Pulse Unit Timing .............................................................. 22.3.6 I/O Port Timing.................................................................................................... 22.3.7 Watchdog Timer Timing...................................................................................... 22.3.8 Serial Communication Interface Timing.............................................................. 22.3.9 High Speed A/D Converter Timing ⎯ SH7014 ⎯ ............................................. 22.3.10 Mid-speed Converter Timing ⎯ SH7016, SH7017 ⎯ ........................................ 22.3.11 Measuring Conditions for AC Characteristics ..................................................... 22.4 A/D Converter Characteristics .......................................................................................... 559 560 562 562 564 566 579 581 582 583 583 584 586 588 589 Appendix A On-Chip Supporting Module Registers ................................................ 591 A.1 A.2 Addresses .......................................................................................................................... 591 Functions........................................................................................................................... 600 Appendix B I/O Port Block Diagrams........................................................................... 682 Appendix C Pin States ....................................................................................................... 707 Rev.5.00 Sep. 27, 2007 Page xxxii of xxxiv REJ09B0398-0500 C.1 C.2 Pin States........................................................................................................................... 707 Pin States of Bus Related Signals ..................................................................................... 709 Appendix D Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions ................................................................................. 713 Appendix E Product Code Lineup .................................................................................. 714 Appendix F Package Dimensions ................................................................................... 715 Rev.5.00 Sep. 27, 2007 Page xxxiii of xxxiv REJ09B0398-0500 Rev.5.00 Sep. 27, 2007 Page xxxiv of xxxiv REJ09B0398-0500 1. SH7014/16/17 Overview Section 1 SH7014/16/17 Overview 1.1 SH7014/16/17 Overview The SH7014/16/17 CMOS single-chip microprocessors integrate a Renesas Technology-original architecture, high-speed CPU with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In particular, the SH7040 series has a 1-kbyte on-chip cache, which allows an improvement in CPU performance during external memory access. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller, and I/O ports. Memory or peripheral LSIs can be connected efficiently with an external memory access support function. This greatly reduces system cost. This LSI has an F-ZTAT * version with on-chip flash memory and a mask ROM version. These versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. Notes: F-ZTAT (Flexible ZTAT) is a trademark of Renesas Technology Corp. 1.1.1 CPU: • Original Renesas Technology architecture • 32-bit internal data bus • General-register machine ⎯ Sixteen 32-bit general registers ⎯ Three 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction set ⎯ Instruction length: 16-bit fixed length for improved code efficiency ⎯ Load-store architecture (basic operations are executed between registers) Rev.5.00 Sep. 27, 2007 Page 1 of 716 REJ09B0398-0500 TM SH7014/16/17 Series Features 1. SH7014/16/17 Overview ⎯ Delayed branch instructions reduce pipeline disruption during branch ⎯ Instruction set based on C language • Instruction execution time: one instruction/cycle (35 ns/instruction at 28.7-MHz operation) • Address space: Architecture supports 4 Gbytes • On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) and multiplication/accumulation operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two to four cycles • Five-stage pipeline Cache Memory: • 1-kbyte instruction cache • Caching of instruction codes and PC relative read data • 4-byte line length (1 longword: 2 instruction lengths) • 256 entry cache tags • Direct map method • On-chip ROM/RAM, and on-chip I/O areas not objects of cache • Used in common with on-chip RAM; 2 kbytes of on-chip RAM used as address array/data array when cache is enabled Interrupt Controller (INTC): • Seven external interrupt pins (NMI, IRQ × 6) • Twenty-eight internal interrupt sources • Sixteen programmable priority levels Bus State Controller (BSC): • Supports external extended memory access ⎯ 8-bit, or 16-bit external data bus • Memory address space divided into five areas (four areas of SRAM space, one area of DRAM space) with the following settable features: ⎯ Number of wait cycles ⎯ Outputs chip-select signals for each area ⎯ During DRAM space access: • Outputs RAS and CAS signals for DRAM • Can generate a RAS precharge time assurance Tp cycle Rev.5.00 Sep. 27, 2007 Page 2 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview • DRAM burst access function ⎯ Supports high-speed access mode for DRAM • DRAM refresh function ⎯ Programmable refresh interval ⎯ Supports CAS-before-RAS refresh and self-refresh modes • Wait cycles can be inserted using an external WAIT signal • Address data multiplex I/O devices can be accessed Note: No bus release Direct Memory Access Controller (DMAC) (2 Channels): • Supports cycle-steal and burst transfers • Supports single address mode and dual address mode transfers • Priority order: fixed at channel 0 > channel 1 • Transfer counter: 16 bits • Transfer request sources: external DREQ input, auto-request, and on-chip supporting modules • Address space: 4 Gbytes • Choice of 8-, 16-, or 32-bit transfer data size Multifunction Timer/Pulse Unit (MTU) (3 Channels): • Maximum 8 types of waveform output or maximum 16 types of pulse I/O processing possible based on 16-bit timer, 3 channels • 8 dual-use output compare/input capture registers • 8 independent comparators • 8 types of counter input clock • Input capture function • Pulse output mode ⎯ One shot, toggle, PWM • Phase calculation mode ⎯ 2-phase encoder calculation processing Compare Match Timer (CMT) (Two Channels): • 16-bit free-running counter • One compare register • Generates an interrupt request upon compare match Rev.5.00 Sep. 27, 2007 Page 3 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Watchdog Timer (WDT) (One Channel): • Watchdog timer or interval timer • Count overflow can generate an internal reset, external signal, or interrupt Serial Communication Interface (SCI) (Two Channels): (Per Channel): • Asynchronous or clock-synchronous mode is selectable • Can transmit and receive simultaneously (full duplex) • On-chip dedicated baud rate generator • Multiprocessor communication function I/O Ports: • SH7014 ⎯ Input/output: 35 ⎯ Input: 8 ⎯ Total: 43 • SH7016/17 ⎯ Input/output: 74 ⎯ Input: 8 ⎯ Total: 82 A/D Converter: • 10 bits × 8 channels • The SH7014 has a high-speed A/D converter, while the SH7016 and SH7017 have a midspeed A/D converter. On-Chip Memory: • ROM ⎯ SH7014: ROMless ⎯ SH7016: 64 kbytes (mask ROM) ⎯ SH7017: 128 kbytes (flash ROM) • RAM: SH7014/16: 3 kbytes (1 kbyte when cache is used) SH7017: 4 kbytes (2 kbytes when cache is used) Rev.5.00 Sep. 27, 2007 Page 4 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Operating Modes: • Operating modes ⎯ Non-extended ROM mode (SH7014/16/17) ⎯ Extended ROM mode (SH7016/17) ⎯ Single-chip mode (SH7016/17) • Processing states ⎯ Program execution state ⎯ Exception processing state • Power-down modes ⎯ Sleep mode ⎯ Software standby mode Clock Pulse Generator (CPG): • On-chip clock pulse generator ⎯ On-chip clock-doubling PLL circuit Product Lineup: Product Code HD6417014F28 On-Chip ROM ROMless On-Chip RAM A/D Precision 3 kB 3 kB Frequency/ Voltage Temperature Package ±15 LSB 28.7 MHz/5 V −20 to +75°C FP-112 (high-speed A/D) ±8 LSB 28.7 MHz/5 V −20 to +75°C FP-112 (high-speed A/D) ±4 LSB 28.7 MHz/5 V −20 to +75°C FP-112 (mid-speed A/D) ±4LSB 28.7 MHz/5 V −20 to +75°C FP-112 (mid-speed A/D) HD6417014RF28 ROMless HD6437016F28 HD64F7017F28 64 kB 3 kB mask ROM 128 kB flash memory 4 kB Rev.5.00 Sep. 27, 2007 Page 5 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview 1.2 Block Diagram Figure 1.1 is a block diagram of the SH7014. Figure 1.2 is a block diagram of the SH7016/17. PA15/CK RD WRH WRL CS1 CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3/RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLCAP PLLVSS VCC PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18 PB5/IRQ3/RDWR PB4/IRQ2/CASH PB3/IRQ1/CASL PB2/IRQ0/RAS A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Watchdog timer RAM (3 kB)/ cache (1 kB) PLL PLLVCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS CPU Direct memory access controller Interrupt controller Bus state controller Serial communication interface (×2 channels) Compare match timer (×2 channels) Multifunction timer/ pulse unit A/D converter : Peripheral address bus : Peripheral data bus : Internal address bus : Internal upper data bus : Internal lower data bus Figure 1.1 Block Diagram of the SH7014 Rev.5.00 Sep. 27, 2007 Page 6 of 716 REJ09B0398-0500 PE15/DACK1 PE14/DACK0/AH PE13 PE12 PE11 PE10 PE9 PE8 PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE3/TIOC0D/DRAK1 PE2/TIOC0C/DREQ1 PE1/TIOC0B/DRAK0 PE0/TIOC0A/DREQ0 PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 1. SH7014/16/17 Overview PA5/SCK1/DREQ1/IRQ1 PA2/SCK0/DREQ0/IRQ0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PB8/IRQ6/A20/WAIT PA7/TCLKB/CS3 PA6/TCLKA/CS2 PB5/IRQ3/RDWR PB4/IRQ2/CASH PB3/IRQ1/CASL PA13/WRH PA12/WRL PA3/RXD1 PA0/RXD0 PA4/TXD1 PA1/TXD0 PA11/CS1 PA10/CS0 PA14/RD PA15/CK PB9/IRQ7/A21 PB2/IRQ0/RAS PB1/A17 PB7/A19 RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcc PLLCAP PLLVss Vcc/FWP* Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss AVcc AVss Serial communication interface (×2 channels) Multifunction timer/ pulse unit PB6/A18 PB0/A16 PC15/A15 PC14/A14 PC13/A13 Flash ROM (128 kB)/ mask ROM (64 kB) RAM (4 kB/3 kB)/ cache (1 kB) PC12/A12 PC11/A11 PC10/A10 PC9/A9 PLL PC8/A8 PC7/A7 PC6/A6 CPU Direct memory access controller Interrupt controller Bus state controller PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD15/D15 PD14/D14 PD13/D13 PD12/D12 A/D converter Watchdog timer Compare match timer (×2 channels) PD11/D11 PD10/D10 PD9/D9 PD8/D8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 : Peripheral address bus : Peripheral data bus : Internal address bus : Internal upper data bus : Internal lower data bus PE9 PE13 PE12 PE11 PE10 PE8 PE2/TIOC0C/DREQ1 Note: * VCC in the SH7016, FWP in the SH7017 (except FWE pin in the programmer mode). Figure 1.2 Block Diagram of the SH7016, SH7017 Rev.5.00 Sep. 27, 2007 Page 7 of 716 REJ09B0398-0500 PE0/TIOC0A/DREQ0 PE15/DACK1 PE14/DACK0/AH PE7/TIOC2B PE6/TIOC2A PE5/TIOC1B PE4/TIOC1A PE3/TIOC0D/DRAK1 PE1/TIOC0B/DRAK0 PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 1. SH7014/16/17 Overview 1.3 1.3.1 Pin Arrangement and Pin Functions Pin Arrangement Figure 1.3 shows the pin arrangement for the SH7014 (top view). RES PA15/CK PLLVSS PLLCAP PLLVCC MD0 MD1 VCC NMI MD2 EXTAL MD3 XTAL VSS D0 D1 D2 D3 D4 VCC D5 D6 D7 VSS D8 D9 D10 D11 Figure 1.3 SH7014 Pin Arrangement (FP-112 Top View) Rev.5.00 Sep. 27, 2007 Page 8 of 716 REJ09B0398-0500 PE14/DACK0/AH PE15/DACK1 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 VCC A17 VSS PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH VSS PB5/IRQ3/RDWR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A VSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVSS PF6/AN6 PF7/AN7 AVCC VSS PE5/TIOC1B VCC PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 VSS PE11 PE12 PB13 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 FP-112 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D12 VSS D13 D14 D15 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 CS1 VSS WRL VCC WRH WDTOVF RD VSS PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18 1. SH7014/16/17 Overview Figure 1.4 shows the pin arrangement for the 144-pin QFP pin arrangement. Vcc/FWP* PD10/D10 58 PD11/D11 57 PA15/CK PLLCAP PD0/D0 PD1/D1 PD2/D2 PD3/D3 PD4/D4 PD5/D5 PD6/D6 PD7/D7 PD8/D8 60 PD9/D9 59 PLLVss PLLVcc EXTAL XTAL MD0 MD1 MD2 MD3 RES NMI Vss Vcc 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A Vss PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVcc Vss PE5/TIOC1B Vcc PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 Vss PE11 PE12 PE13 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 61 Vss 56 55 54 53 52 51 50 49 48 47 46 45 PD12/D12 Vss PD13/D13 PD14/D14 PD15/D15 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PA10/CS0 PA11/CS1 Vss PA12/WRL Vcc PA13/WRH WDTOVF PA14/RD Vss PB9/IRQ7/A21 PB8/IRQ6/A20/WAIT PB7/A19 PB6/A18 FP-112 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PE14/DACK0/AH Vss Vcc Vss PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH Vss Note: * VCC in the SH7016, FWP in the SH7017 (except FWE pin in the programmer mode). Figure 1.4 SH7016, SH7017 Pin Arrangement (QFP-112 Top View) Rev.5.00 Sep. 27, 2007 Page 9 of 716 REJ09B0398-0500 PB5/IRQ3/RDWR PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15A15 PB0/A16 PE15/DACK1 PB1/A17 1. SH7014/16/17 Overview 1.3.2 Table 1.1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Arrangement by Mode Pin Arrangement by Mode for SH7017F (FP-112 Pin) MCU Mode PE14/DACK0/AH PE15/DACK1 VSS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16 VCC PB1/A17 VSS PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH VSS PB5/IRQ3/RDWR PB6/A18 PB7/A19 Programmer Mode NC NC VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 VCC NC VSS NC NC A17 VSS NC NC NC Rev.5.00 Sep. 27, 2007 Page 10 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 MCU Mode PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 VSS PA14/RD WDTOVF PA13/WRH VCC PA12/WRL VSS PA11/CS1 PA10/CS0 PA9/TCLKD/IRQ3 PA8/TCLKC/IRQ2 PA7/TCLKB/CS3 PA6/TCLKA/CS2 PA5/SCK1/DREQ1/IRQ1 PA4/TXD1 PA3 /RXD1 PA2/SCK0/DREQ0/IRQ0 PA1/TXD0 PA0/RXD0 PD15/D15 PD14/D14 PD13/D13 VSS PD12/D12 PD11/D11 PD10/D10 PD9/D9 PD8/D8 VSS PD7/D7 PD6/D6 Programmer Mode NC NC VSS NC NC NC VCC NC VSS NC NC CE OE WE NC VCC NC NC VCC VCC NC NC NC NC VSS NC NC NC NC NC VSS D7 D6 Rev.5.00 Sep. 27, 2007 Page 11 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Pin No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 MCU Mode PD5/D5 VCC PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0 VSS XTAL MD3 EXTAL MD2 NMI VCC (FWP) MD1 MD0 PLLVCC PLLCAP PLLVSS PA15/CK RES PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A VSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 Programmer Mode D5 VCC D4 D3 D2 D1 D0 VSS XTAL MD3 EXTAL MD2 VCC FWE MD1 MD0 PLLVCC PLLCAP PLLVSS NC RES NC NC NC NC NC VSS VSS VSS VSS VSS VSS VSS Rev.5.00 Sep. 27, 2007 Page 12 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 MCU Mode AVSS PF6/AN6 PF7/AN7 AVCC VSS PE5/TIOC1B VCC PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 VSS PE11 PE12 PE13 Programmer Mode VSS VSS VSS VCC VSS NC VCC NC NC NC NC NC VSS NC NC NC Rev.5.00 Sep. 27, 2007 Page 13 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview 1.3.3 Pin Functions Table 1.2 lists the pin functions. Table 1.2 Pin Functions Symbol VCC I/O I Name Supply Function Connects to power supply. Connect all VCC pins to the system supply. No operation will occur if there are any open pins. VSS I Ground Connects to ground. Connect all VSS pins to the system ground. No operation will occur if there are any open pins. Clock PLLVCC PLLVSS PLLCAP EXTAL I I I I PLL supply PLL ground PLL capacitance External clock On-chip PLL oscillator supply. On-chip PLL oscillator ground. On-chip PLL oscillator external capacitance connection pin. Connect a crystal oscillator. Also, an external clock can be input to the EXTAL pin. Connect a crystal oscillator. Supplies the system clock to peripheral devices. Power-on reset when low Overflow output signal from WDT Determines the operating mode. Do not change input value during operation. Protects flash memory from being written or deleted. Non-maskable interrupt request pin. Enables selection of whether to accept on the rising or falling edge. Classification Power supply XTAL CK System control RES WDTOVF I O I O Crystal System clock Power-on reset Watchdog timer overflow Mode set Operating mode MD0 to MD3 I control FWP Interrupts NMI I I Flash memory write protect Non-maskable interrupt IRQ0 to IRQ3, IRQ6, IRQ7 Address bus A0 to A21 I Interrupt requests Maskable interrupt request pins. 0 to 3, 6,7 Allows selection of level input and edge input. Address bus Outputs addresses. O Rev.5.00 Sep. 27, 2007 Page 14 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Classification Data bus Bus control Symbol D0 to D15 CS0 to CS3 RD WRH WRL WAIT I/O I/O O O O O I Name Data bus Chip selects 0 to 3 Read Upper write Lower write Wait Function 16-bit bidirectional data bus Chip select signals for external memory or devices. Indicates reading from an external device. Indicates writing the upper 8 bits of external data. Indicates writing the lower 8 bits of external data. Input causes insertion of wait cycles into the bus cycle during external space access. Timing signal for DRAM row address strobe. Timing signal for DRAM column address strobe. Output when the upper 8 bits of data are accessed. CASL O Lower column address strobe Timing signal for DRAM column address strobe. Output when the lower 8 bits of data are accessed. RDWR AH O O DRAM read/write Address hold DRAM write strobe signal. Address hold timing signal for devices using an address/data multiplex bus. Input pins for external clocks to the MTU counter. RAS CASH O O Row address strobe Upper column address strobe TCLKA Multifunction Timer Pulse Unit TCLKB (MTU) TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D I MTU timer clock input I/O MTU input capture/output compare (channel 0) Channel 0 input capture input/output compare output/PWM output pins. Rev.5.00 Sep. 27, 2007 Page 15 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Classification Symbol I/O I/O Name MTU input capture/output compare (channel 1) MTU input capture/output compare (channel 2) DMA transfer request (channels 0, 1) DREQ request acknowledgment (channels 0, 1) DMA transfer strobe (channels 0, 1) Transmit data (channels 0, 1) Receive data (channels 0, 1) Serial clock (channels 0, 1) Analog supply Analog ground Analog input General purpose port Function Channel 1 input capture input/output compare output/PWM output pins. TIOC1A Multifunction Timer Pulse Unit TIOC1B (MTU) TIOC2A TIOC2B I/O Channel 2 input capture input/output compare output/PWM output pins. Direct memory access controller (DMAC) DREQ0 to DREQ1 DRAK0 to DRAK1 DACK0 to DACK1 I Input pin for external requests for DMA transfer. Output the input sampling acknowledgment of external DMA transfer requests. Output a strobe to the external I/O of external DMA transfer requests. SCI0, SCI1 transmit data output pins. SCI0, SCI1 receive data input pins. SCI0, SCI1 clock input/output pins. Analog supply; connected to VCC. Analog supply; connected to VSS. Analog signal input pins. General purpose input/output port pins. Each bit can be designated for input/output. O O Serial communication interface (SCI) TxD0 to TxD1 RxD0 to RxD1 SCK0 to SCK1 O I I/O I I I I/O A/D Converter AVCC AVSS AN0 to AN7 I/O ports PA0 to PA9, PA15 (SH7014) PA0 to PA15 (SH7016/17) PB2 to PB9 (SH7014) PB0 to PB9 (SH7016/17) I/O General purpose port General purpose input/output port pins. Each bit can be designated for input/output. PC0 to PC15 I/O (SH7016/17) General purpose port General purpose input/output port pins. Each bit can be designated for input/output. Rev.5.00 Sep. 27, 2007 Page 16 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Classification I/O ports Symbol I/O Name General purpose port Function General purpose input/output port pins. Each bit can be designated for input/output. PE0 to PE15 I/O General purpose port General purpose input/output port pins. Each bit can be designated for input/output. PF0 to PF7 I General purpose port General purpose input port pins. PD0 to PD15 I/O (SH7016/17) Usage Notes 1. Unused input pins should be pulled up or pulled down. 2. The WDTOVF pin should not be pulled down in the SH7017 F-ZTAT version. However, if it is necessary to pull this pin down, a resistance of 100 kΩ or higher should be used. Rev.5.00 Sep. 27, 2007 Page 17 of 716 REJ09B0398-0500 1. SH7014/16/17 Overview Rev.5.00 Sep. 27, 2007 Page 18 of 716 REJ09B0398-0500 2. CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers. 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. 0 2. Figure 2.1 General Registers Rev.5.00 Sep. 27, 2007 Page 19 of 716 REJ09B0398-0500 2. CPU 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows a control register. 31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 ST SR: Status register T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. This bit always read 0. The write value should always be 0. Bits I0 to I3: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. This bit always read 0. The write value should always be 0. 31 GBR 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area. 31 Figure 2.2 Control Registers Rev.5.00 Sep. 27, 2007 Page 20 of 716 REJ09B0398-0500 2. CPU 2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows a system register. 31 MACH MACL 0 Multiply and accumulate (MAC) registers high and low (MACH, MACL): Stores the results of multiply and accumulate operations. Procedure register (PR): Stores a return address from a subroutine procedure. Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. 31 PR 0 31 PC 0 Figure 2.3 System Registers 2.1.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I3 to I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Classification General registers Rev.5.00 Sep. 27, 2007 Page 21 of 716 REJ09B0398-0500 2. CPU 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4). 31 Longword 0 Figure 2.4 Longword Operand 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.5). Address m + 1 Address m 31 Byte Address 2n Address 4n 23 Byte Word Longword 15 Byte Address m + 3 7 Byte Word 0 Address m + 2 Figure 2.5 Byte, Word, and Longword Alignment 2.2.3 Immediate Data Format Byte (8-bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Rev.5.00 Sep. 27, 2007 Page 22 of 716 REJ09B0398-0500 2. CPU Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 2.3.1 Instruction Features RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 35 ns at 28.7 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data (table 2.2). Table 2.2 Sign Extension of Word Data Description Data is sign-extended to 32 bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. Example of Conventional CPU ADD.W #H'1234,R0 SH7014/16/17 CPU MOV.W ADD @(disp,PC),R1 R1,R0 ·········· .DATA.W H'1234 Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Rev.5.00 Sep. 27, 2007 Page 23 of 716 REJ09B0398-0500 2. CPU Table 2.3 Delayed Branch Instructions Description Executes an ADD before branching to TRGET Example of Conventional CPU ADD.W BRA R1,R0 TRGET SH7014/16/17 CPU BRA ADD TRGET R1,R0 Multiplication/Accumulation Operation: 16-bit × 16-bit → 32-bit multiplication operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit and 32-bit × 32-bit + 64bit → 64-bit multiplication/accumulation operations are executed in two to four cycles. T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed (table 2.4). Table 2.4 T Bit Description T bit is set when R0 ≥ R1. The program branches to TRGET0 when R0 ≥ R1 and to TRGET1 when R0 < R1. Example of Conventional CPU CMP.W BGE BLT R1,R0 TRGET0 TRGET1 #1,R0 TRGET SH7014/16/17 CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET T bit is not changed by ADD. T bit is SUB.W set when R0 = 0. The program BEQ branches if R0 = 0. Immediate Data: Byte (8-bit) immediate data resides in instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5). Rev.5.00 Sep. 27, 2007 Page 24 of 716 REJ09B0398-0500 2. CPU Table 2.5 Immediate Data Accessing SH7014/16/17 CPU MOV MOV.W .DATA.W #H'12,R0 @(disp,PC),R0 ................. H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 MOV.L #H'12345678,R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 Classification 8-bit immediate 16-bit immediate 32-bit immediate MOV.L Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing SH7014/16/17 CPU MOV.L MOV.B .DATA.L @(disp,PC),R1 @R1,R0 .................. H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0 Classification Absolute address 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the preexisting displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing SH7014/16/17 CPU MOV.W MOV.W .DATA.W @(disp,PC),R0 @(R0,R1),R2 .................. H'1234 Note: @(disp,PC) accesses the immediate data. Rev.5.00 Sep. 27, 2007 Page 25 of 716 REJ09B0398-0500 Example of Conventional CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement 2. CPU 2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Mode Direct register addressing Indirect register addressing Post-increment indirect register addressing Addressing Modes and Effective Addresses Instruction Format Effective Addresses Calculation Rn @Rn The effective address is register Rn. (The operand is the contents of register Rn.) The effective address is the content of register Rn. Rn Rn Equation ⎯ Rn @Rn+ The effective address is the content of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn Rn (After the instruction executes) Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Byte: Rn − 1 → Rn Word: Rn − 2 → Rn Longword: Rn − 4 → Rn (Instruction executed with Rn after calculation) Pre-decrement indirect register addressing @–Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn − 1/2/4 1/2/4 − Rn − 1/2/4 Rev.5.00 Sep. 27, 2007 Page 26 of 716 REJ09B0398-0500 2. CPU Addressing Mode Indirect register addressing with displacement Instruction Format Effective Addresses Calculation @(disp:4, The effective address is Rn plus a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4 Equation Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Indirect indexed @(R0, Rn) The effective address is the Rn value plus R0. register Rn addressing + R0 Rn + R0 Rn + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the GBR value plus an GBR) 8-bit displacement (disp). The value of disp is zeroextended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) × 1/2/4 + GBR + disp × 1/2/4 Byte: GBR + disp Word: GBR + disp × 2 Longword: GBR + disp × 4 Rev.5.00 Sep. 27, 2007 Page 27 of 716 REJ09B0398-0500 2. CPU Addressing Mode Instruction Format Effective Addresses Calculation Equation Indirect indexed @(R0, GBR) The effective address is the GBR value plus the R0. GBR + R0 GBR addressing GBR + R0 GBR + R0 PC relative addressing with displacement @(disp:8, The effective address is the PC value plus an 8-bit PC) displacement (disp). The value of disp is zeroextended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) × 2/4 (for longword) PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 Word: PC + disp × 2 Longword: PC & H'FFFFFFFC + disp × 4 + Rev.5.00 Sep. 27, 2007 Page 28 of 716 REJ09B0398-0500 2. CPU Addressing Mode PC relative addressing Instruction Format Effective Addresses Calculation disp:8 Equation The effective address is the PC value sign-extended PC + disp × 2 with an 8-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) × 2 + PC + disp × 2 disp:12 The effective address is the PC value sign-extended PC + disp × 2 with a 12-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) × 2 + PC + disp × 2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + Rn PC + Rn Immediate addressing #imm:8 #imm:8 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions are zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions are sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and is quadrupled. ⎯ ⎯ ⎯ Rev.5.00 Sep. 27, 2007 Page 29 of 716 REJ09B0398-0500 2. CPU 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Table 2.9 Instruction Formats Source Operand ⎯ 0 xxxx xxxx xxxx Instruction Formats 0 format 15 xxxx Destination Operand ⎯ Example NOP n format 15 xxxx nnnn xxxx xxxx 0 ⎯ Control register or system register Control register or system register nnnn: Direct register nnnn: Direct register nnnn: Indirect predecrement register Control register or system register Control register or system register ⎯ MOVT STS Rn MACH,Rn STC.L SR,@-Rn m format 15 xxxx mmmm xxxx 0 xxxx mmmm: Direct register mmmm: Indirect post-increment register mmmm: Direct register LDC LDC.L Rm,SR @Rm+,SR JMP BRAF @Rm Rm mmmm: PC ⎯ relative using Rm Rev.5.00 Sep. 27, 2007 Page 30 of 716 REJ09B0398-0500 2. CPU Source Operand mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiply/ accumulate) nnnn*: Indirect post-increment register (multiply/ accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 xxxx xxxx mmmmdddd: indirect register with displacement R0 (Direct register) Destination Operand nnnn: Direct register nnnn: Indirect register MACH, MACL Instruction Formats nm format 15 0 xxxx nnnn mmmm xxxx Example ADD MOV.L Rm,Rn Rm,@Rn MAC.W @Rm+,@Rn+ nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0 0 nnnn dddd nnnndddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register MOV.B R0,@(disp,Rn) nmd format 15 0 xxxx nnnn mmmm dddd mmmm: Direct register MOV.L Rm,@(disp,Rn) mmmmdddd: Indirect register with displacement MOV.L @(disp,Rm),Rn Rev.5.00 Sep. 27, 2007 Page 31 of 716 REJ09B0398-0500 2. CPU Source Operand 0 xxxx dddd dddd Instruction Formats d format 15 xxxx Destination Operand R0 (Direct register) Example MOV.L @(disp,GBR),R0 dddddddd: Indirect GBR with displacement R0 (Direct register) dddddddd: PC relative with displacement dddddddd: PC relative dddddddd: Indirect GBR with displacement R0 (Direct register) MOV.L R0,@(disp,GBR) MOVA @(disp,PC),R0 BF BRA label label ⎯ ⎯ d12 format 15 xxxx dddd nd8 format 15 xxxx nnnn i format 15 xxxx 0 dddd dddd 0 dddd dddd 0 dddddddddddd: PC relative (label = disp + PC) nnnn: Direct register MOV.L @(disp,PC),Rn dddddddd: PC relative with displacement iiiiiiii: Immediate Indirect indexed GBR R0 (Direct register) ⎯ nnnn: Direct register AND.B #imm,@(R0,GBR) AND TRAPA ADD #imm,R0 #imm #imm,Rn xxxx iiii iiii iiiiiiii: Immediate iiiiiiii: Immediate ni format 15 xxxx nnnn Note: * iiiiiiii: Immediate 0 iiii iiii In multiply/accumulate instructions, nnnn is the source register. Rev.5.00 Sep. 27, 2007 Page 32 of 716 REJ09B0398-0500 2. CPU 2.4 Instruction Set by Classification Table 2.10 Classification of Instructions Operation Classification Types Code Function Data transfer 5 MOV Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check 33 No. of Instructions 39 MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply/accumulate, double-length multiply/accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Rev.5.00 Sep. 27, 2007 Page 33 of 716 REJ09B0398-0500 2. CPU Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 11 14 No. of Instructions 14 Rev.5.00 Sep. 27, 2007 Page 34 of 716 REJ09B0398-0500 2. CPU Operation Classification Types Code Function System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Shift into power-down mode Storing control register data Storing system register data Trap exception handling 142 No. of Instructions 31 Table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification. Rev.5.00 Sep. 27, 2007 Page 35 of 716 REJ09B0398-0500 2. CPU Table 2.11 Instruction Code Format Item Instruction Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement*1 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 . . . 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted*2 Value of T bit after instruction is executed. An em-dash (⎯) in the column means no change. Instruction code MSB ↔ LSB Operation →, ← (xx) M/Q/T & | ^ ~ n ⎯ ⎯ Execution cycles T bit Notes: 1. Depending on the operand size, displacement is scaled ×1, ×2, or ×4. For details, see the SH-1/SH-2/SH-DSP Software Manual. 2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. Rev.5.00 Sep. 27, 2007 Page 36 of 716 REJ09B0398-0500 2. CPU Table 2.12 Data Transfer Instructions Instruction MOV #imm,Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 Operation #imm → Sign extension → Rn (disp × 2 + PC) → Sign extension → Rn (disp × 4 + PC) → Rn Rm → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → Sign extension → Rn (Rm) → Sign extension → Rn (Rm) → Rn Exec. Cycles 1 1 1 1 1 1 1 1 1 1 T Bit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B @(disp,Rm),R0 MOV.W @(disp,Rm),R0 MOV.L @(disp,Rm),Rn MOV.B Rm,@(R0,Rn) Rn − 1 → Rn, Rm → (Rn) 1 Rn − 2 → Rn, Rm → (Rn) 1 Rn − 4 → Rn, Rm → (Rn) 1 (Rm) → Sign extension → Rn,Rm + 1 → Rm (Rm) → Sign extension → Rn,Rm + 2 → Rm (Rm) → Rn,Rm + 4 → Rm R0 → (disp + Rn) R0 → (disp × 2 + Rn) Rm → (disp × 4 + Rn) (disp + Rm) → Sign extension → R0 (disp × 2 + Rm) → Sign extension → R0 (disp × 4 + Rm) → Rn Rm → (R0 + Rn) 1 1 1 1 1 1 1 1 1 1 Rev.5.00 Sep. 27, 2007 Page 37 of 716 REJ09B0398-0500 2. CPU Exec. Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0 Rn Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 Operation Rm → (R0 + Rn) Rm → (R0 + Rn) (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Rn R0 → (disp + GBR) R0 → (disp × 2 + GBR) R0 → (disp × 4 + GBR) (disp + GBR) → Sign extension → R0 (disp × 2 + GBR) → Sign extension → R0 (disp × 4 + GBR) → R0 disp × 4 + PC → R0 T → Rn Rm → Swap the bottom two bytes → Rn Rm → Swap two consecutive words → Rn Rm: Middle 32 bits of Rn → Rn T Bit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn 0010nnnnmmmm1101 1 ⎯ Rev.5.00 Sep. 27, 2007 Page 38 of 716 REJ09B0398-0500 2. CPU Table 2.13 Arithmetic Operation Instructions Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 Operation Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, Carry → T Rn + Rm → Rn, Overflow → T If R0 = imm, 1 → T If Rn = Rm, 1 → T If Rn ≥ Rm with unsigned data, 1 → T Exec. Cycles 1 1 1 1 1 1 1 T Bit ⎯ ⎯ Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 CMP/EQ #imm,R0 CMP/EQ Rm,Rn CMP/HS Rm,Rn CMP/GE Rm,Rn CMP/HI Rm,Rn CMP/GT Rm,Rn CMP/PL Rn CMP/PZ Rn CMP/STR Rm,Rn If Rn ≥ Rm with signed 1 data, 1 → T If Rn > Rm with unsigned data, 1 → T If Rn > Rm with signed data, 1 → T If Rn > 0, 1 → T If Rn ≥ 0, 1 → T If Rn and Rm have an equivalent byte, 1→T Single-step division (Rn/Rm) 1 1 1 1 1 DIV1 DIV0S DIV0U Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 1 MSB of Rn → Q, MSB 1 of Rm → M, M ^ Q → T 0 → M/Q/T 1 Rev.5.00 Sep. 27, 2007 Page 39 of 716 REJ09B0398-0500 2. CPU Exec. Cycles 2 to 4* Instruction DMULS.L Rm,Rn Instruction Code 0011nnnnmmmm1101 Operation Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bit Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bit Rn − 1 → Rn, when Rn is 0, 1 → T. When Rn is nonzero, 0 → T A byte in Rm is signextended → Rn A word in Rm is signextended → Rn A byte in Rm is zeroextended → Rn A word in Rm is zeroextended → Rn Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 → 64 bit Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bit Rn × Rm → MACL, 32 × 32 → 32 bit Signed operation of Rn × Rm → MAC 16 × 16 → 32 bit Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bit 0 − Rm → Rn 0 − Rm − T → Rn, Borrow → T T Bit ⎯ DMULU.L Rm,Rn 0011nnnnmmmm0101 2 to 4* ⎯ DT Rn 0100nnnn00010000 1 Comparison result ⎯ ⎯ ⎯ ⎯ EXTS.B Rm,Rn EXTS.W Rm,Rn EXTU.B Rm,Rn EXTU.W Rm,Rn MAC.L @Rm+,@Rn+ 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 1 1 1 1 3/ ⎯ (2 to 4)* 3/(2)* ⎯ MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 0010nnnnmmmm1111 2 to 4* 1 to 3* ⎯ ⎯ MULS.W Rm,Rn MULU.W Rm,Rn 0010nnnnmmmm1110 1 to 3* ⎯ NEG NEGC Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 1 1 ⎯ Borrow Rev.5.00 Sep. 27, 2007 Page 40 of 716 REJ09B0398-0500 2. CPU Exec. Cycles 1 1 1 Instruction SUB SUBC SUBV Note: * Rm,Rn Rm,Rn Rm,Rn Instruction Code 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 Operation Rn − Rm → Rn Rn − Rm − T → Rn, Borrow → T Rn − Rm → Rn, Underflow → T T Bit ⎯ Borrow Overflow The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) Rev.5.00 Sep. 27, 2007 Page 41 of 716 REJ09B0398-0500 2. CPU Table 2.14 Logic Operation Instructions Instruction AND AND Rm,Rn #imm,R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ∼Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) If (Rn) is 0, 1 → T; 1 → MSB of (Rn)* Rn & Rm; if the result is 0, 1 → T R0 & imm; if the result is 0, 1 → T (R0 + GBR) & imm; if the result is 0, 1 → T Rn ^ Rm → Rn R0 ^ imm → R0 (R0 + GBR) ^ imm → (R0 + GBR) Exec. Cycles 1 1 3 1 1 1 3 4 1 1 3 1 1 3 T Bit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Test result Test result Test result Test result ⎯ ⎯ ⎯ AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) TAS.B @Rn* TST TST Rm,Rn #imm,R0 TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0 XOR.B #imm,@(R0,GBR) Note: * The on-chip DMAC bus cycles are not inserted between the read and write cycles of TAS instruction execution. Rev.5.00 Sep. 27, 2007 Page 42 of 716 REJ09B0398-0500 2. CPU Table 2.15 Shift Instructions Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T T ← Rn ← 0 MSB → Rn → T T ← Rn ← 0 0 → Rn → T Rn2 → Rn Rn8 → Rn Rn16 → Rn Exec. Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit MSB LSB MSB LSB MSB LSB MSB LSB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SHLL16 Rn SHLR16 Rn Rev.5.00 Sep. 27, 2007 Page 43 of 716 REJ09B0398-0500 2. CPU Table 2.16 Branch Instructions Instruction BF label Instruction Code Operation Exec. Cycles 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 T Bit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10001011dddddddd If T = 0, disp × 2 + PC → PC; if T = 1, NOP 10001111dddddddd Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, NOP 10001001dddddddd If T = 1, disp × 2 + PC → PC; if T = 0, NOP 10001101dddddddd Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, NOP 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 0000mmmm00100011 Delayed branch, Rm + PC → PC 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC 0100mmmm00101011 Delayed branch, Rm → PC 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 0000000000001011 Delayed branch, PR → PC BF/S label BT label BT/S label BRA label BRAF Rm BSR label BSRF Rm JMP JSR RTS @Rm @Rm Note: One state when it does not branch. Rev.5.00 Sep. 27, 2007 Page 44 of 716 REJ09B0398-0500 2. CPU Table 2.17 System Control Instructions Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 SR,Rn GBR,Rn VBR,Rn SR,@–Rn GBR,@–Rn VBR,@–Rn MACH,Rn MACL,Rn PR,Rn 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Operation 0→T 0 → MACH, MACL Rm → SR Rm → GBR Rm → VBR (Rm) → SR, Rm + 4 → Rm (Rm) → GBR, Rm + 4 → Rm (Rm) → VBR, Rm + 4 → Rm Rm → MACH Rm → MACL Rm → PR (Rm) → MACL, Rm + 4 → Rm (Rm) → PR, Rm + 4 → Rm No operation Delayed branch, stack area → PC/SR 1→T Sleep SR → Rn GBR → Rn VBR → Rn Rn − 4 → Rn, SR → (Rn) Rn − 4 → Rn, GBR → (Rn) Rn − 4 → Rn, BR → (Rn) MACH → Rn MACL → Rn PR → Rn Exec. Cycles 1 1 1 1 1 3 3 3 1 1 1 T Bit 0 ⎯ LSB ⎯ ⎯ LSB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS (Rm) → MACH, Rm + 4 → Rm 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1 Rev.5.00 Sep. 27, 2007 Page 45 of 716 REJ09B0398-0500 2. CPU Exec. Cycles 1 1 1 8 Instruction STS.L STS.L STS.L TRAPA MACH,@–Rn MACL,@–Rn PR,@–Rn #imm Instruction Code 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn − 4 → Rn, MACH → (Rn) Rn − 4 → Rn, MACL → (Rn) Rn − 4 → Rn, PR → (Rn) PC/SR → stack area, (imm) → PC T Bit ⎯ ⎯ ⎯ ⎯ Note: The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) and the register used by the next instruction are the same. 2.5 2.5.1 Processing States State Transitions The CPU has four processing states: reset, exception processing, program execution and powerdown. Figure 2.6 shows the transitions between the states. Rev.5.00 Sep. 27, 2007 Page 46 of 716 REJ09B0398-0500 2. CPU From any state when RES = 0 Power-on reset state RES = 1 Reset states Exception processing state When an interrupt source or DMA address error occurs Exception processing source occurs Exception processing ends NMI interrupt source occurs Program execution state SBY bit cleared for SLEEP instruction SBY bit set for SLEEP instruction Sleep mode Standby mode Power-down state Figure 2.6 Transitions between Processing States Rev.5.00 Sep. 27, 2007 Page 47 of 716 REJ09B0398-0500 2. CPU Reset State: The CPU resets in the reset state. When the RES pin level goes low, a power-on reset results. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the power-down state. This state has two modes: sleep mode and standby mode. 2.5.2 Power-Down State Besides the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts, lowering power consumption. There are two power-down state modes: sleep mode and standby mode. Sleep Mode: When standby bit SBY (in the standby control register SBYCR) is cleared to 0 and a SLEEP instruction executed, the CPU moves from program execution state to sleep mode. In the sleep mode, the CPU halts and the contents of its internal registers and the data in on-chip cache (or on-chip RAM) is maintained. The on-chip peripheral modules other than the CPU do not halt in the sleep mode. To return from sleep mode, use a power-on reset, any interrupt, or a DMA address error; the CPU returns to the ordinary program execution state through the exception processing state. Standby Mode: To enter the standby mode, set the standby bit SBY (in the standby control register SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip peripheral module, and oscillator functions are halted. However, when entering standby mode, the DMA master enable bit of the DMAC should be set to 0. If multiplication-related instructions are being executed at the time of entry into standby mode, the values of MACH and MACL will become undefined. Rev.5.00 Sep. 27, 2007 Page 48 of 716 REJ09B0398-0500 2. CPU To return from standby mode, use a power-on reset or an NMI interrupt. For resets, the CPU returns to ordinary program execution state through the exception processing state when placed in a reset state for the duration of the oscillator stabilization time. For NMI interrupts, the CPU returns to ordinary program execution state through the exception processing state after the oscillator stabilization time has elapsed. In this mode, power consumption drops markedly, since the oscillator stops (table 2.18). Table 2.18 Power-Down State State On-Chip On-Chip Cache or I/O Transition Peripheral CPU On-Chip Port Mode Conditions Clock CPU Modules Registers RAM Pins Sleep Execute Run SLEEP instruction with SBY bit cleared to 0 in SBYCR Stand- Execute Halt by SLEEP instruction with SBY bit set to 1 in SBYCR Note: * Halt Run Held Held Held Canceling • • • Interrupt DMA address error Power-on reset NMI interrupt Power-on reset Halt Halt and initialize* Held Held Held or • Hi-Z • (selectable) Differs depending on the peripheral module and pin. Rev.5.00 Sep. 27, 2007 Page 49 of 716 REJ09B0398-0500 2. CPU Rev.5.00 Sep. 27, 2007 Page 50 of 716 REJ09B0398-0500 3. Operating Modes Section 3 Operating Modes 3.1 Operating Modes, Types, and Selection This LSI has five operating modes and three clock modes, determined by the setting of the mode pins (MD3 to MD0). Do not change the mode pin settings during LSI operation (while power is on). Table 3.1 indicates the setting method for the operating mode. Table 3.1 Operating Mode Setting On-Chip ROM Not Active Not Active Active Active Active Pin Setting Mode 1 1 No. FWP MD3* MD2* MD1 MD0 Mode Name 0 1 2* 3* 4 4 CS0 Area 8-bit space 16-bit space 8/16-bit space* ⎯ 8/16-bit space* ⎯ 2 2 1 1 1 1 0 0 0 0 1 x x x x x x x x 1 x x x x x x x x 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 MCU mode 0 MCU mode 1 MCU mode 2 Single chip mode Boot mode* 3 User programming 3 mode* Flash programmer 3 mode* Active 8/16-bit space* ⎯ ⎯ 2 Active Notes: 1. 2. 3. 4. MD2 and MD3 pins select the clock mode in modes 0 to 3 (table 3.2). Set by BCR1 of BSC. Only F-ZTAT. Only SH7016, SH7017. Table 3.2 indicates the setting method for the clock mode. Table 3.2 MD3 0 0 1 1 Clock Mode Setting MD2 0 1 0 1 Clock Mode PLL ON × 1 PLL ON × 2 PLL ON × 4 Reserved Rev.5.00 Sep. 27, 2007 Page 51 of 716 REJ09B0398-0500 3. Operating Modes 3.2 Explanation of Operating Modes Table 3.3 describes the operating modes. Table 3.3 Mode (MCU) Mode 0 (MCU) Mode 1 (MCU) Mode 2 Mode 3 (single chip mode) Clock mode Operating Modes Description CS0 area becomes an external memory space with 8-bit bus width. CS0 area becomes an external memory space with 16-bit bus width. The on-chip ROM becomes effective. The bus width for the on-chip ROM space is 32 bit. Any port can be used, but external addresses can not be employed. The input waveform frequency can be used as is, doubled or quadrupled as an internal clock in modes 0 to 3. 3.3 Pin Configuration Table 3.4 describes the function of each operating mode related pin. Table 3.4 Pin Name XTAL EXTAL PLLCAP MD0 MD1 MD2 MD3 Operating Mode Pin Function Input/Output Input Input Input Input Input Input Input Function Connects to a crystal oscillator Connects to a crystal oscillator, or used for external clock input pin Connects to a capacitor for PLL circuit operation Designates operating mode through the level applied to this pin Designates operating mode through the level applied to this pin Designates clock mode through the level applied to this pin Designates clock mode through the level applied to this pin Rev.5.00 Sep. 27, 2007 Page 52 of 716 REJ09B0398-0500 4. Clock Pulse Generator (CPG) Section 4 Clock Pulse Generator (CPG) 4.1 Overview This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ), as well as the internal clock (φ/2 to φ/8192). The CPG consists of an oscillator, a PLL, and a prescaler. 4.1.1 Block Diagram A block diagram of the clock pulse generator is shown in figure 4.1. PLLCAP CK EXTAL Oscillator XTAL PLL circuit Prescaler MD2 MD3 Clock mode control circuitry φ φ/2 to φ/8192 Within the LSI Figure 4.1 Block Diagram of the Clock Pulse Generator Rev.5.00 Sep. 27, 2007 Page 53 of 716 REJ09B0398-0500 4. Clock Pulse Generator (CPG) 4.2 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.2.1 Connecting a Crystal Oscillator Circuit Configuration: A crystal oscillator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.1. Use a 4 to 10 MHz crystal oscillator (consult your dealer concerning the compatibility of the crystal oscillator and the LSI). CL1 EXTAL 4 to 10 MHz XTAL Rd CL2 CL1 = CL2 = 18 to 22 pF (Recommended value) Figure 4.2 Connection of the Crystal Oscillator (Example) Table 4.1 Damping Resistance Values (Recommended Values) Frequency (MHz) Parameter Rd (Ω) 4 500 8 200 10 0 Crystal Oscillator: Figure 4.3 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 4.2. L EXTAL Co CL Rs XTAL Figure 4.3 Crystal Oscillator Equivalent Circuit Rev.5.00 Sep. 27, 2007 Page 54 of 716 REJ09B0398-0500 4. Clock Pulse Generator (CPG) Table 4.2 Crystal Oscillator Parameters Frequency (MHz) Parameter Rs max (Ω) Co max (pF) 4 120 7 8 80 7 10 60 7 Notes on Board Design: When connecting a crystal oscillator, observe the following precautions: • To prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator circuitry. • When designing the board, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Figures 4.4 and 4.5 show the precautions regarding oscillator block board settings. Crossing of signal lines prohibited CL1 XTAL CL2 EXTAL Figure 4.4 Cautions for Oscillator Circuit System Board Design Rev.5.00 Sep. 27, 2007 Page 55 of 716 REJ09B0398-0500 4. Clock Pulse Generator (CPG) External circuitry such as that shown in figure 4.5 is recommended around the PLL. R1: 3 kΩ PLLCAP Rp: 200 Ω PLLVCC CPB: 0.1 μF* PLLVSS VCC CB: 0.1 μF* VSS C1: 470 pF Note: * CB and CPB are laminated ceramic capacitors (Recommended values) Figure 4.5 Cautions for Use of PLL Oscillator Circuit Place oscillation stabilization capacitor C1 and resistor R1 near the PLL CAP pin, and ensure that these lines do not cross any other signal lines. Supply the C1 ground from PLL VSS. Also, separate PLL VCC and PLL VSS, and the other VCC and VSS pins, from the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. 4.2.2 External Clock Input Method Figure 4.6 shows an example of an external clock input connection. In this case, make the external clock high level to stop it when in standby mode. During operation, make the external input clock frequency 4 to 10 MHz. When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to delay until after the oscillation stabilization time (upon power-on) or after release from standby, in order to ensure the PLL stabilization time. Rev.5.00 Sep. 27, 2007 Page 56 of 716 REJ09B0398-0500 4. Clock Pulse Generator (CPG) EXTAL XTAL Open External clock input 4 to 10 MHz Figure 4.6 Example of External Clock Connection 4.3 Prescaler The prescaler divides the system clock (φ) to generate an internal clock (φ/2 to φ/8192) for supply to peripheral modules. Rev.5.00 Sep. 27, 2007 Page 57 of 716 REJ09B0398-0500 4. Clock Pulse Generator (CPG) Rev.5.00 Sep. 27, 2007 Page 58 of 716 REJ09B0398-0500 5. Exception Processing Section 5 Exception Processing 5.1 5.1.1 Overview Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 5.1 Exception Reset Types of Exception Processing and Priority Order Source Power-on reset Priority High Address error CPU address error DMAC address error Interrupt NMI User break IRQ On-chip peripheral modules: • • • • • • • Instructions Direct memory access controller (DMAC) Multifunction timer/pulse unit (MTU) Serial communication interface (SCI) A/D converter (A/D) Compare match timer (CMT) Watchdog timer (WDT) Bus state controller (BSC) Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay branch Low 1 2 instruction* or instructions that rewrite the PC* ) Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF. Rev.5.00 Sep. 27, 2007 Page 59 of 716 REJ09B0398-0500 5. Exception Processing 5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Exception Timing of Exception Source Detection and the Start of Exception Processing Source Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Trap instruction General illegal instructions Illegal slot instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. Power-on reset Address error Interrupts Instructions When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses). See section 5.1.3, Exception Processing Vector Table, for more information. 0 is then written to the vector base register (VBR) and 1111 is written to the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3 to I0). For address error and instruction exception processing, the I3 to I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. Rev.5.00 Sep. 27, 2007 Page 60 of 716 REJ09B0398-0500 5. Exception Processing 5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table Vector Numbers PC SP (Reserved by system) (Reserved by system) General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) (Reserved by system) CPU address error DMAC address error Interrupts NMI User break (Reserved by system) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 : 31 Trap instruction (user vector) 32 : 63 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF Exception Sources Power-on reset Rev.5.00 Sep. 27, 2007 Page 61 of 716 REJ09B0398-0500 5. Exception Processing Vector Numbers IRQ0 IRQ1 IRQ2 IRQ3 (Reserved by system) (Reserved by system) Interrupt IRQ6 IRQ7 On-chip peripheral module* 64 65 66 67 68 69 70 71 72 : 255 Note: * Exception Sources Interrupts Vector Table Address Offset H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F H'00000120 to H'00000124 : H'000003FC to H'000003FF The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller, and table 6.3, Interrupt Exception Processing Vectors and Priorities. Table 5.4 Calculating Exception Processing Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) × 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Rev.5.00 Sep. 27, 2007 Page 62 of 716 REJ09B0398-0500 5. Exception Processing 5.2 5.2.1 Resets Power-on Reset When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 tcyc (when the clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See Appendix B, Pin Status, for the status of individual pins during the power-on reset status. In the power-on reset status, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU will then operate as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the program counter (PC) and SP and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. Rev.5.00 Sep. 27, 2007 Page 63 of 716 REJ09B0398-0500 5. Exception Processing 5.3 5.3.1 Address Errors Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.5. Table 5.5 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Instruction fetched from external memory space when in single chip mode Data read/write CPU or Word data accessed from even address DMAC Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* External memory space accessed in single-chip mode Note: * See section 8, Bus State Controller. Address Errors None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) Address error occurs Address error occurs Instruction CPU fetch Rev.5.00 Sep. 27, 2007 Page 64 of 716 REJ09B0398-0500 5. Exception Processing 5.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed branch. 5.4 5.4.1 Interrupts Interrupt Sources Table 5.6 shows the sources that start up interrupt exception processing. These are divided into NMI, IRQ and on-chip peripheral modules. Table 5.6 Type NMI IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) IRQ0 to IRQ3, IRQ6, IRQ7 (external input) Direct memory access controller (DMAC) Multifunction timer pulse unit (MTU) Serial communication interface (SCI) A/D converter Compare match timer (CMT) Watchdog timer (WDT) Bus state controller (BSC) Number of Sources 1 6 2 13 8 1 2 1 1 Each interrupt source is allocated a different vector number and vector table offset. See section 6, Interrupt Controller, and table 6.3, Interrupt Exception Processing Vectors and Priorities, for more information on vector numbers and vector table address offsets. Rev.5.00 Sep. 27, 2007 Page 65 of 716 REJ09B0398-0500 5. Exception Processing 5.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority level setting registers A through H (IPRA to IPRH) as shown in table 5.7. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers A to H (IPRA to IPRH), for more information on IPRA to IPRH. Table 5.7 Type NMI IRQ On-chip peripheral module Interrupt Priority Order Priority Level 16 0 to 15 0 to 15 Comment Fixed priority level. Cannot be masked. Set with interrupt priority level setting registers A through H (IPRA to IPRH). Set with interrupt priority level setting registers A through H (IPRA to IPRH). 5.4.3 Interrupt Exception Processing When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt exception processing. Rev.5.00 Sep. 27, 2007 Page 66 of 716 REJ09B0398-0500 5. Exception Processing 5.5 5.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.8. Table 5.8 Type Trap instructions Illegal slot instructions Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC Undefined code anywhere besides in a delay slot Comment ⎯ Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF ⎯ General illegal instructions 5.5.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. Rev.5.00 Sep. 27, 2007 Page 67 of 716 REJ09B0398-0500 5. Exception Processing 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. Illegal slot exception processing also starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 5.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. Rev.5.00 Sep. 27, 2007 Page 68 of 716 REJ09B0398-0500 5. Exception Processing 5.6 When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interruptdisabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.9. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.9 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction*1 Immediately after an interrupt-disabled instruction*2 Address Error Not accepted Accepted Interrupt Not accepted Not accepted Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L 5.6.1 Immediately after a Delayed Branch Instruction When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction located immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after an Interrupt-Disabled Instruction When an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors are accepted. Rev.5.00 Sep. 27, 2007 Page 69 of 716 REJ09B0398-0500 5. Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 5.10. Table 5.10 Types of Stack Status After Exception Processing Ends Types Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Stack Status Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits General illegal instruction SP Start address of illegal instruction SR 32 bits 32 bits Interrupt SP Address of instruction after executed instruction 32 bits SR 32 bits Illegal slot instruction SP Jump destination address of delay branch instruction 32 bits SR 32 bits Rev.5.00 Sep. 27, 2007 Page 70 of 716 REJ09B0398-0500 5. Exception Processing 5.8 5.8.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. Address errors will then also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is −4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. Rev.5.00 Sep. 27, 2007 Page 71 of 716 REJ09B0398-0500 5. Exception Processing Rev.5.00 Sep. 27, 2007 Page 72 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) 6.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 Features The INTC has the following features: • 16 levels of interrupt priority: By setting the eight interrupt-priority level registers, the priorities of IRQ interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. • NMI noise canceler function: NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. 6.1.2 Block Diagram Figure 6.1 is a block diagram of the INTC. Rev.5.00 Sep. 27, 2007 Page 73 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7 Input control CPU Priority ranking judgment Comparator Interrupt request SR DMAC MTU CMT SCI A/D WDT BSC (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 I0 CPU ICR ISR IPR IPRA to IPRH Bus interface Module bus INTC Legend: DMAC: Direct memory access controller MTU: Multifunction timer pulse unit CMT: Compare match timer Serial communication interface SCI: A/D converter A/D: WDT: Watchdog timer BSC: Bus state controller (DRAM Interrupt control register ICR: IRQ ststus register ISR: IPRA to IPRH: Interrupt priority registers A to H Status register SR: Figure 6.1 INTC Block Diagram Rev.5.00 Sep. 27, 2007 Page 74 of 716 REJ09B0398-0500 Internal bus 6. Interrupt Controller (INTC) 6.1.3 Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Name Non-maskable interrupt input pin Interrupt request input pins Pin Configuration Abbreviation NMI IRQ0 to IRQ3, IRQ6, IRQ7 I/O I I Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals 6.1.4 Register Configuration The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 6.2 Name Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt control register IRQ status register Register Configuration Abbr. IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH ICR ISR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value Address H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 * 1 Access Sizes 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 H'FFFF8348 H'FFFF834A H'FFFF834C H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A R(W)* H'0000 Notes: 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags. Rev.5.00 Sep. 27, 2007 Page 75 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.2 Interrupt Sources There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 6.2.1 NMI Interrupts The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. 6.2.2 IRQ Interrupts IRQ interrupts are requested by input from pins IRQ0 to IRQ3, IRQ6, IRQ7. Set the IRQ sense select bits (IRQ0S to IRQ3S, IRQ6S, IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A and B (IPRA and IPRB). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request detection results are maintained until the interrupt request is accepted. Confirmation that IRQ interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Rev.5.00 Sep. 27, 2007 Page 76 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: • Direct memory access controller (DMAC) • Multifunction timer pulse unit (MTU) • Compare match timer (CMT) • Serial communication interface (SCI) • A/D converter (A/D) • Watchdog timer (WDT) • Bus state controller (BSC) A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers C to H (IPRC to IPRH). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.4 Interrupt Exception Vectors and Priority Rankings Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. See table 5.4, Calculating Exception Processing Vector Table Addresses. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to H (IPRA to IPRH). The ranking of interrupt sources for IPRC to IPRH, however, must be the order listed under Priority Order Within IPR Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3. Rev.5.00 Sep. 27, 2007 Page 77 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Table 6.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Vector Table Vector Address No. Offset 11 64 65 66 67 70 71 DEI0 DEI1 TGI0A TGI0B TGI0C TGI0D TCI0V 72 76 88 89 90 91 92 H'0000002C to H'0000002F H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000118 to H'0000011B H'0000011C to H'0000011F H'00000120 to H'00000123 H'00000130 to H'00000133 H'00000160 to H'00000163 H'00000164 to H'00000167 H'00000168 to H'0000016B H'0000016C to H'0000016F H'00000170 to H'00000173 Interrupt Priority (Initial Value) 16 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRD (11 to 8) Low ⎯ Low Priority within IPR Default Corresponding Setting Range Priority IPR (Bits) ⎯ IPRA (15 to 12) IPRA (11 to 8) IPRA (7 to 4) IPRA (3 to 0) IPRB (7 to 4) IPRB (3 to 0) IPRC (15 to 12) IPRC (11 to 8) IPRD (15 to 12) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ High High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ6 IRQ7 DMAC0 DMAC1 MTU0 Rev.5.00 Sep. 27, 2007 Page 78 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Interrupt Vector Vector Table Vector Address No. Offset 96 97 100 101 104 105 108 109 128 129 130 131 132 133 134 135 H'00000180 to H'00000183 H'00000184 to H'00000187 H'00000190 to H'00000193 H'00000194 to H'00000197 H'000001A0 to H'000001A3 H'000001A4 to H'000001A7 H'000001B0 to H'000001B3 H'000001B4 to H'000001B7 H'00000200 to H'00000203 H'00000204 to H'00000207 H'00000208 to H'0000020B H'0000020C to H'0000020F H'00000210 to H'00000213 H'00000214 to H'00000217 H'00000218 to H'0000021B H'0000021C to H'0000021F Interrupt Source MTU1 TGI1A TGI1B TCI1V TCI1U MTU2 TGI2A TGI2B TCI2V TCI2U SCI0 ERI0 RXI0 TXI0 TEI0 SCI1 ERI1 RXI1 TXI1 TEI1 Interrupt Priority (Initial Value) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) Priority within IPR Default Corresponding Setting Range Priority IPR (Bits) IPRD (7 to 4) High Low IPRD (3 to 0) High Low IPRE (15 to 12) High Low IPRE (11 to 8) High Low IPRF (7 to 4) High High Low IPRF (3 to 0) High Low Low Rev.5.00 Sep. 27, 2007 Page 79 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Interrupt Vector Vector Table Vector Address No. Offset 136 138 CMT0 CMT1 WDT BSC Note: * CMI0 CMI1 ITI CMI 144 148 152 153 H'00000220 to H'00000223 H'00000228 to H'0000022B H'00000240 to H'00000243 H'00000250 to H'00000253 H'00000260 to H'00000263 H'00000264 to H'00000267 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRG (7 to 4) IPRG (3 to 0) IPRH (15 to 12) ⎯ ⎯ High Low Low Interrupt Source A/D* ADI Interrupt Priority (Initial Value) 0 to 15 (0) Priority within IPR Default Corresponding Setting Range Priority IPR (Bits) IPRG (15 to 12) ⎯ High Vector No. 136 = SH7014 only 138 = SH7016, SH7017 only Rev.5.00 Sep. 27, 2007 Page 80 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.3 6.3.1 Description of Registers Interrupt Priority Registers A to H (IPRA to IPRH) Interrupt priority registers A to H (IPRA to IPRH) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA to IPRH bits is shown in table 6.4. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Table 6.4 Interrupt Request Sources and IPRA to IPRH Bits Register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H 15 to 12 IRQ0 Reserved DMAC0 MTU0 MTU2 Reserved A/D WDT, BSC 11 to 8 IRQ1 Reserved DMAC1 MTU0 MTU2 Reserved Reserved Reserved 7 to 4 IRQ2 IRQ6 Reserved MTU1 Reserved SCI0 CMT0 Reserved 3 to 0 IRQ3 IRQ7 Reserved MTU1 Reserved SCI1 CMT1 Reserved Rev.5.00 Sep. 27, 2007 Page 81 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If multiple on-chip peripheral modules are assigned to WDT and BSC, those multiple modules are set to the same priority rank. IPRA to IPRH are initialized to H'0000 by a power-on reset. They are not initialized in standby mode. 6.3.2 Interrupt Control Register (ICR) The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 to IRQ3, IRQ6, IRQ7 and indicates the input signal level to the NMI pin. It is initialized by power-on reset, but is not initialized by standby mode. Bit: 15 NMIL Initial value: R/W: Bit: * R 7 IRQ0S Initial value: R/W: Note: * 0 R/W 14 ⎯ 0 R 6 IRQ1S 0 R/W 13 ⎯ 0 R 5 IRQ2S 0 R/W 12 ⎯ 0 R 4 IRQ3S 0 R/W 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 ⎯ 0 R 9 ⎯ 0 R 1 IRQ6S 0 R/W 8 NMIE 0 R/W 0 IRQ7S 0 R/W When NMI input is high: 1; when NMI input is low: 0 Bit 15⎯NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15 NMIL 0 1 Description NMI input level is low NMI input level is high Bits 14 to 9, 3, 2⎯Reserved: These bits always read as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 82 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Bit 8⎯NMI Edge Select (NMIE) Bit 8 NMIE 0 1 Description Interrupt request is detected on falling edge of NMI input Interrupt request is detected on rising edge of NMI input (initial value) Bits 7 to 4, 1, 0⎯IRQ0 to IRQ3, IRQ6, IRQ7 Sense Select (IRQ0S to IRQ3S, IRQ6S, IRQ7S): These bits set the IRQ0 to IRQ3, IRQ6, IRQ7 interrupt request detection mode. Bits 7 to 4, 1, 0 IRQ0S to IRQ3S, IRQ6S, IRQ7S 0 1 Description Interrupt request is detected on low level of IRQ input Interrupt request is detected on falling edge of IRQ input (initial value) 6.3.3 IRQ Status Register (ISR) The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3, IRQ6, IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1. A power-on reset initializes ISR but the standby mode does not. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 IRQ0F Initial value: R/W: 0 R/W 14 ⎯ 0 R 6 IRQ1F 0 R/W 13 ⎯ 0 R 5 IRQ2F 0 R/W 12 ⎯ 0 R 4 IRQ3F 0 R/W 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 ⎯ 0 R 9 ⎯ 0 R 1 IRQ6F 0 R/W 8 ⎯ 0 R 0 IRQ7F 0 R/W Bits 15 to 8, 3, 2⎯Reserved: These bits always read as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 83 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Bits 7 to 4, 1, 0⎯IRQ0 to IRQ3, IRQ6, IRQ7 Flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F): These bits display the IRQ0 to IRQ3, IRQ6, IRQ7 interrupt request status. Bits 7 to 4, 1, 0 IRQ0F to IRQ3F, Detection Setting IRQ6F, IRQ7F 0 Level detection Edge detection Description No IRQn interrupt request exists. Clear conditions: When IRQn input is high level No IRQn interrupt request was detected. Clear conditions: 1. When a 0 is written after reading IRQnF = 1 status 2. When IRQn interrupt exception processing has been executed (initial value) 1 Level detection Edge detection An IRQn interrupt request exists. Set conditions: When IRQn input is low level An IRQn interrupt request was detected. Set conditions: When a falling edge occurs at an IRQn input ISR.IRQnF IRQnS (0: level, 1: edge) IRQ pin Level detection Edge detection SQ CPU interrupt request Selection RESIRQn R (IRQn interrupt acceptance/IRQnF = 0 write after IRQnF = 1 read) Figure 6.2 External Interrupt Process Rev.5.00 Sep. 27, 2007 Page 84 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.4 6.4.1 Interrupt Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers A to H (IPRA to IPRH). Lower-priority interrupts are ignored. They are held pending until interrupt requests designated as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by accessing the IRQ status register (ISR). See section 6.2.2, IRQ Interrupts, for details. Interrupts held pending due to edge detection are cleared by a power-on reset. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting range (as indicated in table 6.3) is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.4). 5. SR and PC are saved onto the stack. 6. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR). 7. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. Rev.5.00 Sep. 27, 2007 Page 85 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Program execution state No Interrupt? Yes NMI? Yes No Level 15 interrupt? Save SR to stack Yes Save PC to stack Copy accept-interrupt level to I3 to I0 Reads exception vector table Branches to exception service routine Yes I3 to I0 ≤ level 14? No Yes No Level 14 interrupt? Yes I3 to I0 ≤ level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No Legend: I3 to I0: Interrupt mask bits of status register Figure 6.3 Interrupt Sequence Flowchart Rev.5.00 Sep. 27, 2007 Page 86 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.4.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Processing Rev.5.00 Sep. 27, 2007 Page 87 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.5 Interrupt Response Time Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is accepted. Table 6.5 Interrupt Response Time Number of States Item DMAC active judgment NMI, Peripheral Module 0 or 1 IRQ 1 Notes 1 state required for interrupt signals for which DMAC activation is possible Compare identified interrupt priority with SR mask level Wait for completion of sequence currently being executed by CPU 2 3 X (≥ 0 ) The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the PC and SR saves and vector address fetch. Time from start of interrupt exception processing until fetch of first instruction of exception service routine starts Interrupt Total: response Minimum: time Maximum: 5 + m1 + m2 + m3 7 + m1 + m2 + m3 10 12 + 2 (m1 + m2 + m3) + m4 9 + m1 + m2 + m3 12 13 + 2 (m1 + m2 + m3) + m4 0.35 to 0.42 μs at 28.7 MHz 0.67 to 0.70 μs at 28.7 MHz* Note: When m1 = m2 = m3 = m4 = 1 m1 to m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev.5.00 Sep. 27, 2007 Page 88 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) Interrupt acceptance 5 + m1 + m2 + m3 3 m1 m2 1 m3 1 1 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction 3 FDEEMMEMEE F FDE Legend: F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 6.5 Pipeline when an IRQ Interrupt is Accepted Rev.5.00 Sep. 27, 2007 Page 89 of 716 REJ09B0398-0500 6. Interrupt Controller (INTC) 6.6 Data Transfer with Interrupt Request Signals The following data transfers can be done using interrupt request signals: • Activate DMAC only, without generating CPU interrupt Among interrupt sources, those designated as DMAC activating sources are masked and not input to the INTC. The masking condition is listed below: Mask condition = DME × (DE0 × source selection 0 + DE1) Figure 6.6 shows a control block diagram. Interrupt source Interrupt source flag clear (by DMAC) DMAC Interrupt source (those not designated as DMAC activating sources) CPU interrupt request Figure 6.6 Interrupt Control Block Diagram 6.6.1 Handling DMAC Activating Sources but Not CPU Interrupt Sources 1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources and DTC activating sources are masked regardless of the interrupt priority level register settings or DTC register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears activating sources at the time of data transfer. 6.6.2 Treating CPU Interrupt Sources but Not DMAC Activating Sources 1. Either do not select the DMAC as a source, or clear the DME bit to 0. 2. When interrupts occur, interrupt requests are sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt processing routine. Rev.5.00 Sep. 27, 2007 Page 90 of 716 REJ09B0398-0500 7. Cache Memory (CAC) Section 7 Cache Memory (CAC) 7.1 Overview The LSI has an on-chip cache memory (CAC: CAChe) with 1 kbyte of cache data and a 256-entry cache tag. The cache data and cache tag space can be used as on-chip RAM space when the cache is not being used. 7.1.1 Features The CAC has the following features. The cache tag and cache data configuration is shown in figure 7.1. • 1-kbyte capacity • External memory (CS space and DRAM space) instruction code and PC relative data caching • 256 entry cache tag (tag address 15 bits) • 4-byte line length • Direct map replacement algorithm • Valid flag (1 bit) included for purges Valid bit (1 bit) Cache tag Tag address (15 bits) Cache data Data (32 bits) 15 8 2 CPU address Tag Entry Offset address address 256 entries CMP Data bus Hit signal Figure 7.1 Cache Tag and Cache Data Configuration Rev.5.00 Sep. 27, 2007 Page 91 of 716 REJ09B0398-0500 7. Cache Memory (CAC) 7.1.2 Block Diagram Figure 7.2 shows a block diagram of the cache. CCR Cache tag Cache controller Cache data Internal address bus Cache Bus state controller External bus interface Legend: CCR: Cache control register Figure 7.2 Cache Block Diagram Internal data bus Rev.5.00 Sep. 27, 2007 Page 92 of 716 REJ09B0398-0500 7. Cache Memory (CAC) 7.1.3 Register Configuration The cache has one register, which can be used to control the enabling or disabling of each cache space. The register configuration is shown in table 7.1. Table 7.1 Name Cache control register Note: * Register Configuration Abbreviation CCR R/W R/W Initial Value H'0000* Address H'FFFF8740 Access Size (Bits) 8, 16, 32 Bits 15 to 5 are undefined. Rev.5.00 Sep. 27, 2007 Page 93 of 716 REJ09B0398-0500 7. Cache Memory (CAC) 7.2 7.2.1 Register Explanation Cache Control Register (CCR) The cache control register (CCR) selects the cache enable/disable of each space. The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is not initialized by standby mode. Bit: 15 ⎯ Initial value: R/W: Bit: * R 7 ⎯ Initial value: R/W: Note: * * R 14 ⎯ * R 6 ⎯ * R 13 ⎯ * R 5 ⎯ * R 12 ⎯ * R 4 CE DRAM 0 R/W 11 ⎯ * R 3 CE CS3 0 R/W 10 ⎯ * R 2 CE CS2 0 R/W 9 ⎯ * R 1 CE CS1 0 R/W 8 ⎯ * R 0 CE CS0 0 R/W Bits 15 to 5 are undefined. Bits 15 to 5⎯Reserved: Reading these bits gives undefined values. The write value should always be 0. Bit 4⎯DRAM Space Cache Enable (CEDRAM): Selects whether to use DRAM space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 4 CEDRAM 0 1 Description DRAM space cache disabled DRAM space cache enabled (initial value) Rev.5.00 Sep. 27, 2007 Page 94 of 716 REJ09B0398-0500 7. Cache Memory (CAC) Bit 3⎯CS3 Space Cache Enable (CECS3): Selects whether to use CS3 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 3 CECS3 0 1 Description CS3 space cache disabled CS3 space cache enabled (initial value) Bit 2⎯CS2 Space Cache Enable (CECS2): Selects whether to use CS2 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 2 CECS2 0 1 Description CS2 space cache disabled CS2 space cache enabled (initial value) Bit 1⎯CS1 Space Cache Enable (CECS1): Selects whether to use CS1 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 1 CECS1 0 1 Description CS1 space cache disabled CS1 space cache enabled (initial value) Bit 0⎯CS0 Space Cache Enable (CECS0): Selects whether to use CS0 space as a cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use. Bit 0 CECS0 0 1 Description CS0 space cache disabled CS0 space cache enabled (initial value) Rev.5.00 Sep. 27, 2007 Page 95 of 716 REJ09B0398-0500 7. Cache Memory (CAC) 7.3 Address Array and Data Array There is a special cache space for controlling the cache. This space is divided into an address array and a data array, where addresses (tag address, including valid bit) and data (4-byte line length) for cache control are recorded. The special cache space is shown in table 7.2. It can be used as on-chip RAM space when the cache is not being used. Table 7.2 Special Cache Space Address H'FFFFF000 to H'FFFFF3FF H'FFFFF400 to H'FFFFF7FF Size 1 kbyte 1 kbyte Bus Width 32 bits 32 bits Space Classification Address array Data array 7.3.1 Cache Address Array Read/Write Space The cache address array has a compulsory read/write (figure 7.3). 31 Address 10 9 Entry address (8 bits) ⎯ (10 bits) 21 0 Upper 22 bits of the address array space address (22 bits) 31 26 25 24 ⎯ (6 bits) Tag address (15 bits) Valid bit (1 bit) 10 9 ⎯ (2 bits) 0 Data Figure 7.3 Cache Address Array Address Array Read: Designates entry address and reads out the corresponding tag address value/valid bit value. Address Array Write: Designates entry address and writes the designated tag address value/valid bit value. Rev.5.00 Sep. 27, 2007 Page 96 of 716 REJ09B0398-0500 7. Cache Memory (CAC) 7.3.2 Cache Data Array Read/Write Space The cache data array has a compulsory read/write (figure 7.4). 31 Address 31 Data Data (32 bits) Upper 22 bits of the data array space address (22 bits) 10 9 Entry address (8 bits) 21 0 ⎯ (2 bits) 0 Figure 7.4 Cache Data Array Data Array Read: Designates entry address and reads out the corresponding line of data. Data Array Write: Designates entry address and writes designated data to the corresponding line. Rev.5.00 Sep. 27, 2007 Page 97 of 716 REJ09B0398-0500 7. Cache Memory (CAC) 7.4 7.4.1 Usage Notes Cache Initialization Always initialize the cache before enabling it. Specifically, use an address array write to write 0 to all valid bits for all entries (256 times), that is,those in the address range H'FFFFF000 to H'FFFFF3FFF. 7.4.2 Forced Access to Address Array and Data Array While the cache is enabled, it is not possible to write to the address array or data array via the CPU, or DMAC, and a read will return an undefined value. The cache must be disabled before making a forced access to the address array or data array. 7.4.3 Cache Miss Penalty and Cache Fill Timing When a cache miss occurs, a single idle cycle is generated as a penalty immediately before the cache fill (access from external memory in the event of a cache miss), as shown in figure 7.5. However, in the case of consecutive cache misses, idle cycles are not generated for the second and subsequent cache misses, as shown in figure 7.6. As the timing for a cache fill from normal space, the CS assert period immediately before the end of the bus cycle (or the last bus cycle when two or four bus cycles are generated, such as in a word access to 8-bit space) is extended by an additional cycle, as shown in figures 7.5 and 7.6. Similarly, as the timing for a cache fill from DRAM space, the RAS assert period immediately before the end of the bus cycle is extended by an additional cycle as shown in figure 7.7. In RAS down mode, the next bus cycle is delayed by one cycle as shown in figure 7.8. Rev.5.00 Sep. 27, 2007 Page 98 of 716 REJ09B0398-0500 7. Cache Memory (CAC) CK Internal address Address CSn RD Data Mis-hit Idle cycle Idle cycle Idle cycle CS assert extension Figure 7.5 Cache Fill Timing in Case of Non-Consecutive Cache Miss from Normal Space (No Wait, No CS Assert Extension) CK Internal address Address CSn RD Data CS assert additional extension Miss-hit Figure 7.6 Cache Fill Timing in Case of Consecutive Cache Misses from Normal Space (No Wait, CS Assert Extension) Rev.5.00 Sep. 27, 2007 Page 99 of 716 REJ09B0398-0500 7. Cache Memory (CAC) CK Internal address Address RAS CASx Miss-hit Idle cycle ROW Idle cycle COLUMN RAS assert extension Idle cycle Data Figure 7.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space (Normal Mode, TPC = 0, RCD = 0, No Wait) CS space access DRAM access DRAM access CK Internal address Address RAS CASx Miss-hit ROW COLUMN Wait CS space Miss-hit COLUMN RAS assert extension Data Figure 7.8 Cache Fill Timing in Case of Consecutive Cache Misses from DRAM Space (RAS Down Mode, TPC = 0, RCD = 0, No Wait) 7.4.4 Cache Hit after Cache Miss The first cache hit after a cache miss is regarded as a cache miss, and a cache fill without idle cycle generation is performed. The next hit operates as a cache hit. Rev.5.00 Sep. 27, 2007 Page 100 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Section 8 Bus State Controller (BSC) 8.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like DRAM, SRAM, and ROM to be linked directly to the LSI without external circuitry. 8.1.1 Features The BSC has the following features: • Address space is divided into five spaces ⎯ A maximum linear 2 Mbytes for CS0 address space in modes with on-chip ROM enabled, and a maximum linear 4 Mbytes in modes with on-chip ROM disabled ⎯ A maximum linear 4 Mbytes for each of address spaces CS1, CS2, and CS3 ⎯ A maximum linear 16 Mbytes for DRAM dedicated space ⎯ Bus width can be selected for each space (8 or 16 bits) ⎯ Wait states can be inserted by software for each space ⎯ Wait states can be inserted via the WAIT pin in external memory space accesses ⎯ Outputs control signals for each space according to the type of memory connected • On-chip ROM/RAM interfaces ⎯ On-chip RAM access of 32 bits in 1 state ⎯ On-chip ROM access of 32 bits in 1 state • Direct interface to DRAM ⎯ Multiplexes row/column addresses according to DRAM capacity ⎯ Supports high-speed page mode and RAS down mode • Access control for each type of memory, peripheral LSI ⎯ Address/data multiplex function • Refresh ⎯ Supports CAS-before-RAS refresh (auto-refresh) and self-refresh • Refresh counter can be used as an interval timer ⎯ Interrupt request generated upon compare match (CMI interrupt request signal) Rev.5.00 Sep. 27, 2007 Page 101 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.1.2 Block Diagram Figure 8.1 shows the BSC block diagram. Bus interface WAIT Wait control unit WCR1 WCR2 CS0 to CS3 AH RD RDWR WRH, WRL CASH, CASL RAS CMI interrupt request Area control unit BCR1 BCR2 DCR RTCSR Memory control unit RTCNT Comparator Peripheral bus RTCOR Interrupt controller BSC Legend: WCR1: Wait control register 1 WCR2: Wait control register 2 BCR1: Bus control register 1 BCR2: Bus control register 2 DCR: RTCNT: RTCOR: RTCSR: DRAM area control register Refresh timer counter Refresh timer constant register Refresh timer control/status register Figure 8.1 BSC Block Diagram Rev.5.00 Sep. 27, 2007 Page 102 of 716 REJ09B0398-0500 Module bus Internal bus 8. Bus State Controller (BSC) 8.1.3 Pin Configuration Table 8.1 shows the bus state controller pin configuration. Table 8.1 Signal A21 to A0 D15 to D0 CS0 to CS3 RD WRH WRL RDWR RAS CASH CASL AH WAIT Pin Configuration I/O O I/O O O O O O O O O O I Description Address output (A21 to A18 become input ports in power-on reset) 16-bit data bus. D15-D0 are address output and data I/O during address/data multiplex I/O. Chip select Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also output during DRAM access. Strobe that indicates a write cycle to the higher byte (D15 to D8) for ordinary space/multiplex I/O. Also output during DRAM access. Strobe that indicates a write cycle to the lower byte (D7 to D0) for ordinary space/multiplex I/O. Also output during DRAM access. Strobe indicating a write cycle to DRAM (used for DRAM space) RAS signal for DRAM (used for DRAM space) CAS signal when accessing the higher byte (D15 to D8) of DRAM (used for DRAM space) CAS signal when accessing the lower byte (D7 to D0) of DRAM (used for DRAM space) Signal to hold the address during address/data multiplex Wait state request signal 8.1.4 Register Configuration The BSC has eight registers. These registers are used to control wait states, bus width, and interfaces with memories like DRAM, SRAM, and ROM, as well as refresh control. The register configurations are listed in table 8.2. All registers are 16 bits. Do not access DRAM space before completing the memory interface settings. All BSC registers are all initialized by a power-on reset. Values are maintained in standby mode. Rev.5.00 Sep. 27, 2007 Page 103 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Table 8.2 Name Register Configuration Abbr. BCR1 BCR2 WCR1 WCR2 DCR R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address H'200F H'FFFF H'FFFF H'000F H'0000 H'0000 H'0000 H'0000 Access Size Bus control register 1 Bus control register 2 Wait state control register 1 Wait state control register 2 DRAM area control register H'FFFF8620 8, 16, 32 H'FFFF8622 8, 16, 32 H'FFFF8624 8, 16, 32 H'FFFF8626 8, 16, 32 H'FFFF862A 8, 16, 32 H'FFFF862C 8, 16, 32 H'FFFF862E 8, 16, 32 H'FFFF8630 8, 16, 32 Refresh timer control/status register RTCSR Refresh timer counter Refresh time constant register RTCNT RTCOR 8.1.5 Address Map Figure 8.2 shows the address format used by the SH7014. A31 to A24 A23, A22 A21 A0 Output address: Output from the address pins CS space selection: Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS space when 00000000 (H'00) DRAM space when 00000001 (H'01) Reserved (do not access) when 00000010 to 11111110 (H'02 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF) Figure 8.2 Address Format This LSI uses 32-bit addresses: • A31 to A24 are used to select the type of space and are not output externally. • Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits A31 to A24 are 00000000. • A21 to A0 are output externally. Rev.5.00 Sep. 27, 2007 Page 104 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Table 8.3 shows an address map. Table 8.3 Address Map 5 • In on-chip ROM enabled mode* Address 4 Space Memory Size Bus Width H'00000000 to H'0001FFFF* On-chip ROM On-chip ROM H'00020000 to H'001FFFFF H'00200000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF H'01000000 to H'01FFFFFF H'02000000 to H'FFFF7FFF Reserved CS0 space CS1 space CS2 space CS3 space DRAM space Reserved On-chip peripheral module Ordinary space Ordinary space Ordinary space 128 kbytes 32 bits 1 1 1 2 2 Mbytes 4 Mbytes 4 Mbytes 8/16 bits* 8/16 bits* 8/16 bits* 8/16 bits* Ordinary space or multiplex 4 Mbytes I/O space DRAM 16 Mbytes 8/16 bits* 1 H'FFFF8000 to H'FFFF87FF On-chip peripheral module H'FFFF8800 to H'FFFFEFFF Reserved 6 2 kbytes 8/16 bits H'FFFFF000 to H'FFFFFFFF* On-chip RAM On-chip RAM 4 kbytes 32 bits Rev.5.00 Sep. 27, 2007 Page 105 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) • In on-chip ROM disabled mode Address H'00000000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF H'01000000 to H'01FFFFFF H'02000000 to H'FFFF7FFF Space CS0 space CS1 space CS2 space CS3 space DRAM space Reserved On-chip peripheral module 2 kbytes 8/16 bits Memory Ordinary space Ordinary space Ordinary space Size 4 Mbytes 4 Mbytes 4 Mbytes Bus Width 8/16 bits* 8/16 bits* 8/16 bits* 8/16 bits* 3 1 1 2 Ordinary space or multiplex 4 Mbytes I/O space DRAM 16 Mbytes 8/16 bits* 1 H'FFFF8000 to H'FFFF87FF On-chip peripheral module H'FFFF8800 to H'FFFFEFFF Reserved 6 H'FFFFF000 to H'FFFFFFFF* On-chip RAM On-chip RAM 4 kbytes 32 bits Notes: Do not access reserved space, as operation cannot be guaranteed in this case. In single-chip mode, space other than on-chip ROM, on-chip RAM, and on-chip peripheral module space cannot be used. 1. Selected by on-chip register settings. 2. Ordinary space: selected by on-chip register settings. Multiplex I/O space: 8/16 bits selected by the A14 bit. 3. 8/16 bits selected by the mode pin. 4. In the 64-kbyte on-chip ROM version (SH7016), on-chip ROM addresses are H'00000000 to H'0000FFFF, and addresses H'00010000 to H'0001FFFF are reserved space. 5. SH7016/17 only. 6. In the 3-kbyte on-chip RAM versions (SH7014/16), on-chip RAM addresses are H'FFFFF000 to H'FFFFFBFF, and addresses H'FFFFFC00 to H'FFFFFFFF are reserved space. Rev.5.00 Sep. 27, 2007 Page 106 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.2 8.2.1 Description of Registers Bus Control Register 1 (BCR1) BCR1 is a 16-bit read/write register that selects multiplex I/O, and specifies the bus size of the CS spaces. Write bits 8 to 0 of BCR1 during the initialization stage after a power-on reset, and do not change the values thereafter. In on-chip ROM ineffective mode, do not access any CS space other than CS0 until after completion of register initialization. BCR1 is initialized by power-on resets to H'200F, but is not initialized by software standbys. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: 0 R 14 ⎯ 0 R 6 ⎯ 0 R 13 ⎯ 1 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R 3 A3SZ 1 R/W 10 ⎯ 0 R 2 A2SZ 1 R/W 9 ⎯ 0 R 1 A1SZ 1 R/W 8 IOE 0 R/W 0 A0SZ 1 R/W Note: Do not write 1 to bits 4 to 7, as operation is not guaranteed in this case. Bits 15, 14, 12 to 9⎯Reserved: These bits always read as 0. The write value should always be 0. Bit 13⎯Reserved: This bit always read as 1. The write value should always be 1. Bit 8⎯Multiplex I/O Enable (IOE): Selects the use of CS3 space as ordinary space or address/data multiplex I/O space. A 0 selects ordinary space and a 1 selects address/data multiplex I/O space. When address/data multiplex I/O space is selected, the address and data are multiplexed and output from the data bus. When CS3 space is an address/data multiplex I/O space, bus size is decided by the A14 bit (A14 = 0: 8 bit, A14 = 1: 16 bit). Bit 8 IOE 0 1 Description CS3 space is ordinary space CS3 space is address/data multiplex I/O space (initial value) Rev.5.00 Sep. 27, 2007 Page 107 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bits 7 to 4⎯Reserved: These bits read 0 after a reset. The write value should always be 0. Operation is not guaranteed if the write value is 1. Bit 3⎯CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. This is effective only when CS3 space is ordinary space. When CS3 space is an address/data multiplex I/O space, bus size is decided by the A14 bit. Bit 3 A3SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (initial value) Bit 2⎯CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. Bit 2 A2SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (initial value) Bit 1⎯CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. Bit 1 A1SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (initial value) Bit 0⎯CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size. Bit 0 A0SZ 0 1 Description Byte (8-bit) size Word (16-bit) size (initial value) Note: A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode, the CS0 space bus size is specified by the mode pin. Rev.5.00 Sep. 27, 2007 Page 108 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.2.2 Bus Control Register 2 (BCR2) BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized by power-on resets to H'FFFF, but is not initialized by software standbys. Bit: 15 IW31 Initial value: R/W: Bit: 1 R/W 7 CW3 Initial value: R/W: 1 R/W 14 IW30 1 R/W 6 CW2 1 R/W 13 IW21 1 R/W 5 CW1 1 R/W 12 IW20 1 R/W 4 CW0 1 R/W 11 IW11 1 R/W 3 SW3 1 R/W 10 IW10 1 R/W 2 SW2 1 R/W 9 IW01 1 R/W 1 SW1 1 R/W 8 IW00 1 R/W 0 SW0 1 R/W Bits 15 to 8⎯Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with the area specification of the previous access. Refer to section 8.6, Waits between Access Cycles, for details. IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00 specify the idle between cycles for CS0 space. Bit 15 IW31 0 Bit 14 IW30 0 1 1 0 1 Description No idle cycle after accessing CS3 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) Rev.5.00 Sep. 27, 2007 Page 109 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bit 13 IW21 0 Bit 12 IW20 0 1 1 0 1 Description No idle cycle after accessing CS2 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) Bit 11 IW11 0 Bit 10 IW10 0 1 Description No idle cycle after accessing CS1 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) 1 0 1 Bit 9 IW01 0 Bit 8 IW00 0 1 Description No idle cycle after accessing CS0 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles (initial value) 1 0 1 Bits 7 to 4⎯Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when doing consecutive accesses of the same CS space. When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IW and CW. Refer to section 8.6, Waits between Access Cycles, for details. CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space. Bit 7 CW3 0 1 Description No CS3 space continuous access idle cycles One CS3 space continuous access idle cycle (initial value) Rev.5.00 Sep. 27, 2007 Page 110 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bit 6 CW2 0 1 Description No CS2 space continuous access idle cycles One CS2 space continuous access idle cycle (initial value) Bit 5 CW1 0 1 Description No CS1 space continuous access idle cycles One CS1 space continuous access idle cycle (initial value) Bit 4 CW0 0 1 Description No CS0 space continuous access idle cycles One CS0 space continuous access idle cycle (initial value) Bits 3 to 0⎯CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending write data hold time. Refer to section 8.3.3, CS Assert Extension Function, for details. SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access. Bit 3 SW3 0 1 Description No CS3 space CS assert extension CS3 space CS assert extension (initial value) Bit 2 SW2 0 1 Description No CS2 space CS assert extension CS2 space CS assert extension (initial value) Rev.5.00 Sep. 27, 2007 Page 111 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bit 1 SW1 0 1 Description No CS1 space CS assert extension CS1 space CS assert extension (initial value) Bit 0 SW0 0 1 Description No CS0 space CS assert extension CS0 space CS assert extension (initial value) 8.2.3 Wait Control Register 1 (WCR1) WCR1 is a 16-bit read/write register that specifies the number of wait cycles (0 to 15) for each CS space. WCR1 is initialized by power-on resets to H'FFFF, but is not initialized by software standbys. Bit: 15 W33 Initial value: R/W: Bit: 1 R/W 7 W13 Initial value: R/W: 1 R/W 14 W32 1 R/W 6 W12 1 R/W 13 W31 1 R/W 5 W11 1 R/W 12 W30 1 R/W 4 W10 1 R/W 11 W23 1 R/W 3 W03 1 R/W 10 W22 1 R/W 2 W02 1 R/W 9 W21 1 R/W 1 W01 1 R/W 8 W20 1 R/W 0 W00 1 R/W Bits 15 to 12⎯CS3 Space Wait Specification (W33, W32, W31, W30): Specifies the number of waits for CS3 space access. Bit 15 W33 0 0 Bit 14 W32 0 0 ⋅⋅⋅ 1 1 1 1 15 wait external wait input enabled (initial value) Bit 13 W31 0 0 Bit 12 W30 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled Rev.5.00 Sep. 27, 2007 Page 112 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bits 11 to 8⎯CS2 Space Wait Specification (W23, W22, W21, W20): Specifies the number of waits for CS2 space access. Bit 11 W23 0 0 Bit 10 W22 0 0 ⋅⋅⋅ 1 1 1 1 15 wait external wait input enabled (initial value) Bit 9 W21 0 0 Bit 8 W20 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled Bits 7 to 4⎯CS1 Space Wait Specification (W13, W12, W11, W10): Specifies the number of waits for CS1 space access. Bit 7 W13 0 0 Bit 6 W12 0 0 ⋅⋅⋅ 1 1 1 1 15 wait external wait input enabled (initial value) Bit 5 W11 0 0 Bit 4 W10 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled Bits 3 to 0⎯CS0 Space Wait Specification (W03, W02, W01, W00): Specifies the number of waits for CS0 space access. Bit 3 W03 0 0 Bit 2 W02 0 0 ⋅⋅⋅ 1 1 1 1 15 wait external wait input enabled (initial value) Bit 1 W01 0 0 Bit 0 W00 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled Rev.5.00 Sep. 27, 2007 Page 113 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.2.4 Wait Control Register 2 (WCR2) WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space and CS space for DMA single address mode transfers. Do not perform any DMA single address transfers before WCR2 is set. WCR2 is initialized by power-on resets to H'000F, but is not initialized by software standbys. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: 0 R 14 ⎯ 0 R 6 ⎯ 0 R 13 ⎯ 0 R 5 DDW1 0 R/W 12 ⎯ 0 R 4 DDW0 0 R/W 11 ⎯ 0 R 3 DSW3 1 R/W 10 ⎯ 0 R 2 DSW2 1 R/W 9 ⎯ 0 R 1 DSW1 1 R/W 8 ⎯ 0 R 0 DSW0 1 R/W Bits 15 to 6⎯Reserved: These bits always read as 0. The write value should always be 0. Bits 5 and 4⎯DRAM Space DMA Single Address Mode Access Wait Specification (DDW1, DDW0): Specifies the number of waits for DRAM space access during DMA single address mode accesses. These bits are independent of the DWW and DWR bits of the DCR. Bit 5 DDW1 0 1 Bit 4 DDW0 0 1 0 1 Description 2-cycle (no wait) external wait disabled 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled (initial value) Rev.5.00 Sep. 27, 2007 Page 114 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bits 3 to 0⎯CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2, DSW1, DSW0): Specifies the number of waits for CS space access (0 to 15) during DMA single address mode accesses. These bits are independent of the W bits of the WCR1. Bit 3 DSW3 0 0 1 Bit 2 DSW2 0 0 ⋅⋅⋅ 1 1 1 15 wait (external wait input enabled) (initial value) Bit 1 DSW1 0 0 Bit 0 DSW0 0 1 Description No wait (external wait input disabled) 1 wait (external wait input enabled) 8.2.5 DRAM Area Control Register (DCR) DCR is a 16-bit read/write register that selects the number of waits, operation mode, number of address multiplex shifts and the like for DRAM control. After a power-on reset, write the initial values to the bits in DCR and do not change the values afterward. Do not perform any DRAM space accesses before DCR initial settings are completed. DCR is initialized by power-on resets to H'0000, but is not initialized by software standbys. Bit: 15 TPC Initial value: R/W: Bit: 0 R/W 7 DIW Initial value: R/W: 0 R/W 14 RCD 0 R/W 6 ⎯ 0 R 13 TRAS1 0 R/W 5 BE 0 R/W 12 TRAS0 0 R/W 4 RASD 0 R/W 11 DWW1 0 R/W 3 ⎯ 0 R 10 DWW0 0 R/W 2 SZ0 0 R/W 9 DWR1 0 R/W 1 AMX1 0 R/W 8 DWR0 0 R/W 0 AMX0 0 R/W Bit 15⎯RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after RAS is negated before next assert. Bit 15 TPC 0 1 Description 1.5 cycles 2.5 cycles Rev.5.00 Sep. 27, 2007 Page 115 of 716 REJ09B0398-0500 (initial value) 8. Bus State Controller (BSC) Bit 14⎯RAS-CAS Delay Cycle Count (RCD): Specifies the number of row address output cycles. Bit 14 RCD 0 1 Description 1 cycle 2 cycles (initial value) Bits 13 and 12⎯CAS-Before-RAS Refresh RAS Assert Cycle Count (TRAS1 and TRAS0): Specify the number of RAS assert cycles for CAS before RAS refreshes. Bit 13 TRAS1 0 Bit 12 TRAS0 0 1 1 0 1 Description 2.5 cycles 3.5 cycles 4.5 cycles 5.5 cycles (initial value) Bits 11 and 10⎯DRAM Write Cycle Wait Count (DWW1 and DWW0): Specifies the number of DRAM write cycle column address output cycles. Bit 11 DWW1 0 Bit 10 DWW0 0 1 1 0 1 Description 2-cycle (no wait) external wait disabled 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled (initial value) Bits 9 and 8⎯DRAM Read Cycle Wait Count (DWR1 and DWR0): Specifies the number of DRAM read cycle column address output cycles. Bit 9 DWR1 0 Bit 8 DWR0 0 1 1 0 1 Description 2-cycle (no wait) external wait disabled 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled (initial value) Rev.5.00 Sep. 27, 2007 Page 116 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bit 7⎯DRAM Idle Cycle Count (DIW): Specifies whether to insert idle cycles, either when accessing a different external space (CS space) or when doing a DRAM write, after DRAM reads. Bit 7 DIW 0 1 Description No idle cycles 1 idle cycle (initial value) Bit 6⎯Reserved: This bit always read as 0. The write value should always be 0. Bit 5⎯Burst Enable (BE): Specifies the DRAM operation mode. Bit 5 BE 0 1 Description Burst disabled DRAM high-speed page mode enabled. (initial value) Bit 4⎯RAS Down Mode (RASD): Specifies the DRAM operation mode. Bit 4 RASD 0 1 Description Access DRAM by RAS up mode Access DRAM by RAS down mode (initial value) Bit 3⎯Reserved: This bit read 0 after a reset. The write value should always be 0. Operation is not guaranteed if the write value is 1. Bit 2⎯DRAM Bus Width Specification (SZ0): Specifies the DRAM space bus width. Bit 2 SZ0 0 1 Description Byte (8-bit) Word (16-bit) (initial value) Rev.5.00 Sep. 27, 2007 Page 117 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bits 1 and 0⎯DRAM Address Multiplex (AMX1 and AMX0): Specifies the DRAM address multiplex count. Bit 1 AMX1 0 Bit 0 AMX0 0 1 1 0 1 Description 9 bit 10 bit 11 bit 12 bit (initial value) 8.2.6 Refresh Timer Control/Status Register (RTCSR) RTCSR is a 16-bit read/write register that selects the refresh mode and the clock input to the refresh timer counter (RTCNT), and controls compare match interrupts (CMI). RTCSR is initialized by power-on resets to H'0000, but is not initialized by software standbys. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: 0 R 14 ⎯ 0 R 6 CMF 0 R/W 13 ⎯ 0 R 5 CMIE 0 R/W 12 ⎯ 0 R 4 CKS2 0 R/W 11 ⎯ 0 R 3 CKS1 0 R/W 10 ⎯ 0 R 2 CKS0 0 R/W 9 ⎯ 0 R 1 RFSH 0 R/W 8 ⎯ 0 R 0 RMD 0 R/W Bits 15 to 7⎯Reserved: These bits always read as 0. The write value should always be 0 Rev.5.00 Sep. 27, 2007 Page 118 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bit 6⎯Compare Match Flag (CMF): This status flag, which indicates that the values of RTCNT and RTCOR match, is set/cleared under the following conditions: Bit 6 CMF 0 1 Description Clear condition: After RTCSR is read when CMF is 1, 0 is written in CMF. (initial value) Set condition: RTCNT = RTCOR. When both RTCNT and RTCOR are in an initialized state (when values have not been rewritten since initialization, and RTCNT has not had its value changed due to a countup), RTCNT and RTCOR match, as both are H'0000, but in this case CMF is not set. Bit 5⎯Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request caused by the CMF bit of the RTCSR when CMF is set to 1. Bit 5 CMIE 0 1 Description Disables an interrupt request caused by CMF Enables an interrupt request caused by CMF (initial value) Bits 4 to 2⎯Clock Select (CKS2 to CKS0): Select the clock to input to RTCNT from among the seven types of internal clock obtained from dividing the system clock (φ). Bit 4 CKS2 0 Bit 3 CKS1 0 Bit 2 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Stops count-up φ/2 φ/8 φ/32 φ/128 φ/512 φ/2048 φ/4096 (initial value) Rev.5.00 Sep. 27, 2007 Page 119 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Bit 1⎯Refresh Control (RFSH): Selects whether to use refresh control for DRAM. Bit 1 RFSH 0 1 Description Do not refresh DRAM Refresh DRAM (initial value) Bit 0⎯Refresh Mode (RMD): When the RFSH bit is 1, this bit selects normal refresh or selfrefresh. When the RFSH bit is 1, self-refresh mode is entered immediately after the RMD bit is set to 1. When RMD is cleared to 0, a CAS-before-RAS refresh is performed at the interval set in the refresh time constant register (RTCNT). When set for self-refresh, the this LSI enters self-refresh mode immediately unless it is in the middle of a DRAM access. If it is, it enters self-refresh mode when the access ends. Refresh requests from the interval timer are ignored in self-refresh mode. Bit 0 RMD 0 1 Description CAS-before-RAS refresh Self-refresh (initial value) Rev.5.00 Sep. 27, 2007 Page 120 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.2.7 Refresh Timer Counter (RTCNT) RTCNT is a 16-bit read/write register that is used as an 8-bit up counter for refreshes or generating interrupt requests. RTCNT counts up with the clock selected by the CKS2 to CKS0 bits of the RTCSR. RTCNT values can always be read/written by the CPU. When RTCNT matches RTCOR, RTCNT is cleared to H'0000 and the CMF flag of the RTCSR is set to 1. If the RFSH bit of RTCSR is 1 and the RMD bit is 0 at this time, a CAS-before-RAS refresh is performed. Additionally, if the CMIE bit of RTCSR is a 1, a compare match interrupt (CMI) is generated. Bits 15 to 8 are reserved and play no part in counter operation. They are always read as 0. RTCNT is initialized by power-on resets to H'0000, but is not initialized by software standbys. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 14 ⎯ 0 R 6 13 ⎯ 0 R 5 12 ⎯ 0 R 4 11 ⎯ 0 R 3 10 ⎯ 0 R 2 9 ⎯ 0 R 1 8 ⎯ 0 R 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.5.00 Sep. 27, 2007 Page 121 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.2.8 Refresh Time Constant Register (RTCOR) RTCOR is a 16-bit read/write register that establishes the compare match period with RTCNT. The values of RTCOR and RTCNT are constantly compared. When the values correspond, the compare match flag of RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the RTCSR is set to 1 and the RMD bit is 0, a refresh request signal is produced by this match. The refresh request signal is held until a refresh operation is performed. If the refresh request is not processed before the next match, the previous request becomes ineffective. When the CMIE bit of the RTSCR is set to 1, an interrupt request is sent to the interrupt controller by this match signal. The interrupt request is output continuously until the CMF bit of the RTSCR is cleared. Bits 15 to 8 are reserved and cannot be used in setting the period. They always read 0. RTCOR is initialized by power-on resets to H'0000, but is not initialized by software standbys. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 14 ⎯ 0 R 6 13 ⎯ 0 R 5 12 ⎯ 0 R 4 11 ⎯ 0 R 3 10 ⎯ 0 R 2 9 ⎯ 0 R 1 8 ⎯ 0 R 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.5.00 Sep. 27, 2007 Page 122 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.3 Accessing Ordinary Space A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM direct connections. 8.3.1 Basic Timing Figure 8.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are performed in 2 states. T1 CK T2 Address CSn RD Read Data Write WRx Data Figure 8.3 Basic Timing of Ordinary Space Access During a read, irrespective of operand size, all bits in the data bus width for the access space (address) are fetched by the LSI on RD, using the required byte locations. During a write, the following signals are associated with transfer of these actual byte locations: WRH (bits 15 to 8) and WRL (bits 7 to 0). Rev.5.00 Sep. 27, 2007 Page 123 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.3.2 Wait State Control The number of wait states inserted into ordinary space access states can be controlled using the WCR settings (figure 8.4). The specified number of Tw cycles are inserted as software wait cycles at the timing shown in figure 8.4. T1 CK TW T2 Address CSn RD Read Data WRx Write Data Figure 8.4 Wait Timing of Ordinary Space Access (Software Wait Only) When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when Tw state shifts to T2 state. Rev.5.00 Sep. 27, 2007 Page 124 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) T1 CK Address CSn RD Read Data WRx Write Data WAIT TW TW TW0 T2 Figure 8.5 Wait State Timing of Ordinary Space Access (Wait States from Software Wait 2 State + WAIT Signal) Rev.5.00 Sep. 27, 2007 Page 125 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.3.3 CS Assert Period Extension Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period beyond the length of the CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. Th and Tf cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD and WRx signals are not. Further, data is extended up to the Tf cycle, which is effective for gate arrays and the like, which have slower write operations. Th CK T1 T2 Tf Address CSn RD Read Data WRx Write Data DACK Figure 8.6 CS Assert Period Extension Function Rev.5.00 Sep. 27, 2007 Page 126 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.4 8.4.1 DRAM Access DRAM Direct Connection When address space A31 to A24 = H'01 has been accessed, the corresponding space becomes a 16-Mbyte DRAM space, and the DRAM interface function can be used to directly connect this LSI to DRAM. Row address and column address are always multiplexed for DRAM space. The amount of row address multiplexing can be selected as from 9 to 12 bits by setting the AMX1 and AMX0 bits of the DCR. Table 8.4 AMX Bits and Address Multiplex Output Row Address AMX1 0 AMX0 0 Shift Amount 9 bits Output Address A21 to A15 A14 to A0 1 10 bits A21 to A14 A13 to A0 1 0 11 bits A21 to A13 A12 to A0 1 12 bits A21 to A12 A11 to A0 Output Pins A21 to A15 A23 to A9 A21 to A14 A23 to A10 A21 to A13 A23 to A11 A21 to A12 A23 to A12 A21 to A0 A21 to A0 A21 to A0 A21 to A0 A21 to A0 A21 to A0 Column Address Output Address A21 to A0 Output Pins A21 to A0 In addition to ordinary read and write accesses, burst mode access using high speed page mode is supported. Rev.5.00 Sep. 27, 2007 Page 127 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.4.2 Basic Timing This LSI supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of 3 cycles for normal mode. Figure 8.7 shows the basic DRAM access timing. DRAM space access is controlled by RAS, CASx and RDWR signals. The following signals are associated with transfer of these actual byte locations: CASH (bits 15 to 8) and CASL (bits 7 to 0). However, the signals for ordinary space, WRx and RD, are also output during the DMAC single transfer column address cycle period. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc is the CAS assert cycle and Tc2 is the read data fetch cycle. Tp CK Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR Row Column Tr Tc1 Tc2 Figure 8.7 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, No Waits) Rev.5.00 Sep. 27, 2007 Page 128 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.4.3 Wait State Control Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1, DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and writes. The timing with waits inserted is shown in figures 8.8 through 8.11. External waits can be inserted at the time of software waits 2, 3. The sampling location is the same as that of ordinary space: at one cycle before the Tc2 cycle clock rise. Wait cycles are extended by external waits. Tp CK Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR Row Column Tr Tc1 Tcw1 Tc2 Figure 8.8 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, One Wait) Rev.5.00 Sep. 27, 2007 Page 129 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Tp CK Address Data RAS CASx RDWR Data RAS Read CASx RDWR Row Column Tpw Tr Trw Tc1 Tcw1 Tcw2 Tcw2 Write Figure 8.9 DRAM Bus Cycle (Normal Mode, TPC = 1, RCD = 1, Two Waits) Rev.5.00 Sep. 27, 2007 Page 130 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Tp CK Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR Row Column Tr Tc1 Tcw1 Tcw2 Tcw3 Tc2 Figure 8.10 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, Three Waits) Rev.5.00 Sep. 27, 2007 Page 131 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Tp CK Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR WAIT Row Column Tr Tc1 Tcw1 Tcw2 Tcw0 Tc2 Figure 8.11 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, Two Waits + Wait Due to WAIT Signal) Rev.5.00 Sep. 27, 2007 Page 132 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.4.4 Burst Operation High-Speed Page Mode: When the burst enable bit (BE) of the DCR is set, burst accesses can be performed using high speed page mode. The timing is shown in figure 8.12. Wait cycles can be inserted during burst accesses by using the DCR. Tp CK Address Data RAS Write CASx RDWR Data RAS Read CASx RDWR Row Column Column Tr Tc1 Tc2 Tc1 Tc2 Figure 8.12 DRAM Bus Cycle (High-Speed Page Mode) RAS Down Mode: There are some instances where even if burst operation is selected, continuous accesses to DRAM will not occur, but another space will be accessed instead part way through the access. In such cases, if the RAS signal is maintained at low level during the time the other space is accessed, it is possible to continue burst operation at the time the next DRAM same row address is accessed. This is called RAS down mode. To use RAS down mode, set both the BE and RASD bits of the DCR to 1. Figures 8.13 and 8.14 show operation in RAS up and down modes. Rev.5.00 Sep. 27, 2007 Page 133 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) CS space access T1 T2 DRAM access Tp CK Tr Tc1 Tc2 DRAM access Tp Tr Tc1 Tc2 Address Row Column CS space Row Column RAS CASx Data Figure 8.13 DRAM Access Normal Operation (RAS Up Mode) CS space access T1 T2 DRAM access Tc1 Tc2 DRAM access Tp CK Tr Tc1 Tc2 Address RAS Row Column CS space Column CASx Data Figure 8.14 RAS Down Mode Rev.5.00 Sep. 27, 2007 Page 134 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.4.5 Refresh Timing The bus state controller is equipped with a function to control refreshes of DRAM. CAS-beforeRAS (CBR) refresh or self-refresh can be selected by setting the RTCSR's RMD bit. CAS-before-RAS Refresh: For CBR refreshes, set the RCR's RMD bit to 0 and the RFSH bit to 1. Also write the values in RTCNT and RTCOR necessary to fulfill the refresh interval prescribed for the DRAM being used. When a clock is selected with the CKS2 to CKS0 bits of the RSTCR, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared to the RTCOR value and a CBR refresh is performed when the two match. RTCNT is cleared at that time and the count starts again. Figure 8.15 shows the timing for the CBR refresh operation. The number of RAS assert cycles in the refresh cycle is set by the TRAS1, TRAS0 bits of the DCR. TRp CK TRr1 TRr2 TRc TRc RAS CASx Figure 8.15 CAS-Before-RAS Refresh Timing (TRAS1, TRAS0 = 0, 0) Self-Refresh: When both the RMD and RFSH bits of the RTCSR are set to 1, the CAS signal and RAS signal are output and the DRAM enters self-refresh mode, as shown in figure 8.16. Do not access DRAM during self-refreshes, in order to preserve DRAM data. When performing DRAM accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row addresses within the time prescribed for the particular DRAM. Rev.5.00 Sep. 27, 2007 Page 135 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) TRp CK TRr1 TRr2 TRc TRc RAS CASx Figure 8.16 Self-Refresh Timing 8.5 Address/Data Multiplex I/O Space Access When the BCR1 register IOE bit is set to 1, the D15 to D0 pins can be used for multiplexed address/data I/O for the CS3 space. Consequently, peripheral LSIs requiring address/data multiplexing can be directly connected to this LSI. Address/data multiplex I/O space bus width is selected by the A14 bit, and is 8 bit when A14 = 0 and 16 bit when A14 = 1. 8.5.1 Basic Timing When the IOE bit of the BCR1 is set to 1, CS3 space becomes address/data multiplex I/O space. When this space is accessed, addresses and data are multiplexed. When the A14 address bit is 0, the bus size becomes 8 bit and addresses and data are input and output through the D7 to D0 pins. When the A14 address bit is 1, the bus size becomes 16 bit and address output and data I/O occur through the D15 to D0 pins. Access for the address/data multiplex I/O space is controlled by the AH, RD and WRx signals. Address/data multiplex I/O space accesses are done after a 3-cycle (fixed) address output, as an ordinary space type access (figure 8.17). Rev.5.00 Sep. 27, 2007 Page 136 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) Ta1 CK Address CS3 AH RD Data input Data WRx Data Address output Data output Address output Ta2 Ta3 Ta4 T1 T2 Read Write Figure 8.17 Address/Data Multiplex I/O Space Access Timing (No Waits) Rev.5.00 Sep. 27, 2007 Page 137 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.5.2 Wait State Control Setting the WCR controls waits during address/data multiplex I/O space accesses. Software wait and external wait insertion timing is the same as during ordinary space accesses. The timing for one software wait + one external wait inserted is shown in figure 8.18. Ta1 CK Address Ta2 Ta3 Ta4 T1 TW TWo T2 CS3 AH RD Data WRx Write Data WAIT Address output Data output Address output Data input Read Figure 8.18 Address/Data Multiplex I/O Space Access Wait State Timing (One Software Wait + One External Wait) Rev.5.00 Sep. 27, 2007 Page 138 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.5.3 CS Assertion Extension The timing diagram when CS assertion extension is set for address/data multiplexed I/O space access is shown in figure 8.19. Ta1 Ta2 Ta3 Ta4 Th T1 T2 Tf Address CS3 AH RD Data WRx Write Data Address output Data output Address output Data input Read Figure 8.19 Wait Timing for Address/Data Multiplexed I/O Space When CS Assertion Extension is Set Rev.5.00 Sep. 27, 2007 Page 139 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.6 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once. 8.6.1 Prevention of Data Bus Conflicts For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of the BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 8.20 shows an example of idles between cycles. In this example, 1 idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, 1 idle cycle is inserted. Rev.5.00 Sep. 27, 2007 Page 140 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) T1 CK Address T2 Tidle T1 T2 CSn CSm RD WRx Data CSn space read Idle cycle CSm space write Figure 8.20 Idle Cycle Insertion Example IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this LSI, to do write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. DIW specifies the number of idle cycles required, after a DRAM space read either to read other external spaces (CS space), or for this LSI, to do write accesses. 0 to 3 cycles can be specified for CS space, and 0 to 1 cycle for DRAM space. Rev.5.00 Sep. 27, 2007 Page 141 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.6.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of the BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 8.21 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write accessed. T1 CK Address T2 Tidle T1 T2 CSn RD WRx Data CSn space access Idle cycle CSn space access Figure 8.21 Same Space Consecutive Access Idle Cycle Insertion Example Rev.5.00 Sep. 27, 2007 Page 142 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.7 Bus Arbitration It has two internal bus masters, the CPU and the DMAC. The priority ranking for determining bus right transfer between these bus masters is: Refresh > DMAC > CPU 8.8 Memory Connection Examples Figures 8.22 to 8.27 show examples of the memory connections. As A21 to A18 become input ports in power-on reset, they should be handled (e.g. pulled down) as necessary. 32 k × 8 bits ROM CE OE A0 to A14 I/O0 to I/O7 SH7014/16/17 CSn RD A0 to A14 D0 to D7 Figure 8.22 8-Bit Data Bus Width ROM Connection 256 k × 16 bits ROM CE OE A0 to A17 I/O0 to I/O15 SH7014/16/17 CSn RD A0 A1 to A18 D0 to D15 Figure 8.23 16-Bit Data Bus Width ROM Connection Rev.5.00 Sep. 27, 2007 Page 143 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 123 k × 8 bits SRAM CS OE A0 to A16 WE I/O0 to I/O7 SH7014/16/17 CSn RD A0 to A16 WRL D0 to D7 Figure 8.24 8-Bit Data Bus Width SRAM Connection 128 k × 8 bits SRAM CS OE A0 to A16 WE I/O0 to I/O7 SH7014/16/17 CSn RD A0 A1 to A17 WRH D8 to D15 WRL D0 to D7 CS OE A0 to A16 WE I/O0 to I/O7 Figure 8.25 16-Bit Data Bus Width SRAM Connection Rev.5.00 Sep. 27, 2007 Page 144 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 512 k × 8 bits DRAM RAS WE OE A0 to A9 CASL AD0 to AD7 A0 to A9 CAS I/O0 to I/O7 SH7014/16/17 RAS RDWR Figure 8.26 8-Bit Data Bus Width DRAM Connection 256 k × 16 bits DRAM RAS WE OE A0 A1 to A9 CASH CASL AD0 to AD15 A0 to A8 UCAS LCAS I/O0 to I/O15 SH7014/16/17 RAS RDWR Figure 8.27 16-Bit Data Bus Width DRAM Connection 8.9 On-chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 8.5. Table 8.5 On-chip Peripheral I/O Register Access SCI 8bit 2cyc MTU 16bit 2cyc INTC 16bit 2cyc PFC, PORT 16bit 2cyc CMT 16bit 2cyc A/D* 16bit 2cyc WDT 16bit 3cyc DMAC 16bit 3cyc CACHE 16bit 3cyc On-chip Peripheral Module Connected bus width Access cycle Note: * The A/D in the SH7016 and SH7017 has an 8-bit width and is accessed in 3 cyc. Rev.5.00 Sep. 27, 2007 Page 145 of 716 REJ09B0398-0500 8. Bus State Controller (BSC) 8.10 CPU Operation when Program Is in External Memory In the SH7014, SH7016, and SH7017 F-ZTAT™, two words (equivalent to two instructions) are normally fetched in a single instruction fetch. This is also true when the program is located in external memory, irrespective of whether the external memory bus width is 8 or 16 bits. If the program counter value immediately after the program branches is an odd-word (2n + 1) address, or if the program counter value immediately before the program branches is an even-word (2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the respective word instruction. Rev.5.00 Sep. 27, 2007 Page 146 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Section 9 Direct Memory Access Controller (DMAC) 9.1 Overview The SH7014 includes an on-chip two-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (transfer request acknowledge signal), external memories, memorymapped external devices, and on-chip peripheral modules (except for the DMAC and BSC). Using the DMAC reduces the burden on the CPU and increases operating efficiency of the LSI as a whole. 9.1.1 Features The DMAC has the following features: • Two channels • Four Gbytes of address space in the architecture • Byte, word, or longword selectable data transfer unit • 64 k (65,536) transfers • Single or dual address mode. ⎯ Single address mode: Either the transfer source or transfer destination (peripheral device) is accessed by a DACK signal while the other is accessed by address. One transfer unit of data is transferred in each bus cycle. ⎯ Dual address mode: Both the transfer source and transfer destination are accessed by address. Values set in a DMAC internal register indicate the accessed address for both the transfer source and transfer destination. Two bus cycles are required for one data transfer. • Channel function: Dual address mode and single address mode external requests can be accepted. • Transfer requests: There are three DMAC transfer activation requests, as indicated below. ⎯ External request: From two DREQ pins. DREQ can be detected either by falling edge or by low level. These can be received by all channels. ⎯ Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as SCI or A/D. These can be received by all channels. ⎯ Auto-request: The transfer request is generated automatically within the DMAC. • Selectable bus modes: Cycle-steal mode or burst mode • The DMAC priority order is fixed at 0 > 1. Rev.5.00 Sep. 27, 2007 Page 147 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.1.2 Block Diagram Figure 9.1 is a block diagram of the DMAC. DMAC module On-chip ROM* Circuit control Register control Peripheral bus Internal bus SARn On-chip RAM On-chip peripheral module DARn DMATCRn Activation control CHCRn DREQ0, DREQ1 MTU SCI0, SCI1 A/D converter DEIn DACK0, DACK1 DRAK0, DRAK1 External ROM External RAM External I/O (memory mapped) External I/O (with acknowledge) Bus state controller DMAOR Request priority control Bus interface Legend: DMAC source address register SARn: DMAC destination address register DARn: DMATCRn: DMAC transfer count register DMAC channel control register CHCRn: DMAOR: DMAC operation register Notes: n = 0, 1 * SH7016, SH7017 only Figure 9.1 DMAC Block Diagram Rev.5.00 Sep. 27, 2007 Page 148 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.1.3 Pin Configuration Table 9.1 shows the DMAC pins. Table 9.1 Channel 0 DMAC Pin Configuration Name DMA transfer request DMA transfer request acknowledge DREQ0 acceptance confirmation Symbol DREQ0 DACK0 DRAK0 I/O I O O Function DMA transfer request input from external device to channel 0 DMA transfer strobe output from channel 0 to external device Sampling receive acknowledge output for DMA transfer request input from external source DMA transfer request input from external device to channel 1 DMA transfer strobe output from channel 1 to external device Sampling receive acknowledge output for DMA transfer request input from external source 1 DMA transfer request DMA transfer request acknowledge DREQ1 acceptance confirmation DREQ1 DACK1 DRAK1 I O O Rev.5.00 Sep. 27, 2007 Page 149 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.1.4 Register Configuration Table 9.2 summarizes the DMAC registers. DMAC has a total of 9 registers. Each channel has four control registers. One other control register is shared by all channels. Table 9.2 DMAC Registers Abbreviation SAR0 DAR0 R/W R/W R/W Initial Value Undefined Undefined Undefined 1 Channel Name 0 DMA source address register 0 DMA destination address register 0 Address Register Access Size Size 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16, 32* 16* 4 2 H'FFFF86C0 32 bit H'FFFF86C4 32 bit H'FFFF86C8 32 bit 2 DMA transfer count DMATCR0 R/W register 0 DMA channel control register 0 1 DMA source address register 1 DMA destination address register 1 CHCR0 SAR1 DAR1 R/W* R/W R/W 3 H'00000000 H'FFFF86CC 32 bit Undefined Undefined Undefined H'FFFF86D0 32 bit H'FFFF86D4 32 bit H'FFFF86D8 32 bit 2 2 2 DMA transfer count DMATCR1 R/W register 1 DMA channel control register 1 Shared DMA operation register CHCR1 DMAOR R/W* R/W* 1 3 H'00000000 H'FFFF86DC 32 bit H'0000 H'FFFF86B0 16 bit 2 1 Notes: 1. Write 0 after reading 1 in bit 1 of CHCR0, CHCR1 and in bits 1 and 2 of the DMAOR to clear flags. No other writes are allowed. 2. For 16-bit access of SAR0, SAR1, DAR0, DAR1, and CHCR0, CHCR1, the 16-bit value on the side not accessed is held. 3. DMATCR has a 16-bit configuration: bits 0 to 15. Writing to the upper 16 bits (bits 16 to 31) is invalid, and these bits always read 0. 4. Only 16-bit access for DMAOR. 5. Do not attempt to access an empty address. If an access is attemped, the system operation is not guarenteed. Rev.5.00 Sep. 27, 2007 Page 150 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.2 9.2.1 Register Descriptions DMA Source Address Registers 0, 1 (SAR0, SAR1) DMA source address registers 0, 1 (SAR0, SAR1) are 32-bit read/write registers that specify the source address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next source address. In single-address mode, SAR values are ignored when a device with DACK has been specified as the transfer source. Specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. Operation cannot be guaranteed on any other addresses. The initial value after power-on resets or in software standby mode is undefined. Bit: 31 ⎯ R/W 23 ⎯ R/W 30 ⎯ R/W 22 ⎯ R/W 29 ⎯ R/W 21 ⎯ R/W 28 ⎯ R/W … … Initial value: R/W: … … 27 ⎯ R/W … … … … ⎯ R/W ⎯ R/W ⎯ R/W 26 ⎯ R/W 2 25 ⎯ R/W 1 24 ⎯ R/W 0 Initial value: R/W: Bit: Rev.5.00 Sep. 27, 2007 Page 151 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.2.2 DMA Destination Address Registers 0, 1 (DAR0, DAR1) DMA destination address registers 0, 1 (DAR0, DAR1) are 32-bit read/write registers that specify the destination address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next destination address. In single-address mode, DAR values are ignored when a device with DACK has been specified as the transfer destination. Specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. Operation cannot be guaranteed on any other address. The initial value after power-on resets or in software standby mode, is undefined. Bit: 31 ⎯ R/W 23 ⎯ R/W 30 ⎯ R/W 22 ⎯ R/W 29 ⎯ R/W 21 ⎯ R/W 28 ⎯ R/W … … Initial value: R/W: … … 27 ⎯ R/W … … … … ⎯ R/W ⎯ R/W ⎯ R/W 26 ⎯ R/W 2 25 ⎯ R/W 1 24 ⎯ R/W 0 Initial value: R/W: Bit: Rev.5.00 Sep. 27, 2007 Page 152 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.2.3 DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1) DMA transfer count registers 0, 1 (DMATCR0, DMATCR1) are 16-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count). Specifying a H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 65,536 transfers. While DMAC is in operation, the number of transfers to be performed is indicated. The initial value after power-on resets or in software standby mode is undefined. Upper sixteen bits of this register are read as 0 and the write value should always be 0. Bit: 31 ⎯ Initial value: R/W: Bit: 0 R 23 ⎯ Initial value: R/W: Bit: ⎯ R 15 ⎯ R/W 7 ⎯ R/W 30 ⎯ 0 R 22 ⎯ ⎯ R 14 ⎯ R/W 6 ⎯ R/W 29 ⎯ 0 R 21 ⎯ ⎯ R 13 ⎯ R/W 5 ⎯ R/W 28 ⎯ 0 R 20 ⎯ ⎯ R 12 ⎯ R/W 4 ⎯ R/W 27 ⎯ 0 R 19 ⎯ ⎯ R 11 ⎯ R/W 3 ⎯ R/W 26 ⎯ 0 R 18 ⎯ ⎯ R 10 ⎯ R/W 2 ⎯ R/W 25 ⎯ 0 R 17 ⎯ ⎯ R 9 ⎯ R/W 1 ⎯ R/W 24 ⎯ 0 R 16 ⎯ ⎯ R 8 ⎯ R/W 0 ⎯ R/W Initial value: R/W: Bit: Initial value: R/W: Rev.5.00 Sep. 27, 2007 Page 153 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.2.4 DMA Channel Control Registers 0, 1 (CHCR0, CHCR1) DMA channel control registers 0, 1 (CHCR0, CHCR1) is a 32-bit read/write register where the operation and transmission of each channel is designated. Bits 31 to 19 and bit 7 should always read 0. The written value should also be 0. They are initialized to 0 by a power-on reset and in software standby mode. Bit: 31 ⎯ Initial value: R/W: Bit: 0 R 23 ⎯ Initial value: 0 R Bit: 15 DM1 Initial value: R/W: Bit: 0 R/W 7 ⎯ Initial value: R/W: Note: * 0 R 30 ⎯ 0 R 22 ⎯ 0 R 14 DM0 0 R/W 6 DS 0 R/W 29 ⎯ 0 R 21 ⎯ 0 R 13 SM1 0 R/W 5 TM 0 R/W 28 ⎯ 0 R 20 ⎯ 0 R 12 SM0 0 R/W 4 TS1 0 R/W 27 ⎯ 0 R 19 ⎯ 0 R 11 RS3 0 R/W 3 TS0 0 R/W 26 ⎯ 0 R 18 RL 0 R/W 10 RS2 0 R/W 2 IE 0 R/W 25 ⎯ 0 R 17 AM 0 R/W 9 RS1 0 R/W 1 TE 0 R/(W)* 24 ⎯ 0 R 16 AL 0 R/W 8 RS0 0 R/W 0 DE 0 R/W TE bit: Allows only 0 write after reading 1. Rev.5.00 Sep. 27, 2007 Page 154 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bit 18⎯Request Check Level (RL): Selects whether to output DRAK notifying external device of DREQ received, with active high or active low. Bit 18 RL 0 1 Description Output DRAK with active high Output DRAK with active low (initial value) Bit 17⎯Acknowledge Mode (AM): In dual address mode, selects whether to output DACK in the data write cycle or data read cycle. In single address mode, DACK is always output irrespective of the setting of this bit. Bit 17 AM 0 1 Description Outputs DACK during read cycle Outputs DACK during write cycle (initial value) Bit 16⎯Acknowledge Level (AL): Specifies whether to set DACK (acknowledge) signal output to active high or active low. Bit 16 AL 0 1 Description Active high output Active low output (initial value) Bits 15 and 14⎯Destination Address Mode 1, 0 (DM1 and DM0): These bits specify increment/decrement of the DMA transfer destination address. These bit specifications are ignored when transferring data from an external device to address space in single address mode. Bit 15 DM1 0 Bit 14 DM0 0 1 1 0 1 Description Destination address fixed (initial value) Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Destination address decremented (−1 during 8-bit transfer, −2 during 16-bit transfer, −4 during 32-bit transfer) Setting prohibited Rev.5.00 Sep. 27, 2007 Page 155 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bits 13 and 12⎯Source Address Mode 1, 0 (SM1 and SM0): These bits specify increment/decrement of the DMA transfer source address. These bit specifications are ignored when transferring data from an external device to address space in single address mode. Bit 13 SM1 0 Bit 12 SM0 0 1 1 0 1 Description Source address fixed (initial value) Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Source address decremented (−1 during 8-bit transfer, −2 during 16-bit transfer, −4 during 32-bit transfer) Setting prohibited Bits 11 to 8⎯Resource Select 3 to 0 (RS3 to RS0): These bits specify the transfer request source. Bit 11 RS3 0 Bit 10 RS2 0 Bit 9 RS1 0 Bit 8 RS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description External request, dual address mode Prohibited External request, single address mode. External address space → external device. External request, single address mode. External device → external address space. Auto-request Prohibited MTU TGI0A MTU TGI1A MTU TGI2A Prohibited Prohibited A/D ADI SCI0 TXI0 SCI0 RXI0 SCI1 TXI1 SCI1 RXI1 (initial value) Rev.5.00 Sep. 27, 2007 Page 156 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bit 6⎯DREQ Select (DS): Sets the sampling method for the DREQ pin in external request mode to either low-level detection or falling-edge detection. When specifying an on-chip peripheral module or auto-request as the transfer request source, this bit setting is ignored. The sampling method is fixed at falling-edge detection in cases other than auto-request. Bit 6 DS 0 1 Description Low-level detection Falling-edge detection (initial value) Bit 5⎯Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 5 TM 0 1 Description Cycle steal mode Burst mode (initial value) Bits 4 and 3⎯Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer. Bit 4 TS1 0 Bit 3 TS0 0 1 1 0 1 Description Specifies byte size (8 bits) Specifies word size (16 bits) Specifies longword size (32 bits) Prohibited (initial value) Bit 2⎯Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the number of data transfers specified in the DMATCR (when TE = 1). Bit 2 IE 0 1 Description Interrupt request not generated after DMATCR-specified transfer count (initial value) Interrupt request enabled on completion of DMATCR specified number of transfers Rev.5.00 Sep. 27, 2007 Page 157 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bit 1⎯Transfer End Flag (TE): This bit is set to 1 after the number of data transfers specified by the DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing of the DE bit or DME bit of the DMAOR) the TE is not set to 1. With this bit set to 1, data transfer is disabled even if the DE bit is set to 1. Bit 1 TE 0 Description DMATCR-specified transfer count not ended (initial value) Clear condition: 0 write after TE = 1 read, Power-on reset, standby mode 1 DMATCR specified number of transfers completed Bit 0⎯DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0 DE 0 1 Description Operation of the corresponding channel disabled Operation of the corresponding channel enabled (initial value) Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3 to RS0 settings). With an external request or on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is enabled. If this bit is cleared during a data transfer, transfer is suspended. If the DE bit has been set, but TE = 1, then if the DME bit of the DMAOR is 0, and the NMI or AE bit of the DMAOR is 1, transfer enable mode is not entered. Rev.5.00 Sep. 27, 2007 Page 158 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.2.5 DMAC Operation Register (DMAOR) The DMAOR is a 16-bit read/write register that specifies the transfer mode of the DMAC. Bits 15 to 3 of this register always read as 0. The write value should always be 0. Register values are initialized to 0 during power-on reset or in software standby mode. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: Note: * 0 R 14 ⎯ 0 R 6 ⎯ 0 R 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 AE 0 R/(W)* 9 ⎯ 0 R 1 NMIF 0 R/(W)* 8 ⎯ 0 R 0 DME 0 R 0 write only is valid after 1 is read. Bit 2⎯Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU cannot write a 1 to the AE bit. Clearing is effected by 0 write after 1 read. Bit 2 AE 0 1 Description No address error, DMA transfer enabled Clearing condition: Write AE = 0 after reading AE = 1 Address error, DMA transfer disabled Setting condition: Address error due to DMAC (initial value) Rev.5.00 Sep. 27, 2007 Page 159 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bit 1⎯NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a 0 write after 1 read. Bit 1 NMIF 0 1 Description No NMI interrupt, DMA transfer enabled Clearing condition: Write NMIF = 0 after reading NMIF = 1 NMI has occurred, DMC transfer prohibited Set condition: NMI interrupt occurrence (initial value) Bit 0⎯DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended. Even when the DME bit is set, when the TE bit of the CHCR is 1, or its DE bit is 0, transfer is disabled in the case of an NMI of the DMAOR or when AE = 1. Bit 0 DME 0 1 Description Disable operation on all channels Enable operation on all channels (initial value) Rev.5.00 Sep. 27, 2007 Page 160 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.3 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. Transfer can be in either the single address mode or the dual address mode. The bus mode can be either burst or cycle steal. 9.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer unit of data (determined by TS0 and TS1 setting). For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Rev.5.00 Sep. 27, 2007 Page 161 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Figure 9.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? Yes Transfer request occurs?*1 Yes No No *2 *3 Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR − 1 → DMATCR, SAR and DAR updated DMATCR = 0? Yes No Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer aborted No DEI interrupt request (when IE = 1) Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer ends Notes: 1. 2. 3. No Normal end In auto-request mode, transfer begins when NMIF, AE, and TE are all 0, and the DE and DME bits are set to 1. DREQ level detection in burst mode (external request) or cycle-steal mode. DREQ edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 9.2 DMAC Transfer Flowchart Rev.5.00 Sep. 27, 2007 Page 162 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.3.2 DMA Transfer Requests DMA transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0 bits of the DMA channel control registers 0, 1 (CHCR0, CHCR1). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0, CHCR1 and the DME bit of the DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0, CHCR1 and the NMIF and AE bits of DMAOR are all 0). External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an external device. Choose one of the modes shown in table 9.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit of CHCR0, CHCR1 (DS = 0 is level detection, DS = 1 is edge detection). The source of the transfer request does not have to be the data transfer source or destination. Table 9.3 RS3 0 RS2 0 Selecting External Request Modes with the RS Bits RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Single address mode Source Any* External memory or memory-mapped external device External device with DACK Destination Any* External device with DACK External memory or memory-mapped external device 1 Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, BSC). Rev.5.00 Sep. 27, 2007 Page 163 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.4, there are eight transfer request signals: three from the multifunction timer pulse unit (MTU), which are compare match or input capture interrupts; the receive data full interrupts (RxI) and transmit data empty interrupts (TxI) of the two serial communication interfaces (SCI); and the A/D conversion end interrupt (ADI) of the A/D converter. When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. The transfer request source need not be the data transfer source or transfer destination. However, when the transfer request is set by RxI (transfer request because SCI's receive data is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set by TxI (transfer request because SCI's transmit data is empty), the transfer destination must be the SCI's transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the data transfer destination must be the A/D converter register. Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits DMA Transfer DestinRequest Signal Source ation Bus Mode TGI0A TGI1A TGI2A Any* Any* Any* 1 1 1 DMAC Transfer RS3 RS2 RS1 RS0 Request Source 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 MTU* MTU* MTU* 2 2 2 Any* Any* Any* 1 1 1 Burst/cycle steal Burst/cycle steal Burst/cycle steal Prohibited Prohibited A/D SCI0* transmit block SCI0* receive block SCI1* transmit block SCI1* receive block 3 3 3 3 4 1 ADI TxI0 RxI0 TxI1 RxI1 ADDR* Any* Any* 1 Burst/cycle steal Burst/cycle steal Burst/cycle steal Burst/cycle steal Burst/cycle steal TDR0 Any* 1 RDR0 Any* 1 TDR1 Any* 1 RDR1 Notes: 1. External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, BSC). 2. MTU: Multifunction timer pulse unit. 3. SCI0, SCI1: Serial communications interface. 4. ADDR: A/D converter's A/D register. In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt enable bit for each module, and output an interrupt signal. Rev.5.00 Sep. 27, 2007 Page 164 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) When an on-chip peripheral module's interrupt request signal is used as a DMA transfer request signal, interrupts for the CPU are not generated. When a DMA transfer is conducted corresponding with one of the transfer request signals in table 9.4, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in burst mode with the last transfer. 9.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. The channel priority order is fixed at channel 0 > channel 1. 9.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode, in which either the transfer source or destination is accessed using an acknowledge signal, or dual address mode, in which both the transfer source and destination addresses are output. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 9.5 Supported DMA Transfers Destination MemoryMapped External Device External External On-Chip with DACK Memory Device Memory Single Dual Dual Dual Dual Single Dual Dual Dual Dual Not available Dual Dual Dual Dual On-Chip Peripheral Module Not available Dual Dual Dual Dual Source External device with DACK Not available External memory Memory-mapped external device On-chip memory Single Single Not available On-chip peripheral module Not available Notes: 1. Single: Single address mode 2. Dual: Dual address mode Rev.5.00 Sep. 27, 2007 Page 165 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Address Modes Single Address Mode: In the single address mode, both the transfer source and destination are external; one (selectable) is accessed by a DACK signal while the other is accessed by an address. In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a transfer request acknowledge DACK signal to one external device to access it while outputting an address to the other end of the transfer. Figure 9.3 shows an example of a transfer between an external memory and an external device with DACK in which the external device outputs data to the data bus while that data is written in external memory in the same bus cycle. External address bus External data bus This LSI DMAC External memory External device with DACK DACK DREQ : Data flow Figure 9.3 Data Flow in Single Address Mode Two types of transfers are possible in the single address mode: (a) transfers between external devices with DACK and memory-mapped external devices, and (b) transfers between external devices with DACK and external memory. The only transfer requests for either of these is the external request (DREQ). Figure 9.4 shows the DMA transfer timing for the single address mode. Rev.5.00 Sep. 27, 2007 Page 166 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) CK A21 to A0 CSn D15 to D0 WRH WRL DACK Data that is output from the external device with DACK WR signal to external memory space DACK signal to external devices with DACK (active low) a. External device with DACK to external memory space Address output to external memory space CK A21 to A0 CSn D15 to D0 RD DACK Data that is output from external memory space RD signal to external memory space DACK signal to external device with DACK (active low) b. External memory space to external device with DACK Address output to external memory space Figure 9.4 Example of DMA Transfer Timing in the Single Address Mode Dual Address Mode: Dual address mode is used for access of both the transfer source and destination by address. Transfer source and destination can be accessed either internally or externally. In dual address mode, data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external memory transfer shown in figure 9.5, data is read from one of the memories by the DMAC during a read cycle, then written to the other external memory during the subsequent write cycle. Figure 9.6 shows the timing for this operation. Rev.5.00 Sep. 27, 2007 Page 167 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 1st bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is taken as the address, and data stored in the DMAC's data buffer is written to the transfer destination module. Figure 9.5 Operation during Dual Address Mode Rev.5.00 Sep. 27, 2007 Page 168 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) CK Transfer source address Transfer destination address A21 to A0 CSn D15 to D0 RD WRH, WRL DACK Data read cycle (1st cycle) Data write cycle (2nd cycle) Note: Transfer between external memories with DACK are output during read cycle. Figure 9.6 Example of Transfer Timing in Dual Address Mode Rev.5.00 Sep. 27, 2007 Page 169 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bus Modes Select the appropriate bus mode in the TM bits of CHCR0, CHCR1. There are two bus modes: cycle steal and burst. Cycle-Steal Mode: In the cycle steal mode, the bus right is given to another bus master after each one-transfer-unit (byte, word, or longword) DMAC transfer. When the next transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. The cycle steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 9.7 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions are dual address mode and DREQ level detection. DREQ Bus control returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read Write CPU DMAC DMAC CPU Read Write CPU Figure 9.7 DMA Transfer Example in the Cycle-Steal Mode Burst Mode: Once the bus right is obtained, the transfer is performed continuously until the transfer end condition is satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after the bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. Figure 9.8 shows an example of DMA transfer timing in the burst mode. Transfer conditions are single address mode and DREQ level detection. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 9.8 DMA Transfer Example in the Burst Mode Rev.5.00 Sep. 27, 2007 Page 170 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 9.6 shows the relationship between request modes and bus modes by DMA transfer category. Table 9.6 Relationship of Request Modes and Bus Modes by DMA Transfer Category Request Mode External External 1 1 Address Mode Transfer Category Single External device with DACK and external memory External device with DACK and memory-mapped external device Dual Bus* Mode B/C B/C B/C B/C B/C B/C B/C* B/C B/C* B/C B/C* B/C* 3 3 3 5 Transfer Usable Size (Bits) Channels 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32 8/16/32* 8/16/32* 4 4 4 0,1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 * 0, 1 1 External memory and external memory Any* External memory and memory-mapped Any* external device Memory-mapped external device and memory-mapped external device External memory and on-chip memory External memory and on-chip peripheral module Memory-mapped external device and on-chip memory Memory-mapped external device and on-chip peripheral module On-chip memory and on-chip memory On-chip memory and on-chip peripheral module On-chip peripheral module and onchip peripheral module Any* Any* Any* Any* Any* Any* Any* Any* 1 1 2 1 2 1 2 2 3 4 Notes: 1. External request, auto-request or on-chip peripheral module request enabled. However, in the case of on-chip peripheral module request, it is not possible to specify the SCI or A/D converter for the transfer request source. 2. External request, auto-request or on-chip peripheral module request possible. However, if transfer request source is also the SCI or A/D converter, the transfer source or transfer destination must be the SCI or A/D converter. 3. When the transfer request source is the SCI, only cycle steal mode is possible. 4. Access size permitted by register of on-chip peripheral module that is the transfer source or transfer destination. 5. B: Burst, C: Cycle steal Rev.5.00 Sep. 27, 2007 Page 171 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority Order When a given channel is transferring in burst mode, and a transfer request is issued to channel 0, which has a higher priority ranking, transfer on channel 0 begins immediately. Channel 1 transfer is continued after transfer on channel 0 are completely ended, whether the channel 0 setting is cycle steal mode or burst mode. 9.3.5 Number of Bus Cycle States and DREQ Pin Sample Timing Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. For details, see section 8, Bus State Controller. DREQ Pin Sampling Timing and DRAK Signal: In external request mode, the DREQ pin is sampled by either falling edge or low-level detection. When a DREQ input is detected, a DMAC bus cycle is issued and DMA transfer effected, at the earliest, after three states. However, in burst mode when single address operation is specified, a dummy cycle is inserted for the first bus cycle. In this case, the actual data transfer starts from the second bus cycle. Data is transferred continuously from the second bus cycle. The dummy cycle is not counted in the number of transfer cycles, so there is no need to recognize the dummy cycle when setting the DMATCR. DREQ sampling from the second time begins from the start of the transfer one bus cycle prior to the DMAC transfer generated by the previous sampling. DRAK is output once for the first DREQ sampling, irrespective of transfer mode or DREQ detection method. In burst mode, using edge detection, DREQ is sampled for the first cycle only, so DRAK is also output for the first cycle only. Therefore, the DREQ signal negate timing can be ascertained, and this facilitates handshake operations of transfer requests with the DMAC. Cycle Steal Mode Operations: In cycle steal mode, DREQ sampling timing is the same irrespective of dual or single address mode, or whether edge or low-level DREQ detection is used. For example, DMAC transfer begins (figure 9.9), at the earliest, three cycles from the first sampling timing. The second sampling begins at the start of the transfer one bus cycle prior to the start of the DMAC transfer initiated by the first sampling (i.e., from the start of the CPU(3) transfer). At this point, if DREQ detection has not occurred, sampling is executed every cycle thereafter. As in figure 9.10, whatever cycle the CPU transfer cycle is, the next sampling begins from the start of the transfer one bus cycle before the DMAC transfer begins. Figure 9.9 shows an example of output during DACK read and figure 9.10 an example of output during DACK write. Rev.5.00 Sep. 27, 2007 Page 172 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) CPU(5) DMAC(R) DMAC(W) 1st sampling DREQ CK DRAK CPU(1) CPU(2) CPU(3) DMAC(R) DMAC(W) 2nd sampling CPU(4) DMAC(R) DMAC(W) Figure 9.9 Cycle Steal, Dual Address and Level Detection (Fastest Operation) Rev.5.00 Sep. 27, 2007 Page 173 of 716 REJ09B0398-0500 DACK Bus cycle 1st sampling 2nd sampling CK Rev.5.00 Sep. 27, 2007 Page 174 of 716 REJ09B0398-0500 CPU DMAC(R) CPU DMAC(W) CPU DMAC (R) 9. Direct Memory Access Controller (DMAC) DREQ DRAK Bus cycle CPU DACK Figure 9.10 Cycle Steal, Dual Address and Level Detection (Normal Operation) Note: With cycle-steal and dual address operation, sampling timing is the same whether DREQ detection is by level or by edge. 9. Direct Memory Access Controller (DMAC) Figures 9.11 and 9.12 show cycle steal mode and single address mode. In this case, transfer begins at earliest three cycles after the first DREQ sampling. The second sampling begins from the start of the transfer one bus cycle before the start of the first DMAC transfer. In single address mode, the DACK signal is output during the DMAC transfer period. CK DREQ DRAK Bus cycle CPU CPU CPU DMAC CPU DMAC CPU DMAC Figure 9.11 Cycle Steal, Single Address and Level Detection (Fastest Operation) Rev.5.00 Sep. 27, 2007 Page 175 of 716 REJ09B0398-0500 DACK 9. Direct Memory Access Controller (DMAC) CPU DMAC CPU DRAK DREQ Figure 9.12 Cycle Steal, Single Address and Level Detection (Normal Operation) Rev.5.00 Sep. 27, 2007 Page 176 of 716 REJ09B0398-0500 DACK Note: With cycle-steal and single address operation, sampling timing is the same whether DREQ detection is by level or by edge. CK Bus cycle CPU CPU CPU DMAC 9. Direct Memory Access Controller (DMAC) Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with dual address and level detection is shown in figures 9.13 and 9.14. DREQ sampling timing in burst mode with dual address and level detection is virtually the same as that of cycle steal mode. For example, DMAC transfer begins (figure 9.13), at the earliest, three cycles after the timing of the first sampling. The second sampling also begins from the start of the transfer one bus cycle before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued, DMAC transfer continues. Therefore, the “transfer one bus cycle before the start of the DMAC transfer” may be a DMAC transfer. In burst mode, the DACK output period is the same as that of cycle steal mode. Figure 9.14 shows the normal operation of this burst mode. Rev.5.00 Sep. 27, 2007 Page 177 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) DMAC(R) CK DRAK Bus cycle CPU CPU CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) CPU Figure 9.13 Burst Mode, Dual Address and Level Detection (Fastest Operation) Rev.5.00 Sep. 27, 2007 Page 178 of 716 REJ09B0398-0500 DREQ DACK 9. Direct Memory Access Controller (DMAC) CK DRAK CPU DREQ CPU CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) Figure 9.14 Burst Mode, Dual Address and Level Detection (Normal Operation) Rev.5.00 Sep. 27, 2007 Page 179 of 716 REJ09B0398-0500 DACK Bus cycle 9. Direct Memory Access Controller (DMAC) Burst Mode, Single Address, and Level Detection: DREQ sampling timing in burst mode with single address and level detection is shown in figures 9.15 and 9.16. In burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle, at the earliest, three cycles after timing of the first sampling. Data during this period is undefined, and the DACK signal is not output. Nor is the number of DMAC transfers counted. The actual DMAC transfer begins after one dummy bus cycle output. The dummy cycle is not counted either at the start of the second sampling (transfer one bus cycle before the start of the first DMAC transfer). Therefore, the second sampling is not conducted from the bus cycle starting the dummy cycle, but from the start of the CPU(3) bus cycle. Thereafter, as long the DREQ is continuously sampled, no dummy cycle is inserted. DREQ sampling timing during this period begins from the start of the transfer one bus cycle before the start of DMAC transfer, in the same way as with cycle steal mode. As with the fourth sampling in figure 9.15, once DMAC transfer is interrupted, a dummy cycle is again inserted at the start as soon as DMAC transfer is resumed. The DACK output period in burst mode is the same as in cycle steal mode. Rev.5.00 Sep. 27, 2007 Page 180 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) CPU(4) Dummy 4th sampling 3rd sampling 2nd sampling 1st sampling CK DRAK Bus cycle CPU(1) CPU(2) CPU(3) Dummy DMAC DMAC DMAC Figure 9.15 Burst Mode, Single Address and Level Detection (Fastest Operation) Rev.5.00 Sep. 27, 2007 Page 181 of 716 REJ09B0398-0500 DREQ DACK 9. Direct Memory Access Controller (DMAC) CK DRAK CPU CPU CPU Dummy DMAC DMAC DMAC DREQ Figure 9.16 Burst Mode, Single Address and Level Detection (Normal Operation) Rev.5.00 Sep. 27, 2007 Page 182 of 716 REJ09B0398-0500 DACK Bus cycle 9. Direct Memory Access Controller (DMAC) Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 9.17, DMAC transfer begins, at the earliest, three cycles after the timing of the first sampling. Thereafter, DMAC transfer continues until the end of the data transfer count set in the DMATCR. DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first cycle only. When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput an edge request. The remaining transfer restarts after the first DRAK output. The DACK output period in burst mode is the same as in cycle steal mode. Rev.5.00 Sep. 27, 2007 Page 183 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) CK DRAK Bus cycle CPU CPU CPU Figure 9.17 Burst Mode, Dual Address and Edge Detection Rev.5.00 Sep. 27, 2007 Page 184 of 716 REJ09B0398-0500 DREQ DACK 9. Direct Memory Access Controller (DMAC) Burst Mode, Single Address, and Edge Detection: In burst mode with single address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 9.18, a dummy cycle is inserted, at the earliest, three cycles after the timing for the first sampling. During this period, data is undefined, and DACK is not output. Nor is the number of DMAC transfers counted. The actual DMAC transfer begins after one dummy bus cycle output. Thereafter, DMAC transfer continues until the data transfer count set in the DMATCR has ended. DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first cycle only. When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput an edge request. DRAK is output once, and the remaining transfer restarts after output of one dummy cycle. The DACK output period in burst mode is the same as in cycle steal mode. Rev.5.00 Sep. 27, 2007 Page 185 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) CK DRAK CPU CPU CPU Dummy DMAC DMAC DMAC DMAC DREQ Figure 9.18 Burst Mode, Single Address and Edge Detection Rev.5.00 Sep. 27, 2007 Page 186 of 716 REJ09B0398-0500 DACK Bus cycle 9. Direct Memory Access Controller (DMAC) 9.3.6 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and for all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (DMATCR) is 0, or when the DE bit of the channel's CHCR is cleared to 0. • When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) is requested of the CPU. • When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR. The TE bit is not set when this happens. Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or when the DME bit in the DMAOR is cleared to 0. • When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their transfers. The DMAC obtains the bus rights, and if these flags are set to 1 during execution of a transfer, DMAC halts operation when the transfer processing currently being executed ends, and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bits are set to 1 during a transfer, the DMA source address register (SAR), designation address register (DAR), and DMA transfer count register (DMATCR) are all updated. The TE bit is not set. To resume the transfers after NMI interrupt or address error processing, clear the appropriate flag bit to 0. To avoid restarting a transfer on a particular channel, clear its DE bit to 0. When the processing of a one unit transfer is complete. In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and DMATCR values are updated. • When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR aborts the transfers on all channels. The TE bit is not set. Rev.5.00 Sep. 27, 2007 Page 187 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.3.7 DMAC Access from CPU The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of three basic clock (CLK) cycles are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. 9.4 9.4.1 Examples of Use Example of DMA Transfer between On-Chip SCI and External Memory In this example, on-chip serial communication interface channel 0 (SCI0) received data is transferred to external memory using the DMAC channel 1. Table 9.7 indicates the transfer conditions and the setting values of each of the registers. Table 9.7 Transfer Conditions and Register Set Values for Transfer between On-chip SCI and External Memory Register SAR1 DAR1 DMATCR1 CHCR1 Value H'FFFF81A5 H'00400000 H'00000040 H'00004D05 Transfer Conditions Transfer source: RDR0 of on-chip SCI0 Transfer destination: external memory Transfer count: 64 times Transfer source address: fixed Transfer destination address: incremented Transfer request source: SCI0 (RDR0) Bus mode: cycle steal Transfer unit: byte Interrupt request generation at end of transfer Channel priority ranking: 0 > 1 DMAOR H'0001 Rev.5.00 Sep. 27, 2007 Page 188 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.4.2 Example of DMA Transfer between External RAM and External Device with DACK In this example, an external request, single address mode transfer with external memory as the transfer source and an external device with DACK as the transfer destination is executed using DMAC channel 1. Table 9.8 indicates the transfer conditions and the setting values of each of the registers. Table 9.8 Transfer Conditions and Register Set Values for Transfer between External RAM and External Device with DACK Register SAR1 DAR1 DMATCR1 CHCR1 Value H'00400000 (access by DACK) H'00000020 H'00002269 Transfer Conditions Transfer source: external RAM Transfer destination: external device with DACK Transfer count: 32 times Transfer source address: decremented Transfer destination address: (setting ineffective) Transfer request source: external pin (DREQ1) edge detection Bus mode: burst Transfer unit: word No interrupt request generation at end of transfer Channel priority ranking: 0 > 1 DMAOR H'0001 Rev.5.00 Sep. 27, 2007 Page 189 of 716 REJ09B0398-0500 9. Direct Memory Access Controller (DMAC) 9.5 Usage Notes 1. Other than the DMA operation register (DMAOR) accessing in word (16 bit) units, access all registers in word (16 bit) or longword (32 bit) units. 2. When rewriting the RS0 to RS3 bits of CHCR0, CHCR1, first clear the DE bit to 0 (set the DE bit to 0 before doing rewrites with a CHCR byte address). 3. When an NMI interrupt is input, the NMIF bit of the DMAOR is set even when the DMAC is not operating. 4. Set the DME bit of the DMAOR to 0 and make certain that any DMAC received transfer request processing has been completed before entering standby mode. 5. Do not access the DMAC or BSC on-chip peripheral modules from the DMAC. 6. When activating the DMAC, do the CHCR or DMAOR setting as the final step. There are instances where abnormal operation will result if any other registers are established last. 7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write a 0 to the DMATCR, even when executing the maximum number of transfers on the same channel. There are instances where abnormal operation will result if this is not done. 8. When detecting external requests by falling edge, maintain the external request pin at high level when performing the DMAC establishment. 9. When operating in single address mode, establish an external address as the address. There are instances where abnormal operation will result if an internal address is established. 10. Do not access DMAC register empty addresses (H'FFFF86B2 to H'FFFF86BF, H'FFFF86E4 to H'FFFF86FF). Operation cannot be guaranteed when empty addresses are accessed. Rev.5.00 Sep. 27, 2007 Page 190 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Section 10 Multifunction Timer Pulse Unit (MTU) 10.1 Overview The SuperH microcomputer has an on-chip 16-bit multifunction timer pulse unit (MTU) with three channels of 16-bit timers. 10.1.1 Features • Can process a maximum of eight different pulse outputs and inputs. • Has eight timer general registers (TGR): four for channel 0, and two each for channels 1 and 2 that can be set to function independently as output compare or input capture. The channel 0 TGRC and TGRD registers can be used as buffer registers. • Can select eight counter input clock sources for all channels • All channels can be set for the following operating modes: ⎯ Compare match waveform output: 0 output/1 output/toggle output selectable. ⎯ Input capture function: Selectable rising edge, falling edge, or both rising and falling edge detection. ⎯ Counter clearing function: Counters can be cleared by a compare-match or input capture. ⎯ Synchronizing mode: Two or more timer counters (TCNT) can be written to simultaneously. Two or more timer counters can be simultaneously cleared by a comparematch or input capture. Counter synchronization functions enable synchronized register input/output. ⎯ PWM mode: PWM output can be provided with any duty cycle. When combined with the counter synchronizing function, up to seven-phase PWM output is enabled (with channels 0 to 2 set to PWM mode 2 and channel 0 synchronized with the TGR0A register (channels 0 to 2 phase output: 3, 2, 2)). • Channels 0 can be set for buffer operation ⎯ Input capture register double buffer configuration possible ⎯ Output compare register automatic re-write possible • Channels 1, 2 can be independently set to the phase counting mode ⎯ Two-phase encoder pulse up/down count possible • Cascade connection operation ⎯ Can be operated as a 32-bit counter by using the channel 2 input clock for channel 1 overflow/underflow • High speed access via internal 16-bit bus Rev.5.00 Sep. 27, 2007 Page 191 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) • Thirteen interrupt sources ⎯ Channel 0 has four compare-match/input capture interrupts and one overflow interrupt which can be requested independently. ⎯ Channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. • Automatic transfer of register data ⎯ Block transfer, 1-word data transfers and 1-byte data transfers are possible through DMAC activation. • A/D converter conversion start trigger can be generated ⎯ Channels 0 to 2 compare-match/input capture signals can be used as A/D converter conversion start triggers. Table 10.1 summarizes the MTU functions. Rev.5.00 Sep. 27, 2007 Page 192 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Table 10.1 MTU Functions Item Counter clocks Channel 0 Channel 1 Channel 2 Internal: φ/1, φ/4, φ/16, φ/64, φ/256, φ/1024 External: Eight to each channel from TCLKA, TCLKB, TCLKC, and TCLKD TGR0A TGR0B TGR0C TGR0D TIOC0A TIOC0B TIOC0C TIOC0D TGR1A TGR1B No TIOC1A TIOC1B TGR2A TGR2B No TIOC2A TIOC2B General registers General registers/buffer registers Input/output pins Counter clear function Compare match output 0 1 Toggle Input capture function Synchronization Buffer operation PWM mode 1 PWM mode 2 Phase counting mode DMAC activation TGR compare-match TGR compare-match TGR compare-match or input capture or input capture or input capture Yes Yes Yes Yes Yes Yes Yes Yes No TGR0A compare match or input capture Yes Yes Yes Yes Yes No Yes Yes Yes TGR1A compare match or input capture TGR1A com-pare match or input capture Yes Yes Yes Yes Yes No Yes Yes Yes TGR2A compare match or input capture TGR2A com-pare match or input capture A/D conversion start trigger TGR0A com-pare match or input capture Rev.5.00 Sep. 27, 2007 Page 193 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Item Interrupt sources Channel 0 Channel 1 Channel 2 Compare match/input Compare match/input Compare match/input capture 0A capture 1A capture 2A Compare match/input Compare match/input Compare match/input capture 0B capture 1B capture 2B Compare match/input Overflow capture 0C Compare match/input Underflow capture 0D Overflow ⎯ Overflow Underflow ⎯ Rev.5.00 Sep. 27, 2007 Page 194 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.1.2 Block Diagram Figure 10.1 is the block diagram of the MTU. (Clock input) Internal clock: φ/1 φ/4 φ/16 φ/64 φ/256 φ/1024 External clock: TCLKA TCLKB TCLKC TCLKD (I/O pins) Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B TSTR TSYR Control logic Channel 2 TCR TMDR TIOR TIER TSR Shared Module data bus BUS I/F Internal data bus A/D conversion start request signal Channels 0 to 2 control logic Channel 1 TCR TMDR TIOR TIER TSR TCNT TGRA TGRB (Interrupt request signal) Channel 0: TGI0A TGI0B TGI0C TGI0D TGI0V Channel 1: TGI1A TGI1B TGI1V TGI1U Channel 2: TGI2A TGI2B TGI2V TGI2U Channel 0 TCR TMDR TIORH TIORL TIER TSR Figure 10.1 MTU Block Diagram TCNT TGRA TGRB TGRC TGRD TCNT TGRA TGRB Rev.5.00 Sep. 27, 2007 Page 195 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.1.3 Pin Configuration Table 10.2 summarizes the MTU pins. Table 10.2 Pin Configuration Channel Name Shared Clock input A Clock input B Clock input C Clock input D 0 Pin Name I/O Function TCLKA TCLKB TCLKC TCLKD I I I I Clock A input pin (A-phase input pin in channel 1 phase counting mode) Clock B input pin (B-phase input pin in channel 1 phase counting mode) Clock C input pin (A-phase input pin in channel 2 phase counting mode) Clock D input pin (B-phase input pin in channel 2 phase counting mode) Input TIOC0A capture/output compare-match 0A TIOC0B Input capture/output compare-match 0B Input TIOC0C capture/output compare-match 0C TIOC0D Input capture/output compare-match 0D I/O TGR0A input capture input/output compare output/PWM output pin I/O TGR0B input capture input/output compare output/PWM output pin I/O TGR0C input capture input/output compare output/PWM output pin I/O TGR0D input capture input/output compare output/PWM output pin I/O TGR1A input capture input/output compare output/PWM output pin I/O TGR1B input capture input/output compare output/PWM output pin I/O TGR2A input capture input/output compare output/PWM output pin I/O TGR2B input capture input/output compare output/PWM output pin 1 Input TIOC1A capture/output compare-match 1A TIOC1B Input capture/output compare-match 1B 2 Input TIOC2A capture/output compare-match 2A TIOC2B Input capture/output compare-match 2B Note: The TIOC pins output undefined values when they are set to input capture and timer output by the pin function controller (PFC). Rev.5.00 Sep. 27, 2007 Page 196 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.1.4 Register Configuration Table 10.3 summarizes the MTU register configuration. Table 10.3 Register Configuration Channel Name Shared Timer start register Timer synchro register 0 Timer control register 0 Timer mode register 0 Abbreviation R/W TSTR TSYR TCR0 TMDR0 R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'00 H'00 H'00 H'C0 H'00 H'00 H'40 Address Access Size 1 (Bits) * H'FFFF8240 8, 16, 32 H'FFFF8241 H'FFFF8260 H'FFFF8261 H'FFFF8262 H'FFFF8263 H'FFFF8264 H'FFFF8265 H'FFFF8266 16, 32 H'FFFF8268 H'FFFF826A H'FFFF826C H'FFFF826E H'FFFF8280 8, 16, 32 H'FFFF8281 H'FFFF8282 H'FFFF8284 H'FFFF8285 H'FFFF8286 16, 32 H'FFFF8288 H'FFFF828A Timer I/O control register 0H TIOR0H Timer I/O control register 0L TIOR0L Timer interrupt enable register 0 Timer status register 0 Timer counter 0 General register 0A General register 0B General register 0C General register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 General register 1A General register 1B TIER0 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 TGR1A TGR1B R/(W)* H'C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 R/(W)* H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF Rev.5.00 Sep. 27, 2007 Page 197 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Abbreviation R/W TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B R/W R/W R/W R/W 2 Channel Name 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 General register 2A General register 2B Initial Value H'00 H'C0 H'00 H'40 Address Access Size 1 (Bits) * H'FFFF82A0 8, 16, 32 H'FFFF82A1 H'FFFF82A2 H'FFFF82A4 H'FFFF82A5 H'FFFF82A6 16, 32 H'FFFF82A8 H'FFFF82AA R/(W)* H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF Notes: Do not access empty addresses. 1. 16-bit registers (TCNT, TGR) cannot be read or written in 8-bit units. 2. Write 0 to clear flags. Rev.5.00 Sep. 27, 2007 Page 198 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.2 10.2.1 MTU Register Descriptions Timer Control Register (TCR) The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The MTU has three TCR registers, one for each of the channels 0 to 2. TCR is initialized to H'00 by a power-on reset or the standby mode. Channel 0: TCR0 Bit: 7 CCLR2 Initial value: R/W: 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Channels 1, 2: TCR1, TCR2 Bit: 7 ⎯ Initial value: R/W: 0 R 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W Rev.5.00 Sep. 27, 2007 Page 199 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 7 to 5⎯Counter Clear 2 to 0 (CCLR2 to CCLR0): Select the counter clear source for the TCNT counter. Channels 0 Bit 7 Bit 6 CCLR2 CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 1 0 0 1 1 0 1 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of 1 other channel counters operating in sync.* TCNT clear disabled TCNT is cleared by TGRC compare-match or input capture* TCNT is cleared by TGRD compare-match or input capture* 2 2 Synchronizing clear: TCNT is cleared in synchronization with clear of 1 other channel counters operating in sync* Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization. 2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because the buffer registers have priority and compare-match/input captures do not occur. Channels 1, 2 Bit 7 Bit 6 1 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with 2 clear of other channel counters operating in sync* Notes: 1. The bit 7 of channels 1 and 2 is reserved. It always reads 0, and cannot be modified. 2. Setting the SYNC bit of the TSYR to 1 sets the synchronization. Rev.5.00 Sep. 27, 2007 Page 200 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 4 and 3⎯Clock Edge 1, 0 (CKEG1 and CKEG0): CKEG1 and CKEG0 select the input clock edges. When counting is done on both edges of the internal clock the input clock frequency becomes 1/2 (Example: both edges of φ/4 = rising edge of φ/2). When phase count mode is used with channels 1, 2, these settings are ignored, as the phase count mode settings have priority. Bit 4 Bit 3 CKEG1 CKEG0 Description 0 0 1 1 X Count on rising edges Count on falling edges Count on both rising and falling edges (initial value) Notes: 1. X: 0 or 1, don't care. 2. Internal clock edge selection is effective when the input clock is φ/4 or slower. These settings are ignored when φ/1, or the overflow/underflow of another channel is selected for the input clock. Bits 2 to 0⎯Timer Prescaler 2 to 0 (TPSC2 to TPSC0): TPSC2 to TPSC0 select the counter clock source for the TCNT. An independent clock source can be selected for each channel. Table 10.4 shows the possible settings for each channel. Table 10.4 MTU Clock Sources Internal Clock Channel 0 1 2 Note: φ/1 O O O φ/4 O O O φ/ 16 O O O φ/ 64 O O O φ/ 256 X O X External Clock Other Channel Overflow/ TCL TCL TCL φ/ KA KB KC 1024 Underflow X X O X O X O O O O O O O X O TCL KD O X X Symbols: O: Setting possible X: Setting impossible Rev.5.00 Sep. 27, 2007 Page 201 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channel 0 Bit 2 Bit 1 TPSC2 TPSC1 0 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with φ/1 Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input External clock: count with the TCLKC pin input External clock: count with the TCLKD pin input (initial value) Channel 1 Bit 2 Bit 1 TPSC2 TPSC1 0 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with φ/1 Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input Internal clock: count with φ/256 Count with the TCNT2 overflow/underflow (initial value) Note: These settings are ineffective when channel 1 is in phase counting mode. Rev.5.00 Sep. 27, 2007 Page 202 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channel 2 Bit 2 Bit 1 TPSC2 TPSC1 0 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: count with φ/1 Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input External clock: count with the TCLKC pin input Internal clock: count with φ/1024 (initial value) Note: These settings are ineffective when channel 2 is in phase counting mode. 10.2.2 Timer Mode Register (TMDR) The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset or the standby mode. Channel 0: TMDR0 Bit: 7 ⎯ Initial value: R/W: 1 R 6 ⎯ 1 R 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Channels 1, 2: TMDR1, TMDR2 Bit: 7 ⎯ Initial value: R/W: 1 R 6 ⎯ 1 R 5 ⎯ 0 R 4 ⎯ 0 R 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Rev.5.00 Sep. 27, 2007 Page 203 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 7 and 6⎯Reserved: These bits always read as 1. The write value should always be 1. Bit 5⎯Buffer Operation B (BFB): Designates whether to use the TGRB register for normal operation, or buffer operation in combination with the TGRD register. When using TGRD as a buffer register, no TGRD register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRD registers. This bit always read as 0. The write value should always be 0. Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD buffer operation (initial value) Bit 4⎯Buffer Operation A (BFA): Designates whether to use the TGRA register for normal operation, or buffer operation in combination with the TGRC register. When using TGRC as a buffer register, no TGRC register input capture/output compares are generated. This bit is reserved in channels 1 and 2, which have no TGRC registers. This bit always read as 0. The write value should always be 0. Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC buffer operation (initial value) Rev.5.00 Sep. 27, 2007 Page 204 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 3 to 0⎯Modes 3 to 0 (MD3 to MD0): These bits set the timer operation mode. Bit 3 MD3 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Note: * 0 1 Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2 Phase counting mode 1* Phase counting mode 2* Phase counting mode 3* Phase counting mode 4* Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) (initial value) Phase measurement mode can not be set for channel 0. 10.2.3 Timer I/O Control Register (TIOR) The TIOR is a register that controls the TGR. The MTU has four TIOR registers, two for channels 0 and one each for channels 1 and 2. TIOR is initialized to H'00 by a power-on reset or the standby mode. Channel 0: TIOR0H Channels 1, 2: TIOR1, TIOR2 Bit: 7 IOB3 Initial value: R/W: 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Rev.5.00 Sep. 27, 2007 Page 205 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 7 to 4⎯I/O Control B3 to B0 (IOB3 to IOB0): These bits set the TGRB register function. Bits 3 to 0⎯I/O Control A3 to B0 (IOA3 to IOA0): These bits set the TGRA register function. Channel 0: TIOR0L Bit: 7 IOD3 Initial value: R/W: 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W Note: When the TGRC or TGRD registers are set for buffer operation, these settings become ineffective and the operation is as a buffer register. Bits 7 to 4⎯I/O Control D3 to D0 (IOD3 to IOD0): These bits set the TGRD register function. Bits 3 to 0⎯I/O Control C3 to C0 (IOC3 to IOC0): These bits set the TGRC register function. Rev.5.00 Sep. 27, 2007 Page 206 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channel 0 (TIOR0H Register) Bits 7 to 4⎯I/O Control B3 to B0 (IOB3 to IOB0): These bits set the TGR0B register function. Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Capture input source Input capture on TCNT1 count is channel 1/ up/count down count clock TGR0B is an input capture register Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Capture input source Input capture on rising edge is the TIOC0B pin Input capture on falling edge Input capture on both edges TGR0B is an output compare register Output disabled Initial output is 0 (initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 207 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 3 to 0⎯I/O Control A3 to A0 (IOA3 to IOA0): These bits set the TGR0A register function. Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Capture input source Input capture on TCNT1 count is channel 1/ up/count down count clock Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Capture input source Input capture on rising edge TGR0A is the TIOC0A pin is an input Input capture on falling edge capture register Input capture on both edges TGR0A is an output compare register Output disabled Initial output is 0 (initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 208 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channel 0 (TIOR0L Register) Bits 7 to 4⎯I/O Control D3 to D0 (IOD3 to IOD0): These bits set the TGR0D register function. Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 Description 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: When the BFB bit of TMDR0 is set to 1 and TGR0D is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. Capture input source Input capture on TCNT1 count is channel 1/ up/count down count clock Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Capture input source Input capture on rising edge TGR0D is an input is the TIOC0D pin Input capture on falling edge capture Input capture on both edges register Output disabled TGR0D is an output Initial output is 0 compare register (initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 209 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 3 to 0⎯I/O Control C3 to C0 (IOC3 to IOC0): These bits set the TGR0C register function. Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: When the BFA bit of TMDR0 is set to 1 and TGR0C is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. Capture input source Input capture on TCNT1 count is channel 1/ up/count down count clock Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Capture input source Input capture on rising edge TGR0C is an input is the TIOC0C pin Input capture on falling edge capture Input capture on both edges register Description Output disabled TGR0C is an output Initial output is 0 compare register (initial value) Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 210 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channel 1 (TIOR1 Register) Bits 7 to 4⎯I/O Control B3 to B0 (IOB3 to IOB0): These bits set the TGR1B register function. Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Capture input Input capture on channel source TGR0C 0/TGR0C compare-match/input compare/match capture generation input capture TGR1B is an input capture register Capture input source is the TIOC1B pin Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Description TGR1B is an output compare register Output disabled (initial value) Initial output is 0 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 211 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 3 to 0⎯I/O Control A3 to A0 (IOA3 to IOA0): These bits set the TGR1A register function. Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Capture input Input capture on channel source is TGR0A 0/TGR0A compare-match/input capture generation comparematch/input capture TGR1A is an input capture register Capture input source is the TIOC1A pin Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Description TGR1A is an output compare register Output disabled (initial value) Initial output is 0 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 212 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channel 2 (TIOR2 Register) Bits 7 to 4⎯I/O Control B3 to B0 (IOB3 to IOB0): These bits set the TGR2B register function. Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Input capture on rising edge Input capture on falling edge Input capture on both edges TGR2B is an input capture register Capture input source is the TIOC2B pin Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Description TGR2B is an output compare register Output disabled (initial value) Initial output is 0 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Rev.5.00 Sep. 27, 2007 Page 213 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 3 to 0⎯I/O Control A3 to A0 (IOA3 to IOA0): These bits set the TGR2A register function. Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Input capture on rising edge Input capture on falling edge Input capture on both edges TGR2A is an input capture register Capture input source is the TIOC2A pin Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match Input capture on rising edge Input capture on falling edge Input capture on both edges Description TGR2A is an output compare register Output disabled (initial value) Initial output is 0 Output 0 on compare-match Output 1 on compare-match Toggle output on compare-match 10.2.4 Timer Interrupt Enable Register (TIER) The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel. The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a reset or by standby mode. Channel 0: TIER0 Bit: 7 TTGE Initial value: R/W: 0 R/W 6 ⎯ 1 R 5 ⎯ 0 R 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Rev.5.00 Sep. 27, 2007 Page 214 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Channels 1, 2: TIER1, TIER2 Bit: 7 TTGE Initial value: R/W: 0 R/W 6 ⎯ 1 R 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 ⎯ 0 R 2 ⎯ 0 R 1 TGIEB 0 R/W 0 TGIEA 0 R/W Bit 7⎯A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an A/D conversion start request by a TGRA register input capture/compare-match. Bit 7 TTGE 0 1 Description Disable A/D conversion start requests Enable A/D conversion start request generation (initial value) Bit 6⎯Reserved: This bit always read as 1. The write value should always be 1. Bit 5⎯Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1. This bit is reserved for channel 0. It always reads as 0. The write value should always be 0. Bit 5 TCIEU 0 1 Description Disable UDF interrupt requests (TCIU) Enable UDF interrupt requests (TCIU) (initial value) Bit 4⎯Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the overflow flag TCFV of the timer status register (TSR) is set to 1. Bit 4 TCIEV 0 1 Description Disable TCFV interrupt requests (TCIV) Enable TCFV interrupt requests (TCIV) (initial value) Rev.5.00 Sep. 27, 2007 Page 215 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bit 3⎯TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when the TGFD bit of the channel 0 TSR register is set to 1. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0. Bit 3 TGIED 0 1 Description Disable interrupt requests (TGID) due to the TGFD bit Enable interrupt requests (TGID) due to the TGFD bit (initial value) Bit 2⎯TGR Interrupt Enable C (TGIEC): Enables or disables TGFC interrupt requests when the TGFC bit of the Channel 0 TSR register is set to 1. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0. Bit 2 TGIEC 0 1 Description Disable interrupt requests (TGIC) due to the TGFC bit Enable interrupt requests (TGIC) due to the TGFC bit (initial value) Bit 1⎯TGR Interrupt Enable B (TGIEB): Enables or disables TGFB interrupt requests when the TGFB bit of the TSR register is set to 1. Bit 1 TGIEB 0 1 Description Disable interrupt requests (TGIB) due to the TGFB bit Enable interrupt requests (TGIB) due to the TGFB bit (initial value) Bit 0⎯TGR Interrupt Enable A (TGIEA): Enables or disables TGFA interrupt requests when the TGFA bit of the TSR register is set to 1. Bit 0 TGIEA 0 1 Description Disable interrupt requests (TGIA) due to the TGFA bit Enable interrupt requests (TGIA) due to the TGFA bit (initial value) Rev.5.00 Sep. 27, 2007 Page 216 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.2.5 Timer Status Register (TSR) The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset or by standby mode. Channel 0: TSR0 Bit: 7 ⎯ Initial value: R/W: Note: * 1 R 6 ⎯ 1 R 5 ⎯ 0 R 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Only 0 writes to clear the flags are possible. Channels 1, 2: TSR1, TSR2 Bit: 7 TCFD Initial value: R/W: Note: * 1 R 6 ⎯ 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 ⎯ 0 R 2 ⎯ 0 R 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Only 0 writes to clear the flags are possible. Bit 7⎯Count Direction Flag (TCFD): This status flag indicates the count direction of the channel 1, 2 TCNT counters. This bit is reserved in channel 0. This bit always reads as 1. The write value should always be 1. Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (initial value) Bit 6⎯Reserved: This bit always reads as 1. The write value should always be 1. Rev.5.00 Sep. 27, 2007 Page 217 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bit 5⎯Underflow Flag (TCFU): This status flag indicates the occurrence of a channel 1, 2 TCNT counter underflow. This bit is reserved in channel 0. This bit always reads as 0. The write value should always be 0. Bit 5 TCFU 0 1 Description Clear condition: With TCFU = 1, a 0 write to TCFU after reading it (initial value) Set condition: When the TCNT value underflows (H'0000 → H'FFFF) Bit 4⎯Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter overflow. Bit 4 TCFV 0 1 Description Clear condition: With TCFV = 1, a 0 write to TCFV after reading it (initial value) Set condition: When the TCNT value overflows (H'FFFF → H'0000) Bit 3⎯Input Capture/Output Compare Flag D (TGFD): This status flag indicates the occurrence of a channel 0 TGRD register input capture or compare-match. This bit is reserved in channels 1 and 2. It always reads as 0. The write value should always be 0. Bit 3 TGFD 0 1 Description Clear condition: With TGFD = 1, a 0 write to TGFD following a read (initial value) Set conditions: • • When TGRD is functioning as an output compare register (TCNT = TGRD) When TGRD is functioning as input capture (the TCNT value is sent to TGRD by the input capture signal) Rev.5.00 Sep. 27, 2007 Page 218 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bit 2⎯Input Capture/Output Compare Flag C (TGFC): This status flag indicates the occurrence of a Channel 0 TGRC register input capture or compare-match. This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0. Bit 2 TGFC 0 1 Description Clear condition: With TGFC = 1, a 0 write to TGFC following a read Set conditions: • • When TGRC is functioning as an output compare register (TCNT = TGRC) When TGRC is functioning as input capture (the TCNT value is sent to TGRC by the input capture signal) (initial value) Bit 1⎯Input Capture/Output Compare Flag B (TGFB): This status flag indicates the occurrence of a TGRB register input capture or compare-match. Bit 1 TGFB 0 1 Description Clear condition: With TGFB = 1, a 0 write to TGFB following a read (initial value) Set conditions: • • When TGRB is functioning as an output compare register (TCNT = TGRB) When TGRB is functioning as input capture (the TCNT value is sent to TGRB by the input capture signal) Rev.5.00 Sep. 27, 2007 Page 219 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bit 0⎯Input Capture/Output Compare Flag A (TGFA): This status flag indicates the occurrence of a TGRA register input capture or compare-match. Bit 0 TGFA 0 1 Description Clear condition: With TGFA = 1, a 0 write to TGFA following a read (Cleared by DMAC transfer due to TGFA) (initial value) Set conditions: • • When TGRA is functioning as an output compare register (TCNT = TGRA) When TGRA is functioning as input capture (the TCNT value is sent to TGRA by the input capture signal) 10.2.6 Timer Counters (TCNT) The timer counters (TCNT) are 16-bit counters, with one for each channel, for a total of three. The TCNT are initialized to H'0000 by a power-on reset and when in standby mode. Accessing the TCNT counters in 8-bit units is prohibited. Always access in 16-bit units. Channel Abbreviation 0 1 2 Note: * TCNT0 TCNT1 TCNT2 Function Increment counter Increment/decrement counter* Increment/decrement counter* Can only be used as an increment/decrement counter in phase counting mode, with other channel overflow/underflow counting. It becomes an increment counter in all other cases. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.5.00 Sep. 27, 2007 Page 220 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.2.7 Timer General Register (TGR) Each timer general register (TGR) is a 16-bit register that can function as either an output compare register or an input capture register. There are a total of eight TGR, four for channel 0, and two each for channels 1 and 2. The TGRC and TGRD of channel 0 can be set to operate as buffer registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB with TGRD. The TGRs are initialized to H'FFFF by a power-on reset or in standby mode. Accessing of the TGRs in 8-bit units is disabled; they may only be accessed in 16-bit units. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 10.2.8 Timer Start Register (TSTR) The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer counters (TCNT) of channels 0 to 2. TSTR is initialized to H'00 upon power-on reset or standby mode. Bit: 7 ⎯ Initial value: R/W: 0 R 6 ⎯ 0 R 5 ⎯ 0 R 4 ⎯ 0 R 3 ⎯ 0 R 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Rev.5.00 Sep. 27, 2007 Page 221 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 2 to 0⎯Counter Start 4 to 0 (CST4 to CST0): Select the start and stop of the timer counters (TCNT). The counter start to channel and bit to channel correspondence are indicated in the tables below. Counter Start CST2 CST1 CST0 Channel Channel 2 (TCNT2) Channel 1 (TCNT1) Channel 0 (TCNT0) Bit n CSTn 0 1 Description TCNTn count is halted TCNTn counts (initial value) Note: n = 2 to 0. If 0 is written to the CST bit during operation with the TIOC pin in output status, the counter stops, but the TIOC pin output compare output level is maintained. If a write is done to the TIOR register while the CST bit is a 0, the pin output level is updated to the established initial output value. Bits 7 to 3⎯Reserved: These bits always read as 0. The write value should always be 0. 10.2.9 Timer Synchro Register (TSYR) The timer synchro register (TSYR) is an 8-bit read/write register that selects independent or synchronous TCNT counter operation for channels 0 to 2. Channels for which 1 is set in the corresponding bit will be synchronized. TSYR is initialized to H'00 upon power-on reset or standby mode. Bit: 7 ⎯ Initial value: R/W: 0 R 6 ⎯ 0 R 5 ⎯ 0 R 4 ⎯ 0 R 3 ⎯ 0 R 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Rev.5.00 Sep. 27, 2007 Page 222 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Bits 2 to 0⎯Timer Synchronization 2 to 0 (SYNC2 to SYNC0): Selects operation independent of, or synchronized to, other channels. Synchronous operation allows synchronous clears due to multiple TCNT synchronous presets and other channel counter clears. A minimum of two channels must have SYNC bits set to 1 for synchronous operation. For synchronization clearing, it is necessary to set the TCNT counter clear sources (the CCLR2 to CCLR0 bits of the TCR register), in addition to the SYNC bit. The counter start to channel and bit-to-channel correspondence are indicated in the tables below. Counter Start SYNC2 SYNC1 SYNC0 Channel Channel 2 (TCNT2) Channel 1 (TCNT1) Channel 0 (TCNT0) Bit n SYNCn 0 1 Description Timer counter (TCNTn) independent operation (TCNTn preset/clear unrelated to other channels) Timer counter synchronous operation* 1 2 (initial value) TCNTn synchronous preset/ synchronous clear* possible Notes: n = 2 to 0. 1. Minimum of two channel SYNC bits must be set to 1 for synchronous operation. 2. TCNT counter clear sources (CCLR2 to CCLR0 bits of the TCR register) must be set in addition to the SYNC bit in order to have clear synchronization. Bits 7 to 3⎯Reserved: These bits always read as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 223 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.3 10.3.1 Bus Master Interface 16-Bit Registers The timer counters (TCNT) and general registers (TGR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. Figure 10.2 shows an example of 16-bit register access operation. Internal data bus Upper 8 bits Bus master Lower 8 bits TCNTH TCNTL Bus interface Module data bus Figure 10.2 16-Bit Register Access Operation (Bus Master ↔ TCNT (16 Bit)) 10.3.2 8-Bit Registers All registers other than the TCNT and general registers (TGR) are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figures 10.3 to 10.5). Internal data bus Upper 8 bits Bus master Lower 8 bits TCR Bus interface Module data bus Figure 10.3 8-Bit Register Access Operation (Bus Master ↔ TCR (Upper 8 Bits)) Rev.5.00 Sep. 27, 2007 Page 224 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Internal data bus Upper 8 bits Bus master Lower 8 bits TMDR Bus interface Module data bus Figure 10.4 8-Bit Register Access Operation (Bus Master ↔ TMDR (Lower 8 Bits)) Internal data bus Upper 8 bits Bus master Lower 8 bits TCR TMDR Bus interface Module data bus Figure 10.5 8-Bit Register Access Operation (Bus Master ↔ TCR, TMDR (16 Bit)) Rev.5.00 Sep. 27, 2007 Page 225 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.4 10.4.1 Operation Overview The operation modes are described below. Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. General registers (TGR) can be used as output compare registers or input capture registers. Synchronized Operation: The TCNT of a channel set for synchronized operation does a synchronized preset. When any TCNT of a channel operating in the synchronized mode is rewritten, the TCNTs of other channels are simultaneously rewritten as well. The timer synchronization bits of the TSYR registers of multiple channels set for synchronous operation can be set to clear the TCNTs simultaneously. Buffer Operation: When TGR is an output compare register, the buffer register value of the corresponding channel is transferred to the TGR when a compare-match occurs. When TGR is an input capture register, the TCNT counter value is transferred to the TGR when an input capture occur simultaneously the value previously stored in the TGR is transferred to the buffer register. Cascade Connection Operation: The channel 1 and channel 2 counters (TCNT1 and TCNT2) can be connected together to operate as a 32-bit counter. PWM Mode: In PWM mode, a PWM waveform is output. The output level can be set by the TIOR register. Each TGR can be set for PWM waveform output with a duty cycle between 0% and 100%. Phase Counting Mode: In phase counting mode, the phase differential between two clocks input from the channel 1 and channel 2 external clock input pins is detected and the TCNT counter operates as an up/down counter. In phase counting mode, the corresponding TCLK pins become clock inputs and TCNT functions as an up/down counter. It can be used as a two-phase encoder pulse input. 10.4.2 Basic Functions Always select MTU external pin set function using the pin function controller (PFC). Counter Operation: When a start bit (CST0 to CST2) in the timer start register (TSTR) is set to 1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a freerunning mode and a periodic mode. Rev.5.00 Sep. 27, 2007 Page 226 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) To select the counting operation (figure 10.6): 1. Set bits TPSC2 to TPSC0 in the TCR to select the counter clock. At the same time, set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock. 2. To operate as a periodic counter, set the CCLR2 to CCLR0 bits in the TCR to select TGR as a clearing source for the TCNT. 3. Set the TGR selected in step 2 as an output compare register using the timer I/O control register (TIOR). 4. Write the desired cycle value in the TGR selected in step 2. 5. Set the CST bit in the TSTR to 1 to start counting. Counting mode selection Select counter clock 1 Periodic counter Select counter clear source Select output compare register Set period Start counting Periodic counter Free-running counter 2 3 4 5 Start counting Free-running counter 5 Figure 10.6 Procedure for Selecting the Counting Operation Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves them all in the free-running mode. When a bit in the TSTR is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. When the count overflows from H'FFFF to H'0000, the TCFV bit in the timer status register (TSR) is set to 1. If the TCIEV bit in the timer's corresponding timer interrupt enable register (TIER) is set to 1, the MTU will make an interrupt request to the interrupt controller. After the TCNT overflows, counting continues from H'0000. Figure 10.7 shows an example of free-running counter operation. Rev.5.00 Sep. 27, 2007 Page 227 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.7 Free-Running Counter Operation Periodic Counter Operation Example: Periodic counter operation is obtained for a given channel's TCNT by selecting compare-match as a TCNT clear source. Set the TGR register for period setting to output compare register and select counter clear upon compare-match using the CCLR2 to CCLR0 bits of the timer control register (TCR). After these settings, the TCNT begins incrementing as a periodic counter when the corresponding bit of TSTR is set to 1. When the count matches the TGR register value, the TGF bit in the TSR is set to 1 and the counter is cleared to H'0000. If the TGIE bit of the corresponding TIER is set to 1 at this point, the MTU will make an interrupt request to the interrupt controller. After the compare-match, TCNT continues counting from H'0000. Figure 10.8 shows an example of periodic counting. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 10.8 Periodic Counter Operation Rev.5.00 Sep. 27, 2007 Page 228 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Compare-Match Waveform Output Function: The MTU can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. Procedure for selecting the compare-match waveform output operation (figure 10.9): 1. Set the TIOR to select 0 output or 1 output for the initial value, and 0 output, 1 output, or toggle output for compare-match output. The TIOC pin will output the set initial value until the first compare-match occurs. 2. Set a value in the TGR to select the compare-match timing. 3. Set the CST bit in the TSTR to 1 to start counting. Output selection Select waveform output mode Select output timing Start counting 1 2 3 Figure 10.9 Procedure for Selecting Compare Match Waveform Output Operation Rev.5.00 Sep. 27, 2007 Page 229 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Waveform Output Operation (0 Output/1 Output): Figure 10.10 shows 0 output/1 output. In the example, TCNT is a free-running counter, 1 is output upon compare-match A and 0 is output upon compare-match B. When the pin level matches the set level, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 TIOCA Time Does not change Does not change 1 output TIOCB Does not change Does not change 0 output Figure 10.10 Example of 0 Output/1 Output Waveform Output Operation (Toggle Output): Figure 10.11 shows the toggle output. In the example, the TCNT operates as a periodic counter cleared by compare-match B, with toggle output at both compare-match A and compare-match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCA Time Toggle output Toggle output TIOCB Figure 10.11 Example of Toggle Output Rev.5.00 Sep. 27, 2007 Page 230 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Input Capture Function: In the input capture mode, the TCNT value is transferred into the TGR register when the input edge is detected at the input capture/output compare pin (TIOC). Detection can take place on the rising edge, falling edge, or both edges. Channels 0 and 1 can use other channel counter input clocks or compare-match signals as input capture sources. The procedure for selecting the input capture operation (figure 10.12) is: 1. Set the TIOR to select the input capture function of the TGR, then select the input capture source, and rising edge, falling edge, or both edges as the input edge. 2. Set the CST bit in the TSTR to 1 to start the TCNT counting. Input selection Select input-capture input Start counting Input capture operation 1 2 Figure 10.12 Procedure for Selecting Input Capture Operation Rev.5.00 Sep. 27, 2007 Page 231 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Input Capture Operation: Figure 10.13 shows input capture. The falling edge of TIOCB and both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to clear at the input capture of the TGRB register. TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 TIOCA Counter cleared by TIOCB input (falling edge) Time TGRA TIOCB H'0005 H'0160 H'0010 TGRB H'0180 Figure 10.13 Input Capture Operation 10.4.3 Synchronous Operation In the synchronizing mode, two or more timer counters can be rewritten simultaneously (synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR settings (synchronized clear). The synchronizing mode can increase the number of TGR registers for a single time base. All three channels can be set for synchronous operation. Rev.5.00 Sep. 27, 2007 Page 232 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Procedure for Selecting the Synchronizing Mode (Figure 10.14): 1. Set 1 in the SYNC bit of the timer synchro register (TSYR) to use the corresponding channel in the synchronizing mode. 2. When a value is written in the TCNT in any of the synchronized channels, the same value is simultaneously written in the TCNT in the other channels. 3. Set the counter to clear with output compare/input capture using bits CCLR2 to CCLR0 in the TCR. 4. Set the counter clear source to synchronized clear using the CCLR2 to CCLR0 bits of the TCR. 5. Set the CST bits for the corresponding channels in the TSTR to 1 to start counting in the TCNT. Select synchronizing mode Set synchronizing mode 1 Synchronized preset 2 Synchronized clear Set TCNT Channel that generated clear source? Yes Select counter clear source Start counting No 3 Set counter synchronous clear Start counting 4 5 5 Synchronized preset Counter clear Synchronized clear Figure 10.14 Procedure for Selecting Synchronizing Operation Rev.5.00 Sep. 27, 2007 Page 233 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Synchronized Operation: Figure 10.15 shows an example of synchronized operation. Channels 0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears by synchronous presets and TGR0B register compare-matches. Accordingly, a three-phase PWM waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A, TIOC1A, and TIOC2A pins. See section 10.4.6, PWM Mode, for details on the PWM mode. TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 TIOC0A TIOC1A TIOC2A Time Synchronized clear on TGR0B compare match Figure 10.15 Synchronized Operation Example Rev.5.00 Sep. 27, 2007 Page 234 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.4.4 Buffer Operation Buffer operation is a function of channels 0, 3, and 4. TGRC and TGRD can be used as buffer registers. Table 10.5 shows the register combinations for buffer operation. Table 10.5 Register Combinations Channel 0 General Register TGR0A TGR0B Buffer Register TGR0C TGR0D The buffer operation differs, depending on whether the TGR has been set as an input capture register or an output compare register. When TGR Is an Output Compare Register: When a compare-match occurs, the corresponding channel buffer register value is transferred to the general register. Figure 10.16 shows an example. Compare match signal Buffer register General register Comparator TCNT Figure 10.16 Compare Match Buffer Operation When TGR Is an Input Capture Register: When an input capture occurs, the timer counter (TCNT) value is transferred to the general register (TGR), and the value that had been held up to that time in the TGR is transferred to the buffer register (figure 10.17). Input capture signal Buffer register General register TCNT Figure 10.17 Input Capture Buffer Operation Rev.5.00 Sep. 27, 2007 Page 235 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Procedure for Setting Buffer Mode (Figure 10.18): 1. Use the timer I/O control register (TIOR) to set the TGR as either an input capture or output compare register. 2. Use the timer mode register (TMDR) BFA, and BFB bits to set the TGR for buffer mode. 3. Set the CST bit in the TSTR to 1 to start the count operation. Buffer mode Select TGR function 1 Select buffer mode 2 Start counting 3 Buffer mode Figure 10.18 Buffer Operation Setting Procedure Buffer Operation Examples⎯when TGR Is an Output Compare Register: Figure 10.19 shows an example of channel 0 set to PWM mode 1, and the TGRA and TGRC registers set for buffer operation. The TCNT counter is cleared by a compare-match B, and the output is a 1 upon compare-match A and 0 output upon compare-match B. Because buffer mode is selected, a compare-match A changes the output, and the buffer register TGRC value is simultaneously transferred to the general register TGRA. This operation is repeated with each occurrence of a compare-match A. See section 10.4.6, PWM Mode, for details on the PWM mode. Rev.5.00 Sep. 27, 2007 Page 236 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) TCNT value TGR0B H'0450 H'0200 TGR0A H'0000 H'0200 TGR0C Transfer TGR0A TIOC0A H'0200 H'0450 H'0520 H'0450 Time H'0520 Figure 10.19 Buffer Operation Example (Output Compare Register) Buffer Operation Examples⎯when TGR Is an Input Capture Register: Figure 10.20 shows an example of TGRA set as an input capture register with the TGRA and TGRC registers set for buffer operation. The TCNT counter is cleared by a TGRA register input capture, and the TIOCA pin input capture input edge is selected as both rising and falling edge. Because buffer mode is selected, an input capture A causes the TCNT counter value to be stored in the TGRA register, and the value that was stored in the TGRA up until that time is simultaneously transferred to the TGRC register. Rev.5.00 Sep. 27, 2007 Page 237 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) TCNT value H'0F07 H'09FB H'0532 H'0000 TIOC0A TGRA TGRC H'0532 H'0F07 H'0532 H'09FB H'0F07 Time Figure 10.20 Buffer Operation Example (Input Capture Register) 10.4.5 Cascade Connection Mode Cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. This function operates by using the TPSC2 to TPSC0 bits of the TCR register to set the channel 1 counter clock to count by TCNT2 counter overflow/underflow. Note: When channel 1 is set to phase counting mode, the counter clock settings become ineffective. Table 10.6 shows the cascade connection combinations. Table 10.6 Cascade Connection Combinations Combination Channel 1, channel 2 Upper 16 Bits TCNT1 Lower 16 Bits TCNT2 Rev.5.00 Sep. 27, 2007 Page 238 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Procedure for Setting Cascade Connection Mode (Figure 10.21): 1. Set the TPSC2 to TPSC 0 bits of the channel 1 timer control register (TCR) to B'111 to select “count by TCNT2 overflow/underflow.” 2. Set the CST bits corresponding to the upper and lower 16 bits in the TSTR to 1 to start the count operation. Cascade connection operation Select cascade connection Start counting Cascade connection operation 1 2 Figure 10.21 Procedure for Selecting Cascade Connection Mode Cascade Connection Operation Examples⎯Phase Counting Mode: Figure 10.22 shows an example of operation when the TCNT1 counter is set to count on TCNT2 overflow/underflow and channel 2 is set to phase counting mode. The TCNT1 counter increments with a TCNT2 counter overflow and decrements with a TCNT2 underflow. TCLKA TCLKB TCNT2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT1 0000 0001 0000 Figure 10.22 Cascade Connection Operation Example (Phase Counting Mode) Rev.5.00 Sep. 27, 2007 Page 239 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.4.6 PWM Mode PWM mode outputs the various PWM waveforms from output pins. Output levels of 0 output, 1 output, or toggle output can be selected as the output level for the compare-match of each TGR. A period can be set for a register by using the TGR compare-match as a counter clear source. All channels can be independently set to PWM mode. Synchronous operation is also possible. There are two PWM modes: • PWM mode 1 Generates PWM output using the TGRA and TGRB registers, and TGRC and TGRD registers as pairs. The initial output values are those established in the TGRA and TGRC registers. When the values set in TGR registers being used as a pair are equal, output values will not change even if a compare-match occurs. A maximum of four-phase PWM output is possible for PWM mode 1. • PWM mode 2 Generates PWM output using one TGR register as a period register and another as a duty cycle register. The output value of each pin upon a counter clear is the initial value established by the TIOR register. When the values set in the period register and duty register are equal, output values will not change even if a compare-match occurs. Table 10.7 lists the combinations of PWM output pins and registers. Table 10.7 Combinations of PWM Output Pins and Registers Output Pin Channel 0 (AB pair) 0 (CD pair) 1 2 Register TGR0A TGR0B TGR0C TGR0D TGR1A TGR1B TGR2A TGR2B PWM Mode 1 TIOC0A TIOC0C TIOC1A TIOC2A PWM Mode 2 TIOC 0A TIOC 0B TIOC 0C TIOC 0D TIOC 1A TIOC 1B TIOC 2A TIOC 2B Note: PWM output of the period setting TGR is not possible in PWM mode 2. Rev.5.00 Sep. 27, 2007 Page 240 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Procedure for Selecting the PWM Mode (Figure 10.23): 1. Set bits TPSC2 to TPSC0 in the TCR to select the counter clock source. At the same time, set bits CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock. 2. Set bits CCLR2 to CCLR0 in the TCR to select the TGR to be used as a counter clear source. 3. Set the period in the TGR selected in step 2, and the duty cycle in another TGR. 4. Using the timer I/O control register (TIOR), set the TGR selected in step 3 to act as an output compare register, and select the initial value and output value. 5. Set the MD3 to MD 0 bits in TMDR to select the PWM mode. 6. Set the CST bit in the TSTR to 1 to let the TCNT start counting. PWM mode Select counter clock 1 Select counter clear source 2 Select waveform output level 3 Set TGR 4 Select PWM mode 5 Start counting 6 PWM mode Figure 10.23 Procedure for Selecting the PWM Mode Rev.5.00 Sep. 27, 2007 Page 241 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) PWM Mode Operation Examples⎯PWM Mode 1 (Figure 10.24): A TGRA register comparematch is used as a TCNT counter clear source, the TGRA register initial output value and output compare output value are both 0, and the TGRB register output compare output value is a 1. In this example, the value established in the TGRA register becomes the period and the value established in the TGRB register becomes the duty cycle. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 TIOCA Time Figure 10.24 PWM Mode Operation Example (Mode 1) Rev.5.00 Sep. 27, 2007 Page 242 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) PWM Mode Operation Examples⎯PWM Mode 2 (Figure 10.25): Channels 0 and 1 are set for synchronous operation, TGR1B register compare-match is used as a TCNT counter clear source, the other TGR register initial output value is 0 and output compare output value is 1, and a 5-phase PWM waveform is output. In this example, the value established in the TGR1B register becomes the period and the value established in the other TGR register becomes the duty cycle. TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Counter cleared on TGR1B compare match Time Figure 10.25 PWM Mode Operation Example (Mode 2) 0% Duty Cycle: Figure 10.26 shows an example of a 0% duty cycle PWM waveform output in PWM mode. TCNT value TGRB rewrite TGRA TGRB TGRB rewrite TGRB rewrite Time TIOCA 0% duty cycle Figure 10.26 PWM Mode Operation Example (0% Duty Cycle) Rev.5.00 Sep. 27, 2007 Page 243 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 100% Duty Cycle: Figure 10.27 shows an example of a 100% duty cycle PWM waveform output in PWM mode. In PWM mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter. TCNT value TGRA TGRB rewrite Output does not change if period register and duty cycle register compare matches occur simultaneously TGRB rewrite TGRB TGRB rewrite Time TIOCA 100% duty cycle TCNT value TGRA TGRB rewrite Output does not change if period register and duty cycle register compare matches occur simultaneously TGRB rewrite TGRB TGRB rewrite Time TIOCA 100% duty cycle 0% duty cycle Figure 10.27 PWM Mode Operation Example (100% Duty Cycle) 10.4.7 Phase Counting Mode The phase counting mode detects the phase differential of two external clock inputs and counts the TCNT counter up or down. This mode can be set for channels 1 and 2. When set in the phase counting mode, an external clock is selected for the counter input clock, regardless of the settings of the TPSC2 to TPSC0 bits of TCR or the CKEG1 and CKEG0 bits. TCNT also becomes an up/down counter. Since the TCR CCLR1/CCLR0 bits, TIOR, TIER, and TGR functions are all enabled, input capture and compare-match functions and interrupt sources can be used. When the TCNT counter is incrementing, an overflow sets the TSR register TCFV (overflow flag). When it is decrementing, an underflow sets the TCFU (underflow flag). Rev.5.00 Sep. 27, 2007 Page 244 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) The TSR register TCFD bit is a count direction flag. Read the TCFD flag to confirm whether the TCNT is incrementing or decrementing. Table 10.8 shows the correspondence between channels and external clock pins. Table 10.8 Phase Counting Mode Clock Input Pins Channel 1 2 A Phase Input Pin TCLKA TCLKC B Phase Input Pin TCLKB TCLKD Procedure for Selecting the Phase Counting Mode (Figure 10.28): 1. Set the MD3 to MD0 bits of the timer mode register (TMDR) to select the phase counting mode. 2. Set the CST bit of the timer start register (TSTR) to 1 to start the count. Phase counting mode Select phase counting mode Start counting Phase counting mode 1 2 Figure 10.28 Procedure for Selecting the Phase Counting Mode Phase Counting Operation Examples: The phase counting mode uses the phase difference between two external clocks to increment/decrement the TCNT counter. There are 4 modes, depending on the count conditions. Phase Counting Mode 1: Figure 10.29 shows an example of phase counting mode 1 operation. Table 10.9 lists the up counting and down counting conditions for the TCNT. Rev.5.00 Sep. 27, 2007 Page 245 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement Time Figure 10.29 Phase Counting Mode 1 Operation Table 10.9 Phase Count Mode 1 Up/Down Counting Conditions TCLKA (Channel 1) TCLKC (Channel 2) 1 (high level) 0 (low level) Rising edge Falling edge 1 (high level) 0 (low level) Rising edge Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Rising edge Falling edge 0 (low level) 1 (high level) Falling edge Rising edge 1 (high level) 0 (low level) Decrement Operation Increment Rev.5.00 Sep. 27, 2007 Page 246 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Phase Count Mode 2: Figure 10.30 shows an example of phase counting mode 2 operation. Table 10.10 lists the up counting and down counting conditions for the TCNT. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Increment Decrement Time Figure 10.30 Phase Counting Mode 2 Operation Table 10.10 Phase Count Mode 2 Up/Down Counting Conditions TCLKA (Channel 1) TCLKC (Channel 2) 1 (high level) 0 (low level) Rising edge Falling edge 1 (high level) 0 (low level) Rising edge Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Rising edge Falling edge 0 (low level) 1 (high level) Falling edge Rising edge 1 (high level) 0 (low level) Decrement Increment Does not count (don't care) Operation Does not count (don't care) Rev.5.00 Sep. 27, 2007 Page 247 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Phase Count Mode 3: Figure 10.31 shows an example of phase counting mode 3 operation. Table 10.11 lists the up counting and down counting conditions for the TCNT. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Increment Decrement Time Figure 10.31 Phase Counting Mode 3 Operation Table 10.11 Phase Count Mode 3 Up/Down Counting Conditions TCLKA (Channel 1) TCLKC (Channel 2) 1 (high level) 0 (low level) Rising edge Falling edge 1 (high level) 0 (low level) Rising edge Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Rising edge Falling edge 0 (low level) 1 (high level) Falling edge Rising edge 1 (high level) 0 (low level) Increment Decrement Does not count (don't care) Operation Does not count (don't care) Rev.5.00 Sep. 27, 2007 Page 248 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Phase Count Mode 4: Figure 10.32 shows an example of phase counting mode 4 operation. Table 10.12 lists the up counting and down counting conditions for the TCNT. TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) TCNT value Increment Decrement Time Figure 10.32 Phase Counting Mode 4 Operation Table 10.12 Phase Count Mode 4 Up/Down Counting Conditions TCLKA (Channel 1) TCLKC (Channel 2) 1 (high level) 0 (low level) Rising edge Falling edge 1 (high level) 0 (low level) Rising edge Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Rising edge Falling edge 0 (low level) 1 (high level) Falling edge Rising edge 1 (high level) 0 (low level) Does not count (don't care) Decrement Does not count (don't care) Operation Increment Phase Counting Mode Application Example: Figure 10.33 shows an example where channel 1 is set to phase counting mode and is teamed with channel 0 to input a two-phase encoder pulse for a servo motor to accurately detect position and speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A phase and B phase are input to the TCLKA and TCLKB pins. Channel 0 is set so that the TCNT counter is cleared on a TGR0C register compare-match, and the TGR0A and TGR0C registers are used with the compare-match function to establish the speed control and position control periods. The TGR0B register is used with the input capture function, Rev.5.00 Sep. 27, 2007 Page 249 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) and the TGR0B and TGR0D registers are employed for buffer operation. The channel 1 counter input clock is used as the TGR0B register input capture source, and a pulse width of four times the 2-phase encoder pulse is detected. The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0 TGR0A and TGR0C register compare-match is used as an input capture source, and all of the control period increment and decrement values are stored. This procedure enables the accurate detection of position and speed. Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) TGR0C (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 + − + − Figure 10.33 Phase Count Mode Application Example Rev.5.00 Sep. 27, 2007 Page 250 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.5 10.5.1 Interrupts Interrupt Sources and Priority Ranking The MTU has three interrupt sources: TGR register compare-match/input captures, TCNT counter overflows and TCNT counter underflows. Because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled. When an interrupt source is generated, the corresponding status flag in the timer status register (TSR) is set to 1. If the corresponding enable/disable bit in the timer input enable register (TIER) is set to 1 at this time, the MTU makes an interrupt request of the interrupt controller. The interrupt request is canceled by clearing the status flag to 0. The channel priority order can be changed with the interrupt controller. The priority ranking within a channel is fixed. For more information, see section 6, Interrupt Controller. Table 10.13 lists the MTU interrupt sources. Input Capture/Compare Match Interrupts: If the TGIE bit of the timer input enable register (TIER) is already set to 1 when the TGF flag in the timer status register (TSR) is set to 1 by a TGR register input capture/compare-match of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TGF flag to 0. The MTU has 8 input capture/compare-match interrupts; four for channel 0, and two each for channels 1 and 2. Overflow Interrupts: If the TCIEV bit of the TIER is already set to 1 when the TCFV flag in the TSR is set to 1 by a TCNT counter overflow of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TCFV flag to 0. The MTU has three overflow interrupts, one for each channel. Underflow Interrupts: If the TCIEU bit of the TIER is already set to 1 when the TCFU flag in the TSR is set to 1 by a TCNT counter underflow of any channel, an interrupt request is sent to the interrupt controller. The interrupt request is canceled by clearing the TCFU flag to 0. The MTU has two underflow interrupts, one each for channels 1 and 2. Rev.5.00 Sep. 27, 2007 Page 251 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Table 10.13 MTU Interrupt Sources Channel 0 Interrupt Source TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Note: * Description TGR0A input capture/compare-match TGR0B input capture/compare-match TGR0C input capture/compare-match TGR0D input capture/compare-match TCNT0 overflow TGR1A input capture/compare-match TGR1B input capture/compare-match TCNT1 overflow TCNT1 underflow TGR2A input capture/compare-match TGR2B input capture/compare-match TCNT2 overflow TCNT2 underflow DMAC Activation Yes No No No No Yes No No No Yes No No No Low Priority* High Indicates the initial status following reset. The ranking of channels can be altered using the interrupt controller. 10.5.2 DMAC Activation The TGRA register input capture/compare-match interrupt of any channel can be used as a source to activate the on-chip DMAC. For details, refer to section 9, Direct Memory Access Controller (DMAC). The MTU has three TGRA register input capture/compare-match interrupts, one for any channel, that can be used as DMAC activation sources. 10.5.3 A/D Converter Activation The TGRA register input capture/compare-match of any channel can be used to activate the onchip A/D converter. If the TTGE bit of the TIER is already set to 1 when the TGFA flag in the TSR is set to 1 by a TGRA register input capture/compare-match of any of the channels, an A/D conversion start request is sent to the A/D converter. If the MTU conversion start trigger is selected at such a time on the A/D converter side when this happens, the A/D conversion starts. Rev.5.00 Sep. 27, 2007 Page 252 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) The MTU has three TGRA register input capture/compare-match interrupts, one for each channel, that can be used as A/D converter activation sources. 10.6 10.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Count timing for the TCNT counter with internal clock operation is shown in figure 10.34. Count timing with external clock operation (normal mode) is shown in figure 10.35, and figure 10.36 shows count timing with external clock operation (phase counting mode). φ Internal clock TCNT input clock TCNT N−1 N N+1 N+2 Falling edge Rising edge Falling edge Figure 10.34 TCNT Count Timing during Internal Clock Operation φ Internal clock TCNT input clock TCNT N−1 N N+1 N+2 Falling edge Rising edge Falling edge Figure 10.35 TCNT Count Timing during External Clock Operation (Normal Mode) Rev.5.00 Sep. 27, 2007 Page 253 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) φ External clock TCNT input clock N−1 N N+1 Falling edge Rising edge Falling edge TCNT Figure 10.36 TCNT Count Timing during External Clock Operation (Phase Counting Mode) Output Compare Output Timing: The compare-match signal is generated at the final state of TCNT and TGR matching. When a compare-match signal is issued, the output value set in TIOR is output to the output compare output pin (the TIOC pin). After TCNT and TGR matching, a compare-match signal is not issued until immediately before the TCNT input clock. Output compare output timing (normal mode and PWM mode) is shown in figure 10.37. φ TCNT input clock TCNT N N+1 TGR Comparematch signal TIOC pin N Figure 10.37 Output Compare Output Timing (Normal Mode/PWM Mode) Rev.5.00 Sep. 27, 2007 Page 254 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Input Capture Signal Timing: Figure 10.38 illustrates input capture timing. φ Input capture input Input capture signal TCNT N N+1 N+2 Rising edge Falling edge TGR N N+2 Figure 10.38 Input Capture Input Signal Timing Counter Clearing Timing Due to Compare-Match/Input Capture: Timing for counter clearing due to compare-match is shown in figure 10.39. Figure 10.40 shows the timing for counter clearing due to input capture. φ Comparematch signal Counter clear signal TCNT N H'0000 TGR N Figure 10.39 Counter Clearing Timing (Compare-Match) Rev.5.00 Sep. 27, 2007 Page 255 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) φ Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 10.40 Counter Clearing Timing (Input Capture) Buffer Operation Timing: Compare-match buffer operation timing is shown in figure 10.41. Figure 10.42 shows input capture buffer operation timing. φ TCNT Comparematch signal Comparematch buffer signal TGRA, TGRB n n+1 n N TGRC, TGRD N Figure 10.41 Buffer Operation Timing (Compare-Match) Rev.5.00 Sep. 27, 2007 Page 256 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) φ Input capture signal Input capture signal buffer N N+1 TCNT TGRA, TGRB n N N+1 TGRC, TGRD n N Figure 10.42 Buffer Operation Timing (Input Capture) Rev.5.00 Sep. 27, 2007 Page 257 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.6.2 Interrupt Signal Timing Setting TGF Flag Timing during Compare-Match: Figure 10.43 shows timing for the TGF flag of the timer status register (TSR) due to compare-match, as well as TGI interrupt request signal timing. φ TCNT input clock TCNT N N+1 TGR Comparematch signal TGF flag N TGI interrupt Figure 10.43 TGI Interrupt Timing (Compare Match) Rev.5.00 Sep. 27, 2007 Page 258 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Setting TGF Flag Timing during Input Capture: Figure 10.44 shows timing for the TGF flag of the timer status register (TSR) due to input capture, as well as TGI interrupt request signal timing. φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.44 TGI Interrupt Timing (Input Capture) Rev.5.00 Sep. 27, 2007 Page 259 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Setting Timing for Overflow Flag (TCFV)/Underflow Flag (TCFU): Figure 10.45 shows timing for the TCFV flag of the timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing. Figure 10.46 shows timing for the TCFU flag of the timer status register (TSR) due to underflow, as well as TCIU interrupt request signal timing. φ TCNT input clock TCNT (underflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 10.45 TCIV Interrupt Setting Timing φ TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF TCIU interrupt Figure 10.46 TCIU Interrupt Setting Timing Rev.5.00 Sep. 27, 2007 Page 260 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Status Flag Clearing Timing: The status flag is cleared when the CPU reads a 1 status followed by a 0 write. For DMA controller activation, clearing can also be done automatically. Figure 10.47 shows the timing for status flag clearing by the CPU. Figure 10.48 shows timing for clearing due to the DMA controller. TSR write cycle T1 φ Address T2 TSR address Write signal Status flag Interrupt request signal Figure 10.47 Timing of Status Flag Clearing by the CPU DMAC read cycle T1 T2 φ Source address Destination address DMAC write cycle T1 T2 Address Status flag Interrupt request signal Figure 10.48 Timing of Status Flag Clearing by DMAC Activation Rev.5.00 Sep. 27, 2007 Page 261 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7 Usage Notes This section describes contention and other matters requiring special attention during MTU operations. 10.7.1 Input Clock Limitations The input clock pulse width, in the case of single edge, must be 1.5 states or greater, and 2.5 states or greater for both edges. Normal operation cannot be guaranteed with lesser pulse widths. In phase counting mode, the phase difference between the two input clocks and the overlap must be 1.5 states or greater for each, and the pulse width must be 2.5 states or greater. Input clock conditions for phase counting mode are shown in figure 10.49. Phase Phase difference difference Overlap Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap: 1.5 states or greater Pulse width: 2.5 states or greater Figure 10.49 Phase Difference, Overlap, and Pulse Width in Phase Count Mode 10.7.2 Note on Cycle Setting When setting a counter clearing by compare-match, clearing is done in the final state when TCNT matches the TGR value (update timing for count value on TCNT match). The actual number of states set in the counter is given by the following equation: f= φ (N + 1) (f: counter frequency, φ: operating frequency, N: value set in the TGR) Rev.5.00 Sep. 27, 2007 Page 262 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.3 Contention between TCNT Write and Clear If a counter clear signal is issued in the T2 state during the TCNT write cycle, TCNT clearing has priority, and TCNT write is not conducted (figure 10.50). TCNT write cycle T1 φ Address Write signal Counter clear signal TCNT N H'0000 TCNT address T2 Figure 10.50 TCNT Write and Clear Contention Rev.5.00 Sep. 27, 2007 Page 263 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.4 Contention between TCNT Write and Increment If a count-up signal is issued in the T2 state during the TCNT write cycle, TCNT write has priority, and the counter is not incremented (figure 10.51). TCNT write cycle T1 φ Address T2 TCNT address Write signal TCNT input clock TCNT N M TCNT write data Figure 10.51 TCNT Write and Increment Contention Rev.5.00 Sep. 27, 2007 Page 264 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.5 Contention between Buffer Register Write and Compare Match If a compare-match occurs in the T2 state of the TGR write cycle, data is transferred by the buffer operation from the buffer register to the TGR. Data to be transferred on channel 0 is that after write (figure 10.52). TGR write cycle T1 φ Address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register TGR N M M Buffer register address T2 Figure 10.52 TGR Write and Compare-Match Contention (Channel 0) Rev.5.00 Sep. 27, 2007 Page 265 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.6 Contention between TGR Read and Input Capture If an input capture signal is issued in the T1 state of the TGR read cycle, the read data is that after input capture transfer (figure 10.53). TGR read cycle T1 φ Address Read signal Input capture signal TGR X M TGR address T2 Internal data bus M Figure 10.53 TGR Read and Input Capture Contention Rev.5.00 Sep. 27, 2007 Page 266 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.7 Contention between TGR Write and Input Capture If an input capture signal is issued in the T2 state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure 10.54). TGR write cycle T1 φ Address Write signal Input capture signal TCNT TGR M M TGR address T2 Figure 10.54 TGR Write and Input Capture Contention Rev.5.00 Sep. 27, 2007 Page 267 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.8 Contention between Buffer Register Write and Input Capture If an input capture signal is issued in the T2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 10.55). Buffer register write cycle T1 φ Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address T2 Figure 10.55 Buffer Register Write and Input Capture Contention Rev.5.00 Sep. 27, 2007 Page 268 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.9 Contention between TGR Write and Compare Match If a compare-match occurs in the T2 state of the TGR write cycle, data is written to the TGR and a compare-match signal is issued (figure 10.56). TGR write cycle T1 φ Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address T2 Figure 10.56 TGR Write and Compare Match Contention 10.7.10 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT1 count (during a TCNT2 overflow/underflow) in the T2 state of the TCNT2 write cycle, the write to TCNT2 is conducted, and the TCNT1 count signal is prohibited. At this point, if there is match with TGR1A and the TCNT1 value, a compare signal is issued. Furthermore, when the TCNT1 count clock is selected as the input capture source of channel 0, TGRA0 to TGRD0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB1, TGRB1 carries out input capture operation. The timing is shown in figure 10.57. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Rev.5.00 Sep. 27, 2007 Page 269 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) TCNT write cycle T1 φ Address Write signal TCNT2 H'FFFE H'FFFF TCNT2 write data TGR2A, TGR2B Channel 2 comparematch signal A/B TCNT1 input clock TCNT1 TGR1A Channel 1 comparematch signal A TGR1B Channel 1 inputcapture signal B TCNT0 P N M M M Disabled H'FFFF N N+1 TCNT2 address T1 TGR0A to TGR0D Channel 0 input capture signal A to D Q P Figure 10.57 TCNT2 Write and Overflow/Underflow Contention with Cascade Connection Rev.5.00 Sep. 27, 2007 Page 270 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.58 shows the operation timing when a TGR compare-match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF flag Disabled TCFV flag Figure 10.58 Contention between Overflow and Counter Clearing Rev.5.00 Sep. 27, 2007 Page 271 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.7.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 10.59 shows the operation timing in this case. TCNT write cycle T1 φ T2 Address TCNT address Write signal TCNT input clock TCNT H'FFFF N TCNT write data Disabled TCFV flag Figure 10.59 Contention between TCNT Write and Overflow 10.7.13 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode 1 In PWM mode 1, the TGRA and TGRB registers are used in pairs and PWM waveform is output to the TIOCA pin. In the same manner, the TGRC and TGRD registers are used in pairs and PWM waveform is output to the TIOCC pin. If either the TGRC or TGRD register is operating as a buffer register, the TIOCC pin cannot execute default output setting or PWM waveform output with the I/O control register (TIOR). Note that for channel 0, the TIOCC pin allows both default output setting by TIOR and PWM output when setting buffer operation only for the TGRD register in PWM mode 1. When using channel 0 in PWM mode 1 and setting buffer operation, use both the TGRC and TGRD registers as buffer registers. Rev.5.00 Sep. 27, 2007 Page 272 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) 10.8 10.8.1 MTU Output Pin Initialization Operating Modes The MTU has the following four operating modes. Waveform output is possible in all of these modes. • Normal mode (channels 0 to 2) • PWM mode 1 (channels 0 to 2) • PWM mode 2 (channels 0 to 2) • Phase counting modes 1 to 4 (channels 1 and 2) The MTU output pin initialization method for each of these modes is described in this section. 10.8.2 Reset Start Operation The MTU output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: Channel number and port notation are substituted for *. 10.8.3 Operation in Case of Re-Setting Due to Error during Operation, Etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has four operating modes, as stated above. There are thus 16 mode transition combinations. Possible mode transition combinations are shown in table 10.14. Rev.5.00 Sep. 27, 2007 Page 273 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) Table 10.14 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM Legend: Normal: PWM1: PWM2: PCM: Normal (1) (5) (9) (13) PWM1 (2) (6) (10) (14) PWM2 (3) (7) (11) (15) PCM (4) (8) (12) (16) Normal mode PWM mode 1 PWM mode 2 Phase counting modes 1 to 4 The above abbreviations are used in some places in following descriptions. 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. • In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC*D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. • In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. • In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. • In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 10.14. The active level is assumed to be low. Rev.5.00 Sep. 27, 2007 Page 274 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.60 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 10.60 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. After a reset, MTU output is low and ports are in the high-impedance state. 2. After a reset, the TMDR setting is for normal mode. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 4. Set MTU output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Not necessary when restarting in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 275 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.61 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 10.61 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.60. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 276 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 10.62 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) Figure 10.62 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.60. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 277 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.63 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after resetting. 1 2 RESET TMDR (normal) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 10.63 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.60. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 278 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (5) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 10.64 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 10.64 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. After a reset, MTU output is low and ports are in the high-impedance state. 2. Set PWM mode 1. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) 4. Set MTU output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 279 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (6) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 10.65 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) • Not initialized (TIOC*B) Figure 10.65 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.64. 10. Not necessary when restarting in PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 280 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 10.66 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) • Not initialized (cycle register) Figure 10.66 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.64. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 281 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.67 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after resetting. 1 2 RESET TMDR (PWM1) 3 4 5 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 6 Match 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 10.67 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.64. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 282 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (9) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 10.68 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) Figure 10.68 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. After a reset, MTU output is low and ports are in the high-impedance state. 2. Set PWM mode 2. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC*A is the cycle register.) 4. Set MTU output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 283 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (10) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 10.69 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) • Not initialized (TIOC*B) Figure 10.69 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.68. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 284 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (11) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 10.70 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) • Not initialized (cycle register) Figure 10.70 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.68. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 285 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (12) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.71 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after resetting. 1 2 3 4 5 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) Figure 10.71 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.68. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 286 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (13) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.72 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 10.72 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. After a reset, MTU output is low and ports are in the high-impedance state. 2. Set phase counting mode. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 4. Set MTU output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 287 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (14) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.73 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 10.73 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 10.72. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 288 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (15) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 10.74 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) Figure 10.74 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 10.72. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 289 of 716 REJ09B0398-0500 10. Multifunction Timer Pulse Unit (MTU) (16) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.75 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 PFC TSTR Match Error PFC TSTR TMDR (MTU) (1) occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU output TIOC*A TIOC*B Port output PEn PEn Note: n = 0 to 15 Hi-Z Hi-Z Figure 10.75 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 10.72. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.5.00 Sep. 27, 2007 Page 290 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) Section 11 Watchdog Timer (WDT) 11.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When the watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. The WDT is also used in recovering from the standby mode. 11.1.1 Features The WDT has the following features: • Works in watchdog timer mode or interval timer mode. • Outputs WDTOVF in the watchdog timer mode. When the counter overflows in the watchdog timer mode, overflow signal WDTOVF is output externally. You can select whether to reset the chip internally when this happens. • Generates interrupts in the interval timer mode. When the counter overflows, it generates an interval timer interrupt. • Clears standby mode. • Works with eight counter input clocks. Rev.5.00 Sep. 27, 2007 Page 291 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.1.2 Block Diagram Figure 11.1 is the block diagram of the WDT. Overflow Interrupt control Clock Clock select ITI (interrupt signal) WDTOVF Internal reset signal* Reset control φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources RSTCSR TCNT TCSR Module bus WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Bus interface Note: * The internal reset signal can be generated by setting the register. Figure 11.1 WDT Block Diagram 11.1.3 Pin Configuration Table 11.1 shows the pin configuration. Table 11.1 Pin Configuration Pin Watchdog timer overflow Abbreviation WDTOVF I/O O Function Outputs the counter overflow signal in the watchdog timer mode Rev.5.00 Sep. 27, 2007 Page 292 of 716 REJ09B0398-0500 Internal data bus 11. Watchdog Timer (WDT) 11.1.4 Register Configuration Table 11.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 11.2 WDT Registers Address Name Timer control/status register Timer counter Reset control/status register Abbreviation R/W TCSR TCNT RSTCSR R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'1F Write* 1 Read* 2 H'FFFF8610 H'FFFF8610 H'FFFF8611 H'FFFF8612 H'FFFF8613 Notes: 1. Write by word transfer. It cannot be written in byte or longword. 2. Read by byte transfer. It cannot be read in word or longword. 3. Only 0 can be written in bit 7 to clear the flag. 11.2 11.2.1 Register Descriptions Timer Counter (TCNT) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of the TCSR. The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not initialized in the standby mode. Rev.5.00 Sep. 27, 2007 Page 293 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.2.2 Timer Control/Status Register (TCSR) Bit: 7 OVF Initial value: R/W: 0 R/(W) 6 WT/IT 0 R/W 5 TME 0 R/W 4 ⎯ 1 R 3 ⎯ 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for details.) Its functions include selecting the timer mode and clock source. Bits 7 to 5 are initialized to 000 by a power-on reset or in standby mode. Bits 2 to 0 are initialized to 000 by a power-on reset, but retain their values in the standby mode. Bit 7⎯Overflow Flag (OVF): Indicates that the TCNT has overflowed from H'FF to H'00 in the interval timer mode. It is not set in the watchdog timer mode. Bit 7 OVF 0 1 Description No overflow of TCNT in interval timer mode Cleared by reading OVF, then writing 0 in OVF TCNT overflow in the interval timer mode (initial value) Bit 6⎯Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. When the TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6 WT/IT 0 1 Description Interval timer mode: interval timer interrupt request to the CPU when TCNT overflows (initial value) Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. (Section 11.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in the watchdog timer mode.) Rev.5.00 Sep. 27, 2007 Page 294 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) Bit 5⎯Timer Enable (TME): Enables or disables the timer. Bit 5 TME 0 1 Description Timer disabled: TCNT is initialized to H'00 and count-up stops (initial value) Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. Bits 4 and 3⎯Reserved: These bits always read as 1. The write value should always be 1. Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the system clock (φ). Description Bit 2 CKS2 0 0 0 0 1 1 1 1 Note: * Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Clock Source φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Overflow Interval* (φ = 28.7 MHz) 573.4 μs 1.1 ms 2.3 ms 4.6 ms 9.2 ms 36.7 ms 73.4 ms (initial value) 17.9 μs The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Rev.5.00 Sep. 27, 2007 Page 295 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.2.3 Reset Control/Status Register (RSTCSR) Bit: 7 WOVF Initial value: R/W: 0 R/(W)* 6 RSTE 0 R/W 5 ⎯ 0 R 4 ⎯ 1 R 3 ⎯ 1 R 2 ⎯ 1 R 1 ⎯ 1 R 0 ⎯ 1 R Note: * Only 0 can be written in bit 7 to clear the flag. The RSTCSR is an 8-bit readable and writable register. (The RSTCSR differs from other registers in that it is more difficult to write. See section 11.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by the overflow of the WDT. It is initialized to H'1F in standby mode. Bit 7⎯Watchdog Timer Overflow Flag (WOVF): Indicates that the TCNT has overflowed (H'FF to H'00) in the watchdog timer mode. It is not set in the interval timer mode. Bit 7 WOVF 0 1 Description No TCNT overflow in watchdog timer mode Set by TCNT overflow in watchdog timer mode (initial value) Cleared when software reads WOVF, then writes 0 in WOVF Bit 6⎯Reset Enable (RSTE): Selects whether to reset the chip internally if the TCNT overflows in the watchdog timer mode. Bit 6 RSTE 0 1 Description Not reset when TCNT overflows Reset when TCNT overflows (initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. Bit 5⎯Reserved: This bit always read as 0. The write value should always be 0. Bits 4 to 0⎯Reserved: These bits always read as 1. The write value should always be 1. Rev.5.00 Sep. 27, 2007 Page 296 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.2.4 Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. The TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the TCSR) (figure 11.2). This transfers the write data from the lower byte to the TCNT or TCSR. Writing to the TCNT 15 Address: H'FFFF8610 H'5A 8 7 Write data 0 Writing to the TCSR 15 Address: H'FFFF8610 H'A5 8 7 Write data 0 Figure 11.2 Writing to the TCNT and TCSR Writing to the RSTCSR: The RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) are different, as shown in figure 11.3. To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE bit is not affected. To write to the RSTE bit, the upper byte must be H'5A and the lower byte must be the write data. The values of bit 6 of the lower byte is transferred to the RSTE bit, respectively. The WOVF bit is not affected. Rev.5.00 Sep. 27, 2007 Page 297 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) Writing 0 to the WOVF bit 15 Address: H'FFFF8612 H'A5 8 7 H'00 0 Writing to the RSTE bit 15 Address: H'FFFF8612 H'5A 8 7 Write data 0 Figure 11.3 Writing to the RSTCSR Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR, H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR. 11.3 11.3.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if the TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally (figure 11.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 φ clock cycles. If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. The internal reset signal is output for 512 φ clock cycles. When a watchdog overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit is cleared to 0. The following are not initialized a WDT reset signal: • PFC (Pin Function Controller) function register • I/O port register Initializing is only possible by external power-on reset. Rev.5.00 Sep. 27, 2007 Page 298 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1 Time WT/IT = 1 H'00 written in TCNT TME = 1 WDTOVF and internal reset generated WDTOVF signal 128 φ clocks Internal reset signal* Legend: WT/IT: Timer mode select bit TME: Timer enable bit 512 φ clocks Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 11.4 Operation in the Watchdog Timer Mode Rev.5.00 Sep. 27, 2007 Page 299 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 11.5). TCNT value H'FF Overflow Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI Time Legend: ITI: Interval timer interrupt request generation Figure 11.5 Operation in the Interval Timer Mode 11.3.3 Clearing the Standby Mode The watchdog timer has a special function to clear the standby mode with an NMI interrupt. When using the standby mode, set the WDT as described below. Before Transition to the Standby Mode: The TME bit in the TCSR must be cleared to 0 to stop the watchdog timer counter before it enters the standby mode. The chip cannot enter the standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 20.3, AC Characteristics, for the oscillation settling time. Recovery from the Standby Mode: When an NMI request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected by bits CKS2 to CKS0 before the standby mode was entered. When the TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. For details on the standby mode, see section 19, Power Down State. Rev.5.00 Sep. 27, 2007 Page 300 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.3.4 Timing of Setting the Overflow Flag (OVF) In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and an interval timer interrupt is simultaneously requested (figure 11.6). CK TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 11.6 Timing of Setting the OVF 11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 11.7). CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 11.7 Timing of Setting the WOVF Bit Rev.5.00 Sep. 27, 2007 Page 301 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.4 11.4.1 Usage Notes TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 11.8). TCNT write cycle T1 CK Address Internal write signal TCNT input clock TCNT N M Counter write data TCNT address T2 T3 Figure 11.8 Contention between TCNT Write and Increment 11.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 11.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev.5.00 Sep. 27, 2007 Page 302 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) 11.4.4 System Reset with WDTOVF If a WDTOVF signal is input to the RES pin, the LSI cannot initialize correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 11.9. SH7014/16/17 Reset input RES Reset signal to entire system WDTOVF Figure 11.9 Example of a System Reset Circuit with a WDTOVF Signal 11.4.5 Internal Reset with the Watchdog Timer If the RSTE bit is cleared to 0 in the watchdog timer mode, the LSI will not reset internally when a TCNT overflow occurs, but the TCNT and TCSR in the WDT will reset. Rev.5.00 Sep. 27, 2007 Page 303 of 716 REJ09B0398-0500 11. Watchdog Timer (WDT) Rev.5.00 Sep. 27, 2007 Page 304 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) 12.1 Overview This LSI has a serial communication interface (SCI) with two independent channels, both of which possess the same functions. The SCI supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 Features The SCI has the following features: • Select asynchronous or clock synchronous as the serial communications mode. ⎯ Asynchronous mode: Serial data communications are synched by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs a standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. • Data length: seven or eight bits • Stop bit length: one or two bits • Parity: even, odd, or none • Multiprocessor bit: one or none • Receive error detection: parity, overrun, and framing errors • Break detection: by reading the RxD level directly when a framing error occurs ⎯ Clocked synchronous mode: Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a clock synchronous communication function. There is one serial data communication format. • Data length: eight bits • Receive error detection: overrun errors • Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. • On-chip baud rate generator with selectable bit rates. • Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external). Rev.5.00 Sep. 27, 2007 Page 305 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) • Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receiveerror interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SSR SCR BRR φ φ/4 φ/16 φ/64 RxD RSR TSR SMR Transmit/ receive control Baud rate generator TxD Parity generation Parity check SCK Clock External clock TEI TXI RXI ERI SCI Legend: RSR : Receive shift register RDR: Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : SCR : SSR : BRR : Serial mode register Serial control register Serial status register Bit rate register Figure 12.1 SCI Block Diagram Rev.5.00 Sep. 27, 2007 Page 306 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.1.3 Pin Configuration Table 12.1 summarizes the SCI pins by channel. Table 12.1 SCI Pins Channel 0 Pin Name Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin Abbreviation Input/Output SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output 12.1.4 Register Configuration Table 12.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or clock synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 12.2 Registers Channel Name 0 Serial mode register Bit rate register Abbreviation R/W SMR0 BRR0 R/W R/W R/W R/W 1 Initial Value Address* H'00 H'FF H'00 H'FF 2 Access Size H'FFFF81A0 8, 16 H'FFFF81A1 8, 16 H'FFFF81A2 8, 16 H'FFFF81A3 8, 16 H'FFFF81A4 8, 16 H'FFFF81A5 8, 16 H'FFFF81B0 8, 16 H'FFFF81B1 8, 16 H'FFFF81B2 8, 16 H'FFFF81B3 8, 16 H'FFFF81B4 8, 16 H'FFFF81B5 8, 16 Serial control register SCR0 Transmit data register TDR0 Serial status register SSR0 R/(W)* H'84 R R/W R/W R/W R/W 1 Receive data register RDR0 1 Serial mode register Bit rate register SMR1 BRR1 H'00 H'00 H'FF H'00 H'FF Serial control register SCR1 Transmit data register TDR1 Serial status register SSR1 R/(W)* H'84 R H'00 Receive data register RDR1 Notes: 1. The only value that can be written is a 0 to clear the flags. 2. Do not access empty addresses. Rev.5.00 Sep. 27, 2007 Page 307 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.2 12.2.1 Register Descriptions Receive Shift Register (RSR) Bit: 7 ⎯ 6 ⎯ 5 ⎯ 4 ⎯ 3 ⎯ 2 ⎯ 1 ⎯ 0 ⎯ R/W: The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the RDR. The CPU cannot read or write the RSR directly. 12.2.2 Receive Data Register (RDR) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into the RDR for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset or in standby mode. 12.2.3 Transmit Shift Register (TSR) Bit: 7 ⎯ 6 ⎯ 5 ⎯ 4 ⎯ 3 ⎯ 2 ⎯ 1 ⎯ 0 ⎯ R/W: The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data Rev.5.00 Sep. 27, 2007 Page 308 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1, however, the SCI does not load the TDR contents into the TSR. The CPU cannot read or write the TSR directly. 12.2.4 Transmit Data Register (TDR) Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the TDR during serial transmission from the TSR. The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset or in standby mode. 12.2.5 Serial Mode Register (SMR) Bit: 7 C/A Initial value: R/W: 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset or in standby mode. Rev.5.00 Sep. 27, 2007 Page 309 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 7⎯Communication Mode (C/A): Selects whether the SCI operates in the asynchronous or clock synchronous mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (initial value) Bit 6⎯Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6 CHR 0 1 Note: * Description Eight-bit data Seven-bit data* When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. (initial value) Bit 5⎯Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. Bit 5 PE 0 1 Note: * Description Parity bit not added or checked Parity bit added and checked* When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. (initial value) Rev.5.00 Sep. 27, 2007 Page 310 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 4⎯Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and check. The O/E setting is ignored in the clock synchronous mode, or in the asynchronous mode when parity addition and check is disabled. Bit 4 O/E 0 1 Description Even parity* Odd parity* 2 1 (initial value) Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Bit 3⎯Stop Bit Length (STOP): Selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock synchronous mode because no stop bits are added. Bit 3 STOP 0 1 Description One stop bit* 1 2 (initial value) Two stop bits* Notes: 1. In transmitting, a single bit of 1 is added at the end of each transmitted character. 2. In transmitting, two bits of 1 are added at the end of each transmitted character. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Rev.5.00 Sep. 27, 2007 Page 311 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 2⎯Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in the asynchronous mode; it is ignored in the clock synchronous mode. For the multiprocessor communication function, see section 12.3.3, Multiprocessor Communication. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (initial value) Bits 1 and 0⎯Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available; φ, φ/4, φ/16, or φ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 12.2.8, Bit Rate Register. Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description φ φ/4 φ/16 φ/64 (initial value) 12.2.6 Serial Control Register (SCR) Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized to H'00 by a power-on reset or in standby mode. Rev.5.00 Sep. 27, 2007 Page 312 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 7⎯Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR. Bit 7 TIE 0 1 Note: * Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. (initial value) Bit 6⎯Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables receiveerror interrupt (ERI) requests. Bit 6 RIE 0 1 Note: * Description Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled* (initial value) Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. Bit 5⎯Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5 TE 0 1 Description Transmitter disabled* Transmitter enabled* 1 (initial value) 2 Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. 2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format in the SMR before setting TE to 1. Rev.5.00 Sep. 27, 2007 Page 313 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 4⎯Receive Enable (RE): Enables or disables the SCI serial receiver. Bit 4 RE 0 1 Description Receiver disabled* Receiver enabled* 1 (initial value) 2 Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. Select the receive format in the SMR before setting RE to 1. Bit 3⎯Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in the clock synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (initial value) MPIE is cleared when the MPIE bit is cleared to 0, or the multiprocessor bit (MPB) is set to 1 in receive data. Multiprocessor interrupts are enabled* Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. Note: * The SCI does not transfer receive data from the RSR to the RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCR are set to 1), and allows the FER and ORER bits to be set. 1 Rev.5.00 Sep. 27, 2007 Page 314 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 2⎯Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2 TEIE 0 1 Note: * Description Transmit-end interrupt (TEI) requests are disabled* Transmit-end interrupt (TEI) requests are enabled.* The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. (initial value) Bits 1 and 0⎯Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC). The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock source, see table 12.9 in section 12.3, Operation. Bit 1 Bit 0 1 CKE1 CKE0 Description* 0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal is 2 ignored) or output pin (output level is undefined) * Clock synchronous mode Internal clock, SCK pin used for synchronous clock 2 output* 0 1 Asynchronous mode Internal clock, SCK pin used for clock output* 3 Clock synchronous mode Internal clock, SCK pin used for synchronous clock output 1 0 Asynchronous mode External clock, SCK pin used for clock input* 4 Clock synchronous mode External clock, SCK pin used for synchronous clock input 1 1 Asynchronous mode External clock, SCK pin used for clock input* 4 Clock synchronous mode External clock, SCK pin used for synchronous clock input Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. 2. Initial value. 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate. Rev.5.00 Sep. 27, 2007 Page 315 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.2.7 Serial Status Register (SSR) The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is initialized to H'84 by a power-on reset or in standby mode. Bit: 7 TDRE Initial value: R/W: Note: * 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W The only value that can be written is a 0 to clear the flag. Bit 7⎯Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from the TDR into the TSR and new serial transmit data can be written in the TDR. Bit 7 TDRE 0 Description TDR contains valid transmit data [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When DMAC writes data in TDR (initial value) TDR does not contain valid transmit data [Setting conditions] • • • Power-on reset or standby mode When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR Rev.5.00 Sep. 27, 2007 Page 316 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 6⎯Receive Data Register Full (RDRF): Indicates that RDR contains received data. Bit 6 RDRF 0 Description RDR does not contain valid received data [Clearing conditions] • • • 1 Power-on reset or standby mode When 0 is written to RDRF after reading RDRF = 1 When DMAC reads data from RDR (initial value) RDR contains valid received data [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost. Bit 5⎯Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] • • 1 Power-on reset or standby mode When 0 is written to ORER after reading ORER = 1 1 (initial value) A receive overrun error occurred [Setting condition] When the next serial reception is completed while RDRF = 1* 2 Notes: 1. The ORER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the clock synchronous mode, serial transmitting is disabled. Rev.5.00 Sep. 27, 2007 Page 317 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 4⎯Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in the asynchronous mode. Bit 4 FER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] • • 1 Power-on reset or standby mode When 0 is written to FER after reading FER = 1 2 1 (initial value) A receive framing error occurred* [Setting condition] When at the end of an SCI receive operation the final stop bit of the receive data 2 is checked and its value* is 0 Notes: 1. The FER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2. When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. In addition, serial transmission cannot continue in clock synchronous mode. Bit 3⎯Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error in the asynchronous mode. Bit 3 PER 0 Description Receiving is in progress or has ended normally* [Clearing conditions] • • 1 Power-on reset or standby mode When 0 is written to PER after reading PER = 1 2 1 (initial value) A receive parity error occurred* [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) Notes: 1. The PER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2. When a parity error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. In addition, serial transmission cannot continue in clock synchronous mode. Rev.5.00 Sep. 27, 2007 Page 318 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Bit 2⎯Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written. Bit 2 TEND 0 Description Transmission is in progress [Clearing conditions] • • 1 When 0 is written to TDRE after reading TDRE = 1 When DMAC writes data in TDR (initial value) End of transmission [Setting conditions] • • • Power-on reset or standby mode When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Bit 1⎯Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a read-only bit and cannot be written. Bit 1 MPB 0 1 Note: * Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. (initial value) Bit 0⎯Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0 MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (initial value) Rev.5.00 Sep. 27, 2007 Page 319 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.2.8 Bit Rate Register (BRR) The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset or in standby mode. Each channel has independent baud rate generator control, so different values can be set in the two channels. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Table 12.3 lists examples of BRR settings in the asynchronous mode; table 12.4 lists examples of BBR settings in the clock synchronous mode. Table 12.3 Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 4 n 2 1 1 0 0 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 8 6 3 3 2 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 −3.55 −6.99 8.51 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 10 7 4 4 3 4.9152 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 −3.03 0.00 6.67 −1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 12 9 6 5 4 6 Error (%) −0.44 0.16 0.16 0.16 0.16 0.16 0.16 −2.34 0.16 −2.34 −6.99 0.00 −2.34 Rev.5.00 Sep. 27, 2007 Page 320 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 7.3728 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 15 11 7 6 5 Error (%) −0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 16 12 8 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 2.12 0.16 −3.55 0.00 −6.99 φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 10 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 21 15 10 9 7 Error (%) −0.25 0.16 0.16 0.16 0.16 0.16 0.16 −1.36 −1.36 1.73 −1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 195 143 71 143 71 143 71 35 23 17 11 10 8 11.0592 Error (%) 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 25 19 12 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 −2.34 0.16 0.00 −2.34 n 2 2 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 20 15 10 9 7 9.8304 Error (%) −0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.59 0.00 −3.03 −1.70 0.00 Rev.5.00 Sep. 27, 2007 Page 321 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 12.288 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 26 19 12 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 −1.23 0.00 2.56 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 29 22 14 13 10 14 Error (%) −0.17 0.16 0.16 0.16 0.16 0.16 0.16 −0.93 1.27 −0.93 1.27 0.00 3.57 φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 34 25 16 15 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 −0.79 0.16 2.12 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 36 27 18 16 13 17.2032 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.90 0.00 −1.75 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 38 28 19 17 14 18 Error (%) −0.12 0.16 0.16 0.16 0.16 0.16 0.16 −0.69 0.16 1.02 −2.34 0.00 −2.34 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 31 23 15 14 11 14.7456 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 −1.70 0.00 Rev.5.00 Sep. 27, 2007 Page 322 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 18.432 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 81 239 119 239 119 239 119 59 39 29 19 17 14 Error (%) −0.22 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 255 127 63 42 31 20 19 15 19.6608 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 −0.78 0.00 1.59 −1.70 0.00 φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 22 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 97 71 142 71 142 71 142 71 47 35 23 21 17 Error (%) −0.35 −0.54 0.16 −0.54 0.16 −0.54 0.16 −0.54 −0.54 −0.54 −0.54 0.00 −0.54 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 97 71 143 71 143 71 143 71 47 35 23 21 17 22.1184 Error (%) 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.54 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 155 77 51 38 25 23 19 24 Error (%) −0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 −2.34 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 42 32 21 19 15 20 Error (%) −0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.94 −1.36 −1.36 0.00 1.73 Rev.5.00 Sep. 27, 2007 Page 323 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 24.576 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 159 79 52 39 26 24 19 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.63 0.00 −1.23 −1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 φ (MHz) Bit Rate (Bits/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 27.0336 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 119 87 175 87 175 87 175 87 58 43 28 26 21 Error (%) 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 −0.56 0.00 1.15 0.12 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 123 90 181 90 181 90 181 90 60 45 29 27 22 28 Error (%) 0.23 0.16 0.16 0.16 0.16 0.16 0.16 0.16 −0.39 −0.93 1.27 0.00 −0.93 N 114 83 167 83 167 83 167 83 55 41 27 25 20 25.8048 Error (%) −0.40 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 −0.75 0.00 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 114 84 168 84 168 84 168 84 55 41 27 25 20 26 Error (%) 0.36 −0.43 0.16 −0.43 0.16 −0.43 0.16 −0.43 0.76 0.76 0.76 0.00 0.76 Rev.5.00 Sep. 27, 2007 Page 324 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Table 12.4 Bit Rates and BRR Settings in Clocked Synchronous Mode φ (MHz) Bit Rate (Bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 4 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 141 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 3 3 2 1 1 0 0 0 0 0 0 ⎯ 0 155 77 155 249 124 249 99 49 24 9 4 ⎯ 0* 3 3 2 2 1 1 0 0 0 0 0 0 0 187 93 187 74 149 74 119 59 29 11 5 2 0* n 8 N n 10 N n 12 N Rev.5.00 Sep. 27, 2007 Page 325 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) φ (MHz) Bit Rate (Bits/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 7M 3 3 2 2 1 1 0 0 0 0 0 0 ⎯ 249 124 249 99 199 99 159 79 39 15 7 3 ⎯ 3 3 2 1 1 0 0 0 0 0 0 0 0 155 77 124 249 124 199 99 49 19 9 4 1 0* 3 3 2 2 1 0 0 0 0 0 0 ⎯ ⎯ ⎯ 187 93 149 74 149 239 119 59 23 11 5 ⎯ ⎯ ⎯ 3 3 2 2 1 1 0 0 0 0 0 0 0 0 218 108 174 87 174 69 139 69 27 13 6 2 1 0* 16 n N n 20 N n 24 N n 28 N Legend: Blank: No setting available ⎯: Setting possible, but error occurs Notes: Settings with an error of 1% or less are recommended. * Continuous transmission/reception is not possible. Rev.5.00 Sep. 27, 2007 Page 326 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) The BRR setting is calculated as follows: Asynchronous mode: N= 64 × 22n−1 φ ×B × 106 − 1 Synchronous mode: N= φ × 106 − 1 64 × 22n−1 × B Legend: B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) φ: Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings n 0 1 2 3 Clock Source φ φ/4 φ/16 φ/64 CKS1 0 0 1 1 CKS2 0 1 0 1 The bit rate error in asynchronous mode is calculated as follows: ⎧ ⎧ φ × 106 Error (%) = ⎨ − 1⎨ × 100 (N + 1) × B × 64 × 22n−1 ⎩ ⎩ Table 12.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used for various frequencies. Tables 12.6 and 12.7 show the maximum rates for external clock input. Rev.5.00 Sep. 27, 2007 Page 327 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Table 12.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings φ (MHz) 4 4.9152 6 7.3728 8 9.8304 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 22 22.1184 24 24.576 25.8048 26 27.0336 28 Maximum Bit Rate (Bits/s) 125000 153600 187500 230400 250000 307200 312500 345600 375000 384000 437500 460800 500000 537600 562500 576000 614400 625000 687500 691200 750000 768000 806400 812500 844800 875000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.5.00 Sep. 27, 2007 Page 328 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Table 12.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) φ (MHz) 4 4.9152 6 7.3728 8 9.8304 10 11.0592 12 12.288 14 14.7456 16 17.2032 18 18.432 19.6608 20 22 22.1184 24 24.576 25.8048 26 27.0336 28 External Input Clock (MHz) 1.0000 1.2288 1.5000 1.8432 2.0000 2.4576 2.5000 2.7648 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.6080 4.9152 5.0000 5.5000 5.5296 6.0000 6.1440 6.4512 6.5000 6.7584 7.0000 Maximum Bit Rate (Bits/s) 62500 76800 93750 115200 125000 153600 156250 172800 187500 192000 218750 230400 250000 268800 281250 288000 307200 312500 343750 345600 375000 384000 403200 406250 422400 437500 Rev.5.00 Sep. 27, 2007 Page 329 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Table 12.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) φ (MHz) 4 6 8 10 12 14 16 18 20 22 24 26 28 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 3.6667 4.0000 4.3333 4.6667 Maximum Bit Rate (Bits/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 3666666.7 4000000.0 4333333.3 4666666.7 Rev.5.00 Sep. 27, 2007 Page 330 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.3 12.3.1 Operation Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in the serial mode register (SMR), as shown in table 12.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 12.9. Asynchronous Mode: • Data length is selectable: seven or eight bits. • Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. • In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. • An internal or external clock can be selected as the SCI clock source. ⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. ⎯ When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Clock Synchronous Mode: • The communication format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors (ORER). • An internal or external clock can be selected as the SCI clock source. ⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and outputs a synchronous clock signal to external devices. ⎯ When an external clock is selected, the SCI operates on the input synchronous clock. The on-chip baud rate generator is not used. Rev.5.00 Sep. 27, 2007 Page 331 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Table 12.8 SMR Settings and SCI Communication Formats SMR Settings Mode Asynchronous Bit 7 C/A 0 Bit 6 CHR 0 Bit 5 PE 0 Bit 2 MP 0 SCI Communication Format Bit 3 Data STOP Length 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 0 * * 1 * * Clock synchronous 1 * * * 1 0 1 0 1 * 8-bit Not set 7-bit 8-bit Not set Set Set 7-bit Not set Set 8-bit Parity Bit Not set Multipro- Stop Bit cessor Bit Length Not set 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Note: Asterisks (*) in the table indicate don't-care bits. Table 12.9 SMR and SCR Settings and SCI Clock Source Selection SMR Mode Bit 7 C/A SCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Clock synchronous 1 0 0 1 1 Note: * 0 1 Select the function in combination with the pin function controller (PFC). External Inputs the synchronous clock Internal External SCI Transmit/Receive Clock Clock Source SCK Pin Function* Internal SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the synchronous clock Asynchronous 0 Rev.5.00 Sep. 27, 2007 Page 332 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.3.2 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idling (marking state) 1 (MSB) D1 D2 D3 D4 D5 D6 D7 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits 1 1 Stop bit 1 Serial data 0 Start bit (LSB) D0 One unit of communication data (characters or frames) Figure 12.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits) Rev.5.00 Sep. 27, 2007 Page 333 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Transmit/Receive Formats: Table 12.10 shows the 12 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 12.10 Serial Communication Formats (Asynchronous Mode) SMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ⎯ ⎯ ⎯ ⎯ MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 START START START START START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12 8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data Legend: START: STOP: P: MPB: ⎯: Start bit Stop bit Parity bit Multiprocessor bit Don't care Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 12.9). Rev.5.00 Sep. 27, 2007 Page 334 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 12.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.3 Output Clock and Communication Data Phase Relationship (Asynchronous Mode) Data Transmit/Receive Operations SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 12.4 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to SCR. 2. Select the communication format in the serial mode register (SMR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. The initial states are the marking transmit state, and the idle receive state (waiting for a start bit). Rev.5.00 Sep. 27, 2007 Page 335 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) 1 Select transmit/receive format in SMR 2 Set value to BRR Wait 3 1-bit interval elapsed? Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary No 4 End Figure 12.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC or the DTC is started by a transmit-data-empty interrupt request (TXI) in order to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0, then clear the TE to 0 in SCR and use the PFC to establish the TxD pin as an output port. Rev.5.00 Sep. 27, 2007 Page 336 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialize Start transmitting 1 Read TDRE bit in SSR 2 No TDRE = 1? Yes Write transmission data to TDR and clear TDRE bit in SSR to 0 3 All data transmitted? Yes Read TEND bit in SSR No TEND = 1? Yes Output break signal? 4 Yes Set DR = 0 Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC No No End transmission Figure 12.5 Sample Flowchart for Transmitting Serial Data Rev.5.00 Sep. 27, 2007 Page 337 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1 bits (stop bits) are output. e. Marking: output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 12.6 shows an example of SCI transmit operation in the asynchronous mode. Rev.5.00 Sep. 27, 2007 Page 338 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 Parity Stop bit bit D7 0/1 1 1 Serial data Data Data D1 1 Idle (marking state) TDRE TEND TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 1 frame TXI request TEI interrupt request Example: 8-bit data with parity and one stop bit Figure 12.6 SCI Transmit Operation in Asynchronous Mode Receiving Serial Data (Asynchronous Mode): Figures 12.7 (1) and (2) show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of the SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read the RDR and RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RxI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Rev.5.00 Sep. 27, 2007 Page 339 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialization 1 Start reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? No Read the RDRF bit in SSR Yes 2 Error handling 3 No RDRF = 1? Yes Read reception data of RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear the RE bit of SCR to 0 End reception Figure 12.7 Sample Flowchart for Receiving Serial Data (1) Rev.5.00 Sep. 27, 2007 Page 340 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Start of error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes No PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR End Figure 12.7 Sample Flowchart for Receiving Serial Data (2) Rev.5.00 Sep. 27, 2007 Page 341 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SMR. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR into the RDR. If the data passes these checks, the SCI sets RDRF to 1 and stores the received data in the RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 12.11. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RxI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 12.8 shows an example of SCI receive operation in the asynchronous mode. Table 12.11 Receive Error Conditions and SCI Operation Receive Error Overrun error Framing error Parity error Abbreviation ORER FER PER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR Rev.5.00 Sep. 27, 2007 Page 342 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 Parity Stop bit bit D7 0/1 1 1 Serial data Data Data D1 1 Idle (marking state) TDRF RXI interrupt request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. Example: 8-bit data with parity and one stop bit. Figure 12.8 SCI Receive Operation 12.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 12.9 shows the example of communication among processors using the multiprocessor format. Rev.5.00 Sep. 27, 2007 Page 343 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 12.8. Clock: See the description in the asynchronous mode section. Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-transmit cycle: receiving processor address H'AA (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID MPB: Multiprocessor bit Example: Sending data H'AA to receiving processor A Figure 12.9 Communication Among Processors Using Multiprocessor Format Transmitting Multiprocessor Serial Data: Figure 12.10 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD pin using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. Rev.5.00 Sep. 27, 2007 Page 344 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialization Start transmission Read TDRE bit in SSR 1 2 No TDRE = 1? Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? Yes Read TEND bit in SSR No 3 TEND = 1? Yes Output break signal? Yes Set DR = 0 Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC No No 4 End transmission Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev.5.00 Sep. 27, 2007 Page 345 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0 bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1 bits (stop bits) are output. e. Marking: output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 12.11 shows an example of SCI receive operation in the multiprocessor format. Rev.5.00 Sep. 27, 2007 Page 346 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Multiprocessor bit Stop Start Data bit bit D0 D1 D7 0/1 1 0 D0 Multiprocessor bit Stop Data bit D1 D7 0/1 1 1 Serial data Start bit 0 1 Idle (marking state) TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame TXI interrupt request TEI interrupt request Example: 8-bit data with multiprocessor bit and one stop bit Figure 12.11 SCI Multiprocessor Transmit Operation Receiving Multiprocessor Serial Data: Figures 12.12 (1) and (2) show a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below. 1. SCI initialization: Set the RxD pin using the PFC. 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error processing, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). Rev.5.00 Sep. 27, 2007 Page 347 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER bits of SSR FER = 1? or ORER =1? No Read RDRF bit in SSR No 1 2 Yes 3 RDRF = 1? Yes Read receive data from RDR No Is ID the station's ID Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? No Read RDRF bit of SSR RDRF = 1? Yes Read receive data from RDR 4 5 No Yes No All data received? Yes Clear RE bit in SCR to 0 End reception Error processing Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev.5.00 Sep. 27, 2007 Page 348 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Start error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit in SCR to 0 Yes Clear ORER and FER bits in SSR to 0 End Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.5.00 Sep. 27, 2007 Page 349 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Figures 12.13 (1) and (2) show examples of SCI receive operation using a multiprocessor format. Start bit 0 Data (ID1) D0 D1 D7 Stop Start Data MPB bit bit (data 1) 1 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idling (marking) MPB MPIE RDRF RDR value RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 ID1 Not station's ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state Figure 12.13 SCI Receive Operation (ID Does Not Match) (1) Rev.5.00 Sep. 27, 2007 Page 350 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Start bit 0 Data (ID2) D0 D1 D7 Stop Start Data MPB bit bit (data 2) 1 1 0 D0 D1 D7 Stop MPB bit 0 1 1 Serial data 1 Idling (marking) MPB MPIE RDRF RDR value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 Station's ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine Example: Own ID matches data, 8-bit data with multiprocessor bit and one stop bit Figure 12.13 Example of SCI Receive Operation (ID Matches) (2) 12.3.4 Clock Synchronous Operation In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 12.14 shows the general format in clock synchronous serial communication. Rev.5.00 Sep. 27, 2007 Page 351 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Transfer direction One unit (character or frame) of communication data Synchronization clock * * LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Note: * High except in continuous transmitting or receiving. Figure 12.14 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In the clock synchronous mode, the SCI transmits or receives data by synchronizing with the falling edge of the synchronization clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 12.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. Note: An overrun error occurs only during the receive operation, and the sync clock is output until the RE bit is cleared to 0. When you want to perform a receive operation in onecharacter units, select external clock for the clock source. Rev.5.00 Sep. 27, 2007 Page 352 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Transmit/Receive Operations SCI Initialization (Clock Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 12.15 is a sample flowchart for initializing the SCI. 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1. Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings. Rev.5.00 Sep. 27, 2007 Page 353 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Start of initialization Clear TE and RE bits to 0 in SCR Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCR (TE and RE are 0) 1 Select transmit/receive format in SMR 2 Set value in BRR Wait 1-bit interval elapsed? Yes Set TE and RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE bits No 3 4 End Figure 12.15 Sample Flowchart for SCI Initialization Transmitting Serial Data (Synchronous Mode): Figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC or DTC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. Rev.5.00 Sep. 27, 2007 Page 354 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialize 1 Start transmitting Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR No All data transmitted? 3 Yes Read TEND flag in SSR TEND = 1? Yes Clear TE bit to 0 in SCR No End Figure 12.16 Sample Flowchart for Serial Transmitting Rev.5.00 Sep. 27, 2007 Page 355 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Figure 12.17 shows an example of SCI transmit operation. Transmit direction Synchronization clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame TXI request TEI request Figure 12.17 Example of SCI Transmit Operation SCI serial transmission operates as follows. 1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data and loads this data from the TDR into the transmit shift register (TSR). 2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data are output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from the TDR into the TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Rev.5.00 Sep. 27, 2007 Page 356 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Receiving Serial Data (Clock Synchronous Mode): Figures 12.18 (1) and (2) show a sample flowchart for receiving serial data. When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is listed below: 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Rev.5.00 Sep. 27, 2007 Page 357 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialization 1 Start reception Read the ORER bit of SSR Yes ORER = 1? No Read RDRF bit of SSR No 3 2 Error processing RDRF = 1? Yes Read receive data from RDR and clear RDRF bit of SSR to 0 4 No All data received? Yes Clear RE bit of SCR to 0 End reception Figure 12.18 Sample Flowchart for Serial Receiving (1) Rev.5.00 Sep. 27, 2007 Page 358 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Error handling Overrun error processing Clear ORER bit of SSR to 0 End Figure 12.18 Sample Flowchart for Serial Receiving (2) Figure 12.19 shows an example of the SCI receive operation. Transfer direction Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI request Read data with RXI interrupt processing routine and clear RDRF bit to 0 1 frame RXI request ERI interrupt request generated by overrun error Figure 12.19 Example of SCI Receive Operation Rev.5.00 Sep. 27, 2007 Page 359 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into the RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the RSR into the RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If the check does not pass (receive error), the SCI operates as indicated in table 12.11 and no further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure is as follows (the steps correspond to the numbers in the flowchart): 1. SCI initialization: Set the TxD and RxD pins using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, simultaneously clear the TE bit and RE bit to 0, then simultaneously set the TE bit and RE bit to 1. Rev.5.00 Sep. 27, 2007 Page 360 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) Initialization Start transmitting/receive 1 Read TDRE bit in SSR No 2 TDRE = 1? Yes Write transmission data in TDR and clear TDRE bit of SSR to 0 Read ORER bit of SSR Yes 3 Error handling 4 ORER = 1? No Read RDRF bit of SSR No RDRF = 1? Yes Read receive data of RDR, and clear RDRF bit of SSR to 0 All data transmitted/and received Yes Clear TE and RE bits of SCR to 0 End transmission/reception 5 No Figure 12.20 Sample Flowchart for Serial Transmission Rev.5.00 Sep. 27, 2007 Page 361 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 12.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in the SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes data in the transmit data register (TDR). RxI is requested when the RDRF bit in the SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR). ERI is requested when the ORER, PER, or FER bit in the SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in the SSR is set to 1. TEI cannot start the DMAC. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 12.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) DMAC Activation No Yes Yes No Low Priority High Rev.5.00 Sep. 27, 2007 Page 362 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.5 Usage Notes Sections 12.5.1 through 12.5.9 provide information for using the SCI. 12.5.1 TDR Write and TDRE Flags The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1. 12.5.2 Simultaneous Multiple Receive Errors Table 12.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the RDR, so receive data is lost. Table 12.13 SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error RDRF 1 0 0 1 1 0 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Transfer RSR → RDR X O O X X O X Overrun error + framing error + parity error 1 Note: O = Receive data is transferred from RSR to RDR. X = Receive data is not transferred from RSR to RDR. Rev.5.00 Sep. 27, 2007 Page 363 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.5.3 Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. 12.5.4 Sending a Break Signal The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the present transmission status. 12.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only) When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. 12.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode In the asynchronous mode, the SCI operates on a base clock of 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 12.21). Rev.5.00 Sep. 27, 2007 Page 364 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 16 clocks 8 clocks Internal 0 base clock Receive data (RxD) Synchronization sampling timing Data sampling timing 78 15 0 −7.5 clocks Start bit +7.5 clocks D0 D1 78 15 0 5 Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in the asynchronous mode can therefore be expressed as: M = 0.5 − 1 D − 0.5 (1 + F) × 100 % − (L − 0.5)F − 2N N Legend: M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0 − 1.0) L : Frame length (L = 9 − 12) F : Absolute deviation of clock frequency From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 − 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%. Rev.5.00 Sep. 27, 2007 Page 365 of 716 REJ09B0398-0500 12. Serial Communication Interface (SCI) 12.5.7 Constraints on DMAC Use • When using an external clock source for the synchronization clock, update the TDR with the DMAC, and then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input in the first four system clocks after the TDR is written, an error may occur (figure 12.22). • Before reading the receive data register (RDR) with the DMAC, select the receive-data-full interrupt (RXI) of the SCI as a start-up source. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4φ or less. Figure 12.22 Example of Clock Synchronous Transmission with DMAC 12.5.8 Cautions for Clock Synchronous External Clock Mode • Set TE = RE = 1 only when the external clock SCK is 1. • Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed from 0 to 1. • When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the RxD D7 bit SCK input, but it cannot be copied to RDR. 12.5.9 Caution for Clock Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is set to zero 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but it cannot be copied to RDR. Rev.5.00 Sep. 27, 2007 Page 366 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Section 13 High Speed A/D Converter ⎯ SH7014 ⎯ 13.1 Overview The high speed A/D converter has 10-bit resolution, and can select from a maximum of eight channels of analog inputs. 13.1.1 Features The high speed A/D converter has the following features: • 10-bit resolution • Eight input channels • High-speed conversion ⎯ Minimum conversion time: 2.9 μs per channel (for 28-MHz operation) 1.4 μs per channel during continuous conversion • Multiple conversion modes ⎯ Select mode/group mode ⎯ Single mode/scan mode ⎯ Buffered operation possible ⎯ 2 channel simultaneous sampling possible • Two types of conversion start ⎯ Software, or timer conversion start trigger (MTU) can be selected. • Eight data registers ⎯ Conversion results stored in 16-bit data registers corresponding to each channel. • Sample and hold function • A/D conversion end interrupt generation ⎯ An A/D conversion end interrupt (ADI) request can be generated on completion of A/D conversions Rev.5.00 Sep. 27, 2007 Page 367 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.1.2 Block Diagram Figure 13.1 is the block diagram of the high speed A/D converter. D/A conversion circuit AVCC AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AVss Internal data bus Bus I/F ADDRB Control logic Multiplexer S&H B + − CMP ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCR ADCSR MTU conversion start trigger Interrupt signal ADI A/D control register A/D control status register A/D data register A A/D data register B A/D data register C A/D data register D CMP: S&H: ADDRE: ADDRF: ADDRG: ADDRH: Comparator array Sample and hold circuit A/D data register E A/D data register F A/D data register G A/D data register H Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: Figure 13.1 High Speed A/D Converter Block Diagram 13.1.3 Pin Configuration Table 13.1 shows the input pins used by the high speed A/D converter. The AVCC and AVSS pins are for the high speed A/D converter internal analog section power supply. Rev.5.00 Sep. 27, 2007 Page 368 of 716 REJ09B0398-0500 Module internal data bus S&H A ADDRA 13. High Speed A/D Converter ⎯ SH7014 ⎯ Table 13.1 Pin Configuration Pin Analog supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O I I I I I I I I I I Function Analog section power supply Analog section ground and A/D conversion reference voltage Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 13.1.4 Register Configuration Table 13.2 shows the configuration of the high speed A/D converter registers. Table 13.2 Register Configuration Name A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H Abbreviation R/W ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH R R R R R R R R Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFF83F0 H'FFFF83F2 H'FFFF83F4 H'FFFF83F6 H'FFFF83F8 H'FFFF83FA H'FFFF83FC H'FFFF83FE H'FFFF83E0 H'FFFF83E1 Access Size 8,16 A/D control/status register ADCSR A/D control register Note: * ADCR R/(W)* H'00 R/W H'00 Only 0 can be written to bit 7 to clear the flag. Rev.5.00 Sep. 27, 2007 Page 369 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.2 13.2.1 Register Descriptions A/D Data Registers A to H (ADDRA to ADDRH) Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 AD7 Initial value: R/W: 0 R 14 ⎯ 0 R 6 AD6 0 R 13 ⎯ 0 R 5 AD5 0 R 12 ⎯ 0 R 4 AD4 0 R 11 ⎯ 0 R 3 AD3 0 R 10 ⎯ 0 R 2 AD2 0 R 9 AD9 0 R 1 AD1 0 R 8 AD8 0 R 0 AD0 0 R The ADDR are 16-bit read only registers for storing A/D conversion results. There are eight of these registers, ADDRA through ADDRH. The A/D converted data is 10-bit data which is sent to the ADDR for the corresponding converted channel for storage. The lower 8 bits of the A/D converted data are transferred to and stored in the lower byte (bits 7 to 0) of the ADDR, and the upper 2 bits are stored into the upper byte (bits 9, 8). Bits 15 to 10 always read as 0. Data reads can be either byte or word. The upper 8 bits of the converted data are transferred upon byte data reads. Additionally, buffered operation is possible by combining ADDRA to ADDRD. Table 13.3 shows the correspondence between the analog input channels and the ADDR. The ADDR are initialized to H'0000 by power-on reset or in standby mode. Rev.5.00 Sep. 27, 2007 Page 370 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Table 13.3 Analog Input Channel and ADDR Correspondence Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Note: * Except during buffer operation A/D Data Register ADDRA* ADDRB* ADDRC* ADDRD* ADDRE ADDRF ADDRG ADDRH 13.2.2 A/D Control/Status Register (ADCSR) Bit: Initial value: R/W: 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 CKS 0 R/W 3 GRP 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Only 0 can be written to bit 7 to clear the flag. The ADCSR is an 8-bit read/write register used for A/D conversion operation control and to indicate status. The ADCSR is initialized to H'00 by power-on reset or in standby mode. Rev.5.00 Sep. 27, 2007 Page 371 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Bit 7⎯A/D End Flag (ADF): This status flag indicates that A/D conversion has ended. Bit 7 ADF 0 Description [Clear conditions] • • 1 • When the DMAC is activated by an ADI interrupt Single mode: When A/D conversion ends after conversion for all designated channels (during buffer operation, this is not set until operation of the specified buffer has ended) Scan mode: After one round of A/D conversion for all specified channels (initial value) With ADF = 1, by reading the ADF flag then writing 0 in ADF [Set conditions] • Bit 6⎯A/D Interrupt Enable (ADIE): Enables or disables interrupt requests (ADI) after A/D conversion ends. Set the ADIE bit while conversion is suspended. Bit 6 ADIE 0 1 Description Disables interrupt requests (ADI) after A/D conversion ends (initial value) Enables interrupt requests (ADI) after A/D conversion ends Bit 5⎯A/D Start (ADST): Selects start or stop for A/D conversion. A 1 is maintained during A/D conversions. The ADST bit can be set to 1 by software, or timer conversion start triggers. Bit 5 ADST 0 1 Description A/D conversion halted • • (initial value) Single mode: Start A/D conversion. Automatically cleared to 0 after conversion for the designated channel ends. Scan mode: Start A/D conversion. Continuous conversion until 0 cleared by software. Rev.5.00 Sep. 27, 2007 Page 372 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Bit 4⎯Clock Select (CKS): Sets the A/D conversion time. Set so that the conversion time is 2 μs or greater in proportion to the operating frequency. Make conversion time changes only while conversion is halted. Bit 4 CKS 0 1 Description Conversion time = 40 states (high speed A/D converter standard clock = φ/2) Conversion time = 80 states (when φ/4 is selected) (initial value) Bit 3⎯Group Mode (GRP): Designates either select mode or group mode for the A/D conversion channel selection. Set the GRP bit only while conversion is halted. Bit 3 GRP 0 1 Description Select mode Group mode (initial value) Bits 2 to 0⎯Channel Select 2 to 0 (CH2 to CH0): These bits, along with the GRP bit, select the analog input channel. Set the input channel only while conversion is halted. Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 Description Select Mode (GRP = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Group Mode (GRP = 1) (initial value) AN0 AN0 to AN1 AN0 to AN2 AN0 to AN3 AN0 to AN4 AN0 to AN5 AN0 to AN6 AN0 to AN7 Rev.5.00 Sep. 27, 2007 Page 373 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.2.3 A/D Control Register (ADCR) Bit: 7 ⎯ Initial value: R/W: 0 R 6 PWR 0 R/W 5 TRGS1 0 R/W 4 TRGS0 0 R/W 3 SCAN 0 R/W 2 DSMP 0 R/W 1 BUFE1 0 R/W 0 BUFE0 0 R/W The ADCR is an 8-bit read/write register used for A/D conversion operation control. The ADCR is initialized to H'00 by power-on reset or in standby mode. Bit 7⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 6⎯Power (PWR): Designates the conversion start mode for the high speed A/D converter. Setting the PWR bit to 1 sets high speed start mode, and a 0 sets to low power conversion mode. See section 13.4.7, Conversion Start Modes for details on the conversion start operation. Set the PWR bit only while conversion is halted. Bit 6 PWR 0 1 Description Low power conversion mode High speed start mode (initial value) Bits 5 and 4⎯Timer Trigger Select 1, 0 (TRGS1, TRGS0): These bits enable or prohibit A/D conversion starts by trigger signals. Set the TRGS1, TRGS0 bits only while conversion is halted. Bit 5 TRGS1 0 Bit 4 TRGS0 0 1 1 0 1 Description Enable A/D conversion start by software (initial value) Enables A/D conversion start by MTU conversion start trigger Reserved Reserved Rev.5.00 Sep. 27, 2007 Page 374 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Bit 3⎯Scan Mode (SCAN): Selects either single mode or scan mode for the A/D conversion operation mode. See section 13.4, Operation, for details on single mode and scan mode operation. Set the SCAN bit only while conversion is halted. Bit 3 SCAN 0 1 Description Single mode Scan mode (initial value) Bit 2⎯Simultaneous Sampling (DSMP): Enables or disables the simultaneous sampling of two channels. See section 13.4.6, Simultaneous Sampling Operation, for details on simultaneous sampling. Set the DSMP bit only while conversion is halted. Bit 2 DSMP 0 1 Description Normal sampling operation Simultaneous sampling operation (initial value) Bits 1 and 0⎯Buffer Enable 1, 0 (BUFE1, BUFE0): These bits select whether to use the ADDRB to ADDRD as buffer registers. Set the BUFE1 and BUFE0 bits only while conversion is halted. Bit 1 BUFE1 0 Bit 0 BUFE0 0 1 1 0 Description Normal operation (initial value) ADDRA and ADDRB buffer operation: conversion result → ADDRA → ADDRB (ADDRB is the buffer register) ADDRA and ADDRC, also ADDRB and ADDRD buffer operation: conversion result 1 → ADDRA → ADDRC, conversion result 2 → ADDRB → ADDRD (ADDRC and ADDRD are buffer registers) ADDRA to ADDRD buffer operation: conversion result → ADDRA → ADDRB → ADDRC → ADDRD (ADDRB to ADDRD are buffer registers) 1 Rev.5.00 Sep. 27, 2007 Page 375 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.3 Bus Master Interface The ADDRA to ADDRH are 16-bit registers with a 16-bit width data bus to the bus master. The bus master can read from ADDRA to ADDRH in either word or byte units. When an ADDR is read in word units, the ADDR contents are transferred to the bus master 16 bits at a time. In byte unit reads, the contents of the most significant eight bits (AD9 to AD2) of the converted data (AD9 to AD0) are transferred to the bus master. Figures 13.2 (1) and (2) show an example of the ADDR read operation. Word data read Data register 0 0 0 0 0 0 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Lower 8 bits Internal data bus Upper 8 bits Bus I/F Figure 13.2 ADDR Read Operation (1) Rev.5.00 Sep. 27, 2007 Page 376 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Byte data read Data register 0 0 0 0 Upper 8 bits 0 0 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Internal data bus Bus I/F Figure 13.2 ADDR Read Operation (2) Rev.5.00 Sep. 27, 2007 Page 377 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.4 Operation • The high speed A/D converter has 10-bit resolution. • In addition to the four operating modes of select or group, and single or scan can be set in combination with buffer operation. • Select mode uses one channel and group mode selects multiple channels. • One start in the single mode performs conversions on all selected channels, and one start in the scan mode performs repeated conversions until stopped by software. • In buffer operation, the previous conversion result is saved in a buffer register at the end of a conversion for the relevant channel. • In simultaneous sampling operation, the analog input voltages of two channels are sampled simultaneously then converted in order. • Software, a timer conversion start trigger (MTU) can be selected as the conversion start condition. • High speed start mode or low power conversion mode can be selected for A/D conversion using the PWR bit setting. • When changing the operation mode or input channel, rewrite the ADCSR, ADCR while the ADST bit is cleared to 0. After rewriting the ADCSR, ADCR, A/D conversion will be restarted when the ADST bit is set to 1. Operation mode or input channel changes can be made simultaneously with ADST bit setting. When stopping an A/D conversion before completion, 0 clear the ADST bit. 13.4.1 Select-Single Mode Choose select-single mode when doing A/D conversions for one channel only. When the ADST bit is set to 1, A/D conversion is started according to the designated conversion start conditions. The ADST bit is held to 1 during the A/D conversion and is automatically cleared to 0 upon completion. The ADF flag is also set to 1 at the end of conversion. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by reading the ADCSR, then writing a 0. Figure 13.3 shows an example of operation in the select-single mode when AN1 is selected. Rev.5.00 Sep. 27, 2007 Page 378 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ ADF ADST Channel 0 Set to 1 by software Conversion standby A/D Conversion Conversion Sampling 1 standby conversion 1 standby Conversion standby Conversion standby Automatic clear Channel 1 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD Conversion result 1 Figure 13.3 High Speed A/D Converter Operation Example (Select-Single Mode) 13.4.2 Select-Scan Mode Choose select-scan mode when doing repeated A/D conversions for one channel. This is useful when doing continuous monitoring of the analog input of one channel. When the ADST bit is set to 1, A/D conversion is started according to the designated conversion start conditions. The ADST bit is held to 1 until 0 cleared by software. A/D conversion for the selected input channel is repeated during that interval. The ADF flag is set to 1 at the end of the first conversion. At this point, if the ADIE bit is set, an ADI interrupt request is issued, and the high speed A/D converter is halted. With the high speed A/D converter in stop mode due to an ADI interrupt request, conversion is restarted when the ADF flag is cleared to 0. The ADF flag is cleared by reading the ADCSR then writing a 0. Figure 13.4 shows an example of operation in the select-scan mode when AN1 is selected. Rev.5.00 Sep. 27, 2007 Page 379 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ ADF ADST Channel 0 Set to 1 by software Conversion standby A/D conversion 5 Channel 1 ConverSampling sion 1 standby Conversion standby A/D conversion 1 Sampling 2 Sampling 3 A/D conversion 2 A/D conversion 3 Sampling 4 Sampling 5 A/D conversion 4 Sampling 6 Channel 2 Channel 3 ADDRA Conversion standby Conversion standby Conversion stopped Cleared to 0 by software ADDRB Conversion result 1 Conversion result 2 Conversion result 3 Conversion result 4 ADDRC ADDRD Figure 13.4 High Speed A/D Converter Operation Example (Select-Scan Mode) 13.4.3 Group-Single Mode Choose group-single mode when doing A/D conversions for multiple channels. When the ADST bit is set to 1, A/D conversion is started according to the designated conversion start conditions. The ADST bit is held to 1 during A/D conversion and is automatically cleared to 0 when all conversions for the designated input channels are completed. The ADF flag is set to 1 when all conversions for the designated input channels are completed. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by reading the ADCSR then writing a 0. Rev.5.00 Sep. 27, 2007 Page 380 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Figure 13.5 shows an example of operation in the group-single mode when AN0 to AN2 are selected. ADF ADST Set to 1 by software A/D Conversion Sampling conversion Conversion standby standby 1 1 A/D Sampling conversion 2 2 Automatic clear Channel 0 Channel 1 Conversion standby Conversion standby Channel 2 Conversion standby Sampling 3 A/D Conversion conversion standby 3 Channel 3 ADDRA ADDRB ADDRC ADDRD Conversion standby Conversion result 1 Conversion result 2 Conversion result 3 Figure 13.5 High Speed A/D Converter Operation Example (Group-Single Mode) 13.4.4 Group-Scan Mode Choose group-scan mode when doing repeated A/D conversions for multiple channels. This is useful when doing continuous monitoring of the analog inputs of multiple channels. When the ADST bit is set to 1, A/D conversion is started according to the designated conversion start conditions. The ADST bit is held to 1 until 0 cleared by software. A/D conversion for the selected input channels is repeated during that interval. Rev.5.00 Sep. 27, 2007 Page 381 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ The ADF flag is set to 1 at the completion of the first conversions of all the designated input channels. At this point, if the ADIE bit is set to 1, an ADI interrupt request is issued, and the high speed A/D converter is temporarily halted. With the high speed A/D converter in stop mode due to an ADI interrupt request, conversion is restarted when the ADF flag is cleared to 0. The ADF flag is cleared by reading the ADCSR, then writing a 0. Figure 13.6 shows an example of operation in the group-scan mode when AN0 to AN2 are selected. Conversion standby Set to 1 by software Cleared to 0 by software Conversion stopped Channel 0 Conversion standby Sampling 1 A/D conversion 1 Sampling 2 A/D conversion 2 Sampling 3 Sampling 4 Conversion standby A/D conversion 3 A/D conversion 4 Sampling 5 Conversion standby A/D conversion 5 Sampling 6 ADF ADST Channel 1 Conversion standby Channel 2 Conversion standby Channel 3 ADDRA ADDRB ADDRC ADDRD Conversion standby Conversion result 1 Conversion result 4 Conversion result 2 Conversion result 5 Conversion result 3 Figure 13.6 High Speed A/D Converter Operation Example (Group-Scan Mode) Rev.5.00 Sep. 27, 2007 Page 382 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.4.5 Buffer Operation When conversion ends on the relevant channel, the conversion result is stored in the ADDR, and simultaneously, the previously stored result is transferred to another ADDR. Buffer operation can be selected from the following: • AN0 → ADDRA → ADDRB (Two-stage, one-group operation) • AN0 → ADDRA → ADDRC, AN1 → ADDRB → ADDRD (Two-stage, two-group operation) • AN0 → ADDRA → ADDRB → ADDRC → ADDRD (Four-stage, one-group operation) To use in combination with simultaneous sampling, set GRP = 1, BUFE1, BUFE0 = B'10 and CH2 = 0. Buffer operation timing is shown in figure 13.7. Rev.5.00 Sep. 27, 2007 Page 383 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ ADF ADST Conversion standby Set to 1 by software Sampling 1 A/D conversion 1 Sampling 2 Sampling 3 A/D conversion 2 A/D conversion 3 Sampling 4 Cleared to 0 by software Sampling 5 A/D conversion 4 Channel 0 Conversion standby Channel 1 Conversion standby Channel 2 Conversion standby Channel 3 Conversion standby ADDRA Conversion result 1 Conversion result 2 Conversion result 3 Conversion result 4 ADDRB Conversion result 1 Conversion result 2 Conversion result 3 ADDRC ADDRD Figure 13.7 Buffer Operation Example (Select Scan Mode: Two-Stage One-Group Operation, When CH2 to CH0 = B'001) Buffer-Only Operation: When performing conversion only on the analog input channels specified by the BUFE1 and BUFE0 bits, select group mode, and you can select the ADF flag setting conditions with the CH2 to CH0 bits. Table 13.4 shows conversion during buffer operation and ADF flag setting conditions. The ADF flag is set at the point in the table when the final conversion has ended. In single mode, conversion is halted after the ADF flag is set to 1. In scan mode, conversion continues, and the converted data is stored in sequence in the buffer registers specified by the BUFE1 and BUFE0 bits. Rev.5.00 Sep. 27, 2007 Page 384 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ When the ADF flag is set to 1, if the ADIE bit is also set to 1, an ADI interrupt is issued. After the ADCSR is read, the ADF flag is cleared by a 0 write. With select single mode, the high speed A/D converter goes into standby mode at the end of every conversion cycle. The high speed A/D converter is restarted by software, or a timer trigger. When the number of conversion cycles shown in table 13.4 have ended, the ADF flag is set to 1. Table 13.4 Conversion Channel and ADF Flag Setting/Clearing Conditions During Buffer Operation 1 Channel Setting CH2 CH1 CH0 0 0 0 1 1 0 1 1 Note: ⎯ * ⎯ BUFE1, BUFE0 = B'01 AN0 1 time (ADDRA) AN0 2 times (ADDRB) * * * * AN0, AN1 2 times (ADDRD) Sampling Channel BUFE1, BUFE0 = B'10 AN0, AN1 1 time (ADDRB) BUFE1, BUFE0 = B'11 AN0 1 time (ADDRA) AN0 2 times (ADDRB) AN0 3 times (ADDRC) AN0 4 times (ADDRD) * See table 13.5. Combined Group Mode and Buffer Operation: Continuous conversion is possible on analog input channels (AN0 and AN1) specified by bits BUFE1 and BUFE0 as well as AN4 to AN7 due to setting of bits CH2 to CH0. Table 13.5 shows conversion during buffer operation and ADF flag setting conditions. The ADF flag is set at the point in the table when the final conversion has ended. In this case, conversion is performed on the analog input corresponding with the ADDR specified in the buffer register. For example, when BUFE1 and BUFE0 = B'11 and CH2 to CH0 = B'110, conversion results are stored in ADDRA and ADDRE to ADDRG. Also, contents of ADDRA to ADDRC before the start of conversion are transferred to ADDRB to ADDRD. In single mode, conversion is halted after the ADF flag has been set to 1. Conversion continues in scan mode. Rev.5.00 Sep. 27, 2007 Page 385 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Table 13.5 Conversion Channel and ADF Flag Setting/Clearing Conditions During Buffer Operation 2 Channel Setting CH2 CH1 CH0 0 0 1 ⎯ 0 1 1 0 0 1 1 0 1 Note: * Sampling Channel BUFE1, BUFE0 = B'01 BUFE1, BUFE0 = B'10 BUFE1, BUFE0 = B'11 * AN0, AN2 (ADDRC) AN0, AN2, AN3 (ADDRD) AN0, AN2 to AN4 (ADDRE) AN0, AN2 to AN5 (ADDRF) AN0, AN2 to AN6 (ADDRG) AN0, AN2 to AN7 (ADDRH) AN0, AN1, AN4 (ADDRE) AN0, AN1, AN4, AN5 (ADDRF) AN0, AN4 (ADDRE) AN0, AN4, AN5 (ADDRF) * * AN0, AN1, AN4 to AN6 AN0, AN4 to AN6 (ADDRG) (ADDRG) AN0, AN1, AN4 to AN7 AN0, AN4 to AN7 (ADDRH) (ADDRH) See table 13.4. ADF Flag Clearing: When the DMAC is started up due to an A/D conversion end interrupt, the ADF flag is cleared when the ADDR specified in table 13.4 or 13.5 has been read. Resetting the Number of Buffer Operations: Clear the BUFE1 and BUFE0 bits to B'00 in conversion standby mode or when the converter has been halted. The number of buffer operations is cleared to 0. Updating Buffer Operations: Clear the BUFE1 and BUFE0 bits to B'00 in conversion standby mode or when the converter has been halted. Thereafter, set BUFE1 and BUFE0, and the buffer operations shown in table 13.4 and 13.5 are performed when conversion is resumed. 13.4.6 Simultaneous Sampling Operation With simultaneous sampling, continuous conversion is conducted with sampling of the input voltages on two channels at the same time. Simultaneous sampling is valid in group mode. Channels for sampling are determined by the CH2 and CH1 bits of the RDSCR. The combinations are shown in table 13.6. For example, if GRP = 1 when CH2 and CH1 = B'11, sampling occurs in order in the following pairs: AN0, AN1→AN2, AN3→AN4, AN5→AN6, AN7. Sampling timing is shown in figure 13.9. Rev.5.00 Sep. 27, 2007 Page 386 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Table 13.6 Simultaneous Sampling Channels Channel Setting CH2 0 CH1 0 1 1 0 1 Sampling Channels, GRP 1 AN0, AN1 AN0, AN1 → AN2, AN3 AN0, AN1 → AN2, AN3 → AN4, AN5 AN0, AN1 → AN2, AN3 → AN4, AN5 → AN6, AN7 ADF ADST Channel 0 Conversion standby Conversion standby Set to 1 by software A/D conversion 1 Automatically cleared Sampling 1 Conversion standby Channel 1 ConverSampling sion 2 standby conversion standby A/D conversion 2 Channel 2 Channel 3 ADDRA ADDRB ADDRC ADDRD Conversion standby Conversion standby Conversion result 1 Conversion result 2 Figure 13.8 Simultaneous Sampling Operation (Group Single Mode) Rev.5.00 Sep. 27, 2007 Page 387 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.4.7 Conversion Start Modes The conversion start mode of the high speed A/D converter is set by the PWR bit of the ADCSR. When the PWR bit is cleared to 0, low-power conversion mode is set and the internal analog circuit becomes inactive. High-speed start mode is set by setting the PWR bit to 1, and the analog circuit becomes active. In the low-power conversion mode, power is applied to the analog circuitry simultaneous to the conversion start (ADST set). When 200 cycles of the reference clock have elapsed, conversion becomes possible for the analog circuit and the first A/D conversion begins. When performing consecutive conversions, the second and later conversions are executed in 20 cycles. Select the basic clock with the CKS bit of the ADCSR. When the A/D conversion ends, ADST is cleared to 0 and the analog circuit power supply is automatically cut off. Because the analog circuit is only active during the A/D conversion operation period in this mode, current consumption can be reduced. In high-speed start mode, ADST is cleared to 0 when A/D conversion ends. Power continues to be supplied to the analog circuitry, and conversion-ready status is maintained. Conversion is restarted immediately by resetting ADST to 1. However, the first conversion after power-on begins 200 cycles after setting ADST. Clear the PWR bit to 0 to switch off the analog power supply. When performing consecutive conversions, the second and later conversions are executed in 20 cycles. Because the analog circuit is always active in this mode, A/D conversion can be executed at high speed. When A/D conversion is forcibly halted by clearing the ADST bit to 0 during conversion in highspeed start mode (when ADST = 1), the first conversion following a restart may not be performed normally. The second and subsequent conversions are performed normally. Figures 13.9 and 13.10 show the timing of the conversion start operation. Rev.5.00 Sep. 27, 2007 Page 388 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Figures 13.9 and 13.10 show examples of conversion start operation timing. ADF Analog circuit power supply ADST Conversion standby Conversion standby Set Clear Set to 1 by software Sampling 1 Cleared to 0 by software A/D conversion 1 Sampling 2 Sampling 3 A/D conversion 2 A/D conversion 3 Channel 0 Channel 1 Channel 2 Conversion standby Conversion standby 200 cycles Conversion result 1 Conversion result 3 Channel 3 ADDRA ADDRB Conversion result 2 ADDRC ADDRD Figure 13.9 Conversion Start Operation (Low-Power Conversion Mode) Rev.5.00 Sep. 27, 2007 Page 389 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ ADF Analog circuit power supply ADST (PWR set to 0) Switched on by software (PWR set to 1) Switched off by software Set to 1 by software Set to 1 by software Conversion standby Sampling 1 A/D conversion 1 Sampling 2 A/D conversion 2 Channel 0 Channel 1 Conversion standby Channel 2 Conversion standby Conversion standby 200 cycles Conversion result 2 Channel 3 ADDRA Conversion result 1 ADDRB ADDRC ADDRD Figure 13.10 Conversion Start Operation (High-Speed Start Mode) Rev.5.00 Sep. 27, 2007 Page 390 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.4.8 A/D Conversion Time The high speed A/D converter has an on-chip sample and hold circuit. The high speed A/D converter samples the input at time tD after the ADST bit is set to 1, and then starts the conversion. The A/D conversion time tCONV is the sum of the conversion start delay time tD, the input sampling time tSPL, and the operating time tCP. This conversion time is not a set value, but is decided by the tD ADCSR write timing, or the timer conversion start trigger generation timing. Figure 13.11 shows an example of A/D conversion timing. Table 13.7 lists A/D conversion times. φ Address Write signal ADST Sampling timing ADF tD tSPL tCONV Legend: tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Operation time tCP: tCP Figure 13.11 A/D Conversion Timing Rev.5.00 Sep. 27, 2007 Page 391 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Table 13.7 A/D Conversion Times CKS = 0 Time A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 1.5 20 42.5 Typ 1.5 20 42.5 Max 1.5 20 42.5 Min 1.5 40 82.5 CKS = 1 Typ 1.5 40 82.5 Max 1.5 40 82.5 Notes: 1. Unit: states 2. Table entries are for when PWR = 1. If 200 states have not elapsed since the ADST bit has been set, no conversions are done until after those 200 states have occurred. When PWR = 0, add 200 states to the first A/D conversion start delay time. When two or more conversions are performed in succession, tcp is 20 cycles when CKS = 0, and 40 cycles when CKS = 1. The CKS bit of the ADCSR is the operation time tCONV, but set so that this is 2 μs or greater. Table 13.8 shows the operating frequency and CKS bit settings. Table 13.8 Operating Frequency and CKS Bit Settings Minimum Conversion Time (μs) CKS 0 1 Conversion Time (States) 42.5 82.5 28 MHz ⎯ 2.9 20 MHz 2.1 4.2 16 MHz 2.6 5.0 10 MHz 4.3 8.3 8 MHz 5.3 10.3 Note: The indication "⎯" means the setting is not available. Rev.5.00 Sep. 27, 2007 Page 392 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.5 Interrupts The high speed A/D converter generates an A/D conversion end interrupt (ADI) upon completion of A/D conversions. The ADI interrupt request can be enabled or disabled by the ADIE bit of the ADCSR. The DMAC can be activated by ADI interrupts. When converted data is read by the DMAC upon an ADI interrupt, consecutive conversions can be done without software responsibility. Table 13.9 lists the high speed A/D converter interrupt sources. During scan mode, if the ADIE bit is set to 1, A/D conversion is temporarily suspended immediately when the ADF flag is set to 1. A/D conversion is restarted when the ADF flag is cleared to 0. When the DMAC is activated by an ADI interrupt, the ADF flag is cleared to 0 when the final specified data register is read. Table 13.9 High Speed A/D Converter Interrupt Sources Interrupt Source ADI Description Interrupt caused by conversion end DMAC Activation Possible Rev.5.00 Sep. 27, 2007 Page 393 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.6 Usage Notes Note the following points concerning the high speed A/D converter. 13.6.1 Analog Input Voltage Range During A/D conversions, see that the voltage applied to the analog input pins AN0 to AN7 is within the range of AVSS ≤ AN0 to AN7 ≤ AVCC. 13.6.2 AVCC, AVSS Input Voltages The AVCC, AVSS input voltages should be AVCC = VCC ±10%, and AVSS = VSS. When not using the high speed A/D converter, make AVCC = VCC and AVSS = VSS. When in standby mode, make VRAM ≤ AVCC ≤ 5.5 V, and AVSS = VSS. VRAM is the RAM standby voltage. 13.6.3 Input Ports Make the time constant of circuitry connected to an input port shorter than the high speed A/D converter sampling time. If the time constant of the circuit is longer, there will be occasions where the input voltage is not adequately sampled. 13.6.4 Conversion Start Modes Current consumption will be different for the A/D conversion operation in high speed start mode and low-power conversion mode according to the PWR bit setting. 13.6.5 A/D Conversion Termination (HD6417014R only) If conversion is terminated while in progress (when ADST = 1) in high-speed start mode (PWR = 1) by clearing the ADST bit, there may be a large degree of error in the first conversion following the restart (on channel 1 in normal mode, or channel 2 in simultaneous sampling mode). Subsequent conversions will be performed normally If A/D conversion is terminated while in progress, use one of the following methods to solve this problem: (a) Ignore the first data following a restart after termination. (b) If the first data after a restart is used, perform a single dummy conversion in single mode after the termination, terminate A/D conversion, then restart. (c) After termination, write 0 to the PWR bit before restarting. (In this case, the first conversion after the restart will begin after the elapse of 200 A/D reference clock cycles.) Rev.5.00 Sep. 27, 2007 Page 394 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ 13.6.6 Handling of Analog Input Pins To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to AN7), connect a protection circuit such as that shown in figure 13.12. This circuit also includes a CR filter function that suppresses error due to noise. The circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. Figure 13.13 shows an equivalent circuit for the analog input pins, and table 13.10 summarizes the analog input pin specifications. AVcc 100Ω AN0 to AN7 * 0.1 μF AVss SH7014 Note: * 10 μF 0.01 μF Figure 13.12 Example of Analog Input Pin Protection Circuit 1.0 kΩ AN0 to AN7 20 pF 1 MΩ Analog multiplexer Note: Numeric values are reference values. High speed A/D converter Figure 13.13 Analog Input Pin Equivalent Circuit Rev.5.00 Sep. 27, 2007 Page 395 of 716 REJ09B0398-0500 13. High Speed A/D Converter ⎯ SH7014 ⎯ Table 13.10 Analog Input Pin Specifications Item Analog input capacitance Permissible signal source impedance Min ⎯ ⎯ Max 20 1 Unit pF kΩ Rev.5.00 Sep. 27, 2007 Page 396 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Section 14 Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.1 Overview The mid-speed A/D converter has 10 bit resolution, and can select from a maximum of eight channels of analog input. 14.1.1 Features The mid-speed A/D converter has the following features: • 10-bit resolution • Eight input channels • Conversion time ⎯ Minimum conversion time: per channel: 6.7 μs (20MHz) • Multiple conversion modes: Single mode/scan mode ⎯ Single mode: 1 channel A/D conversion ⎯ 1 to 4 channel simultaneous conversion • Four 16-bit data registers ⎯ The results of A/D conversion are transferred to and held in the data register for the relevant channel. • Sample and hold function • A/D conversion end interrupt generation ⎯ An A/D conversion end interrupt (ADI) can be generated on completion of A/D conversion. • A/D conversion can be started by MTU trigger input. Rev.5.00 Sep. 27, 2007 Page 397 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.1.2 Block Diagram Figure 14.1 is the block diagram of the mid-speed A/D converter. Module data bus Internal data bus ADDRC ADDRD ADDRA ADDRB ADCSR AVCC 10-bit D/A AVSS Continuous comparison register AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer + − Conparator Sample & hold circuit Control circuit φ/16 φ/8 ADCR Bus interface A/D Converter MTU trigger Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control status register A/D data register A A/D data register B A/D data register C A/D data register D Interrupt signal ADI Figure 14.1 Mid-speed A/D converter block diagram Rev.5.00 Sep. 27, 2007 Page 398 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.1.3 Pin Configuration Table 14.1 shows the input pins used with the mid-speed A/D converter. The eight analog input pins are divided into two groups, with analog input pins 0 to 3 (AN0 to AN3) comprising group 0, and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVCC and AVSS pins are for the mid-speed A/D converter internal analog section power supply. Table 14.1 Pin Configuration Pin Analog supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O I I I I I I I I I I Analog input group 1 Function Analog section power supply Analog section ground and A/D conversion standard voltage Analog input group 0 Rev.5.00 Sep. 27, 2007 Page 399 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.1.4 Register Configuration Table 14.2 shows the register configuration of the mid-speed A/D converter. Table 14.2 Register Configuration Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Note: * Abbreviation R/W ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R R R R R R R R Initial Value Address H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFF8420 H'FFFF8421 H'FFFF8422 H'FFFF8423 H'FFFF8424 H'FFFF8425 H'FFFF8426 H'FFFF8427 H'FFFF8428 H'FFFF8429 Access Size 8, 16 8 8, 16 8 8, 16 8 8, 16 8 8, 16 8, 16 R/(W)* H'00 R/W H'7F Only 0 can be written to bit 7 to clear the flag. Rev.5.00 Sep. 27, 2007 Page 400 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.2 14.2.1 Register Descriptions A/D Data Register A to D (ADDRA to ADDRD) Bit : 15 14 AD8 0 R 13 AD7 0 R 12 AD6 0 R 11 AD5 0 R 10 AD4 0 R 9 AD3 0 R 8 AD2 0 R 7 AD1 0 R 6 AD0 0 R 5 ⎯ 0 R 4 ⎯ 0 R 3 ⎯ 0 R 2 ⎯ 0 R 1 ⎯ 0 R 0 ⎯ 0 R ADDRn : AD9 Initial value : R/W : 0 R Note: n = A to D A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are four registers: ADDRA to ADDRD. The A/D converted data is 10 bit data which is to the ADDR of the corresponding converted channel for storage. The upper 8 bits of the A/D converted data correspond to the upper byte of the ADDR and the lower 2 bits correspond to the lower byte. Bits 5 to 0 of the lower byte of ADDR are reserved and always read 0. Analog input channels and correspondence to ADDR are shown in table 14.3. ADDR can always be read from the CPU. The upper byte may be read directly. The lower byte is transferred through the temporary register (TEMP). For details, see section 14.3, Interface with CPU. ADDR is initialized to H'0000 during power-on reset. Table 14.3 Analog Input Channel and ADDRA to ADDRD Correspondence Analog Input Channel Group AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.5.00 Sep. 27, 2007 Page 401 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.2.2 A/D Control/Status Register (ADCSR) Bit : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 1 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to clear the flag. The A/D control/status register (ADCSR) is register that can read/write in 8 bits and control midspeed A/D converter operations such as mode selection. The ADCSR is initialized to H'00 during power-on reset. Bit 7⎯A/D End Flag (ADF): Status flag that indicates end of A/D conversion. Bit 7 ADF 0 Description [Clear conditions] 1. Writing 0 to ADF after reading ADF with ADF = 1 2. When registers of the mid-speed converter are accessed after the DMAC is activated by ADI interrupt. 1 [Set conditions] 1. 2. Single mode: When A/D conversion is complete Scan mode: When A/D conversion of all designated channels are complete (Initial value) Bit 6⎯A/D Interrupt Enable (ADIE): Enables or disables interrupt request (ADI) due to completion of A/D conversion. Bit 6 ADIE 0 1 Description Disables interrupt request (ADI) due to completion of A/D conversion Enables interrupt request (ADI) due to completion of A/D conversion (Initial value) Rev.5.00 Sep. 27, 2007 Page 402 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Bit 5⎯A/D Start (ADST): Selects start/end of A/D conversion. A 1 is maintained during A/D conversion start. It is also possible to set a 1 by the MTU trigger input. Bit 5 ADST 0 1 Description A/D conversion halted (Initial value) 1. Single mode: Starts A/D conversion. Automatically clears to 0 when conversion of the designated channel is complete 2. Scan mode: Starts A/D conversion. Continuous conversion until cleared to 0 by the software Bit 4⎯Scan Mode (SCAN): Selects the A/D conversion mode from single mode and scan mode. For operations during single/scan mode, see section 14.4, Operation. When switching modes, proceed while ADST = 0. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3⎯Clock Select (CKS): Sets the A/D conversion time. Proceed conversion time switch while ADST = 0. Always set CKS = 0 when operating frequency exceeds 20MHz. Bit 3 CKS 0 1 Description Conversion time = 266 states (max) Conversion time = 134 states (max) (Initial value) Bits 2 to 0⎯Channel select 2 to 0 (CH2 to CH0): Selects the analog input channel along with the SCAN bit. Switch channels while ADST = 0. Rev.5.00 Sep. 27, 2007 Page 403 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 Description Single Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Scan Mode (Initial value) (Initial value) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 0 0 1 1 0 1 14.2.3 A/D Control Register (ADCR) Bit : 7 TRGE 0 R/W : R/W 6 ⎯ 1 R 5 ⎯ 1 R 4 ⎯ 1 R 3 ⎯ 1 R 2 ⎯ 1 R 1 ⎯ 1 R 0 ⎯ 1 R Initial value : A/D control register (ADCR) is register that can read/write in 8 bits and enables or disables A/D conversion start of the MTU trigger input. ADCR is initialized to H'7F during power-on reset. Bit 7⎯Trigger Enable (TRGE): Enables or disables A/D conversion start of input from MTU trigger. Bit 7 TRGE 0 1 Description Disables A/D conversion start of MTU trigger Starts A/D conversion on MTU trigger. (Initial value) Bits 6 to 0⎯Reserved bits: These bits always read as 1. The write value should always be 1. Rev.5.00 Sep. 27, 2007 Page 404 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.3 Interface with CPU Although A/D data register ADDRA to ADDRD are 16-bit registers, the bus width within the chip that integrates with the CPU is 8-bits. So, the lower byte data is read through the temporary register (TEMP). The upper byte data can be read directly. The procedure for reading data from ADDR is as follows: First, read the upper byte data from ADDR. At this time, the upper byte data is read directly into the CPU and the lower byte data is transferred to TEMP of the mid-speed A/D converter. Next, read the lower byte to read the TEMP contents into the CPU. When reading the ADDR in byte size, read the upper byte before the lower byte. Furthermore, it is possible to read only the upper byte, however, please note that contents are not guaranteed when reading only the lower byte. In this case, ADDR can be read from the upper-byte address with a word transfer instruction (such as MOV.W). Figure 14.2 shows the data flow when reading from ADDR. Rev.5.00 Sep. 27, 2007 Page 405 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Module data bus CPU (H'AA) Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) Module data bus CPU (H'40) Bus interface TEMP (H'40) ADDRnH (H'AA) Note: n = A to D ADDRnL (H'40) Figure 14.2 ADDR Access Operation (During Reading of (H'AA40)) Rev.5.00 Sep. 27, 2007 Page 406 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.4 Operation The mid-speed converter operates using the continuous comparison method and is equipped with 10-bit resolution. Operations for the single and scan modes are explained below. 14.4.1 Single Mode (SCAN = 0) The single mode is selected when executing A/D conversion for one channel only. A/D conversion is initiated when the ADST bit of the A/D control/status register is set to 1 by the software or external trigger input. The ADST bit is held to 1 during the A/D conversion and is automatically cleared to 0 upon completion. When conversion is complete, the ADF bit of ADCSR is set to 1. At this time, if the ADIE bit of ADCSR is 1, ADI interrupt request occurs. The ADF bit can be cleared by writing 0 after reading ADF = 1. To switch modes or analog input channels during A/D conversion, clear the ADST bit to 0 and stop A/D conversion to avoid malfunction. After switching (mode/channel change and ADST bit setting can be made at the same time), set the ADST bit to 1 to restart A/D conversion. An example of operation when channel 1 (AN1) is selected in the single mode is shown in figure 14.3. 1. Set operation mode to single mode (SCAN = 0), input channel to AN1 (CH2 = CH1 = 0, CH0 = 1) and A/D interrupt request to enable (ADIE = 1) then start A/D conversion (ADST = 1). 2. When A/D conversion is complete, A/D conversion result is transferred to ADDRB. At the same time, ADF = 1 will become ADF = 0 and the mid-speed converter will standby for conversion. 3. Since ADF = 1 and ADIE = 1, ADI interrupt request will occur. 4. The A/D interrupt process routine will start. 5. After reading ADF = 1, write 0 to ADF. 6. Read the A/D conversion result (ADDRB) and process. 7. End A/D interrupt process routine execution. When ADST bit is set to 1, A/D conversion starts, following steps (2) to (7) above. Rev.5.00 Sep. 27, 2007 Page 407 of 716 REJ09B0398-0500 Set * ADIE Set * A/D conversion start Clear * Clear * Set * ADST ADF Channel 0 (AN0) Operation state Conversion standby Conversion standby A/D conversion (1) A/D conversion (2) Rev.5.00 Sep. 27, 2007 Page 408 of 716 REJ09B0398-0500 Conversion standby Conversion standby Conversion standby Conversion standby Reading conversion result A/D conversion result (1) Reading conversion result A/D conversion result (2) indicates command execution by the software Channel 1 (AN1) Operation state Channel 2 (AN2) Operation state 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Channel 3 (AN3) Operation state ADDRA ADDRB ADDRC Figure 14.3 Operation Example of Mid-speed A/D Converter (Single Mode, Channel 1 Selected) ADDRD Note: * 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.4.2 Scan Mode (SCAN = 1) The scan mode is optimal for monitoring analog input of multiple channels (including channel 1). A/D conversion is started from channel 1 (AN0 for CH2 = 0 and AN4 for CH1 = 1) of the group when the ADST bit of the A/D control/status register (ADCSR) is set to 1 by the software or external trigger input. When multiple channels are selected, A/D conversion of channel 2 (AN1 or AN5) is initiated immediately after completion of the channel 1 conversion. A/D conversion is performed repeatedly on the selected channels until the ADST bit is cleared to 0. The results of conversion are transferred to and held in the ADDR registers for the relevant channels. To switch modes or analog input channels during A/D conversion, clear the ADST bit to 0 and stop A/D conversion to avoid malfunction. After switching (mode/channel change and ADST bit setting can be made at the same time), set ADST bit to 1 to restart A/D conversion from channel 1. An example of operation in scan mode when three channels of group 0 (AN0 to AN2) are selected for A/D conversion is shown in figure 14.4. 1. Set the operation mode to scan mode (SCAN = 1), set the scan group to group 0 (CH2 = 0), set the analog channels to AN0 to AN2 (CH1 = 1, CH0 = 0), and then start A/D conversion (ADST = 1). 2. When A/D conversion for channel 1 (AN0) is complete, A/D conversion result is transferred to ADDRA. Next, channel 2 (AN1) will automatically be selected and conversion will begin. 3. In the same manner, channel 3 (AN2) will be converted. 4. When conversion of all of the selected channels (AN0 to AN2) are complete, ADF will become 1 and channel 1 (AN0) will again be selected and conversion will begin. At this time, if the ADIE bit is set to 1, ADI interrupt request will occur after completing A/D conversion. 5. Steps (2) to (4) will be repeated while ADST bit is set to 1. A/D conversion will stop when setting the ADST bit to 0. When setting the ADST bit to 1, A/D conversion will start again from channel 1 (AN0). Rev.5.00 Sep. 27, 2007 Page 409 of 716 REJ09B0398-0500 A/D continuous conversion Set *1 Clear *1 ADST Clear *1 A/D conversion time Conversion standby A/D conversion(1) Conversion standby Conversion standby Conversion standby A/D conversion(2) A/D conversion(4) ADF Channel 0 (AN0) Operation condition A/D conversion(5) * 2 Conversion standby Rev.5.00 Sep. 27, 2007 Page 410 of 716 REJ09B0398-0500 Conversion standby Conversion standby A/D conversion(3) Channel 1 (AN1) Operation condition Channel 2 (AN2) Operation condition Conversion standby Transfer A/D conversion result(1) 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Channel 3 (AN3) Operation condition ADDRA A/D conversion result(4) ADDRB A/D conversion result(2) ADDRC A/D conversion result(3) ADDRD Figure 14.4 Operation Example of Mid-speed A/D Converter (Scan Mode, Three Channels Selected) (AN0 to AN2) indicates command execution by the software Notes: 1. 2. Data is ignored during conversion 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.4.3 Input Sampling and A/D Conversion Time The mid-speed A/D converter is equipped with a sample and hold circuit. The mid-speed A/D converter samples input after tD hours has elapsed since setting the ADST bit of the A/D control/status register (ADCSR) to 1, then begins conversion. The A/D conversion timing is shown in table 14.4. The A/D conversion time, as shown in figure 14.5, includes both tD and input sampling time. Here, tD is determined by the write timing to ADCSR and is not constant. Thus the conversion time changes in the range shown in table 14.4. The conversion time shown in table 14.4 is the time for the first conversion. For the second conversion and after, the time will be 256 state (fixed) for CKS = 0 and 128 state (fixed) for CKS = 1. Rev.5.00 Sep. 27, 2007 Page 411 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ (1) CK Address (2) Write signal Input sampling timing ADF t D t SPL t CONV Legend: (1): Write cycle of ADCSR (2): Address of ADCSR tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Figure 14.5 A/D Conversion Timing Rev.5.00 Sep. 27, 2007 Page 412 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 Notation Min A/D conversion start delay time tD Input sampling time A/D conversion time tSPL tCCNV 10 ⎯ 259 Typ ⎯ 64 ⎯ Max 17 ⎯ 266 Min 6 ⎯ 131 CKS = 1 Typ ⎯ 32 ⎯ Max 9 ⎯ 134 Note: Numbers in the table are in states (tcyc). 14.4.4 MTU Trigger Input Timing It is possible to start A/D conversion from an MTU trigger input. MTU trigger input is input from MTU when the TRGE bit of the A/D control register (ADCR) is set to 1. A/D conversion is started when the ADST bit of the A/D control/status register (ADCSR) is set to 1 by MTU trigger. Other operations, regardless of whether in the single or scan mode, are the same as when setting the ADST bit to 1 with the software. Figure 14.6 shows an example of external trigger input timing. CK MTU trigger signal ADST A/D conversion Figure 14.6 External Trigger Input Timing Rev.5.00 Sep. 27, 2007 Page 413 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.5 Interrupt The mid-speed A/D converter generates an A/D conversion end interrupt (ADI) on completion of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DMAC can be activated by an ADI interrupt. Having converted data read by the DMAC by means of ADI interrupts allows continuous conversion to be carried out without imposing a load on the software. The mid-speed A/D converter's interrupt source is summarized in table 14.5. When the DMAC are activated by an ADI interrupt, the ADF flag of ADCSR is cleared to 0 by register access of A/D. Table 14.5 Mid-speed A/D converter interrupt factors Interrupt Factor ADI Content Interrupt by conversion complete DMAC Activation enabled Rev.5.00 Sep. 27, 2007 Page 414 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.6 A/D Conversion Precision Definitions The mid-speed A/D converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. In this operation, the absolute precision of the A/D conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. (1) Offset error (2) Full-scale error (3) Quantization error (4) Nonlinearity error The above four kinds of error are described below with reference to figure 14.7. For the sake of clarity, this figure shows 3-bit mid-speed A/D conversion rather than 10-bit mid-speed A/D conversion. Offset error (see figure 14.7 (1)) is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). Full-scale error (see figure 14.7 (2)) is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 111111111 (111 in the figure). Quantization error is the deviation inherent in the mid-speed A/D converter, given by 1/2 LSB (see figure 14.7 (3)). Nonlinearity error is the deviation between the actual A/D conversion characteristic and the ideal A/D conversion characteristic from zero voltage to full-scale voltage (see figure 14.7 (4)). This does not include offset error, full-scale error, and quantization error. Rev.5.00 Sep. 27, 2007 Page 415 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ (2) Full-scale error Digital output Digital output 111 110 101 100 011 010 001 000 0 Ideal A/D conversion Characteristic Ideal A/D conversion Characteristic (4) Nonlinearity error (3) Quantization error Actual A/D conversion characteristic 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS Analog input voltage (1) Offset error Legend: FS: Full-scale voltage Figure 14.7 A/D Conversion Precision Definitions Rev.5.00 Sep. 27, 2007 Page 416 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 14.7 Usage Notes The following points should be noted when using the mid-speed A/D converter. 14.7.1 Analog Voltage Settings (1) Analog input voltage range The voltage applied to analog input pins during A/D conversion should be in the range AVSS ≤ ANn ≤ AVCC (n = 0 to 7). (2) AVCC and AVSS input voltages For the AVCC and AVSS input voltages, set AVCC = VCC = 5V ±10% and AVSS = VSS. When the mid-speed A/D converter is not used, set AVCC = VCC and AVSS = VSS. 14.7.2 Handling of Analog Input Pins To prevent damage from surges and other abnormal voltages at the analog input pins (AN0 to AN7), connect a protection circuit such as that shown in figure 14.8. This circuit also includes a CR filter function that suppresses error due to noise. The circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. Figure 14.9 shows an equivalent circuit for the analog input pins, and table 14.6 summarizes the analog input pin specifications. AVCC 100 Ω AN0 to AN7 * 0.1 μF AVSS SH7016 SH7017 Note: * 10 μF 0.01 μF Figure 14.8 Example of Analog Input Pin Protection Circuit Rev.5.00 Sep. 27, 2007 Page 417 of 716 REJ09B0398-0500 14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯ 1.0 kΩ AN0 to AN7 20 pFΩ 1 MΩ Analog multiplexer Note: Numbers are only to be noted as reference value Mid-speed A/D converter Figure 14.9 Equivalent Circuit for the Analog Input Pins Table 14.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min ⎯ ⎯ Max 20 1 Unit pF kΩ Rev.5.00 Sep. 27, 2007 Page 418 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) Section 15 Compare Match Timer (CMT) 15.1 Overview This LSI has an on-chip compare match timer (CMT) configured of 16-bit timers for two channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 15.1.1 Features The CMT has the following features: • Four types of counter input clock can be selected ⎯ One of four internal clocks (φ/8, φ/32, φ/128, φ/512) can be selected independently for each channel. • Interrupt sources ⎯ A compare match interrupt can be requested independently for each channel. 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the CMT. Rev.5.00 Sep. 27, 2007 Page 419 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) CMI0 φ/8 φ/32 φ/128 φ/512 CMI1 φ/8 φ/32 φ/128 φ/512 Control circuit Clock selection Control circuit Clock selection Comparator Comparator CMCOR0 CMCOR1 CMCSR0 CMCSR1 CMCNT0 CMCNT1 Bus interface Internal bus CMSTR Module bus CMT Legend: CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 15.1 CMT Block Diagram Rev.5.00 Sep. 27, 2007 Page 420 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.1.3 Register Configuration Table 15.1 summarizes the CMT register configuration. Table 15.1 Register Configuration Channel Name Shared 0 Abbreviation R/W R/W R/(W)* R/W R/W R/(W)* R/W R/W Initial Value H'0000 H'0000 H'0000 Address Access Size (Bits) Compare match timer CMSTR start register Compare match timer CMCSR0 control/status register 0 Compare match timer CMCNT0 counter 0 Compare match timer CMCOR0 constant register 0 H'FFFF83D0 8, 16, 32 H'FFFF83D2 8, 16, 32 H'FFFF83D4 8, 16, 32 H'FFFF H'FFFF83D6 8, 16, 32 H'0000 H'0000 H'FFFF83D8 8, 16, 32 H'FFFF83DA 8, 16, 32 1 Compare match timer CMCSR1 control/status register 1 Compare match timer CMCNT1 counter 1 Compare match timer CMCOR1 constant register 1 H'FFFF H'FFFF83DC 8, 16, 32 Note: * The only value that can be written to the CMCSR0 and CMCSR1 CMF bits is a 0 to clear the flags. Rev.5.00 Sep. 27, 2007 Page 421 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.2 15.2.1 Register Descriptions Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by power-on resets and by standby mode. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: 0 R 14 ⎯ 0 R 6 ⎯ 0 R 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 ⎯ 0 R 9 ⎯ 0 R 1 STR1 0 R/W 8 ⎯ 0 R 0 STR0 0 R/W Bits 15 to 2⎯Reserved: These bits always read as 0. The write value should always be 0. Bit 1⎯Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1. Bit 1 STR1 0 1 Description CMCNT1 count operation halted CMCNT1 count operation (initial value) Bit 0⎯Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0. Bit 0 STR0 0 1 Description CMCNT0 count operation halted CMCNT0 count operation (initial value) Rev.5.00 Sep. 27, 2007 Page 422 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.2.2 Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by power-on resets and by standby mode. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 CMF Initial value: R/W: Note: * 0 R/(W)* 14 ⎯ 0 R 6 CMIE 0 R/W 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 ⎯ 0 R 9 ⎯ 0 R 1 CKS1 0 R/W 8 ⎯ 0 R 0 CKS0 0 R/W The only value that can be written is a 0 to clear the flag. Bits 15 to 8 and 5 to 2⎯Reserved: These bits always read as 0. The write value should always be 0. Bit 7⎯Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched. Bit 7 CMF 0 1 Description CMCNT and CMCOR values have not matched Clear condition: Write a 0 to CMF after reading a 1 from it CMCNT and CMCOR values have matched (initial status) Bit 6⎯Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). Bit 6 CMIE 0 1 Description Compare match interrupts (CMI) disabled Compare match interrupts (CMI) enabled (initial status) Rev.5.00 Sep. 27, 2007 Page 423 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) Bits 1, 0⎯Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock (φ). When the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and CKS0. Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description φ/8 φ/32 φ/128 φ/512 (initial status) 15.2.3 Compare Match Timer Counter (CMCNT) The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for generating interrupt requests. When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), the CMCNT is cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT is initialized to H'0000 by power-on resets and by standby mode. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev.5.00 Sep. 27, 2007 Page 424 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by power-on resets and by standby mode. Bit: 15 14 13 12 11 10 9 8 Initial value: R/W: Bit: 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Rev.5.00 Sep. 27, 2007 Page 425 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.3 15.3.1 Operation Period Count Operation When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 15.2 shows the compare match counter operation. CMCNT value CMCOR Counter cleared by CMCOR compare match H'0000 Time Figure 15.2 Counter Operation 15.3.2 CMCNT Count Timing One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be selected by the CKS1, CKS0 bits of the CMCSR. Figure 15.3 shows the timing. CK Internal clock CMCNT input clock CMCNT N−1 N N+1 Figure 15.3 Count Timing Rev.5.00 Sep. 27, 2007 Page 426 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.4 15.4.1 Interrupts Interrupt Sources The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when the interrupt request flag CMF is set to 1 and the interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by using the interrupt controller settings. See section 6, Interrupt Controller, for details. 15.4.2 Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 15.4 shows the CMF bit set timing. Rev.5.00 Sep. 27, 2007 Page 427 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) CK CMCNT input clock CMCNT N 0 CMCOR N Compare match signal CMF CMI Figure 15.4 CMF Set Timing 15.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1. Figure 15.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 CK T2 CMF Figure 15.5 Timing of CMF Clear by the CPU Rev.5.00 Sep. 27, 2007 Page 428 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.5 Usage Notes Take care that the contentions described in sections 15.5.1 to 15.5.3 do not arise during CMT operation. 15.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 15.6 shows the timing. CMCNT write cycle T1 T2 CK Address CMCNT Internal write signal Compare match signal CMCNT N H'0000 Figure 15.6 CMCNT Write and Compare Match Contention Rev.5.00 Sep. 27, 2007 Page 429 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 15.7 shows the timing. CMCNT write cycle T1 T2 CK Address CMCNT Internal write signal CMCNT input clock CMCNT N M CMCNT write data Figure 15.7 CMCNT Word Write and Increment Contention Rev.5.00 Sep. 27, 2007 Page 430 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) 15.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write. Figure 15.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 CK T2 Address CMCNTH Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X Figure 15.8 CMCNT Byte Write and Increment Contention Rev.5.00 Sep. 27, 2007 Page 431 of 716 REJ09B0398-0500 15. Compare Match Timer (CMT) Rev.5.00 Sep. 27, 2007 Page 432 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Section 16 Pin Function Controller (PFC) 16.1 Overview The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. Table 16.1 lists this LSI's multiplexed pins. The multiplex pin functions have restrictions dependent on the operating mode. Table 16.2 lists the pin functions and initial values for each operating mode. Table 16.1 Multiplexed Pins Function 1 Function 2 Port (Related Module) (Related Module) A A A A A A A A A A A A A A A A B B B B B PA15 I/O (port) PA14 I/O (port)* PA13 I/O (port)* PA12 I/O (port)* PA11 I/O (port)* PA10 I/O (port)* PA9 I/O (port) PA8 I/O (port) PA7 I/O (port) PA6 I/O (port) PA5 I/O (port) PA4 I/O (port) PA3 I/O (port) PA2 I/O (port) PA1 I/O (port) PA0 I/O (port) PB9 I/O (port) PB8 I/O (port) PB7 I/O (port) PB6 I/O (port) PB5 I/O (port) CK output (CPG) RD output (BSC) WRH output (BSC) WRL output (BSC) CS1 output (BSC) CS0 output (BSC) TCLKD input (MTU) TCLKC input (MTU) TCLKB input (MTU) TCLKA input (MTU) SCK1 I/O (SCI) TxD1 output (SCI) RxD1 input (SCI) SCK0 I/O (SCI) TxD0 output (SCI) RxD0 input (SCI) IRQ7 input (INTC) IRQ6 input (INTC) ⎯ ⎯ IRQ3 input (INTC) Function 3 Function 4 (Related Module) (Related Module) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IRQ3 (INTC) IRQ2 (INTC) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Pin No. 83 34 36 38 40 41 42 43 44 45 46 47 48 49 50 51 32 31 30 29 CS3 output (BSC) ⎯ CS2 output (BSC) ⎯ DREQ1 input (DMAC) ⎯ ⎯ DREQ0 input (DMAC) ⎯ ⎯ A21 output (BSC) A20 output (BSC) A19 output (BSC) A18 output (BSC) ⎯ IRQ1 input (INTC) ⎯ ⎯ IRQ0 input (INTC) ⎯ ⎯ ⎯ WAIT input (BSC) ⎯ ⎯ RDWR output (BSC) 28 Rev.5.00 Sep. 27, 2007 Page 433 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Function 1 Function 2 Port (Related Module) (Related Module) B B B B B C C C C C C C C C C C C C C C C D D D D D D D D D D PB4 I/O (port) PB3 I/O (port) PB2 I/O (port) PB1 I/O (port)* PB0 I/O (port)* PC15 I/O (port)* PC14 I/O (port)* PC13 I/O (port)* PC12 I/O (port)* PC11 I/O (port)* PC10 I/O (port)* PC9 I/O (port)* PC8 I/O (port)* PC7 I/O (port)* PC6 I/O (port)* PC5 I/O (port)* PC4 I/O (port)* PC3 I/O (port)* PC2 I/O (port)* PC1 I/O (port)* PC0 I/O (port)* PD15 I/O (port)* PD14 I/O (port)* PD13 I/O (port)* PD12 I/O (port)* PD11 I/O (port)* PD10 I/O (port)* PD9 I/O (port)* PD8 I/O (port)* PD7 I/O (port)* PD6 I/O (port)* IRQ2 input (INTC) IRQ1 input (INTC) IRQ0 input (INTC) A17 input (BSC) A16 output (BSC) A15 output (BSC) A14 output (BSC) A13 output (BSC) A12 output (BSC) A11 output (BSC) A10 output (BSC) A9 output (BSC) A8 output (BSC) A7 output (BSC) A6 output (BSC) A5 output (BSC) A4 output (BSC) A3 output (BSC) A2 output (BSC) A1 output (BSC) A0 output (BSC) D15 I/O (BSC) D14 I/O (BSC) D13 I/O (BSC) D12 I/O (BSC) D11 I/O (BSC) D10 I/O (BSC) D9 I/O (BSC) D8 I/O (BSC) D7 I/O (BSC) D6 I/O (BSC) Function 3 Function 4 (Related Module) (Related Module) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Pin No. CASH output (BSC) 26 CASL output (BSC) 25 RAS output (BSC) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 24 22 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 52 53 54 56 57 58 59 60 62 63 Rev.5.00 Sep. 27, 2007 Page 434 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Function 1 Function 2 Port (Related Module) (Related Module) D D D D D D E E E E E E E E E E E E E E E E F F F F F PD5 I/O (port)* PD4 I/O (port)* PD3 I/O (port)* PD2 I/O (port)* PD1 I/O (port)* PD0 I/O (port)* PE15 I/O (port) PE14 I/O (port) PE13 I/O (port) PE12 I/O (port) PE11 I/O (port) PE10 I/O (port) PE9 I/O (port) PE8 I/O (port) PE7 I/O (port) PE6 I/O (port) PE5 I/O (port) PE4 I/O (port) PE3 I/O (port) PE2 I/O (port) PE1 I/O (port) PE0 I/O (port) PF7 input (port) PF6 input (port) PF5 input (port) PF4 input (port) PF3 input (port) D5 I/O (BSC) D4 I/O (BSC) D3 I/O (BSC) D2 I/O (BSC) D1 I/O (BSC) D0 I/O (BSC) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TIOC2B I/O (MTU) TIOC2A I/O (MTU) TIOC1B I/O (MTU) TIOC1A I/O (MTU) TIOC0D I/O (MTU) TIOC0C I/O (MTU) TIOC0B I/O (MTU) TIOC0A I/O (MTU) AN7 input (A/D) AN6 input (A/D) AN5 input (A/D) AN4 input (A/D) AN3 input (A/D) Function 3 Function 4 (Related Module) (Related Module) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DACK1 output (DMAC) DACK0 output (DMAC) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DRAK1 output (DMAC) DREQ1 input (DMAC) DRAK0 output (DMAC) DREQ0 input (DMAC) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AH output (BSC) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Pin No. 64 66 67 68 69 70 2 1 112 111 110 108 107 106 105 104 102 89 88 87 86 85 99 98 96 95 94 Rev.5.00 Sep. 27, 2007 Page 435 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Function 1 Function 2 Port (Related Module) (Related Module) F F F Note: PF2 input (port) PF1 input (port) PF0 input (port) * AN2 input (A/D) AN1 input (A/D) AN0 input (A/D) Function 3 Function 4 (Related Module) (Related Module) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Pin No. 93 92 91 SH7016, SH7017 only Rev.5.00 Sep. 27, 2007 Page 436 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Table 16.2 Pin Functions in Each Operating Mode (SH7014) Pin Name On-Chip ROM Disabled Pin No. FP-112 21, 37, 65, 103 3, 23, 27, 33, 39, 55, 61, 71, 90, 101, 109 70 69 68 67 66 64 63 62 60 59 58 57 56 54 53 52 4 5 6 7 8 9 10 11 Initial Function Vcc Vss MPU Mode 0 Function Settable by PFC Vcc Vss Initial Function Vcc Vss MPU Mode 1 Function Settable by PFC Vcc Vss D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 Rev.5.00 Sep. 27, 2007 Page 437 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Pin Name On-Chip ROM Disabled Pin No. FP-112 12 13 14 15 16 17 18 19 20 22 24 25 26 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 Initial Function A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 CS0 MPU Mode 0 Function Settable by PFC A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH PB5/IRQ3/RDWR PB6/A18 PB7/A19 PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 Initial Function A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 CS0 MPU Mode 1 Function Settable by PFC A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH PB5/IRQ3/RDWR PB6/A18 PB7/A19 PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 Rev.5.00 Sep. 27, 2007 Page 438 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Pin Name On-Chip ROM Disabled Pin No. FP-112 40 38 36 34 83 80 82 74 72 81 76 84 35 79 78 75 73 77 100 97 91 92 93 94 95 96 98 99 85 Initial Function CS1 WRL WRH RD CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0 MPU Mode 0 Function Settable by PFC CS1 WRL WRH RD PA15/CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0/TIOC0A/DREQ0 Initial Function CS1 WRL WRH RD CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0 MPU Mode 1 Function Settable by PFC CS1 WRL WRH RD PA15/CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0/TIOC0A/DREQ0 Rev.5.00 Sep. 27, 2007 Page 439 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Pin Name On-Chip ROM Disabled Pin No. FP-112 86 87 88 89 102 104 105 106 107 108 110 111 112 1 2 Initial Function PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 MPU Mode 0 Function Settable by PFC PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14/DACK0/AH PE15/DACK1 Initial Function PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 MPU Mode 1 Function Settable by PFC PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14/DACK0/AH PE15/DACK1 Rev.5.00 Sep. 27, 2007 Page 440 of 716 REJ09B0398-0500 Pin No. MPU Mode 1 Initial Function PFC Selected Function Possiblilities Initial Function PFC Selected Function Possiblilities Initial Function PFC Selected Function Possiblilities Pin Name On-Chip ROM Disabled MPU Mode0 On-Chip ROM Enabled MPU Mode2 Single Chip Mode FP-112 VCC VCC VCC VCC VCC VCC Initial Function PFC Selected Function Possiblilities 21,37,65 103 VSS VSS VSS VSS VSS VSS VCC VCC 3,23,27,33 39,55,61,71 90,101,109 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PD0/D0 PD1/D1 PD2/D2 PD3/D3 PD4/D4 PD5/D5 PD6/D6 PD7/D7 PD8/D8 PD9/D9 PD10/D10 PD11/D11 PD12/D12 PD13/D13 PD14/D14 PD15/D15 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 VSS VSS Table 16.3 Pin Arrangement in Each Operating Mode (SH7016, SH7017) 70 69 68 67 66 64 63 62 60 59 58 57 56 54 53 52 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 16. Pin Function Controller (PFC) Rev.5.00 Sep. 27, 2007 Page 441 of 716 REJ09B0398-0500 Pin No. MPU Mode 1 Initial Function PFC Selected Function Possiblilities Initial Function PFC Selected Function Possiblilities Initial Function PFC Selected Function Possiblilities Pin Name On-Chip ROM Disabled MPU Mode0 On-Chip ROM Enabled MPU Mode2 Single Chip Mode PC13 PC14 PC15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PC13 PC14 PC15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PC13 PC14 PC15 PB0 PB1 PB2/IRQ0 PB3/IRQ1 PB4/IRQ2 PB5/IRQ3 PB6 PB7 PB8/IRQ6 PB9/IRQ7 PA0/RXD0 PA1/TXD0 PA2/SCK0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/IRQ1 PA6/TCLKA PA7/TCLKB PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PA10 PA11 PA12 PA13 PA14 PA15/CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS A13 A14 A15 A16 A17 PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH PB5/IRQ3/RDWR PB6/A18 PB7/A19 PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 CS1 WRL WRH RD PA15/CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS PC13/A13 PC14/A14 PC15/A15 PB0/A16 PB1/A17 PB2/IRQ0/RAS PB3/IRQ1/CASL PB4/IRQ2/CASH PB5/IRQ3/RDWR PB6/A18 PB7/A19 PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 PA10/CS0 PA11/CS1 PA12/WRL PA13/WRH PA14/RD PA15/CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS A13 A14 A15 A16 A17 PB2/IRQ0/POE0/RAS PB3/IRQ1/POE1/CASL PB4/IRQ2/POE2/CASH PB5/IRQ3/POE3/RDWR PB6/A18 PB7/A19 PB8/IRQ6/A20/WAIT PB9/IRQ7/A21 PA0/RXD0 PA1/TXD0 PA2/SCK0/DREQ0/IRQ0 PA3/RXD1 PA4/TXD1 PA5/SCK1/DREQ1/IRQ1 PA6/TCLKA/CS2 PA7/TCLKB/CS3 PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 CS0 CS1 WRL WRH RD PA15/CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS A13 A14 A15 A16 A17 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 CS0 CS1 WRL WRH RD CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS 16. Pin Function Controller (PFC) Rev.5.00 Sep. 27, 2007 Page 442 of 716 REJ09B0398-0500 FP-112 Initial Function PFC Selected Function Possiblilities 17 18 19 20 22 24 25 26 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 38 36 34 83 80 82 74 72 81 76 84 35 79 78 75 73 77 100 97 A13 A14 A15 A16 A17 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 CS0 CS1 WRL WRH RD CK PLLVCC PLLVSS EXTAL XTAL PLLCAP NMI RES WDTOVF MD0 MD1 MD2 MD3 VCC AVCC AVSS Pin No. MPU Mode 1 Initial Function PFC Selected Function Possiblilities Initial Function PFC Selected Function Possiblilities Initial Function PFC Selected Function Possiblilities Pin Name On-Chip ROM Disabled MPU Mode0 On-Chip ROM Enabled MPU Mode2 Single Chip Mode PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0/TIOC0A PE1/TIOC0B PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14/DACK0/AH PE15/DACK1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14/DACK0/AH PE15/DACK1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0/TIOC0A/DREQ0 PE1/TIOC0B/DRAK0 PE2/TIOC0C/DREQ1 PE3/TIOC0D/DRAK1 PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A PE7/TIOC2B PE8 PE9 PE10 PE11 PE12 PE13 PE14/DACK0/AH PE15/DACK1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 FP-112 Initial Function PFC Selected Function Possiblilities 91 92 93 94 95 96 98 99 85 86 87 88 89 102 104 105 106 107 108 110 111 112 1 2 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 16. Pin Function Controller (PFC) Rev.5.00 Sep. 27, 2007 Page 443 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.2 Register Configuration Table 16.4 summarizes the registers of the pin function controller. Table 16.4 Pin Function Controller Registers Name Port A I/O register L Abbreviation R/W PAIORL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000* H'4000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 1 Address H'FFFF8386 H'FFFF8387 H'FFFF838C H'FFFF838D H'FFFF838E H'FFFF838F H'FFFF8394 H'FFFF8395 H'FFFF8398 H'FFFF8399 H'FFFF839A H'FFFF839B H'FFFF8396 H'FFFF8397 H'FFFF839C H'FFFF839D H'FFFF83A6 H'FFFF83A7 H'FFFF83AC H'FFFF83AD H'FFFF83B4 H'FFFF83B5 H'FFFF83B8 H'FFFF83B9 H'FFFF83BA H'FFFF83BB Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Port A control register L1 PACRL1 Port A control register L2 PACRL2 Port B I/O register PBIOR Port B control register 1 PBCR1 Port B control register 2 PBCR2 Port C I/O register* 2 PCIOR 2 Port C control register* Port D I/O register L* 2 PCCR PDIORL 2 Port D control register L* PDCRL Port E I/O register PEIOR Port E control register 1 PECR1 Port E control register 2 PECR2 Notes: 1. The port A control register L1 initial value varies depending on the operating mode. 2. SH7016, SH7017 only. Rev.5.00 Sep. 27, 2007 Page 444 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3 16.3.1 Register Descriptions Port A I/O Register L (PAIORL) Bit: 15 PA15 IOR Initial value: R/W: Bit: 0 R/W 7 PA7 IOR Initial value: R/W: 0 R/W 14 PA14 IOR 0 R/W* 6 PA6 IOR 0 R/W 13 PA13 IOR 0 R/W* 5 PA5 IOR 0 R/W 12 PA12 IOR 0 R/W* 4 PA4 IOR 0 R/W 11 PA11 IOR 0 R/W* 3 PA3 IOR 0 R/W 10 PA10 IOR 0 R/W* 2 PA2 IOR 0 R/W 9 PA9 IOR 0 R/W 1 PA1 IOR 0 R/W 8 PA8 IOR 0 R/W 0 PA0 IOR 0 R/W Note: * R only in the SH7014 The port A I/O register L (PAIORL) is a 16-bit read/write register that selects input or output for the 16 pins of port A (11 pins in the SH7014). Bits PA15IOR to PA0IOR correspond to pins PA15/CK to PA0/RXD0. PAIORL is enabled when the port A pins function as general input/outputs (PA15 to PA0), or with the serial clock (SCK1, SCK0). For other functions, it is disabled. When the port A pin functions PA15 to PA0 are SCK1, SCK0, a given pin in port A is an output pin if its corresponding PAIORL bit is set to 1, and an input pin if the bit is cleared to 0. PAIORL is initialized to H'0000 by external power-on reset; however, it is not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings of bits 14 to 10 of this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to bits 14 to 10; these bits are always read as 0, and their write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 445 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.2 Port A Control Registers L1, L2 (PACRL1 and PACRL2) PACRL1 and PACRL2 are 16-bit read/write registers that select the functions of the 16 multiplexed pins of port A (11 pins in the SH7014). PACRL1 selects the function of the PA15/CK to PA8/TCLKC/IRQ2 pins of port A; PACRL2 selects the function of the PA7/TCLKB/CS3 to PA0/RXD0 pins of port A. Port A includes bus control signals (RD, WRH, WRL, CS0 to CS3, and AH) and DMAC control signals (DREQ0 and DREQ1), but in the SH7016 and SH7017, register settings relating to the selection of these pin functions may be invalid depending on the operating mode. For details, see table 16.2, Pin Functions in Each Operating Mode. PACRL1 is initialized by external power-on reset to H'4000 in extended mode, and to H'0000 in single chip mode. PACRL2 is initialized by external power-on reset to H'0000. Neither register is initialized by reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings of bits 12, 10, 8, 6, and 4 of PACRL1 are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. Port A Control Register L1 (PACRL1): Bit: 15 ⎯ Initial value: R/W: 0 R 14 PA15MD 0 (1)*1 R/W 13 ⎯ 0 R 12 PA14MD 0 R/W* 2 11 ⎯ 0 R 10 PA13MD 0 R/W* 2 9 ⎯ 0 R 8 PA12MD 0 R/W* 2 Bit: 7 ⎯ 6 PA11MD 0 R/W* 2 5 ⎯ 0 R 4 3 2 1 0 PA10MD PA9MD1 PA9MD0 PA8MD1 PA8MD0 0 R/W* 2 Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W Notes: 1. Bit 14 is initialized to 1 in extended mode. 2. R only in the SH7014. Rev.5.00 Sep. 27, 2007 Page 446 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 15⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 14⎯PA15 Mode (PA15MD): Selects the function of the PA15/CK pin. Bit 14 PA15MD 0 1 Description General input/output (PA15) Clock output (CK) (single chip mode initial value) (extended mode initial value) Bits 13⎯Reserved: This bit always read as 0. The write value should always be 0. Bit 12⎯PA14 Mode (PA14MD) ⎯SH7016, SH7017⎯: Selects the function of the PA14/RD pin. Bit 12 PA14MD 0 1 Description General input/output (PA14) (RD in on-chip ROM invalid mode) Read output (RD) (PA14 in single chip mode) (initial value) Bit 11⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 10⎯PA13 Mode (PA13MD) ⎯SH7016, SH7017⎯: Selects the function of the PA13/WRH pin. Bit 10 PA13MD 0 1 Description General input/output (PA13) (WRH in on-chip ROM invalid mode) Most significant side write output (WRH) (PA13 in single chip mode) (initial value) Bit 9⎯Reserved: This bit always reads as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 447 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 8⎯PA12 Mode (PA12MD) ⎯SH7016, SH7017⎯: Selects the function of the PA12/WRL pin. Bit 8 PA12MD 0 1 Description General input/output (PA12) (WRL in on-chip ROM invalid mode) Least significant side write output (WRL) (PA12 in single chip mode) (initial value) Bit 7⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 6⎯PA11 Mode (PA11MD) ⎯SH7016, SH7017⎯: Selects the function of the PA11/CS1 pin. Bit 6 PA11MD 0 1 Description General input/output (PA11) (CS1 in on-chip ROM invalid mode) Chip select output (CS1) (PA11 in single chip mode) (initial value) Bit 5⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 4⎯PA10 Mode (PA10MD) ⎯SH7016, SH7017⎯: Selects the function of the PA10/CS0 pin. Bit 4 PA10MD 0 1 Description General input/output (PA10) (CS0 in on-chip ROM invalid mode) Chip select output (CS0) (PA10 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 448 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 3 and 2⎯PA9 Mode 1, 0 (PA9MD1 and PA9MD0): These bits select the function of the PA9/TCLKD/IRQ3 pin. Bit 3 PA9MD1 0 Bit 2 PA9MD0 0 1 1 0 1 Description General input/output (PA9) MTU timer clock input (TCLKD) Interrupt request input (IRQ3) Reserved (initial value) Bits 1 and 0⎯PA8 Mode 1, 0 (PA8MD1 and PA8MD0): These bits select the function of the PA8/TCLKC/IRQ2 pin. Bit 1 PA8MD1 0 Bit 0 PA8MD0 0 1 1 0 1 Description General input/output (PA8) MTU timer clock input (TCLKC) Interrupt request input (IRQ2) Reserved (initial value) Port A Control Register L2 (PACRL2): Bit: 15 PA7 MD1 Initial value: R/W: Bit: 0 R/W 7 ⎯ Initial value: R/W: 0 R 14 PA7 MD0 0 R/W 6 PA3MD 0 R/W 13 PA6 MD1 0 R/W 5 PA2 MD1 0 R/W 12 PA6 MD0 0 R/W 4 PA2 MD0 0 R/W 11 PA5 MD1 0 R/W 3 ⎯ 0 R 10 PA5 MD0 0 R/W 2 PA1MD 0 R/W 9 ⎯ 0 R 1 ⎯ 0 R 8 PA4MD 0 R/W 0 PA0MD 0 R/W Rev.5.00 Sep. 27, 2007 Page 449 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 15 and 14⎯PA7 Mode 1, 0 (PA7MD1 and PA7MD0): These bits select the function of the PA7/TCLKB/CS3 pin. Bit 15 PA7MD1 0 Bit 14 PA7MD0 0 1 1 0 1 Description General input/output (PA7) MTU timer clock input (TCLKB) Chip select output (CS3) (PA7 in single-chip mode) Reserved (initial value) Bits 13 and 12⎯PA6 Mode 1, 0 (PA6MD1 and PA6MD0): These bits select the function of the PA6/TCLKA/CS2 pin. Bit 13 PA6MD1 0 Bit 12 PA6MD0 0 1 1 0 1 Description General input/output (PA6) MTU timer clock input (TCLKA) Chip select output (CS2) (PA6 in single-chip mode) Reserved (initial value) Bits 11 and 10⎯PA5 Mode 1, 0 (PA5MD1 and PA5MD0): These bits select the function of the PA5/SCK1/DREQ1/IRQ1 pin. Bit 11 PA5MD1 0 Bit 10 PA5MD0 0 1 1 0 1 Description General input/output (PA5) Serial clock input/output (SCK1) DMA transfer request received input (DREQ1) (PA5 in single-chip mode) Interrupt request input (IRQ1) (initial value) Bit 9⎯Reserved: This bit always reads as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 450 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 8⎯PA4 Mode (PA4MD): Selects the function of the PA4/TxD1 pin. Bit 8 PA4MD 0 1 Description General input/output (PA4) Transmit data output (TxD1) (initial value) Bit 7⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 6⎯PA3 Mode (PA3MD): Selects the function of the PA3/RxD1 pin. Bit 6 PA3MD 0 1 Description General input/output (PA3) Receive data input (RxD1) (initial value) Bits 5 and 4⎯PA2 Mode 1, 0 (PA2MD1 and PA2MD0): These bits select the function of the PA2/SCK0/DREQ0/IRQ0 pin. Bit 5 PA2MD1 0 Bit 4 PA2MD0 0 1 1 0 1 Description General input/output (PA2) Serial clock input/output (SCK0) DMA transfer request received input (DREQ0) (PA2 in single-chip mode) Interrupt request input (IRQ0) (initial value) Bit 3⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 2⎯PA1 Mode (PA1MD): Selects the function of the PA1/TxD0 pin. Bit 2 PA1MD 0 1 Description General input/output (PA1) Transmit data output (TxD0) (initial value) Bit 1⎯Reserved: This bit always reads as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 451 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 0⎯PA0 Mode (PA0MD): Selects the function of the PA0/RxD0 pin. Bit 0 PA0MD 0 1 Description General input/output (PA0) Receive data input (RxD0) (initial value) 16.3.3 Port B I/O Register (PBIOR) Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 PB7 IOR Initial value: R/W: 0 R/W 14 ⎯ 0 R 6 PB6 IOR 0 R/W 13 ⎯ 0 R 5 PB5 IOR 0 R/W 12 ⎯ 0 R 4 PB4 IOR 0 R/W 11 ⎯ 0 R 3 PB3 IOR 0 R/W 10 ⎯ 0 R 2 PB2 IOR 0 R/W 9 PB9 IOR 0 R/W 1 PB1 IOR 0 R/W* 8 PB8 IOR 0 R/W 0 PB0 IOR 0 R/W* Note: * R only in the SH7014. The port B I/O register L (PBIOR) is a 16-bit read/write register that selects input or output for the ten pins of port B (eight pins in the SH7014). Bits PB9IOR to PB0IOR correspond to the PB9/IRQ7/A21 pin to PB0/A16 pin. PBIOR is enabled when the port B pins function as input/outputs (PB9 to PB0). For other functions, it is disabled. For port B pin functions PB9 to PB0, a given pin in port B is an output pin if its corresponding PBIOR bit is set to 1, and an input pin if the bit is cleared to 0. PBIOR is initialized to H'0000 by external power-on reset; however, it is not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings of bits 1 and 0 of PBIOR are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 452 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.4 Port B Control Registers (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit read/write registers that select the functions of the ten multiplexed pins of port B (eight pins in the SH7014). PBCR1 selects the functions of the top two bits of port B; PBCR2 selects the functions of the bottom eight bits of port B (six bits in the SH7014). Port B includes bus control signals (RDWR, RAS, CASH, CASL, and WAIT) and address outputs (A21 to A16), but in the SH7016 and SH7017, settings in these registers relating to the selection of these pin functions may be invalid in single-chip mode. For details, see table 16.3, Pin Functions in Each Operating Mode. PBCR1 and PBCR2 are both initialized to H'0000 by external power-on reset but are not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings of bits 2 and 0 of PBCR2 are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. Port B Control Register 1 (PBCR1): Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: 0 R 14 ⎯ 0 R 6 ⎯ 0 R 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R 3 PB9 MD1 0 R/W 10 ⎯ 0 R 2 PB9 MD0 0 R/W 9 ⎯ 0 R 1 PB8 MD1 0 R/W 8 ⎯ 0 R 0 PB8 MD0 0 R/W Rev.5.00 Sep. 27, 2007 Page 453 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 15 to 4⎯Reserved: These bits always read as 0. The write value should always be 0. Bits 3 and 2⎯PB9 Mode 1, 0 (PB9MD1 and PB9MD0): PB9MD1 and PB9MD0 select the function of the PB9/IRQ7/A21 pin. Bit 3 PB9MD1 0 Bit 2 PB9MD0 0 1 1 0 1 Description General input/output (PB9) Interrupt request input (IRQ7) Address output (A21) (PB9 in single-chip mode) Reserved (initial value) Bits 1 and 0⎯PB8 Mode 1, 0 (PB8MD1 and PB8MD0): PB8MD1 and PB8MD0 select the function of the PB8/IRQ6/A20/WAIT pin. Bit 1 PB8MD1 0 Bit 0 PB8MD0 0 1 1 0 1 Description General input/output (PB8) Interrupt request input (IRQ6) Address output (A20) (PB8 in single-chip mode) Wait state request input (WAIT) (PB8 in single-chip mode) (initial value) Port B Control Register 2 (PBCR2): Bit: 15 14 13 12 11 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 ⎯ 0 R 0 R/W 2 PB1MD 0 R/W* 0 R/W 1 ⎯ 0 R 0 R/W 0 PB0MD 0 R/W* PB3MD1 PB3MD0 PB2MD1 PB2MD0 Initial value: R/W: Note: * 0 R/W 0 R/W 0 R/W 0 R/W R only in the SH7014. Rev.5.00 Sep. 27, 2007 Page 454 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 15 and 14⎯PB7 Mode 1, 0 (PB7MD1 and PB7MD0): PB7MD1 and PB7MD0 select the function of the PB7/A19 pin. Bit 15 PB7MD1 0 Bit 14: PB7MD0 0 1 1 0 1 Description General input/output (PB7) Reserved Address output (A19) (PB7 in single-chip mode) Reserved (initial value) Bits 13 and 12⎯PB6 Mode 1, 0 (PB6MD1 and PB6MD0): PB6MD1 and PB6MD0 select the function of the PB6/A18 pin. Bit 13 PB6MD1 0 Bit 12 PB6MD0 0 1 1 0 1 Description General input/output (PB6) Reserved Address output (A18) (PB6 in single-chip mode) Reserved (initial value) Bits 11 and 10⎯PB5 Mode 1, 0 (PB5MD1 and PB5MD0): PB5MD1 and PB5MD0 select the function of the PB5/IRQ3/RDWR pin. Bit 11 PB5MD1 0 Bit 10 PB5MD0 0 1 1 0 1 Description General input/output (PB5) Interrupt request input (IRQ3) Reserved Read/write output (RDWR) (PB5 in single-chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 455 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 9 and 8⎯PB4 Mode 1, 0 (PB4MD1 and PB4MD0): PB4MD1 and PB4MD0 select the function of the PB4/IRQ2/CASH pin. Bit 9 PB4MD1 0 Bit 8 PB4MD0 0 1 1 0 1 Description General input/output (PB4) Interrupt request input (IRQ2) Reserved Column address strobe (CASH) (PB4 in single-chip mode) (initial value) Bits 7 and 6⎯PB3 Mode 1, 0 (PB3MD1 and PB3MD0): PB3MD1 and PB3MD0 select the function of the PB3/IRQ1/CASL pin. Bit 7 PB3MD1 0 Bit 6 PB3MD0 0 1 1 0 1 Description General input/output (PB3) Interrupt request input (IRQ1) Reserved Column address strobe (CASL) (PB3 in single-chip mode) (initial value) Bits 5 and 4⎯PB2 Mode 1, 0 (PB2MD1 and PB2MD0): PB2MD1 and PB2MD0 select the function of the PB2/IRQ0/RAS pin. Bit 5 PB2MD1 0 Bit 4 PB2MD0 0 1 1 0 1 Description General input/output (PB2) Interrupt request input (IRQ0) Reserved Row address strobe (RAS) (PB2 in single-chip mode) (initial value) Bit 3⎯Reserved: This bit always reads as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 456 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 2⎯PB1 Mode (PB1MD) ⎯SH7016, SH7017⎯: Selects the function of the PB1/A17 pin. Bit 2 PB1MD 0 1 Description General input/output (PB1) (A17 in on-chip ROM invalid mode) Address output (A17) (PB1 in single chip mode) (initial value) Bit 1⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 0⎯PB0 Mode (PB0MD) ⎯SH7016, SH7017⎯: Selects the function of the PB0/A16 pin. Bit 0 PB0MD 0 1 Description General input/output (PB0) (A16 in on-chip ROM invalid mode) Address output (A16) (PB0 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 457 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.5 Port C I/O Register (PCIOR) ⎯ SH7016, SH7017 ⎯ Bit: 15 PC15 IOR Initial value: R/W: Bit: 0 R/W 7 PC7 IOR Initial value: R/W: 0 R/W 14 PC14 IOR 0 R/W 6 PC6 IOR 0 R/W 13 PC13 IOR 0 R/W 5 PC5 IOR 0 R/W 12 PC12 IOR 0 R/W 4 PC4 IOR 0 R/W 11 PC11 IOR 0 R/W 3 PC3 IOR 0 R/W 10 PC10 IOR 0 R/W 2 PC2 IOR 0 R/W 9 PC9 IOR 0 R/W 1 PC1 IOR 0 R/W 8 PC8 IOR 0 R/W 0 PC0 IOR 0 R/W The port C I/O register (PCIOR) is a 16-bit read/write register that selects input or output for the 16 port C pins. Bits PC15IOR to PC0IOR correspond to pins PC15/A15 to PC0/A0. PCIOR is enabled when the port C pins function as general input/outputs (PC15 to PC0). For other functions, it is disabled. When the port C pin functions are as PC15 to PC0, a given pin in port C is an output pin if its corresponding PCIOR bit is set to 1, and an input pin if the bit is cleared to 0. PCIOR is initialized to H'0000 by external power-on reset; however, it is not initialized for reset by WDT, standby mode, or sleep mode, so the previous values are maintained. The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to this register, and it should not be read or written to. Rev.5.00 Sep. 27, 2007 Page 458 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.6 Port C Control Register (PCCR) ⎯ SH7016, SH7017 ⎯ Bit: 15 PC15 MD Initial value: R/W: Bit: 0 R/W 7 PC7 MD Initial value: R/W: 0 R/W 14 PC14 MD 0 R/W 6 PC6 MD 0 R/W 13 PC13 MD 0 R/W 5 PC5 MD 0 R/W 12 PC12 MD 0 R/W 4 PC4 MD 0 R/W 11 PC11 MD 0 R/W 3 PC3 MD 0 R/W 10 PC10 MD 0 R/W 2 PC2 MD 0 R/W 9 PC9 MD 0 R/W 1 PC1 MD 0 R/W 8 PC8 MD 0 R/W 0 PC0 MD 0 R/W PCCR is a 16-bit read/write register that selects the functions for the sixteen port C multiplexed pins. There are instances when these register settings will be ignored, depending on the operation mode. Refer to table 16.3, Pin Arrangement by Mode, for details. PCCR is initialized to H'0000 by power-on resets but is not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to this register, and it should not be read or written to. Bit 15⎯PC15 Mode (PC15MD): Selects the function of the PC15/A15 pin. Bit 15 PC15MD 0 1 Description General input/output (PC15) (A15 in on-chip ROM invalid mode) Address output (A15) (PC15 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 459 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 14⎯PC14 Mode (PC14MD): Selects the function of the PC14/A14 pin. Bit 14 PC14MD 0 1 Description General input/output (PC14) (A14 in on-chip ROM invalid mode) Address output (A14) (PC14 in single chip mode) (initial value) Bit 13⎯PC13 Mode (PC13MD): Selects the function of the PC13/A13 pin. Bit 13 PC13MD 0 1 Description General input/output (PC13) (A13 in on-chip ROM invalid mode) Address output (A13) (PC13 in single chip mode) (initial value) Bit 12⎯PC12 Mode (PC12MD): Selects the function of the PC12/A12 pin. Bit 12 PC12MD 0 1 Description General input/output (PC12) (A12 in on-chip ROM invalid mode) Address output (A12) (PC12 in single chip mode) (initial value) Bit 11⎯PC11 Mode (PC11MD): Selects the function of the PC11/A11 pin. Bit 11 PC11MD 0 1 Description General input/output (PC11) (A11 in on-chip ROM invalid mode) Address output (A11) (PC11 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 460 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 10⎯PC10 Mode (PC10MD): Selects the function of the PC10/A10 pin. Bit 10 PC10MD 0 1 Description General input/output (PC10) (A10 in on-chip ROM invalid mode) Address output (A10) (PC10 in single chip mode) (initial value) Bit 9⎯PC9 Mode (PC9MD): Selects the function of the PC9/A9 pin. Bit 9 PC9MD 0 1 Description General input/output (PC9) (A9 in on-chip ROM invalid mode) Address output (A9) (PC9 in single chip mode) (initial value) Bit 8⎯PC8 Mode (PC8MD): Selects the function of the PC8/A8 pin. Bit 8 PC8MD 0 1 Description General input/output (PC8) (A8 in on-chip ROM invalid mode) Address output (A8) (PC8 in single chip mode) (initial value) Bit 7⎯PC7 Mode (PC7MD): Selects the function of the PC7/A7 pin. Bit 7 PC7MD 0 1 Description General input/output (PC7) (A7 in on-chip ROM invalid mode) Address output (A7) (PC7 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 461 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 6⎯PC6 Mode (PC6MD): Selects the function of the PC6/A6 pin. Bit 6 PC6MD 0 1 Description General input/output (PC6) (A6 in on-chip ROM invalid mode) Address output (A6) (PC6 in single chip mode) (initial value) Bit 5⎯PC5 Mode (PC5MD): Selects the function of the PC5/A5 pin. Bit 5 PC5MD 0 1 Description General input/output (PC5) (A5 in on-chip ROM invalid mode) Address output (A5) (PC5 in single chip mode) (initial value) Bit 4⎯PC4 Mode (PC4MD): Selects the function of the PC4/A4 pin. Bit 4 PC4MD 0 1 Description General input/output (PC4) (A4 in on-chip ROM invalid mode) Address output (A4) (PC4 in single chip mode) (initial value) Bit 3⎯PC3 Mode (PC3MD): Selects the function of the PC3/A3 pin. Bit 3 PC3MD 0 1 Description General input/output (PC3) (A3 in on-chip ROM invalid mode) Address output (A3) (PC3 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 462 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 2⎯PC2 Mode (PC2MD): Selects the function of the PC2/A2 pin. Bit 2 PC2MD 0 1 Description General input/output (PC2) (A2 in on-chip ROM invalid mode) Address output (A2) (PC2 in single chip mode) (initial value) Bit 1⎯PC1 Mode (PC1MD): Selects the function of the PC1/A1 pin. Bit 1 PC1MD 0 1 Description General input/output (PC1) (A1 in on-chip ROM invalid mode) Address output (A1) (PC1 in single chip mode) (initial value) Bit 0⎯PC0 Mode (PC0MD): Selects the function of the PC0/A0 pin. Bit 0 PC0MD 0 1 Description General input/output (PC0) (A0 in on-chip ROM invalid mode) Address output (A0) (PC0 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 463 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.7 Port D I/O Register L (PDIORL) ⎯ SH7016, SH7017 ⎯ Bit: 15 PD15 IOR Initial value: R/W: Bit: 0 R/W 7 PD7 IOR Initial value: R/W: 0 R/W 14 PD14 IOR 0 R/W 6 PD6 IOR 0 R/W 13 PD13 IOR 0 R/W 5 PD5 IOR 0 R/W 12 PD12 IOR 0 R/W 4 PD4 IOR 0 R/W 11 PD11 IOR 0 R/W 3 PD3 IOR 0 R/W 10 PD10 IOR 0 R/W 2 PD2 IOR 0 R/W 9 PD9 IOR 0 R/W 1 PD1 IOR 0 R/W 8 PD8 IOR 0 R/W 0 PD0 IOR 0 R/W The port D I/O register L (PDIORL) is a 16-bit read/write register that selects input or output for the sixteen port D pins. Bits PD15IOR to PD0IOR correspond to the PD15/D15 pin to PD0/D0 pin. PDIORL is enabled when the port D pins function as general input/outputs (PD15 to PD0). For other functions, it is disabled. For port D pin functions PD15 to PD0, a given pin in port D is an output pin if its corresponding PDIORL bit is set to 1, and an input pin if the bit is cleared to 0. PDIORL is initialized to H'0000 by external power-on reset; however, it is not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to this register, and it should not be read or written to. Rev.5.00 Sep. 27, 2007 Page 464 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.8 Port D Control Register L (PDCRL) ⎯ SH7016, SH7017 ⎯ Bit: 15 PD15 MD Initial value: R/W: Bit: 0 R/W 7 PD7 MD Initial value: R/W: 0 R/W 14 PD14 MD 0 R/W 6 PD6 MD 0 R/W 13 PD13 MD 0 R/W 5 PD5 MD 0 R/W 12 PD12 MD 0 R/W 4 PD4 MD 0 R/W 11 PD11 MD 0 R/W 3 PD3 MD 0 R/W 10 PD10 MD 0 R/W 2 PD2 MD 0 R/W 9 PD9 MD 0 R/W 1 PD1 MD 0 R/W 8 PD8 MD 0 R/W 0 PD0 MD 0 R/W PDCRL is a 16-bit read/write register that selects the multiplexed pin functions for the least significant sixteen port D pins. There are instances when these register settings will be ignored, depending on the operation mode. On-Chip ROM-Disabled Extended Mode: ⎯ Mode 0 (8-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled. ⎯ Mode 1 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled. On-Chip ROM-Enabled Extended Mode: The port D pins are shared as data I/O pins and general I/O pins; PDCRL settings are enabled. Single Chip Mode: The port D pins are general I/O pins; PDCRL settings are disabled. PDCRL is initialized to H'0000 by external power-on reset but is not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to this register, and it should not be read or written to. Rev.5.00 Sep. 27, 2007 Page 465 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 15⎯PD15 Mode (PD15MD): Selects the function of the PD15/D15 pin. Bit 15 PD15MD 0 1 Description General input/output (PD15) (D15 in on-chip ROM invalid mode) Data input/output (D15) (PD15 in single chip mode) (initial value) Bit 14⎯PD14 Mode (PD14MD): Selects the function of the PD14/D14 pin. Bit 14 PD14MD 0 1 Description General input/output (PD14) (D14 in on-chip ROM invalid mode) Data input/output (D14) (PD14 in single chip mode) (initial value) Bit 13⎯PD13 Mode (PD13MD): Selects the function of the PD13/D13 pin. Bit 13 PD13MD 0 1 Description General input/output (PD13) (D13 in on-chip ROM invalid mode) Data input/output (D13) (PD13 in single chip mode) (initial value) Bit 12⎯PD12 Mode (PD12MD): Selects the function of the PD12/D12 pin. Bit 12 PD12MD 0 1 Description General input/output (PD12) (D12 in on-chip ROM invalid mode) Data input/output (D12) (PD12 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 466 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 11⎯PD11 Mode (PD11MD): Selects the function of the PD11/D11 pin. Bit 11 PD11MD 0 1 Description General input/output (PD11) (D11 in on-chip ROM invalid mode) Data input/output (D11) (PD11 in single chip mode) (initial value) Bit 10⎯PD10 Mode (PD10MD): Selects the function of the PD10/D10 pin. Bit 10 PD10MD 0 1 Description General input/output (PD10) (D10 in on-chip ROM invalid mode) Data input/output (D10) (PD10 in single chip mode) (initial value) Bit 9⎯PD9 Mode (PD9MD): Selects the function of the PD9/D9 pin. Bit 9 PD9MD 0 1 Description General input/output (PD9) (D9 in on-chip ROM invalid mode) Data input/output (D9) (PD9 in single chip mode) (initial value) Bit 8⎯PD8 Mode (PD8MD): Selects the function of the PD8/D8 pin. Bit 8 PD8MD 0 1 Description General input/output (PD8) (D8 in on-chip ROM invalid mode) Data input/output (D8) (PD8 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 467 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 7⎯PD7 Mode (PD7MD): Selects the function of the PD7/D7 pin. Bit 7 PD7MD 0 1 Description General input/output (PD7) (D7 in on-chip ROM invalid mode) Data input/output (D7) (PD7 in single chip mode) (initial value) Bit 6⎯PD6 Mode (PD6MD): Selects the function of the PD6/D6 pin. Bit 6 PD6MD 0 1 Description General input/output (PD6) (D6 in on-chip ROM invalid mode) Data input/output (D6) (PD6 in single chip mode) (initial value) Bit 5⎯PD5 Mode (PD5MD): Selects the function of the PD5/D5 pin. Bit 5 PD5MD 0 1 Description General input/output (PD5) (D5 in on-chip ROM invalid mode) Data input/output (D5) (PD5 in single chip mode) (initial value) Bit 4⎯PD4 Mode (PD4MD): Selects the function of the PD4/D4 pin. Bit 4 PD4MD 0 1 Description General input/output (PD4) (D4 in on-chip ROM invalid mode) Data input/output (D4) (PD4 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 468 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 3⎯PD3 Mode (PD3MD): Selects the function of the PD3/D3 pin. Bit 3 PD3MD 0 1 Description General input/output (PD3) (D3 in on-chip ROM invalid mode) Data input/output (D3) (PD3 in single chip mode) (initial value) Bit 2⎯PD2 Mode (PD2MD): Selects the function of the PD2/D2 pin. Bit 2 PD2MD 0 1 Description General input/output (PD2) (D2 in on-chip ROM invalid mode) Data input/output (D2) (PD2 in single chip mode) (initial value) Bit 1⎯PD1 Mode (PD1MD): Selects the function of the PD1/D1 pin. Bit 1 PD1MD 0 1 Description General input/output (PD1) (D1 in on-chip ROM invalid mode) Data input/output (D1) (PD1 in single chip mode) (initial value) Bit 0⎯PD0 Mode (PD0MD): Selects the function of the PD0/D0 pin. Bit 0 PD0MD 0 1 Description General input/output (PD0) (D0 in on-chip ROM invalid mode) Data input/output (D0) (PD0 in single chip mode) (initial value) Rev.5.00 Sep. 27, 2007 Page 469 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.9 Port E I/O Register (PEIOR) The port E I/O register (PEIOR) is a 16-bit read/write register that selects input or output for the 16 port E pins. Bits PE15IOR to PE0IOR correspond to pins PE15/DACK1 to PE0/TIOC0A/DREQ0. PEIOR is enabled when the port E pins function as general input/outputs (PE15 to PE0) or TIOC pin of the MTU. For other functions, it is disabled. When the port E pin functions are as PE15 to PE0, or TIOC pin of the MTU, a given pin in port E is an output pin if its corresponding PEIOR bit is set to 1, and an input pin if the bit is cleared to 0. PEIOR is initialized to H'0000 by external power-on reset; however, it is not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. Bit: 15 PE15 IOR Initial value: R/W: Bit: 0 R/W 7 PE7 IOR Initial value: R/W: 0 R/W 14 PE14 IOR 0 R/W 6 PE6 IOR 0 R/W 13 PE13 IOR 0 R/W 5 PE5 IOR 0 R/W 12 PE12 IOR 0 R/W 4 PE4 IOR 0 R/W 11 PE11 IOR 0 R/W 3 PE3 IOR 0 R/W 10 PE10 IOR 0 R/W 2 PE2 IOR 0 R/W 9 PE9 IOR 0 R/W 1 PE1 IOR 0 R/W 8 PE8 IOR 0 R/W 0 PE0 IOR 0 R/W Rev.5.00 Sep. 27, 2007 Page 470 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) 16.3.10 Port E Control Registers 1, 2 (PECR1 and PECR2) PECR1 and PECR2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port E. PECR1 selects the functions of the upper eight bit pins of port E; PECR2 selects the function of the lower eight bit pins of port E. Port E includes a bus control signal (AH) and DMAC control signals (DACK1, DACK0, DRAK1, and DRAK0), but in the SH7016 and SH7017, settings in these registers relating to the selection of these pin functions may be invalid in single-chip mode. For details, see table 16.3, Pin Functions in Each Operating Mode. PECR1 and PECR2 are both initialized to H'0000 by external power-on reset but are not initialized for reset by WDT, standby mode, or sleep mode, so the previous data is maintained. Port E Control Register 1 (PECR1): Bit: 15 PE15 MD1 Initial value: R/W: Bit: 0 R/W 7 ⎯ Initial value: R/W: 0 R 14 PE15 MD0 0 R/W 6 ⎯ 0 R 13 PE14 MD1 0 R/W 5 ⎯ 0 R 12 PE14 MD0 0 R/W 4 ⎯ 0 R 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 ⎯ 0 R 9 ⎯ 0 R 1 ⎯ 0 R 8 ⎯ 0 R 0 ⎯ 0 R Bits 15 and 14⎯PE15 Mode 1, 0 (PE15MD1 and PE15MD0): These bits select the function of the PE15/DACK1 pin. Bit 15 PE15MD1 0 Bit 14 PE15MD0 0 1 1 0 1 Description Input/output (PE15) Reserved DMA request received output (DACK1) (PE15 in single-chip mode) Reserved (initial value) Rev.5.00 Sep. 27, 2007 Page 471 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 13 and 12⎯PE14 Mode 1, 0 (PE14MD1 and PE14MD0): These bits select the function of the PE14/DACK0/AH pin. Bit 13 PE14MD1 0 Bit 12 PE14MD0 0 1 1 0 1 Description Input/output (PE14) Reserved DMA request received output (DACK0) (PE14 in single-chip mode) Address hold output (AH) (PE14 in single-chip mode) (initial value) Bits 11 to 0⎯Reserved: These bits always reads as 0. The write values should always be 0. Port E Control Register 2 (PECR2): Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 PE3 MD1 Initial value: R/W: 0 R/W 14 PE7MD 0 R/W 6 PE3 MD0 0 R/W 13 ⎯ 0 R 5 PE2 MD1 0 R/W 12 PE6MD 0 R/W 4 PE2 MD0 0 R/W 11 ⎯ 0 R 3 PE1 MD1 0 R/W 10 PE5MD 0 R/W 2 PE1 MD0 0 R/W 9 ⎯ 0 R 1 PE0 MD1 0 R/W 8 PE4MD 0 R/W 0 PE0 MD0 0 R/W Bit 15⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 14⎯PE7 Mode (PE7MD): Selects the function of the PE7/TIOC2B pin. Bit 14 PE7MD 0 1 Description General input/output (PE7) MTU input capture input/output compare output (TIOC2B) (initial value) Bit 13 ⎯Reserved: This bit always reads as 0. The write value should always be 0. Rev.5.00 Sep. 27, 2007 Page 472 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bit 12⎯PE6 Mode (PE6MD): Selects the function of the PE6/TIOC2A pin. Bit 12 PE6MD 0 1 Description General input/output (PE6) MTU input capture input/output compare output (TIOC2A) (initial value) Bit 11⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 10⎯PE5 Mode (PE5MD): Selects the function of the PE5/TIOC1B pin. Bit 10 PE5MD 0 1 Description General input/output (PE5) MTU input capture input/output compare output (TIOC1B) (initial value) Bit 9⎯Reserved: This bit always reads as 0. The write value should always be 0. Bit 8⎯PE4 Mode (PE4MD): Selects the function of the PE4/TIOC1A pin. Bit 8 PE4MD 0 1 Description General input/output (PE4) MTU input capture input/output compare output (TIOC1A) (initial value) Bits 7 and 6⎯PE3 Mode 1, 0 (PE3MD1 and PE3MD0): These bits select the function of the PE3/TIOC0D/DRAK1 pin. Bit 7 PE3MD1 0 Bit 6 PE3MD0 0 1 1 0 1 Description General input/output (PE3) MTU input capture input/output compare output (TIOC0D) DREQ1 request received output (DRAK1) (PE3 in single-chip mode) Reserved (initial value) Rev.5.00 Sep. 27, 2007 Page 473 of 716 REJ09B0398-0500 16. Pin Function Controller (PFC) Bits 5 and 4⎯PE2 Mode 1, 0 (PE2MD1 and PE2MD0): These bits select the function of the PE2/TIOC0C/DREQ1 pin. Bit 5 PE2MD1 0 Bit 4 PE2MD0 0 1 1 0 1 Description General input/output (PE2) MTU input capture input/output compare output (TIOC0C) DREQ1 request receive input (PE2 in single-chip mode) Reserved (initial value) Bits 3 and 2⎯PE1 Mode 1, 0 (PE1MD1 and PE1MD0): These bits select the function of the PE1/TIOC0B/DRAK0 pin. Bit 3 PE1MD1 0 Bit 2 PE1MD0 0 1 1 0 1 Description General input/output (PE1) MTU input capture input/output compare output (TIOC0B) DREQ0 request received output (DRAK0) (PE1 in single-chip mode) Reserved (initial value) Bits 1 and 0⎯PE0 Mode 1, 0 (PE0MD1 and PE0MD0): These bits select the function of the PE0/TIOC0A/DREQ0 pin. Bit 1 PE0MD1 0 Bit 0 PE0MD0 0 1 1 0 1 Description General input/output (PE0) MTU input capture input/output compare output (TIOC0A) DREQ0 request receive input (PE0 in single-chip mode) Reserved (initial value) Rev.5.00 Sep. 27, 2007 Page 474 of 716 REJ09B0398-0500 17. I/O Ports (I/O) Section 17 I/O Ports (I/O) 17.1 Overview The SH7016 and SH7017 have six ports, A to F, and the SH7014 has four ports, A, B, E, and F. The pins of the ports are multiplexed for use as general-purpose I/Os (the port F pins are general input) or for other functions. Use the pin function controller (PFC) to select the function of multiplexed pins. The ports each have one data register for storing pin data. The initialize function after power-on reset differs depending on the operating mode of each pin. See tables 16.2 and 16.3, Pin Arrangement by Mode, for details. 17.2 Port A Port A is a 16-pin input/output port (11-pin in the SH7014) as shown in table 17.1. Rev.5.00 Sep. 27, 2007 Page 475 of 716 REJ09B0398-0500 17. I/O Ports (I/O) Table 17.1 Port A ROM Disabled Extended Mode (Modes 0, 1) PA15 (I/O)/CK (output) RD (output) WRH (output) WRL (output) CS1 (output) CS0 (output) PA9 (I/O)/TCLKD (input)/IRQ3 (input) PA8 (I/O)/TCLKC (input)/IRQ2 (input) PA7 (I/O)/TCLKB (input)/ CS3 (input) PA6 (I/O)/TCLKA (input)/ CS2 (input) PA5 (I/O)/SCK1 (I/O)/ DREQ1 (input)/IRQ1 (input) PA4 (I/O)/TXD1 (output) PA3 (I/O)/RXD1 (input) PA2 (I/O)/SCK0 (I/O)/ DREQ0 (input)/IRQ0 (input) PA1 (I/O)/TXD0 (output) PA0 (I/O)/RXD0 (input) Note: * ROM Enabled Extended Mode (Mode 2)* PA15 (I/O)/CK (output) PA14 (I/O)/RD (output) PA13 (I/O)/WRH (output) PA12 (I/O)/WRL (output) PA11 (I/O)/CS1 (output) PA10 (I/O)/CS0 (output) PA9 (I/O)/TCLKD (input)/ IRQ3 (input) PA8 (I/O)/TCLKC (input)/ IRQ2 (input) PA7 (I/O)/TCLKB (input)/ CS3 (input) PA6 (I/O)/TCLKA (input)/ CS2 (input) PA5 (I/O)/SCK1 (I/O)/ DREQ1 (input)/IRQ1 (input) PA4 (I/O)/TXD1 (output) PA3 (I/O)/RXD1 (input) PA2 (I/O)/SCK0 (I/O)/ DREQ0 (input)/IRQ0 (input) PA1 (I/O)/TXD0 (output) PA0 (I/O)/RXD0 (input) Single Chip Mode* PA15 (I/O)/CK (output) PA14 (I/O) PA13 (I/O) PA12 (I/O) PA11 (I/O) PA10 (I/O) PA9 (I/O)/TCLKD (input)/IRQ3 (input) PA8 (I/O)/TCLKC (input)/IRQ2 (input) PA7 (I/O)/TCLKB (input) PA6 (I/O)/TCLKA (input) PA5 (I/O)/SCK1 (I/O)/ IRQ1 (input) PA4 (I/O)/TXD1 (output) PA3 (I/O)/RXD1 (input) PA2 (I/O)/SCK0 (I/O)/ IRQ0 (input) PA1 (I/O)/TXD0 (output) PA0 (I/O)/RXD0 (input) SH7016, SH7017 only. 17.2.1 Register Configuration Table 17.2 summarizes the port A register. Table 17.2 Port A Register Name Abbreviation R/W R/W Initial Value H'0000 Address H'FFFF8382 H'FFFF8383 Access Size 8, 16, 32 Port A data register L PADRL Rev.5.00 Sep. 27, 2007 Page 476 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.2.2 Port A Data Register L (PADRL) Bit: 15 14 13 12 11 10 9 PA9DR 0 R/W 1 PA1DR 0 R/W 8 PA8DR 0 R/W 0 PA0DR 0 R/W PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR Initial value: R/W: Bit: 0 R/W 7 PA7DR Initial value: R/W: Note: * 0 R/W 0 R/W* 6 PA6DR 0 R/W 0 R/W* 5 PA5DR 0 R/W 0 R/W* 4 PA4DR 0 R/W 0 R/W* 3 PA3DR 0 R/W 0 R/W* 2 PA2DR 0 R/W R only in the SH7014. PADRL is a 16-bit read/write register that stores data for port A. The bits PA15DR to PA0DR correspond to the PA15/CK to PA0/RXD0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PADRL; when PADRL is read, the register value will be output regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PADRL is read. When a value is written to PADRL, that value can be written into PADRL, but it will not affect the pin status. Table 17.3 shows the read/write operations of the port A data register. PADRL is initialized by an external power-on reset. However, PADRL is not initialized for a reset by WDT, standby mode, or sleep mode. The settings of bits 14 to 10 of this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to bits 14 to 10; these bits are always read as 0, and their write value should always be 0. Table 17.3 Read/Write Operation of the Port A Data Register (PADR) PAIOR Pin Status 0 Ordinary input Other function 1 Ordinary output Other function Read Pin status Pin status PADR value PADR value Write Can write to PADR, but it has no effect on pin status Can write to PADR, but it has no effect on pin status Value written is output by pin Can write to PADR, but it has no effect on pin status Rev.5.00 Sep. 27, 2007 Page 477 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.3 Port B Port B is a 10-pin input/output port (8-pin in the SH7014) as shown in table 17.4. Table 17.4 Port B ROM Disabled Extended Mode (Modes 0, 1) PB9 (I/O)/IRQ7 (input)/ A21 (output) PB8 (I/O)/IRQ6 (input)/ A20 (output)/WAIT (input) PB7 (I/O)/A19 (output) PB6 (I/O)/A18 (output) PB5 (I/O)/IRQ3 (input)/RDWR (output) PB4 (I/O)/IRQ2 (input)/ CASH (output) PB3 (I/O)/IRQ1 (input)/ CASL (output) PB2 (I/O)/IRQ0 (input)/ RAS (output) A17 (output) A16 (output) Note: * ROM Enabled Extended Mode (Mode 2)* PB9 (I/O)/IRQ7 (input)/ A21 (output) PB8 (I/O)/IRQ6 (input)/ A20 (output)/WAIT (input) PB7 (I/O)/A19 (output) PB6 (I/O)/A18 (output) PB5 (I/O)/IRQ3 (input)/ RDWR (output) PB4 (I/O)/IRQ2 (input)/ CASH (output) PB3 (I/O)/IRQ1 (input)/ CASL (output) PB2 (I/O)/IRQ0 (input)/ RAS (output) PB1 (I/O)/A17 (output) PB0 (I/O)/A16 (output) Single Chip Mode* PB9 (I/O)/IRQ7 (input) PB8 (I/O)/IRQ6 (input) PB7 (I/O) PB6 (I/O) PB5 (I/O)/IRQ3 (input) PB4 (I/O)/IRQ2 (input) PB3 (I/O)/IRQ1 (input) PB2 (I/O)/IRQ0 (input) PB1 (I/O) PB0 (I/O) SH7016 and SH7017 only. 17.3.1 Register Configuration Table 17.5 summarizes the port B register. Table 17.5 Port B Register Name Port B data register Abbreviation PBDR R/W R/W Initial Value H'0000 Address H'FFFF8390 H'FFFF8391 Access Size 8, 16, 32 Rev.5.00 Sep. 27, 2007 Page 478 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.3.2 Port B Data Register (PBDR) Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 PB7DR Initial value: R/W: 0 R/W 14 ⎯ 0 R 6 PB6DR 0 R/W 13 ⎯ 0 R 5 PB5DR 0 R/W 12 ⎯ 0 R 4 PB4DR 0 R/W 11 ⎯ 0 R 3 PB3DR 0 R/W 10 ⎯ 0 R 2 PB2DR 0 R/W 9 PB9DR 0 R/W 1 PB1DR 0 R/W* 8 PB8DR 0 R/W 0 PB0DR 0 R/W* Note: * R only in the SH7014. PBDR is a 16-bit read/write register that stores data for port B. The bits PB9DR to PB0DR correspond to the PB9/IRQ7/A21 to PB0/A16 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PBDR; when PBDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PBDR is read. When a value is written to PBDR, that value can be written into PBDR, but it will not affect the pin status. table 17.6 shows the read/write operations of the port B data register. PBDR is initialized by an external power-on reset. However, PBDR is not initialized for a reset by WDT, standby mode, or sleep mode. The settings of bits 1 and 0 of this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. Table 17.6 Read/Write Operation of the Port B Data Register (PBDR) PBIOR 0 Pin Status Ordinary input Other function 1 Ordinary output Other function Read Pin status Pin status PBDR value PBDR value Write Can write to PBDR, but it has no effect on pin status Can write to PBDR, but it has no effect on pin status Value written is output by pin Can write to PBDR, but it has no effect on pin status Rev.5.00 Sep. 27, 2007 Page 479 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.4 Port C ⎯ SH7016, SH7017 ⎯ Port C is a 16 pin input/output port as listed in table 17.7. There is no port C in the SH7014. Table 17.7 Port C ROM Disabled Extended Mode (Modes 0, 1) A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) ROM Enabled Extended Mode (Mode 2) PC15 (I/O)/A15 (output) PC14 (I/O)/A14 (output) PC13 (I/O)/A13 (output) PC12 (I/O)/A12 (output) PC11 (I/O)/A11 (output) PC10 (I/O)/A10 (output) PC9 (I/O)/A9 (output) PC8 (I/O)/A8 (output) PC7 (I/O)/A7 (output) PC6 (I/O)/A6 (output) PC5 (I/O)/A5 (output) PC4 (I/O)/A4 (output) PC3 (I/O)/A3 (output) PC2 (I/O)/A2 (output) PC1 (I/O)/A1 (output) PC0 (I/O)/A0 (output) Single Chip Mode PC15 (I/O) PC14 (I/O) PC13 (I/O) PC12 (I/O) PC11 (I/O) PC10 (I/O) PC9 (I/O) PC8 (I/O) PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) 17.4.1 Register Configuration Table 17.8 summarizes the port C register. Table 17.8 Port C Register Name Port C data register Abbreviation PCDR R/W R/W Initial Value H'0000 Address H'FFFF8392 H'FFFF8393 Access Size 8, 16, 32 Rev.5.00 Sep. 27, 2007 Page 480 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.4.2 Port C Data Register (PCDR) Bit: 15 14 13 12 11 10 9 8 PC8DR 0 R/W 0 PC0DR 0 R/W PC15DR PC14DR PC13DR PC12DR PC11DR PC10DR PC9DR Initial value: R/W: Bit: 0 R/W 7 PC7DR Initial value: R/W: 0 R/W 0 R/W 6 PC6DR 0 R/W 0 R/W 5 PC5DR 0 R/W 0 R/W 4 PC4DR 0 R/W 0 R/W 3 PC3DR 0 R/W 0 R/W 2 PC2DR 0 R/W 0 R/W 1 PC1DR 0 R/W PCDR is a 16-bit read/write register that stores data for port C. The bits PC15DR to PC0DR correspond to the PC15/A15 to PC0/A0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PCDR; when PCDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PCDR is read. When a value is written to PCDR, that value can be written into PCDR, but it will not affect the pin status. Table 17.9 shows the read/write operations of the port C data register. PCDR is initialized by an external power-on reset. However, PCDR is not initialized for a reset by WDT, standby mode, or sleep mode. The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to this register, and it should not be read or written to. Table 17.9 Read/Write Operation of the Port C Data Register (PCDR) PCIOR 0 Pin Status Ordinary input Other function 1 Ordinary output Other function Read Pin status Pin status PCDR value PCDR value Write Can write to PCDR, but it has no effect on pin status Can write to PCDR, but it has no effect on pin status Value written is output by pin Can write to PCDR, but it has no effect on pin status Rev.5.00 Sep. 27, 2007 Page 481 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.5 Port D ⎯ SH7016, SH7017 ⎯ Port D is a 16-pin input/output port, as shown in table 17.10. There is no port D in the SH7014. Table 17.10 Port D Extended Mode Without ROM (Mode 0) D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Extended Mode Without ROM (Mode 1) D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Extended Mode With ROM (Mode 2) PD15 (I/O)/D15 (I/O) PD14 (I/O)/D14 (I/O) PD13 (I/O)/D13 (I/O) PD12 (I/O)/D12 (I/O) PD11 (I/O)/D11 (I/O) PD10 (I/O)/D10 (I/O) PD9 (I/O)/D9 (I/O) PD8 (I/O)/D8 (I/O) PD7 (I/O)/D7 (I/O) PD6 (I/O)/D6 (I/O) PD5 (I/O)/D5 (I/O) PD4 (I/O)/D4 (I/O) PD3 (I/O)/D3 (I/O) PD2 (I/O)/D2 (I/O) PD1 (I/O)/D1 (I/O) PD0 (I/O)/D0 (I/O) Single Chip Mode PD15 (I/O) PD14 (I/O) PD13 (I/O) PD12 (I/O) PD11 (I/O) PD10 (I/O) PD9 (I/O) PD8 (I/O) PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) 17.5.1 Register Configuration Table 17.11 summarizes the port D register. Table 17.11 Port D Register Name Abbreviation R/W R/W Initial Value H'0000 Address H'FFFF83A2 H'FFFF83A3 Access Size 8, 16, 32 Port D data register L PDDRL Rev.5.00 Sep. 27, 2007 Page 482 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.5.2 Port D Data Register L (PDDRL) Bit: 15 14 13 12 11 10 9 8 PD8DR 0 R/W 0 PD0DR 0 R/W PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR Initial value: R/W: Bit: 0 R/W 7 PD7DR Initial value: R/W: 0 R/W 0 R/W 6 PD6DR 0 R/W 0 R/W 5 PD5DR 0 R/W 0 R/W 4 PD4DR 0 R/W 0 R/W 3 PD3DR 0 R/W 0 R/W 2 PD2DR 0 R/W 0 R/W 1 PD1DR 0 R/W PDDRL is a 16-bit read/write register that stores data for port D. The bits PD15DR to PD0DR correspond to the PD15/D15 to PD0/D0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PDDRL; when PDDRL is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PDDRL is read. When a value is written to PDDRL, that value can be written into PDDRL, but it will not affect the pin status. Table 17.12 shows the read/write operations of the port D data register. PDDRL is initialized by an external power-on reset. However, PDDRL is not initialized for a reset by WDT, standby mode, or sleep mode. The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there are no pins corresponding to this register, and it should not be read or written to. Table 17.12 Read/Write Operation of the Port D Data Register (PDDR) PDIOR 0 Pin Status Ordinary input Other function 1 Ordinary output Other function Read Pin status Pin status PDDR value PDDR value Write Can write to PDDR, but it has no effect on pin status Can write to PDDR, but it has no effect on pin status Value written is output by pin Can write to PDDR, but it has no effect on pin status Rev.5.00 Sep. 27, 2007 Page 483 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.6 Port E Port E is a 16-pin input/output port, as listed in table 17.13. Table 17.13 Port E Extended Modes (Modes 0, 1, 2)* PE15 (I/O)/ DACK1 (output) PE14 (I/O)/DACK0 (output)/AH (output) PE13 (I/O) PE12 (I/O) PE11 (I/O) PE10 (I/O) PE9 (I/O) PE8 (I/O) PE7 (I/O)/TIOC2B (I/O) PE6 (I/O)/TIOC2A (I/O) PE5 (I/O)/TIOC1B (I/O) PE4 (I/O)/TIOC1A (I/O) PE3 (I/O)/TIOC0D (I/O)/DRAK1 (output) PE2 (I/O)/TIOC0C (I/O)/DREQ1 (input) PE1 (I/O)/TIOC0B (I/O)/DRAK0 (output) PE0 (I/O)/TIOC0A (I/O)/DREQ0 (input) Notes: 1. Modes 0 and 1 only in the SH7014. 2. SH7016 and SH7017 only. 1 Single Chip Mode* PE15 (I/O) PE14 (I/O) PE13 (I/O) PE12 (I/O) PE11 (I/O) PE10 (I/O) PE9 (I/O) PE8 (I/O) 2 PE7 (I/O)/TIOC2B (I/O) PE6 (I/O)/TIOC2A (I/O) PE5 (I/O)/TIOC1B (I/O) PE4 (I/O)/TIOC1A (I/O) PE3 (I/O)/TIOC0D (I/O) PE2 (I/O)/TIOC0C (I/O) PE1 (I/O)/TIOC0B (I/O) PE0 (I/O)/TIOC0A (I/O) 17.6.1 Register Configuration Table 17.14 summarizes the port E register. Table 17.14 Port E Register Name Port E data register Abbreviation PEDR R/W R/W Initial Value H'0000 Address H'FFFF83B0 H'FFFF83B1 Access Size 8, 16, 32 Rev.5.00 Sep. 27, 2007 Page 484 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.6.2 Port E Data Register (PEDR) Bit: 15 14 13 12 11 10 9 8 PE8DR 0 R/W 0 PE0DR 0 R/W PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR Initial value: R/W: Bit: 0 R/W 7 PE7DR Initial value: R/W: 0 R/W 0 R/W 6 PE6DR 0 R/W 0 R/W 5 PE5DR 0 R/W 0 R/W 4 PE4DR 0 R/W 0 R/W 3 PE3DR 0 R/W 0 R/W 2 PE2DR 0 R/W 0 R/W 1 PE1DR 0 R/W PEDR is a 16-bit read/write register that stores data for port E. The bits PE15DR to PE0DR correspond to the PE15/DACK1 to PE0/TIOC0A/DREQ0 pins. When the pins are used as ordinary outputs, they will output whatever value is written in the PEDR; when PEDR is read, the register value will be read regardless of the pin status. When the pins are used as ordinary inputs, the pin status rather than the register value is read directly when PEDR is read. When a value is written to PEDR, that value can be written into PEDR, but it will not affect the pin status. Table 17.15 shows the read/write operations of the port E data register. PEDR is initialized by a external power-on reset. However, PEDR is not initialized for a reset by WDT, standby mode, or sleep mode, so the previous data is retained. Table 17.15 Read/Write Operation of the Port E Data Register (PEDR) PEIOR 0 Pin Status Ordinary input Other function 1 Ordinary output Other function Read Pin status Pin status PEDR value PEDR value Write Can write to PEDR, but it has no effect on pin status Can write to PEDR, but it has no effect on pin status Value written is output by pin Can write to PEDR, but it has no effect on pin status Rev.5.00 Sep. 27, 2007 Page 485 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.7 Port F Port F is an 8-pin input port. All modes are configured in the following way: • PF7 (input)/AN7 (input) • PF6 (input)/AN6 (input) • PF5 (input)/AN5 (input) • PF4 (input)/AN4 (input) • PF3 (input)/AN3 (input) • PF2 (input)/AN2 (input) • PF1 (input)/AN1 (input) • PF0 (input)/AN0 (input) 17.7.1 Register Configuration Table 17.16 summarizes the port F register. Table 17.16 Port F Register Name Port F data register Abbreviation PFDR R/W R Initial Value External pin dependent Address H'FFFF83B3 Access Size 8 Rev.5.00 Sep. 27, 2007 Page 486 of 716 REJ09B0398-0500 17. I/O Ports (I/O) 17.7.2 Port F Data Register (PFDR) Bit: 7 PF7DR Initial value: R/W: * R 6 PF6DR * R 5 PF5DR * R 4 PF4DR * R 3 PF3DR * R 2 PF2DR * R 1 PF1DR * R 0 PF0DR * R Note: * Initial values are dependent on the status of the pins at the time of the reads. PFDR is an 8-bit read-only register that stores data for port F. The bits PF7DR to PF0DR correspond to the PF7/AN7 to PF0/AN0 pins. Any value written into these bits is ignored, and there is no effect on the status of the pins. When any of the bits are read, the pin status rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read out. Table 17.17 shows the read/write operations of the port F data register. PFDR is not initialized by power-on resets, standby mode, or sleep mode (the bits always reflect the pin status). Table 17.17 Read/Write Operation of the Port F Data Register (PFDR) Pin I/O Input Pin Function Ordinary ANn: analog input Note: n = 7 to 0 Read Pin status is read 1 is read Write Ignored (no effect on pin status) Ignored (no effect on pin status) Rev.5.00 Sep. 27, 2007 Page 487 of 716 REJ09B0398-0500 17. I/O Ports (I/O) Rev.5.00 Sep. 27, 2007 Page 488 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Section 18 128 kB Flash Memory (F-ZTAT) 18.1 Features The SH7017 has 128 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Block erase (in single-block units) can be performed. Erasing the entire memory requires erasure of each block in turn. Block erasing can be performed as required on 1 kB, 28 kB, and 32 kB blocks. • Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 μs (typ.) per byte, and the erase time is 100 ms (typ.) per block. • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: ⎯ Boot mode ⎯ User program mode • Automatic bit rate adjustment With data transfer in boot mode, the SH7017's bit rate can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. • Protect modes There are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Rev.5.00 Sep. 27, 2007 Page 489 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.2 18.2.1 Overview Block Diagram Internal address bus Internal data bus (32 bits) Module bus FLMCR1 FLMCR2 EBR1 RAMER Bus interface/controller Operating mode FWP pin Mode pin Flash memory (128 kB) Legend: FLMCR1: FLMCR2: EBR1: RAMER: Flash memory control register 1 Flash memory control register 2 Erase block register 1 RAM emulation register Figure 18.1 Block Diagram of Flash Memory Rev.5.00 Sep. 27, 2007 Page 490 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.2.2 Mode Transitions When the mode pins and the FWP pin are set in the reset state and a reset-start is executed, the SH7017 enters one of the operating modes shown in figure 18.2. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. MD1 = 1, FWP = 1 Reset state *1 User mode RES = 0 RES = 0 MD1 = 1, FWP = 0 RES = 0 MD1 = 0, FWP = 0 RES = 0 *2 FWP = 0 FWP = 1 Programmer mode User program mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 1, MD1 = 0, MD2 = 1, MD3 = 1 Figure 18.2 Flash Memory Mode Transitions Rev.5.00 Sep. 27, 2007 Page 491 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.2.3 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the SH7050 (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program SH7017 Boot program Flash memory RAM SCI1 SH7017 Boot program Flash memory New application program SCI1 RAM Boot program area Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program SH7017 Boot program Flash memory RAM Boot program area Flash memory erase Programming control program SH7017 SCI1 Boot program Flash memory RAM Boot program area New application program Programming control program SCI1 Program execution state Figure 18.3 Boot Mode Rev.5.00 Sep. 27, 2007 Page 492 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) User Program Mode 1. Initial state The FWP assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program SH7017 Boot program Flash memory FWP assessment program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host New application program SH7017 SCI RAM Boot program Flash memory FWP assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program SH7017 Boot program Flash memory FWP assessment program SH7017 SCI RAM Boot program Flash memory FWP assessment program SCI RAM Transfer program Programming/ erase control program Programming/ erase control program Flash memory erase New application program Program execution state Figure 18.4 User Program Mode Rev.5.00 Sep. 27, 2007 Page 493 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. • User Mode • User Program Mode SCI Flash memory RAM Application program Execution state Overlap RAM (emulation is performed on data written in RAM) Emulation block Figure 18.5 Emulation When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev.5.00 Sep. 27, 2007 Page 494 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) • User Program Mode SCI Flash memory RAM Programming control program execution state Application program Overlap RAM (programming data) Programming data Figure 18.6 Programming to the Flash Memory 18.2.5 Differences between Boot Mode and User Program Mode Table 18.1 Differences between Boot Mode and User Program Mode Boot Mode Entire memory erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev.5.00 Sep. 27, 2007 Page 495 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.2.6 Block Configuration The flash memory is divided into three 32 kB blocks, one 28 kB blocks, and four 1 kB blocks. Address H'00000 32 kB 32 kB 128 kB 32 kB 28 kB 1 kB 1 kB 1 kB 1 kB Address H'1FFFF Figure 18.7 Block Configuration 18.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Flash Memory Pins Pin Name Power-on reset Flash memory protect Mode 3 Mode 2 Mode 1 Mode 0 Transmit data Receive data Abbreviation RES FWP MD3 MD2 MD1 MD0 TxD1 RxD1 I/O Input Input Input Input Input Input Output Input Function Power-on reset Flash program/erase protection by hardware Sets SH7017 operating mode Sets SH7017 operating mode Sets SH7017 operating mode Sets SH7017 operating mode Serial transmit data output Serial receive data input Rev.5.00 Sep. 27, 2007 Page 496 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 18.3. Table 18.3 Flash Memory Registers Register Name Flash memory control register 1 Flash memory control register 2 Erase block register 1 RAM emulation register Abbreviation FLMCR1 FLMCR2 EBR1 RAMER R/W R/W* R* 2 1 Initial Value H'00* H'00 1 3 Address H'FFFF8580 H'FFFF8581 Access Size 8 8 8 8, 16, 32 R/W* R/W H'00* 4 H'FFFF8582 H'FFFF8628 H'0000 Notes: FLMCR1, FLMCR2, and EBR1 are 8-bit registers, and RAMER is a 16-bit register. Only byte accesses are valid for FLMCR1, FLMCR2, and EBR1, the access requiring 3 cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a longword access. When a longword write is performed on RAMER, 0 must always be written to the lower word (address H'FFFF8630). Operation is not guaranteed if any other value is written. 1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1. 2. A read in a mode in which on-chip flash memory is disabled will return H'00. 3. When a low level is input to the FWP pin, the initial value is H'80. 4. When a high level is input to the FWP pin, or if a low level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. Rev.5.00 Sep. 27, 2007 Page 497 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.5 18.5.1 Register Descriptions Flash Memory Control Register 1 (FLMCR1) Bit: 7 FWE Initial value: R/W: 1/0 R 6 SWE 0 R/W 5 ESU 0 R/W 4 PSU 0 R/W 3 EV 0 R/W 2 PV 0 R/W 1 E 0 R/W 0 P 0 R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to bits SWE, ESU, PSU, EV, and PV are enabled only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7⎯Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWP pin (hardware-protected state) When a high level is input to the FWP pin (Initial value) Rev.5.00 Sep. 27, 2007 Page 498 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Bit 6⎯Software Write Enable Bit (SWE): Enables or disables the flash memory. This bit should be set before setting bits 5 to 0, and EBR1 bits 7 to 0. Bit 6 SWE 0 1 Description Writes disabled Writes enabled [Setting condition] When FWE = 1 (Initial value) Bit 5⎯Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 4⎯Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Rev.5.00 Sep. 27, 2007 Page 499 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Bit 3⎯Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 2⎯Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 (Initial value) Bit 1⎯Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Rev.5.00 Sep. 27, 2007 Page 500 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Bit 0⎯Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 (Initial value) 18.5.2 Flash Memory Control Register 2 (FLMCR2) Bit: 7 FLER Initial value: R/W: 0 R 6 ⎯ 0 R 5 ⎯ 0 R 4 ⎯ 0 R 3 ⎯ 0 R 2 ⎯ 0 R 1 ⎯ 0 R 0 ⎯ 0 R FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection). FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit 7⎯Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER 0 Description Flash memory is operating normally. Flash memory program/erase protection (error protection) is disabled. [Clearing condition] Power-on reset 1 An error has occurred during flash memory programming/erasing. Flash memory program/erase protection (error protection) is enabled. [Setting condition] See section 18.8.3, Error Protection. (Initial value) Bits 6 to 0⎯Reserved: These bits are always read as 0. Rev.5.00 Sep. 27, 2007 Page 501 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit readable/writable register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 (more than one bit cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 18.4. Bit: 7 EB7 Initial value: R/W: 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Table 18.4 Flash Memory Erase Blocks Block (Size) EB0 (32 kB) EB1 (32 kB) EB2 (32 kB) EB3 (28 kB) EB4 (1 kB) EB5 (1 kB) EB6 (1 kB) EB7 (1 kB) Address H'000000 to H'007FFF H'008000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01EFFF H'01F000 to H'01F3FF H'01F400 to H'01F7FF H'01F800 to H'01FBFF H'01FC00 to H'01FFFF Rev.5.00 Sep. 27, 2007 Page 502 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.5.4 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER is initialized to H'0000 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 18.5. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: 15 ⎯ Initial value: R/W: Bit: 0 R 7 ⎯ Initial value: R/W: 0 R 14 ⎯ 0 R 6 ⎯ 0 R 13 ⎯ 0 R 5 ⎯ 0 R 12 ⎯ 0 R 4 ⎯ 0 R 11 ⎯ 0 R 3 ⎯ 0 R 10 ⎯ 0 R 2 RAMS 0 R/W 9 ⎯ 0 R 1 RAM1 0 R/W 8 ⎯ 0 R 0 RAM0 0 R/W Bits 15 to 3⎯Reserved: These bits are always read as 0. Bit 2⎯RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 2 RAMS 0 1 Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled (Initial value) Bits 1 and 0⎯Flash Memory Area Selection (RAM1, RAM0): These bits are used together with bit 2 to select the flash memory area to be overlapped with RAM. (See table 18.5.) Rev.5.00 Sep. 27, 2007 Page 503 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Table 18.5 Flash Memory Area Divisions Addresses H'FFF800 to H'FFFBFF H'01F000 to H'01F3FF H'01F400 to H'01F7FF H'01F800 to H'01FBFF H'01FC00 to H'01FFFF Legend: *: Don't care Block Name RAM area 1 kB EB4 (1 kB) EB5 (1 kB) EB6 (1 kB) EB7 (1 kB) RAMS 0 1 1 1 1 RAM1 * 0 0 1 1 RAM0 * 0 1 0 1 18.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 18.6. For a diagram of the transitions to the various flash memory modes, see figure 18.2. Table 18.6 Setting On-Board Programming Modes Mode Boot mode Expanded mode Single chip mode Expanded mode Single chip mode Expanded mode Single chip mode User program mode Expanded mode Single chip mode Expanded mode Single chip mode Expanded mode Single chip mode ×4 ×2 ×1 0 ×4 ×2 PLL Multiple ×1 FWP 0 MD3 0 0 0 0 1 1 0 0 0 0 1 1 MD2 0 0 1 1 0 0 0 0 1 1 0 0 MD1 0 0 0 0 0 0 1 1 1 1 1 1 MD0 0 1 0 1 0 1 0 1 0 1 0 1 Rev.5.00 Sep. 27, 2007 Page 504 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI to be used is set to channel asynchronous mode. When a reset-start is executed after the SH7017 pins have been set to boot mode, the boot program built into the SH7017 is started and the programming control program prepared in the host is serially transmitted to the SH7017 via the SCI. In the SH7017, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 18.8, and the boot mode execution procedure in figure 18.9. SH7017 Flash memory Host Write data reception Verify data transmission RXD1 SCI1 TXD1 On-chip RAM Figure 18.8 System Configuration in Boot Mode Rev.5.00 Sep. 27, 2007 Page 505 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate SH7017 measures low period of H'00 data transmitted by host SH7017 calculates bit rate and sets value in bit rate register After bit rate adjustment, SH7017 transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, SH7017 transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte SH7017 transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units SH7017 transmits received programming control program to host as verify data (echo-back) Transfer received programming control program to on-chip RAM No Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, SH7017 transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM n+1→n n = N? Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 18.9 Boot Mode Execution Procedure Rev.5.00 Sep. 27, 2007 Page 506 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Automatic SCI Bit Rate Adjustment Start bit Stop bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 18.10 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the SH7017 measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7017 calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the SH7017. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the SH7017's system clock frequency, there will be a discrepancy between the bit rates of the host and the SH7017. To ensure correct SCI operation, the host's transfer bit rate should be set to 4800bps, 9600bps. Table 18.7 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the SH7017 bit rate is possible. The boot program should be executed within this system clock range. Table 18.7 System Clock Frequencies for which Automatic Adjustment of SH7017 Bit Rate is Possible Host Bit Rate 9600bps 4800bps System Clock Frequency for which Automatic Adjustment of SH7017 Bit Rate is Possible 8 to 28.7MHz 4 to 20MHz Rev.5.00 Sep. 27, 2007 Page 507 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 18.11. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFFFF000 Programming control program area (2 kbytes) H'FFFFF800 Boot program area (2 kbytes) H'FFFFFFFF Figure 18.11 RAM Areas in Boot Mode Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Rev.5.00 Sep. 27, 2007 Page 508 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.6.2 User Program Mode After setting FWP, the user should branch to, and execute, the previously prepared programming/erase control program. As the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip RAM or external memory. Use the following procedure (figure 18.12) to execute the programming control program that writes to flash memory (when transferred to RAM). Write FWP assessment program and transfer program 1 2 FWP = 1 (user program mode) 3 Transfer programming/erase control program to RAM 4 Execute programming/ erase control program in RAM (flash memory rewriting) 5 Execute user application program Figure 18.12 User Program Mode Execution Procedure Note: When programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. Memory cells may not operate normally if overprogrammed or overerased due to program runaway. Rev.5.00 Sep. 27, 2007 Page 509 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program (programming control program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, a low level is input to the FWP pin (programming/erasing will not be executed if a high level is input to the FWP pin). 3. Programming should be performed in the erased state. Do not perform additional programming on previously programmed addresses. 18.7.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 18.7 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. Following the elapse of 10 μs or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0). Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a minimum value of 300 μs or more as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of 50 μs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Use a fixed 200 μs pulse for the write time. Rev.5.00 Sep. 27, 2007 Page 510 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) 18.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSUn bit is cleared at least 10 μs later). The watchdog timer is cleared after the elapse of 10 μs or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of 4 μs or more. When the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. Wait at least 2 μs after the dummy write before performing this read operation. Next, the written data is compared with the verify data, and reprogram data is computed (see figure 18.13) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least 4 μs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than 1000 times on the same bits. Rev.5.00 Sep. 27, 2007 Page 511 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) Start Set SWE-bit of FLMCR1 Wait 10 μs Store 32 bytes write data in write data area and rewrite data area n=1 m=0 Successively write 32-byte data in rewrite data area in RAM to flash memory *1 *5 Data writes must be performed in the memoryerased state. Do not write additional data to an address to which data is already written. *4 Enable WDT Set PSU bit in FLMCR1(2) Wait 50 μs Set PSU bit in FLMCR1(2) Wait 200 μs Set PSU bit in FLMCR1(2) Wait 10 μs Set PSU bit in FLMCR1(2) Wait 10 μs Disable WDT Set PSU bit in FLMCR1(2) Wait 4 μs Perform dummy-write of H'FF to verify address Wait 2 μs Read verify data Increment address *3 *5 *2 *5 *5 *5 Write start *5 Write end *5 n←n+1 Write data = Verify data? OK Operate rewrite data Transfer rewrite data to rewrite data area 32 byte data verify complete? OK Set PSU bit in FLMCR1(2) RAM Write data storage area (32 byte) Wait 4 μs m = 0? OK Clear SWE bit of FLMCR1 Write end NG m=1 *3 *4 NG *5 NG *5 n ≥ 1000? OK Clear SWE bit of FLMCR1 Write failure NG Rewrite data storage area (32 byte) Notes: 1. Transfer data in a byte unit. The lower eight bits of the start address to which data is written must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Transfer 32-byte data even when writing fewer than 32 bytes. In this case, Set H'FF in unused addresses. 2. Read verify data in logword form (32 bits). 3. Already programmed bits are not reprogrammed. Reprogram data is determined by the computation shown below. 4. The write data storage area (32 bytes) and rewrite data storage area (32 bytes) must be located in RAM. The contents of the rewrite data storage area are rewritten as writing progresses. 5. Set the values of x, y, z, α, β, γ, ε, η, and N to match the characteristics of the memory device. Previous write data 0 0 1 1 Verify data (V) Rewrite data (X) 0 1 1 0 0 1 1 1 Description Rewrite should not be performed to bits already written to. Write is incomplete; rewrite should be performed. ⎯ Left in the erased state. Figure 18.13 Program/Program-Verify Flowchart Rev.5.00 Sep. 27, 2007 Page 512 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) • Sample 32-byte programming program The wait time set values (number of loops) are for the case where f = 28.7 MHz. For other frequencies, the set value is given by the following expression: Wait time (μs) × f (MHz) ÷ 4 Registers Used R4 (input): R5 (input): R7 (output): R0 to R3, R8 to R13: FLMCR1 FLMCR2 OK NG Wait10u Wait50u Wait4u Wait2u Wait200u WDT_TCSR WDT_573u SWESET PSU1SET P1SET P1CLEAR PSU1CLEAR PVSET PVCLEAR SWECLEAR MAXVerify ; FlashProgram MOV MOV.L MOV MOV COPY_LOOP .EQU #H'01,R2 #PdataBuff,R0 R4,R12 #8,R13 .EQU $ Rev.5.00 Sep. 27, 2007 Page 513 of 716 REJ09B0398-0500 $ ; R2 work register (1) ; Save program data to work area Program data storage address Programming destination address OK (normal) or NG (error) Work registers .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU H'80 H'81 H'0 H'1 72 359 29 14 1435 H'FFFF8610 H'A579 B'01000000 B'00010000 B'00000001 B'11111110 B'11101111 B'00000100 B'11111011 B'10111111 1000 18. 128 kB Flash Memory (F-ZTAT) MOV.L MOV.L ADD.L ADD.L CMP/PL BT MOV.L LDC ; MOV.L MOV.L OR.B Wait_1 ; MOV.L CMP/GT BT MOV.L Program_Start MOV.L ; Program_loop MOV.L MOV.L MOV.L MOV.L Write_Loop MOV.B MOV.B ADD.L ADD.L CMP/PL BT ; MOV.L MOV.W MOV.W #WDT_TCSR,R1 #WDT_573u,R3 R3,@R1 ; Enable WDT ; 573.4 μs cycle .EQU #0,R10 #32,R3 #PdataBuff,R12 R5,R13 .EQU @R12+,R1 R1,@R13 #1,R13 #-1,R3 R3 Write_Loop $ $ ; Initialize m (R10) to 0 ; Write 32-byte data consecutively #H'20000,R9 R5,R9 Program_Start #FLMCR2,R0 .EQU #0,R9 $ ; Initialize n (R9) to 0 SUBC BF #Wait10u,R3 #FLMCR1,R0 #SWESET,@(R0,GBR) R2,R3 Wait_1 ; Initialize R0 to FLCMR1 address ; Set SWE ; Wait 10 μs @R12+,R1 R1,@R0 #4,R0 #-1,R13 R13 COPY_LOOP #H'FFFF8500,R0 R0,GBR ; Initialize GBR Rev.5.00 Sep. 27, 2007 Page 514 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) ; MOV.L OR.B Wait_2 ; MOV.L OR.B Wait_3 ; MOV.L AND.B Wait_4 ; MOV.L AND.B Wait_5 ; MOV.L MOV.W MOV.W ; MOV.L OR.B Wait_6 ; MOV.L MOV.L MOV.L MOV.L MOV.L ; VerifyLoop MOV.L .EQU R11,@R12 $ ; Write H'FF to verify address Rev.5.00 Sep. 27, 2007 Page 515 of 716 REJ09B0398-0500 PdataBuff,R3 R4,R1 R5,R12 #8,R13 #H'FFFFFFFF,R11 SUBC BF #Wait4u,R3 #PVSET,@(R0,GBR) R2,R3 Wait_6 ; Set PV ; Wait 4 μs #WDT_TCSR,R1 #H'A55F,R3 R3,@R1 ; Disable WDT SUBC BF #Wait10u,R3 #PSU1CLEAR,@(R0,GBR) ; Clear PSU R2,R3 Wait_5 ; Wait 10 μs SUBC BF #Wait10u,R3 #P1CLEAR,@(R0,GBR) R2,R3 Wait_4 ; Clear P ; Wait 10 μs SUBC BF #Wait200u,R3 #P1SET,@(R0,GBR) R2,R3 Wait_3 ; Set P ; Wait 200 μs SUBC BF #Wait50u,R3 #PSU1SET,@(R0,GBR) R2,R3 Wait_2 ; Set PSU ; Wait 50 μs 18. 128 kB Flash Memory (F-ZTAT) MOV.L MOV.L Wait_7 ; MOV.L MOV.L CMP/EQ BT MOV.L XOR NOT OR MOV.L Verify_OK ADD.L ADD.L CMP/PL BT ; MOV.L AND.B Wait_8 ; CMP/PL BF ADD MOV.L MOV.L CMP/EQ BT BRA NOP Program_OK MOV.L Program_end MOV.B .EQU #OK,R7 .EQU #H'00,R0 $ $ ; R7 R6 @(6,R5),R0 R0,@(EBR1,GBR) @(7,R5),R0 R0,@(EBR2,GBR) ; Erase memory block (EBR2) setting ; Erase memory block (EBR1) setting #0,R9 ; Initialize n (R9) to 0 #Wait10u,R3 #FLMCR1,R0 #SWESET,@(R0,GBR) R2,R3 EWait_1 ; Set SWE ; Wait 10 μs 18. 128 kB Flash Memory (F-ZTAT) EWait_4 SUBC BF ; MOV.L AND.B EWait_5 SUBC BF ; MOV.L MOV.W MOV.W ; MOV.L OR.B EWait_6 SUBC BF ; MOV.L BlockVerify_1 MOV.L MOV.L MOV.L EWait_7 SUBC BF ; MOV.L CMP/EQ BF MOV.L CMP/EQ BF MOV.L AND.B EWait_8 SUBC BF ; MOV.L BRA #OK,R7 FlashErase_end ; R7 R6 ; Erase-verify #Wait20u,R3 #EVSET,@(R0,GBR) R2,R3 EWait_6 ; Set EV ; Wait 20 μs #WDT_TCSR,R1 #H'A55F,R3 R3,@R1 ; Disable WDT #Wait10u,R3 #ESUCLEAR,@(R0,GBR) ; Clear ESU R2,R3 EWait_5 ; Wait 10 μs R2,R3 EWait_4 ; Wait 10 μs Rev.5.00 Sep. 27, 2007 Page 522 of 716 REJ09B0398-0500 18. 128 kB Flash Memory (F-ZTAT) NOP ; BlockVerify_NG ADD.L MOV.L AND.B EWait_9 SUBC BF MOV.L CMP/EQ BF MOV.L FlashErase_end MOV.L AND.B ; RTS NOP ; ; Memory block table .ALIGN Flash_BlockData EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 EB8 EB9 EB10 EB11 Dummy Memory block start address: EBR value 4 .EQU $ .EQU #1,R9 #Wait5u,R3 #EVCLEAR,@(R0,GBR) R2,R3 EWait_9 #MAXErase,R7 R7,R9 EraseLoop #NG,R7 .EQU $ #FLMCR1,R0 #SWECLEAR,@(R0,GBR) ; Clear SWE ; R7 MAXErase then erase NG ; Clear EV ; Wait 5 μs $ ; Verify NG, n 50°C f = 28 MHz f = 28 MHz Ta ≤ 50°C Ta > 50°C IOH = −200 μA IOH = −1 mA IOL = 1.6 mA Vin = 0 V, f = 1 MHz, Ta = 25°C Item Pin Symbol Min Typ ⎯ ⎯ ⎯ ⎯ ⎯ 130 100 0.01 ⎯ 140 110 0.01 ⎯ 13 Max ⎯ ⎯ 0.4 80 50 20 180 150 5 20 180 150 5 20 22 Output high- All output pins VOH level voltage Output low- All output pins VOL level voltage Input RES capacitance NMI All other input pins Current Ordinary consumption operation (SH7014) Sleep Standby ICC Cin VCC −0.5 ⎯ 3.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Current Ordinary consumption operation (SH7016, Sleep SH7017) Standby ICC Analog supply current (SH7014) Analog supply current (SH7016, SH7017) RAM standby voltage AICC AICC ⎯ 5 10 mA VRAM 2.0 ⎯ ⎯ V Notes: 1. When the A/D converter is not used (including during standby), do not release the AVCC and AVSS pins. Connect the AVCC pin to VCC and the AVSS pin to VSS. 2. The current consumption is measured when VIHmin = VCC −0.5 V, VIL max = 0.5 V, with all output pins unloaded. 3. The F-ZTAT and mask versions have the same functions, and the electrical characteristics of both are within specification, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. Caution is therefore required in carrying out system design, and when switching between F-ZTAT and mask versions. Rev.5.00 Sep. 27, 2007 Page 561 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Table 22.3 Permitted Output Current Values Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75° C Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL ∑ IOL −IOH ∑ (−IOH) Min ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ Max 2.0 80 2.0 25 Unit mA mA mA mA Note: To assure LSI reliability, do not exceed the output values listed in this table. 22.3 22.3.1 AC Characteristics Clock Timing Table 22.4 Clock Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75° C Item Operating frequency Clock cycle time Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock low-level input pulse width Symbol fOP tcyc tCL tCH tCR tCF fEX tEXcyc tEXL tEXR tEXF tOSC1 tOSC2 Min 4 34.8 10 10 ⎯ ⎯ 4 100 40 40 ⎯ ⎯ 10 10 Max 28.7 250 ⎯ ⎯ 5 5 10 250 ⎯ ⎯ 5 5 ⎯ ⎯ Unit MHz ns ns ns ns ns MHz ns ns ns ns ns ms ms 22.3 22.2 Figures 22.1 EXTAL clock high-level input pulse width tEXH EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby return clock settling time Rev.5.00 Sep. 27, 2007 Page 562 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) tcyc tCH tCL CK 1/2 VCC tCF 1/2 VCC tCR Figure 22.1 System Clock Timing TEXcyc TEXH EXTAL 1/2 VCC VIH VIH VIL TEXF VIL TEXL VIH 1/2 VCC TEXR Figure 22.2 EXTAL Clock Input Timing CK VCC VCC min tOSC1 tOSC2 RES Figure 22.3 Oscillation Settling Time Rev.5.00 Sep. 27, 2007 Page 563 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.2 Control Signal Timing Table 22.5 Control Signal Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75° C Item RES rise/fall RES pulse width NMI rise/fall RES setup time* NMI setup time* IRQ7, IRQ6, IRQ3 to IRQ0 setup time (edge detection)* IRQ7, IRQ6, IRQ3 to IRQ0 setup time (level detection)* NMI hold time IRQ7, IRQ6, IRQ3 to IRQ0 hold time Note: * Symbol tRESr, tRESf tRESW tNMIr, tNMIf tRESS tNMIS tIRQES tIRQLS tNMIH tIRQEH Min ⎯ 20 ⎯ 35 35 35 35 35 35 Max 200 ⎯ 200 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns tcyc ns ns ns ns ns ns ns 22.5 22.4, 22.5 Figure 22.4 The RES, NMI, IRQ7, IRQ6, and IRQ3 to IRQ0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have produced changes at clock rise (for RES) or clock fall (for NMI, IRQ7, IRQ6, and IRQ3 to IRQ0). If the setup times are not provided, recognition is delayed until the next clock rise or fall. Rev.5.00 Sep. 27, 2007 Page 564 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) CK tRESf tRESS RES VIH VIL tRESW VIL tRESr tRESS VIH Figure 22.4 Reset Input Timing CK tNMIH tNMIS VIH VIL NMI tIRQEH IRQ edge tIRQES VIH VIL tIRQLS IRQ level Figure 22.5 Interrupt Signal Input Timing Rev.5.00 Sep. 27, 2007 Page 565 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.3 Bus Timing Table 22.6 Bus Timing Conditions: VCC = 5.0 V ±10%, AVCC = VCC ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item Address delay time CS delay time 1 CS delay time 2 Read strobe delay time 1 Read strobe delay time 2 Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write data delay time Write data hold time WAIT setup time WAIT hold time RAS delay time 1 RAS delay time 2 CAS delay time 1 CAS delay time 2 Read data access time Access time from read strobe Access time from column address Access time from RAS Access time from CAS Row address hold time Row address setup time Data input setup time Data input hold time Symbol Min tAD 2* 3 Max Unit Figure 18 ns 22.6, 22.7, 22.9 to 22.14, 22.17 22.6, 22.7, 22.17 tCSD1 tCSD2 tRSD1 tRSD2 tRDS* tRDH tWSD1 tWSD2 tWDD tWDH tWTS tWTH tRASD1 tRASD2 tCASD1 tCASD2 tACC* tOE* tAA* 1 1 1 4 2* 2* 2* 2* 3 3 3 3 21 21 18 18 ⎯ ⎯ ns ns ns ns ns ns ns ns ns 2 22.6, 22.7, 22.9 to 22.14, 22.17 15 0 2* 2* ⎯ 0 15 0 2* 2* 2* 2* 3 3 3 3 3 3 18 18 35 ⎯ ⎯ 18 18 18 18 ⎯ ⎯ ⎯ 10* ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 22.9 to 22.14 22.6, 22.7 22.8, 22.13, 22.17 22.9 to 22.16 tcyc × (n + 2) − 40 tcyc × (n + 1.5) − 40 tcyc × (n + 2) − 40 tRAC* tCAC* tRAH tASR* tDS tDH 1 1 tcyc × (n + RCD + 2.5) − 40 ⎯ tcyc × (n + 1) − 40 tcyc × (RCD + 0.5) − 15 tcyc × 0.5 − 17.5 tcyc × (m + 0.5) − 25 20 ⎯ ⎯ ⎯ ⎯ ⎯ 5 Rev.5.00 Sep. 27, 2007 Page 566 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Notes: n is the number of waits. m is 0 when the number of DRAM write cycle waits is 0, and 1 otherwise. RCD is the set value of the RCD bit in DCR. 1. If the access time is satisfied, tRDS need not be satisfied. 2. tWDH (max) is a reference value. 3. The delay time Min values are reference values (typ). 4. tRDS is a reference value. 5. At 28.7 MHz, tASR = 0 ns (min) Table 22.7 Bus Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item Write address setup time Write address hold time Write data hold time Symbol Min tAS tWR tWRH 0 5 0 2* 2* tcyc −25 Max ⎯ ⎯ ⎯ 18 18 ⎯ Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns ns 22.6, 22.7, 22.9 to 22.14, 22.17 22.14 22.9 to 22.14 22.15, 22.16 22.17 22.9 to 22.14 22.6 to 22.7 Read/write strobe delay time 1 tRWD1 Read/write strobe delay time 2 tRWD2 High-speed page mode CAS precharge time RAS precharge time CAS setup time AH delay time 1 AH delay time 2 Multiplex address delay time Multiplex address hold time DACK delay time tCP tRP tCSR tAHD1 tAHD2 tMAD tMAH tDACKD1 tcyc × (TPC + 1.5) − 15 ⎯ 10 2* 2* 2* 0 2* ⎯ 18 18 18 ⎯ 21 Notes: TPC is the set value of the TPC bit in DCR. * The delay time Min values are reference values (typ).) Rev.5.00 Sep. 27, 2007 Page 567 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) T1 T2 CK tAD A21 to A0 tCSD1 CSn tRSD1 RD (During read) tACC D15 to D0 (During read) tWSD1 WRx (During write) tAS tWDD D15 to D0 (During write) tDACKD1 DACKn tDACKD1 tWSD2 tWR tWRH tWDH tRDS tRDH tOE tRSD2 tCSD2 Note: tRDH is specified from the first negate timing for A21 to A0, CSn, and RD. Figure 22.6 Basic Cycle (No Waits) Rev.5.00 Sep. 27, 2007 Page 568 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) T1 Tw T2 CK tAD A21 to A0 tCSD1 CSn tRSD1 RD (During read) tACC D15 to D0 (During read) tWSD1 WRx (During write) tAS tWDD D15 to D0 (During write) tDACKD1 DACKn tDACKD1 tWSD2 tWR tWRH tWDH tRDS tRDH tOE tRSD2 tCSD2 Note: tRDH is specified from the first negate timing for A21 to A0, CSn, and RD. Figure 22.7 Basic Cycle (Software Waits) Rev.5.00 Sep. 27, 2007 Page 569 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) T1 Tw Tw Two T2 CK A21 to A0 CSn RD (During read) D15 to D0 (During read) WRx (During write) D15 to D0 (During write) tWTS WAIT tWTH tWTS tWTH DACKn Figure 22.8 Basic Cycle (2 Software Waits + Wait due to WAIT Signal) Rev.5.00 Sep. 27, 2007 Page 570 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Tp Tr Tc1 Tc2 CK tAD tAD Row address tRASD1 tRAH Column address tRASD2 A21 to A0 tASR tRP RAS tCASD1 CASx (During read) RDWR (During read) D15 to D0 (During read) CASx (During write) tRWD1 RDWR (During write) tWDD D15 to D0 (During write) tDACKD1 DACKn tRSD1 RD (During read) WRx (During write) tWSD1 tWSD2 tDS tDH tRAC tCASD2 tAA tCAC tRDS tRDH tCASD1 tCASD2 tRWD2 tWDH tDACKD1 tRSD2 Note: tRDH is specified from the first negate timing for A21 to A0, RAS, and CAS. Figure 22.9 DRAM Cycle (Normal Mode, No Waits) Rev.5.00 Sep. 27, 2007 Page 571 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Tp Tr Tc1 Tcw1 Tc2 CK A21 to A0 tAD tAD Row address tRASD1 tRAH Column address tRASD2 tASR RAS CASx (During read) RDWR (During read) D15 to D0 (During read) CASx (During write) tRP tCASD1 tCASD2 tAA tRAC tCAC tRDS tRDH tCASD1 tCASD2 tRWD1 RDWR (During write) tWDD D15 to D0 (During write) tDACKD1 DACKn tRSD1 RD (During read) WRx (During write) tWSD1 tDS tRWD2 tDH tWDH tDACKD1 tRSD2 tWSD2 Note: tRDH is specified from the first negate timing for A21 to A0, RAS, and CAS. Figure 22.10 DRAM Cycle (Normal Mode, 1 Wait, TPC = 0, RCD = 0) Rev.5.00 Sep. 27, 2007 Page 572 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tc2 CK A21 to A0 tAD tAD Row address Column address tRASD2 tASR RAS CASx (During read) RDWR (During read) tRP tRASD1 tRAH tCASD1 tCASD2 tRAC D15 to D0 (During read) tAA tCAC tRDS tRDH tCASD1 CASx (During write) tRWD1 RDWR (During write) tWDD D15 to D0 (During write) tDACKD1 DACKn tRSD1 RD (During read) tWSD1 WRx (During write) Note: tRDH is specified from the first negate timing for A21 to A0, RAS, and CAS. tDS tDH tCASD2 tRWD2 tWDH tDACKD1 tRSD2 tWSD2 Figure 22.11 DRAM Cycle (Normal Mode, 2 Waits, TPC = 1, RCD = 1) Rev.5.00 Sep. 27, 2007 Page 573 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tcw3 Tc2 CK A21 to A0 tAD tAD Row address Column address tRASD2 tASR RAS CASx (During read) RDWR (During read) tRP tRASD1 tRAH tCASD1 tCASD2 tCAC tRAC tAA tRDS tRDH D15 to D0 (During read) tCASD1 CASx (During write) tRWD1 RDWR (During write) tWDD D15 to D0 (During write) tDACKD1 DACKn tRSD1 RD (During read) tWSD1 WRx (During write) tWSD2 tRSD2 tDACKD1 tDS tDH tWDH tRWD2 tCASD2 Note: tRDH is specified from the first negate timing for A21 to A0, RAS, and CAS. Figure 22.12 DRAM Cycle (Normal Mode, 3 Waits, TPC = 1, RCD = 1) Rev.5.00 Sep. 27, 2007 Page 574 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Tp Tr Tc1 Tcw1 Tcw2 Tcwo Tc2 CK tAD tAD Row address tRASD1 tRAH Column address tRASD2 A21 to A0 tASR RAS CASx (During read) RDWR (During read) D15 to D0 (During read) CASx (During write) tRP tCASD1 tCASD2 tCAC tAA tRAC tCASD1 tRDS tRDH tCASD2 tRWD1 RDWR (During write) tWDD D15 to D0 (During write) tWTS tWTH tWTS tWTH WAIT tDACKD1 DACKn RD (During read) WRx (During write) Note: tRDH is specified from the first negate timing for A21 to A0, RAS, and CAS. tRSD1 tDS tRWD2 tDH tWDH tDACKD1 tRSD2 tWSD1 tWSD2 Figure 22.13 DRAM Cycle (Normal Mode, 2 Waits + Wait due to WAIT Signal) Rev.5.00 Sep. 27, 2007 Page 575 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Tp Tr Tc1 Tc2 Tc1 Tc2 CK tAD tAD Row address tRASD1 tRAH Column address Column address tRASD2 A21 to A0 tASR RAS CASx (During read) RDWR (During read) D15 to D0 (During read) CASx (During write) tRP tCASD1 tCASD2 tCASD1 tCP tCASD2 tAA tRAC tCAC tRDS tAA tRDH tCAC tRDS tRDH tCASD1 tCASD2 tCASD1 tCP tCASD2 tRWD1 RDWR (During write) tDS tWDD D15 to D0 (During write) tDACKD1 DACKn tRSD1 RD (During read) tWSD1 WRx (During write) tRWD2 tRWD1 tRWD2 tDH tWDH tDS tWDD tDH tWDH tDACKD1 tDACKD1 tRSD2 tRSD1 tRSD2 tWSD2 tWSD1 tWSD2 Note: tRDH is specified from the first negate timing for A21 to A0, RAS, and CAS. Figure 22.14 DRAM Cycle (High-Speed Page Mode) Rev.5.00 Sep. 27, 2007 Page 576 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) TRp TRr1 TRr2 TRc TRc CK RAS tCASD1 CASx tRASD1 tCSR tRASD2 tCASD2 RDWR Figure 22.15 CAS Before RAS Refresh (TRAS1 = 0, TRAS0 = 0) TRp TRr1 TRr2 TRc TRcc CK RAS tRASD1 tCSR tCASD1 tRASD2 tCASD2 CASx RDWR Figure 22.16 Self Refresh Rev.5.00 Sep. 27, 2007 Page 577 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Ta1 Ta2 Ta3 Ta4 T1 TW TWo T2 CK tAD A21 to A0 tCSD1 CS3 tAHD1 AH tRSD1 RD (During read) tMAD D15 to D0 (During read) WRx (During write) tMAD D15 to D0 (During write) tWTS tWTH tWTS tWTH WAIT tDACKD1 DACKn tDACKD1 tMAH tWSD1 tWSD2 tWDH tMAH tRDS tRDH tRSD2 tAHD2 tCSD2 tWDD Note: tRDH is specified from the first negate timing for A21 to A0, CS3, and RD. Figure 22.17 Address Data Multiplex I/O Space Cycle (1 Software Wait + 1 External Wait) Rev.5.00 Sep. 27, 2007 Page 578 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.4 Direct Memory Access Controller Timing Table 22.8 shows the Direct Memory Access Controller Timing. Table 22.8 Direct Memory Access Controller Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item DREQ0 and DREQ1 setup time DREQ0 and DREQ1 hold time DRAK output delay time Symbol tDRQS tDRQH tDRAKD Min 18 18 1.5 18 Max ⎯ ⎯ ⎯ ⎯ Unit ns ns tcyc ns 22.19 22.20 Figure 22.18 DREQ0 and DREQ1 pulse width tDRQW CK tDRQS DREQ0, DREQ1 Level tDRQS DREQ0, DREQ1 Edge tDRQS DREQ0, DREQ1 Level clear tDRQH Figure 22.18 DREQ0 and DREQ1 Input Timing (1) Rev.5.00 Sep. 27, 2007 Page 579 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) CK DREQ0, DREQ1 Edge tDRQW Figure 22.19 DREQ0 and DREQ1 Input Timing (2) CK tDRAKD tDRAKD DRAKn Figure 22.20 DRAK Output Delay Time Rev.5.00 Sep. 27, 2007 Page 580 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.5 Multifunction Timer Pulse Unit Timing Table 22.9 shows the Multifunction Timer Pulse Unit Timing Table 22.9 Multifunction Timer Pulse Unit Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item Symbol Min ⎯ 30 35 1.5 2.5 2.5 Max 100 ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns ns ns tcyc tcyc tcyc 22.22 Figure 22.21 Output compare output delay time tTOCD Input capture input setup time Timer input setup time Timer clock pulse width (single edge specification) Timer clock pulse width (both edges specified) Timer clock pulse width (phase measurement mode) tTICS tTCKS tTCKWH/L tTCKWH/L tTCKWH/L CK tTOCD Output compare output tTICS Input capture input Figure 22.21 MTU I/O Timing Rev.5.00 Sep. 27, 2007 Page 581 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) CK tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 22.22 MTU Clock Input Timing 22.3.6 I/O Port Timing Table 22.10 shows the I/O Port Timing. Table 22.10 I/O Port Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item Port output data delay time Port input hold time Port input setup time Symbol tPWD tPRH tPRS Min ⎯ 35 35 Max 100 ⎯ ⎯ Unit ns ns ns Figure 22.23 T1 T2 CK tPRS Port (Read) tPWD Port (Write) tPRH Figure 22.23 I/O Port I/O Timing Rev.5.00 Sep. 27, 2007 Page 582 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.7 Watchdog Timer Timing Table 22.11 shows the Watchdog Timer Timing. Table 22.11 Watchdog Timer Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item WDTOVF delay time Symbol tWOVD Min ⎯ Max 100 Unit ns Figure 22.24 CK WDTOVF tWOVD tWOVD Figure 22.24 Watchdog Timer Timing 22.3.8 Serial Communication Interface Timing Table 22.12 shows the Serial Communication Interface Timing. Table 22.12 Serial Communication Interface Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item Input clock cycle Input clock cycle (clock sync) Input clock pulse width Input clock rise time Input clock fall time Symbol tscyc tscyc tsckw tsckr tsckf tRXS tRXH Min 4 6 0.4 ⎯ ⎯ ⎯ 100 100 Max ⎯ ⎯ 0.6 1.5 1.5 100 ⎯ ⎯ Unit tcyc tcyc tscyc tcyc tcyc ns ns ns 22.26 Figure 22.25 Transmit data delay time (clock sync) tTXD Receive data setup time (clock sync) Receive data hold time (clock sync) Rev.5.00 Sep. 27, 2007 Page 583 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) tsckw SCK0, SCK1 tsckr tsckf tscyc Figure 22.25 Input Clock Timing tscyc SCK0, SCK1 tTXD TXD0, TXD1 (Transmit data) tRXS RXD0, RXD1 (Receive data) tRXH Figure 22.26 SCI I/O Timing (Clock Sync Mode) 22.3.9 High Speed A/D Converter Timing ⎯ SH7014 ⎯ Table 22.13 shows the High-speed A/D Converter Timing. Table 22.13 High-speed A/D Converter Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AV CC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C Item A/D conversion start delay time Input sampling time CKS = 0 CKS = 1 CKS = 0 CKS = 1 A/D conversion time CKS = 0 CKS = 1 tCONV tSPL Symbol tD Min 1.5 1.5 20 40 42.5 82.5 Typ 1.5 1.5 20 40 42.5 82.5 Max 1.5 1.5 20 40 42.5 82.5 Unit tcyc Figure 22.27 Rev.5.00 Sep. 27, 2007 Page 584 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) φ Address Write signal ADST Sampling timing ADF tD tSPL tCONV Legend: tD: A/D conversion start delay time Input sampling time tSPL: tCONV: A/D conversion time Operation time tCP: tCP Figure 22.27 Analog Conversion Timing Rev.5.00 Sep. 27, 2007 Page 585 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.10 Mid-speed Converter Timing ⎯ SH7016, SH7017 ⎯ Table 22.14 shows the Mid-speed A/D Converter Timing. Table 22.14 Mid-speed A/D Converter Timing Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0V, Ta = −20 to +75°C Item A/D conversion start delay time Input sampling time CKS = 0 CKS = 1 CKS = 0 CKS = 1 A/D conversion time CKS = 0 CKS = 1 tCONV tSPL Symbol tD Min 10 6 ⎯ ⎯ 259 131 Typ ⎯ ⎯ 64 32 ⎯ ⎯ Max 17 9 ⎯ ⎯ 266 134 Unit tcyc Figure 22.28 Rev.5.00 Sep. 27, 2007 Page 586 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) (1) CK Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1): Write cycle of ADCSR (2): Address of ADCSR tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Figure 22.28 Analog Conversion Timing Rev.5.00 Sep. 27, 2007 Page 587 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.3.11 Measuring Conditions for AC Characteristics • Input reference levels: ⎯ High level: 2.2 V ⎯ Low level: 0.8 V • Output reference levels: ⎯ High level: 2.0 V ⎯ Low level: 0.8 V IOL LSI output pin CL V DUT output Vref IOH Note: CL is set with the following pins, including the total capacitance of the measurement jig, etc: 30 pF: 50 pF: 70 pF: IOL, IOH: CK, RAS, CASx, RDWR, CS0 to CS3, AH, DACK0, DACK1 A21 to A0, D15 to D0, RD, WRx Port output and peripheral module output pins other than the above. See table 22.3, Permitted Output Current Values. Figure 22.29 Output Test Circuit Rev.5.00 Sep. 27, 2007 Page 588 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) 22.4 A/D Converter Characteristics Tables 22.15 and 22.16 show A/D converter characteristics for the HD6417014 and HD6417014R, and table 22.17 shows A/D converter characteristics for the SH7016 and SH7017. The HD6417014R has an absolute error of ±8 LSB or less. Table 22.15 A/D Converter Characteristics (HD6417014) Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC ±10%, VSS = AVSS = 0 V, Ta = −20 to +75°C 28.7MHz Item Resolution Conversion time* 1 Min 10 ⎯ ⎯ ⎯ ⎯ ⎯ 2 2 Typ 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 10 2.9 20 1 ±8 ±8 ±8 ±0.5 ±15 Unit Bits μs pF kΩ LSB LSB LSB LSB LSB Analog input capacitance Permitted signal source impedance Non-linear error* Offset error* 2 2 Full-scale error* 1 ⎯ ⎯ ⎯ Quantization error* Absolute error* Notes: 1. CKS = 1 2. Reference values Rev.5.00 Sep. 27, 2007 Page 589 of 716 REJ09B0398-0500 22. Electrical Characteristics (5 V 28.7 MHz) Table 22.16 A/D Converter Characteristics (HD6417014R) Conditions: VCC = 5.0 V ±10%, AVCC = VCC ±10%, VCC = AVCC = 0 V, Ta = −20 to +75°C 28.7MHz Item Resolution Conversion time* 1 Min 10 ⎯ ⎯ ⎯ ⎯ ⎯ 2 Typ 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 10 2.9 20 1 ±8 ±8 ±8 ±0.5 ±8 Unit bit μs pF kΩ LSB LSB LSB LSB LSB Analog input capacitance Permission signal source impedance Non-linear error* Offset error* 2 2 Full scale error* Quantize error* Absolute error* 1 ⎯ ⎯ ⎯ 2 Notes: 1. CKS = 1 2. Reference values Table 22.17 A/D Converter Characteristics (SH7016, SH7017) Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, AVCC = VCC = 0 V, VSS = AVSS = 0 V, Ta = −20 to +75°C 28.7MHz Item Resolution Conversion time (when CKS = 0) Analog input capacity Permission signal source impedance Non-linearity error* Offset error* 1 1 1 20MHz min 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ typ 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ max 10 2 min 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 typ 10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ max 10 9.3 20 1 ±3 ±3 ±3 ±0.5 ±4 Unit bit 13.4* μs 20 1 ±3 ±3 ±3 ±0.5 ±4 pF kΩ LSB LSB LSB LSB LSB Full scale error* Quantize error* Absolute error Notes: 1. Reference value 2. 6.7 μs when CKS = 1. Rev.5.00 Sep. 27, 2007 Page 590 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Appendix A On-Chip Supporting Module Registers A.1 Addresses On-Chip I/O Register Addresses Register Abbr. Bit Names Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI Table A.1 Address H'FFFF81A0 SMR0 H'FFFF81A1 BRR0 H'FFFF81A2 SCR0 H'FFFF81A3 TDR0 H'FFFF81A4 SSR0 H'FFFF81A5 RDR0 H'FFFF81A6 ⎯ to H'FFFF81AF H'FFFF81B0 SMR1 H'FFFF81B1 BRR1 H'FFFF81B2 SCR1 H'FFFF81B3 TDR1 H'FFFF81B4 SSR1 H'FFFF81B5 RDR1 H'FFFF81B6 ⎯ to H'FFFF81FF H'FFFF8200 ⎯ to H'FFFF823F H'FFFF8240 TSTR H'FFFF8241 TSYR H'FFFF8242 ⎯ to H'FFFF825F H'FFFF8260 TCR0 H'FFFF8261 TMDR0 H'FFFF8262 TIOR0H H'FFFF8263 TIOR0L H'FFFF8264 TIER0 H'FFFF8265 TSR0 H'FFFF8266 TCNT0 H'FFFF8267 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ MTU ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CST2 SYNC2 ⎯ CST1 SYNC1 ⎯ CST0 SYNC0 ⎯ CCLR2 ⎯ IOB3 IOD3 TTGE ⎯ CCLR1 ⎯ IOB2 IOD2 ⎯ ⎯ CCLR0 BFB IOB1 IOD1 ⎯ ⎯ CKEG1 BFA IOB0 IOD0 TCIEV TCFV CKEG0 MD3 IOA3 IOC3 TGIED TGFD TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Rev.5.00 Sep. 27, 2007 Page 591 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MTU Address H'FFFF8268 TGR0A H'FFFF8269 H'FFFF826A TGR0B H'FFFF826B H'FFFF826C TGR0C H'FFFF826D H'FFFF826E TGR0D H'FFFF826F H'FFFF8270 ⎯ to H'FFFF827F H'FFFF8280 TCR1 H'FFFF8281 TMDR1 H'FFFF8282 TIOR1 H'FFFF8283 ⎯ H'FFFF8284 TIER1 H'FFFF8285 TSR1 H'FFFF8286 TCNT1 H'FFFF8287 H'FFFF8288 TGR1A H'FFFF8289 H'FFFF828A TGR1B H'FFFF828B H'FFFF828C ⎯ to H'FFFF829F H'FFFF82A0 TCR2 H'FFFF82A1 TMDR2 H'FFFF82A2 TIOR2 H'FFFF82A3 ⎯ H'FFFF82A4 TIER2 H'FFFF82A5 TSR2 H'FFFF82A6 TCNT2 H'FFFF82A7 H'FFFF82A8 TGR2A H'FFFF82A9 H'FFFF82AA TGR2B H'FFFF82AB H'FFFF82AC ⎯ to H'FFFF8347 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IOB3 ⎯ TTGE TCFD CCLR1 ⎯ IOB2 ⎯ ⎯ ⎯ CCLR0 ⎯ IOB1 ⎯ TCIEU TCFU CKEG1 ⎯ IOB0 ⎯ TCIEV TCFV CKEG0 MD3 IOA3 ⎯ ⎯ ⎯ TPSC2 MD2 IOA2 ⎯ ⎯ ⎯ TPSC1 MD1 IOA1 ⎯ TGIEB TGFB TPSC0 MD0 IOA0 ⎯ TGIEA TGFA ⎯ ⎯ IOB3 ⎯ TTGE TCFD CCLR1 ⎯ IOB2 ⎯ ⎯ ⎯ CCLR0 ⎯ IOB1 ⎯ TCIEU TCFU CKEG1 ⎯ IOB0 ⎯ TCIEV TCFV CKEG0 MD3 IOA3 ⎯ ⎯ ⎯ TPSC2 MD2 IOA2 ⎯ ⎯ ⎯ TPSC1 MD1 IOA1 ⎯ TGIEB TGFB TPSC0 MD0 IOA0 ⎯ TGIEA TGFA Rev.5.00 Sep. 27, 2007 Page 592 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTC Address H'FFFF8348 IPRA H'FFFF8349 H'FFFF834A IPRB H'FFFF834B H'FFFF834C IPRC H'FFFF834D H'FFFF834E IPRD H'FFFF834F H'FFFF8350 IPRE H'FFFF8351 H'FFFF8352 IPRF H'FFFF8353 H'FFFF8354 IPRG H'FFFF8355 H'FFFF8356 IPRH H'FFFF8357 H'FFFF8358 ICR H'FFFF8359 H'FFFF835A ISR H'FFFF835B H'FFFF835C ⎯ to H'FFFF8381 H'FFFF8382 PADRL H'FFFF8383 H'FFFF8384 ⎯ H'FFFF8385 ⎯ H'FFFF8386 PAIORL H'FFFF8387 H'FFFF8388 ⎯ H'FFFF8389 ⎯ NMIL IRQ0S ⎯ IRQ0F ⎯ ⎯ IRQ1S ⎯ IRQ1F ⎯ ⎯ IRQ2S ⎯ IRQ2F ⎯ ⎯ IRQ3S ⎯ IRQ3F ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IRQ6S ⎯ IRQ6F ⎯ NMIE IRQ7S ⎯ IRQ7F ⎯ PA15DR PA7DR ⎯ ⎯ PA14DR*1 PA13DR*1 PA12DR*1 PA11DR*1 PA10DR*1 PA9DR PA6DR ⎯ ⎯ PA5DR ⎯ ⎯ PA4DR ⎯ ⎯ PA3DR ⎯ ⎯ PA2DR ⎯ ⎯ PA1DR ⎯ ⎯ PA8DR PA0DR ⎯ ⎯ I/O PFC PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR*1 PA8IOR*1 *1 *1 *1 *1 *1 PA7IOR ⎯ ⎯ PA6IOR ⎯ ⎯ PA5IOR ⎯ ⎯ PA4IOR ⎯ ⎯ PA3IOR ⎯ ⎯ PA2IOR ⎯ ⎯ PA1IOR ⎯ ⎯ PA0IOR ⎯ ⎯ Rev.5.00 Sep. 27, 2007 Page 593 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 ⎯ ⎯ ⎯ ⎯ PA7MD1 ⎯ ⎯ PB7DR 2 Address Bit 6 ⎯ ⎯ PA15MD PA11MD *1 PA7MD0 PA3MD ⎯ PB6DR PC14DR PC6DR ⎯ PB6IOR Bit 5 ⎯ ⎯ ⎯ ⎯ PA6MD1 PA2MD1 ⎯ PB5DR PC13DR PC5DR ⎯ PB5IOR Bit 4 ⎯ ⎯ PA14MD *1 PA10MD 1 * PA6MD0 PA2MD0 ⎯ PB4DR PC12DR PC4DR ⎯ PB4IOR Bit 3 ⎯ ⎯ ⎯ PA9MD1 PA5MD1 ⎯ ⎯ PB3DR PC11DR PC3DR ⎯ PB3IOR Bit 2 ⎯ ⎯ PA13MD 1 * PA9MD0 PA5MD0 PA1MD ⎯ PB2DR PC10DR PC2DR ⎯ PB2IOR Bit 1 ⎯ ⎯ ⎯ PA8MD1 ⎯ ⎯ PB9DR PB1DR* PC9DR PC1DR PB9IOR 1 Bit 0 ⎯ ⎯ PA12MD 1 * PA8MD0 PA4MD PA0MD PB8DR PB0DR* PC8DR PC0DR PB8IOR 1 Module PFC H'FFFF838A ⎯ H'FFFF838B ⎯ H'FFFF838C PACRL1 H'FFFF838D H'FFFF838E PACRL2 H'FFFF838F H'FFFF8390 PBDR H'FFFF8391 H'FFFF8392 PCDR* H'FFFF8393 H'FFFF8394 PBIOR H'FFFF8395 H'FFFF8396 PCIOR*2 H'FFFF8397 H'FFFF8398 PBCR1 H'FFFF8399 H'FFFF839A PBCR2 H'FFFF839B H'FFFF839C PCCR*2 H'FFFF839D H'FFFF839E ⎯ H'FFFF839F ⎯ H'FFFF83A0 ⎯ H'FFFF83A1 ⎯ H'FFFF83A2 PDDRL*2 H'FFFF83A3 H'FFFF83A4 ⎯ H'FFFF83A5 ⎯ I/O PC15DR PC7DR ⎯ PB7IOR PFC PB1IOR*1 PB0IOR*1 PC8IOR PC0IOR ⎯ PB8MD0 PB4MD0 PB0MD*1 PC8MD PC0MD ⎯ ⎯ ⎯ ⎯ PD8DR PD0DR ⎯ ⎯ PD8IOR PD0IOR ⎯ ⎯ ⎯ ⎯ PFC I/O PC15IOR PC14IOR PC13IOR PC12IOR PC11IOR PC10IOR PC9IOR PC7IOR ⎯ ⎯ PB7MD1 PB3MD1 PC15MD PC7MD ⎯ ⎯ ⎯ ⎯ PD15DR PD7DR ⎯ ⎯ PC6IOR ⎯ ⎯ PB7MD0 PB3MD0 PC14MD PC6MD ⎯ ⎯ ⎯ ⎯ PD14DR PD6DR ⎯ ⎯ PC5IOR ⎯ ⎯ PB6MD1 PB2MD1 PC13MD PC5MD ⎯ ⎯ ⎯ ⎯ PD13DR PD5DR ⎯ ⎯ PC4IOR ⎯ ⎯ PB6MD0 PB2MD0 PC12MD PC4MD ⎯ ⎯ ⎯ ⎯ PD12DR PD4DR ⎯ ⎯ PC3IOR ⎯ PB9MD1 PB5MD1 ⎯ PC11MD PC3MD ⎯ ⎯ ⎯ ⎯ PD11DR PD3DR ⎯ ⎯ PC2IOR ⎯ PB9MD0 PB5MD0 PC1IOR ⎯ PB8MD1 PB4MD1 PB1MD*1 ⎯ PC10MD PC2MD ⎯ ⎯ ⎯ ⎯ PD10DR PD2DR ⎯ ⎯ PC9MD PC1MD ⎯ ⎯ ⎯ ⎯ PD9DR PD1DR ⎯ ⎯ H'FFFF83A6 PDIORL*2 PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR H'FFFF83A7 H'FFFF83A8 ⎯ H'FFFF83A9 ⎯ H'FFFF83AA ⎯ H'FFFF83AB ⎯ PD7IOR ⎯ ⎯ ⎯ ⎯ PD6IOR ⎯ ⎯ ⎯ ⎯ PD5IOR ⎯ ⎯ ⎯ ⎯ PD4IOR ⎯ ⎯ ⎯ ⎯ PD3IOR ⎯ ⎯ ⎯ ⎯ PD2IOR ⎯ ⎯ ⎯ ⎯ PD1IOR ⎯ ⎯ ⎯ ⎯ Rev.5.00 Sep. 27, 2007 Page 594 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. 2 Bit Names Bit 7 PD15MD PD7MD ⎯ ⎯ PE15DR PE7DR ⎯ PF7DR Bit 6 PD14MD PD6MD ⎯ ⎯ PE14DR PE6DR ⎯ PF6DR Bit 5 PD13MD PD5MD ⎯ ⎯ PE13DR PE5DR ⎯ PF5DR Bit 4 PD12MD PD4MD ⎯ ⎯ PE12DR PE4DR ⎯ PF4DR Bit 3 PD11MD PD3MD ⎯ ⎯ PE11DR PE3DR ⎯ PF3DR Bit 2 PD10MD PD2MD ⎯ ⎯ PE10DR PE2DR ⎯ PF2DR Bit 1 PD9MD PD1MD ⎯ ⎯ PE9DR PE1DR ⎯ PF1DR Bit 0 PD8MD PD0MD ⎯ ⎯ PE8DR PE0DR ⎯ PF0DR PE8IOR PE0IOR ⎯ ⎯ ⎯ ⎯ PE4MD PE0MD0 ⎯ ⎯ PFC I/O Module PFC Address H'FFFF83AC PDCRL* H'FFFF83AD H'FFFF83AE ⎯ H'FFFF83AF ⎯ H'FFFF83B0 PEDR H'FFFF83B1 H'FFFF83B2 PFDR H'FFFF83B3 H'FFFF83B4 PEIOR H'FFFF83B5 H'FFFF83B6 ⎯ H'FFFF83B7 ⎯ H'FFFF83B8 PECR1 H'FFFF83B9 H'FFFF83BA PECR2 H'FFFF83BB H'FFFF83BC ⎯ to H'FFFF83CF H'FFFF83D0 CMSTR H'FFFF83D1 PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE7IOR ⎯ ⎯ PE6IOR ⎯ ⎯ PE5IOR ⎯ ⎯ PE4IOR ⎯ ⎯ PE3IOR ⎯ ⎯ PE2IOR ⎯ ⎯ ⎯ ⎯ PE5MD PE1MD0 ⎯ PE1IOR ⎯ ⎯ ⎯ ⎯ ⎯ PE0MD1 ⎯ PE15MD1 PE15MD0 PE14MD1 PE14MD0 ⎯ ⎯ ⎯ PE3MD1 ⎯ ⎯ PE7MD PE3MD0 ⎯ ⎯ ⎯ PE2MD1 ⎯ ⎯ PE6MD PE2MD0 ⎯ ⎯ ⎯ PE1MD1 ⎯ ⎯ ⎯ ⎯ CMF ⎯ ⎯ ⎯ CMIE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ STR1 ⎯ CKS1 ⎯ STR0 ⎯ CKS0 CMT H'FFFF83D2 CMCSR0 H'FFFF83D3 H'FFFF83D4 CMCNT0 H'FFFF83D5 H'FFFF83D6 CMCOR0 H'FFFF83D7 H'FFFF83D8 CMCSR1 H'FFFF83D9 H'FFFF83DA CMCNT1 H'FFFF83DB H'FFFF83DC CMCOR1 H'FFFF83DD H'FFFF83DE ⎯ H'FFFF83DF ⎯ ⎯ CMF ⎯ CMIE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CKS1 ⎯ CKS0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Rev.5.00 Sep. 27, 2007 Page 595 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 ADF ⎯ ⎯ Bit 6 ADIE PWR ⎯ Bit 5 ADST TRGS1 ⎯ Bit 4 CKS TRGS0 ⎯ Bit 3 GRP SCAN ⎯ Bit 2 CH2 DSMP ⎯ Bit 1 CH1 BUFE1 ⎯ Bit 0 CH0 BUFE0 ⎯ Module A/D (High speed) (SH7014) Address H'FFFF83E0 ADCSR H'FFFF83E1 ADCR H'FFFF83E2 ⎯ to H'FFFF83EF H'FFFF83F0 ADDRA H'FFFF83F1 H'FFFF83F2 ADDRB H'FFFF83F3 H'FFFF83F4 ADDRC H'FFFF83F5 H'FFFF83F6 ADDRD H'FFFF83F7 H'FFFF83F8 ADDRE H'FFFF83F9 H'FFFF83FA ADDRF H'FFFF83FB H'FFFF83FC ADDRG H'FFFF83FD H'FFFF83FE ADDRH H'FFFF83FF H'FFFF8400 ⎯ to H'FFFF841F H'FFFF8420 ADDRA H'FFFF8421 H'FFFF8422 ADDRB H'FFFF8423 H'FFFF8424 ADDRC H'FFFF8425 H'FFFF8426 ADDRD H'FFFF8427 H'FFFF8428 ADCSR H'FFFF8429 ADCR H'FFFF842A ⎯ to H'FFFF857F ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ⎯ AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ⎯ AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE ⎯ AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE ⎯ ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ AD7 ⎯ ADST ⎯ ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ AD6 ⎯ SCAN ⎯ ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ AD5 ⎯ CKS ⎯ ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ AD4 ⎯ CH2 ⎯ ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ AD3 ⎯ CH1 ⎯ ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ AD2 ⎯ CH0 ⎯ ⎯ A/D (Midspeed) (SH7016 /17) Rev.5.00 Sep. 27, 2007 Page 596 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 FWE FLER EB7 ⎯ Bit 6 SWE ⎯ EB6 ⎯ Bit 5 ESU1 ⎯ EB5 ⎯ Bit 4 PSU1 ⎯ EB4 ⎯ Bit 3 EV1 ⎯ EB3 ⎯ Bit 2 PV1 ⎯ EB2 ⎯ Bit 1 E1 ⎯ EB1 ⎯ Bit 0 P1 ⎯ EB0 ⎯ Module FLASH (F-ZTAT version only) Address H'FFFF8580 FLMCR1 H'FFFF8581 FLMCR2 H'FFFF8582 EBR1 H'FFFF8583 ⎯ to H'FFFF860F H'FFFF8610 TCSR H'FFFF8610 TCNT*3 H'FFFF8611 TCNT* 4 OVF WT/IT TME ⎯ ⎯ CKS2 CKS1 CKS0 WDT H'FFFF8612 RSTCSR*3 WOVF H'FFFF8613 RSTCSR* WOVF H'FFFF8614 SBYCR SBY 4 RSTE RSTE HIZ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Powerdown state BSC H'FFFF8615 ⎯ to H'FFFF861F H'FFFF8620 BCR1 H'FFFF8621 H'FFFF8622 BCR2 H'FFFF8623 H'FFFF8624 WCR1 H'FFFF8625 H'FFFF8626 WCR2 H'FFFF8627 H'FFFF8628 RAMER ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IW31 CW3 W33 W13 ⎯ ⎯ ⎯ ⎯ ⎯ IW30 CW2 W32 W12 ⎯ ⎯ ⎯ ⎯ ⎯ IW21 CW1 W31 W11 ⎯ DDW1 ⎯ ⎯ ⎯ IW20 CW0 W30 W10 ⎯ DDW0 ⎯ ⎯ A3SZ IW11 SW3 W23 W03 ⎯ DSW3 ⎯ ⎯ A2SZ IW10 SW2 W22 W02 ⎯ DSW2 ⎯ ⎯ A1SZ IW01 SW1 W21 W01 ⎯ DSW1 ⎯ IOE A0SZ IW00 SW0 W20 W00 ⎯ DSW0 ⎯ FLASH (F-ZTAT version only) H'FFFF8629 ⎯ ⎯ ⎯ ⎯ ⎯ RAMS RAM1 RAM0 H'FFFF862A DCR H'FFFF862B H'FFFF862C RTCSR H'FFFF862D H'FFFF862E RTCNT H'FFFF862F H'FFFF8630 RTCOR H'FFFF8631 H'FFFF8632 ⎯ to H'FFFF86AF TPC DIW ⎯ ⎯ ⎯ RCD ⎯ ⎯ CMF ⎯ TRAS1 BE ⎯ CMIE ⎯ TRAS0 RASD ⎯ CKS2 ⎯ DWW1 ⎯ ⎯ CKS1 ⎯ DWW0 SZ0 ⎯ CKS0 ⎯ DWR1 AMX1 ⎯ RFSH ⎯ DWR0 AMX0 ⎯ RMD ⎯ BSC ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Rev.5.00 Sep. 27, 2007 Page 597 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 ⎯ ⎯ ⎯ Bit 6 ⎯ ⎯ ⎯ Bit 5 ⎯ ⎯ ⎯ Bit 4 ⎯ ⎯ ⎯ Bit 3 ⎯ ⎯ ⎯ Bit 2 ⎯ AE ⎯ Bit 1 ⎯ NMIF ⎯ Bit 0 ⎯ DME ⎯ Module DMAC Address H'FFFF86B0 DMAOR H'FFFF86B1 H'FFFF86B2 ⎯ to H'FFFF86BF H'FFFF86C0 SAR0 H'FFFF86C1 H'FFFF86C2 H'FFFF86C3 H'FFFF86C4 DAR0 H'FFFF86C5 H'FFFF86C6 H'FFFF86C7 H'FFFF86C8 DMATCR0 H'FFFF86C9 H'FFFF86CA H'FFFF86CB H'FFFF86CC CHCR0 H'FFFF86CD H'FFFF86CE H'FFFF86CF H'FFFF86D0 SAR1 H'FFFF86D1 H'FFFF86D2 H'FFFF86D3 H'FFFF86D4 DAR1 H'FFFF86D5 H'FFFF86D6 H'FFFF86D7 H'FFFF86D8 DMATCR1 H'FFFF86D9 H'FFFF86DA H'FFFF86DB H'FFFF86DC CHCR1 H'FFFF86DD H'FFFF86DE H'FFFF86DF ⎯ ⎯ DM1 ⎯ ⎯ ⎯ DM0 DS ⎯ ⎯ SM1 TM ⎯ ⎯ SM0 TS1 ⎯ ⎯ RS3 TS0 ⎯ RL RS2 IE ⎯ AM RS1 TE ⎯ AL RS0 DE ⎯ ⎯ DM1 ⎯ ⎯ ⎯ DM0 DS ⎯ ⎯ SM1 TM ⎯ ⎯ SM0 TS1 ⎯ ⎯ RS3 TS0 ⎯ RL RS2 IE ⎯ AM RS1 TE ⎯ AL RS0 DE Rev.5.00 Sep. 27, 2007 Page 598 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Register Abbr. Bit Names Bit 7 ⎯ Bit 6 ⎯ Bit 5 ⎯ Bit 4 ⎯ Bit 3 ⎯ Bit 2 ⎯ Bit 1 ⎯ Bit 0 ⎯ Module ⎯ Address H'FFFF87E0 ⎯ to H'FFFF873F H'FFFF8740 CCR H'FFFF8741 H'FFFF8742 ⎯ to H'FFFF87FF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CECS2 ⎯ ⎯ CECS1 ⎯ ⎯ CECS0 ⎯ CAC CEDRAM CECS3 ⎯ ⎯ Notes: 1. 2. 3. 4. Reserved bit in the SH7014. In the SH7014, this address is reserved and must not be accessed. Write address. Read address. For details, see section 13.2.4, Notes on Register Access, in section 13, Watchdog Timer. Rev.5.00 Sep. 27, 2007 Page 599 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers A.2 Functions Register acronym Start address Access size Module SCI Serial Mode Register (SMR) H'FFFF81A0 (Channel 0) H'FFFF81B0 (Channel 1) 8/16 Item Register outline Bit Nmae Initial value R/W Bit 7 Bit 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Bit functions Value 0 1 0 6 Character Length (CHR) 1 0 5 Parity Enable (PE) 1 0 4 Parity Mode (O/E) 1 0 3 Stop Bit Length (STOP) 1 0 Multiprocessor Mode (MP) 2 1 00 1, 0 Clock Select 1 and 0 1 (CKS1 and CKS0) 10 1 Name Communication Mode (C/A) Description Asynchronous mode Clock synchronous mode 8-bit data 7-bit data Parity bit not added or checked Parity bit added and checked Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected φ/4 φ/16 φ/64 φ/256 (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) (Initial value) Bit numbers Bit acronym Initial bit values Descriptions of bit settings (When two or more bits are described as a set, the higher bits are on the left and the lower bits on the right.) Rev.5.00 Sep. 27, 2007 Page 600 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers INTC Interrupt Priority Register A (IPRA) Bit Item Bit Name Initial value R/W Bit 15 to 12 11 to 8 7 to 4 3 to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name (IRQ0 priority level setting) (IRQ1 priority level setting) (IRQ2 priority level setting) (IRQ3 priority level setting) Description Sets the IRQ0 priority level Sets the IRQ1 priority level Sets the IRQ2 priority level Sets the IRQ3 priority level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H'FFFF8348 8/16/32 Interrupt Priority Register B (IPRB) Bit Item Bit Name Initial value R/W Bit 7 to 4 3 to 0 15 ― 0 R 14 ― 0 R 13 ― 0 R 12 ― 0 R 11 ― 0 R 10 ― 0 R 9 ― 0 R 8 ― 0 R 0 0 7 6 H'FFFF834A 8/16/32 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Sets the IRQ6 priority level Sets the IRQ7 priority level Name (IRQ6 priority level setting) (IRQ7 priority level setting) Rev.5.00 Sep. 27, 2007 Page 601 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers INTC Interrupt Priority Register C (IPRC) Bit Item Bit Name Initial value R/W Bit 15 to 12 11 to 8 0 0 0 0 0 0 0 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R/W R/W R/W R/W R/W R/W R/W R/W Name (DMAC0 priority level setting) (DMAC1 priority level setting) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H'FFFF834C 8/16/32 Description Sets the DMAC0 priority level Sets the DMAC1 priority level Interrupt Priority Register D (IPRD) Bit Item Bit Name Initial value R/W Bit 15 to 12 11 to 8 7 to 4 3 to 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 H'FFFF834E 8/16/32 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name (MTU0 priority level setting) (MTU0 priority level setting) (MTU1 priority level setting) (MTU1 priority level setting) Description Sets the MTU0 priority level Sets the MTU0 priority level Sets the MTU1 priority level Sets the MTU1 priority level Rev.5.00 Sep. 27, 2007 Page 602 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers INTC Interrupt Priority Register E (IPRE) Bit Item Bit Name Initial value R/W Bit 15 to 12 11 to 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Name (MTU2 priority level setting) (MTU2 priority level setting) 15 14 13 12 11 10 9 8 7 ― 0 R 6 ― 0 R 5 ― 0 R 4 ― 0 R 3 ― 0 R 2 ― 0 R 1 ― 0 R 0 ― 0 R H'FFFF8350 8/16/32 Description Sets the MTU2 priority level Sets the MTU2 priority level Interrupt Priority Register F (IPRF) Bit Item Bit Name Initial value R/W Bit 7 to 4 3 to 0 15 ― 0 R 14 ― 0 R 13 ― 0 R 12 ― 0 R 11 ― 0 R 10 ― 0 R 9 ― 0 R 8 ― 0 R 0 7 H'FFFF8352 8/16/32 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Sets the SCI0 priority level Sets the SCI1 priority level Name (SCI0 priority level setting) (SCI1 priority level setting) Rev.5.00 Sep. 27, 2007 Page 603 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers INTC Interrupt Priority Register G (IPRG) Bit Item Bit Name Initial value R/W Bit 15 to 12 7 to 4 3 to 0 0 0 0 0 R/W R/W R/W R/W 15 14 13 12 11 ― 0 R 10 ― 0 R 9 ― 0 R 8 ― 0 R 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Sets the A/D priority level Sets the CMT0 priority level Sets the CMT1 priority level 7 6 5 4 3 2 1 0 H'FFFF8354 8/16/32 Name (A/D priority level setting) (CMT0 priority level setting) (CMT1 priority level setting) Interrupt Priority Register H (IPRH) Bit Item Bit Name Initial value R/W Bit 15 to 12 0 0 0 0 R/W R/W R/W R/W 15 14 13 12 11 ― 0 R 10 ― 0 R 9 ― 0 R 8 ― 0 R 7 ― 0 R H'FFFF8356 8/16/32 6 ― 0 R 5 ― 0 R 4 ― 0 R 3 ― 0 R 2 ― 0 R 1 ― 0 R 0 ― 0 R Name (WDT and BSC priority level setting) Description Set the WDT and BSC priority level Rev.5.00 Sep. 27, 2007 Page 604 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers INTC Interrupt Control Register (ICR) Bit Item Bit Name Initial value R/W Item Bit Name Initial value R/W Note: * 15 NMIL * R 7 IRQ0S 0 R/W 14 ― 0 R 6 IRQ1S 0 R/W 13 ― 0 R 5 IRQ2S 0 R/W 12 ― 0 R 4 IRQ3S 0 R/W 11 ― 0 R 3 ― 0 R 10 ― 0 R 2 ― 0 R 9 ― 0 R 1 IRQ6S 0 R/W 8 NMIE 0 R/W 0 IRQ7S 0 R/W H'FFFF8358 8/16/32 When NMI input is high: 1; when NMI input is low: 0 Bit 15 Name NMI Input Level (NMIL) Value 0 1 NMI input level is low NMI input level is high Description 8 NMI Edge Select (NMIE) 0 1 Interrupt request is detected on falling edge of NMI input (initial value) Interrupt request is detected on rising edge of NMI input Interrupt request is detected on low level of IRQ input (initial value) Interrupt request is detected on falling edge of IRQ input 7 to 4, 1, 0 IRQ0 to IRQ3, IRQ6, IRQ7 Sense Select (IRQ0S to IRQ3S, IRQ6S, IRQ7S) 0 1 Rev.5.00 Sep. 27, 2007 Page 605 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers INTC IRQ Status Register (ISR) Bit Item Bit name Initial value H'FFFF835A 8/16/32 15 ― 0 R 7 IRQ0F 0 R/W 14 ― 0 R 6 IRQ1F 0 R/W 13 ― 0 R 5 IRQ2F 0 R/W 12 ― 0 R 4 IRQ3F 0 R/W Detection Setting Level detection 11 ― 0 R 3 ― 0 R 10 ― 0 R 2 ― 0 R 9 ― 0 R 1 IRQ6F 0 R/W 8 ― 0 R 0 IRQ7F 0 R/W R/W Item Bit name Initial value R/W Bit 7 to 4, 1, 0 Name IRQ0 to IRQ3, IRQ6, IRQ7 Flags (IRQ0F to IRQ3F, IRQ6F, IRQ7F) Value 0 Description No IRQn interrupt request exists. Clear condition: When IRQn input is high level No IRQn interrupt request was detected. (initial value) Clear conditions: 1. When a 0 is written after reading IRQnF = 1 status 2. When IRQn interrupt exception processing has been execute Edge detection 1 Level detection Edge detection An IRQn interrupt request exists. Set condition: When IRQn input is low level An IRQn interrupt request was detected. Set condition: When a falling edge occurs at an IRQn input Rev.5.00 Sep. 27, 2007 Page 606 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers CAC Cache Control Register (CCR) Bit Item Bit name Initial value H'FFFF8740 8/16/32 15 ― * R 7 ― * R * Undefined 14 ― * R 6 ― * R 13 ― * R 5 ― * R 12 ― * R 4 CEDRAM 0 R/W 11 ― * R 3 CECS3 0 R/W 10 ― * R 2 CECS2 0 R/W 9 ― * R 1 CECS1 0 R/W 8 ― * R 0 CECS0 0 R/W R/W Item Bit name Initial value R/W Note: Bit 4 3 2 1 0 Name DRAM Space Cache Enable (CEDRAM) CS3 Space Cache Enable (CECS3) CS2 Space Cache Enable (CECS2) CS1 Space Cache Enable (CECS1) CS0 Space Cache Enable (CECS0) Value 0 1 0 1 0 1 0 1 0 1 Description DRAM space cache disabled DRAM space cache enabled CS3 space cache disabled CS3 space cache enabled CS2 space cache disabled CS2 space cache enabled CS1 space cache disabled CS1 space cache enabled CS0 space cache disabled CS0 space cache enabled (initial value) (initial value) (initial value) (initial value) (initial value) Rev.5.00 Sep. 27, 2007 Page 607 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Bus Control Register 1 (BCR1) Bit Item Bit name Initial value H'FFFF8620 8/16/32 15 ― 0 R 7 ― 0 R 14 ― 0 R 6 ― 0 R Name 13 ― 0 R 5 ― 0 R 12 ― 0 R 4 ― 0 R Value 0 1 0 1 0 1 0 1 0 11 ― 0 R 3 A3SZ 1 R/W 10 ― 0 R 2 A2SZ 1 R/W Description 9 ― 0 R 1 A1SZ 1 R/W 8 IOE 0 R/W 0 A0SZ 1 R/W R/W Item Bit name Initial value R/W Bit 8 3 2 1 0 Note: Multiplex I/O Enable (IOE) CS3 Space Size Specification (A3SZ) CS2 Space Size Specification (A2SZ) CS1 Space Size Specification (A1SZ) CS0 Space Size Specification (A0SZ) CS3 space is ordinary space Byte (8-bit) size Word (16-bit) size Byte (8-bit) size Word (16-bit) size Byte (8-bit) size Word (16-bit) size Byte (8-bit) size (initial value) CS3 space is address/data multiplex I/O space (initial value) (initial value) (initial value) 1 Word (16-bit) size (initial value) A0SZ is effective only in on-chip ROM effective mode. In on-chip ROM ineffective mode, the CS0 space bus size is specified by the mode pin. Rev.5.00 Sep. 27, 2007 Page 608 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Bus Control Register 2 (BCR2) Bit Item Bit name Initial value H'FFFF8622 8/16/32 15 IW31 1 R/W 7 CW3 1 R/W 14 IW30 1 R/W 6 CW2 1 R/W Name 13 IW21 1 R/W 5 CW1 1 R/W Value IW31, IW30 0 1 IW21, IW20 0 1 IW11, IW10 0 1 IW01, IW00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 12 IW20 1 R/W 4 CW0 1 R/W 11 IW11 1 R/W 3 SW3 1 R/W 10 IW10 1 R/W 2 SW2 1 R/W Description 9 IW01 1 R/W 1 SW1 1 R/W 8 IW00 1 R/W 0 SW0 1 R/W R/W Item Bit name Initial value R/W Bit 15 to 8 Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00) No idle cycle after accessing CS3 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles No idle cycle after accessing CS2 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles No idle cycle after accessing CS1 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles No idle cycle after accessing CS0 space Inserts one idle cycle Inserts two idle cycles Inserts three idle cycles No CS3 space continuous access idle cycles One CS3 space continuous access idle cycle (initial value) No CS2 space continuous access idle cycles One CS2 space continuous access idle cycle (initial value) No CS1 space continuous access idle cycles One CS1 space continuous access idle cycle (initial value) No CS0 space continuous access idle cycles One CS0 space continuous access idle cycle (initial value) No CS3 space CS assert extension CS3 space CS assert extension (initial value) (initial value) (initial value) (initial value) (initial value) 7 6 5 4 3 Idle Specification for Continuous Access (CW3) Idle Specification for Continuous Access (CW2) Idle Specification for Continuous Access (CW1) Idle Specification for Continuous Access (CW0) CS Assert Extension Specification (SW3) Rev.5.00 Sep. 27, 2007 Page 609 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Bit 2 1 0 Name CS Assert Extension Specification (SW2) CS Assert Extension Specification (SW1) CS Assert Extension Specification (SW0) Value 0 1 0 1 0 1 Description No CS2 space CS assert extension CS2 space CS assert extension No CS1 space CS assert extension CS1 space CS assert extension No CS0 space CS assert extension CS0 space CS assert extension (initial value) (initial value) (initial value) Rev.5.00 Sep. 27, 2007 Page 610 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Wait Control Register 1 (WCR1) Bit Item Bit name Initial value H'FFFF8624 8/16/32 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 W33 W32 W31 W30 W23 W22 W21 W20 W13 W12 W11 W10 W03 W02 W01 W00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name CS3 Space Wait Specification (W33 to W30) 0 0 1 Value 0 0 … 1 0 0 … 1 1 0 0 … 1 1 0 0 … 1 1 1 1 15 wait external wait input enabled (initial value) 1 0 0 1 0 1 15 wait external wait input enabled (initial value) No wait (external wait input disabled) 1 wait external wait input enabled 1 0 0 1 0 1 15 wait external wait input enabled (initial value) No wait (external wait input disabled) 1 wait external wait input enabled 1 0 0 1 0 1 15 wait external wait input enabled (initial value) No wait (external wait input disabled) 1 wait external wait input enabled 0 0 0 1 Description No wait (external wait input disabled) 1 wait external wait input enabled R/W Bit 15 to 12 11 to 8 CS2 Space Wait Specification (W23 to W20) 0 0 7 to 4 CS1 Space Wait Specification (W13 to W10) 0 0 3 to 0 CS0 Space Wait Specification (W03 to W00) 0 0 Rev.5.00 Sep. 27, 2007 Page 611 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Wait Control Register 2 (WCR2) Bit Item Bit name Initial value H'FFFF8626 8/16/32 15 ― 0 R 7 ― 0 R 14 ― 0 R 6 ― 0 R Name 13 ― 0 R 5 DDW1 0 R/W 12 ― 0 R 4 DDW0 0 R/W Value 0 0 1 1 0 1 0 1 0 0 … 1 1 1 1 0 0 0 1 11 ― 0 R 3 DSW3 1 R/W 10 ― 0 R 2 DSW2 1 R/W 9 ― 0 R 1 DSW1 1 R/W 8 ― 0 R 0 DSW0 1 R/W R/W Item Bit name Initial value R/W Bit 5, 4 Description 2-cycle (no wait) external wait disabled (initial value) 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled No wait (external wait input disabled) 1 wait (external wait input enabled) 15 wait (external wait input enabled) (initial value) DRAM Space DMA Single Address Mode Access Wait Specification (DDW1, DDW0) 3 to 0 CS Space DMA Single Address Mode Access Wait Specification (DSW3 to DSW0) 0 0 DRAM Area Control Register (DCR) Bit Item Bit name Initial value H'FFFF862A 8/16/32 15 TPC 0 R/W 7 DIW 0 R/W 14 RCD 0 R/W 6 ― 0 R 13 TRAS1 0 R/W 5 BE 0 R/W 12 TRAS0 0 R/W 4 RASD 0 R/W 11 DWW1 0 R/W 3 ― 0 R 10 DWW0 0 R/W 2 SZ0 0 R/W 9 DWR1 0 R/W 1 AMX1 0 R/W 8 DWR0 0 R/W 0 AMX0 0 R/W R/W Item Bit name Initial value R/W Rev.5.00 Sep. 27, 2007 Page 612 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Bit 15 14 13, 12 Name RAS Precharge Cycle Count (TPC) RAS—CAS Delay Cycle Count (RCD) CAS—Before-RAS Refresh RAS Assert Cycle Count (TRAS1 and TRAS0) 0 0 1 1 11, 10 DRAM Write Cycle Wait Count (DWW1 and DWW0) 0 0 1 1 9, 8 DRAM Read Cycle Wait Count (DWR1 and DWR0) 0 0 1 1 7 5 4 2 1, 0 DRAM Idle Cycle Count (DIW) Burst Enable (BE) RAS Down Mode (RASD) DRAM Bus Width Specification (SZ0) DRAM Address Multiplex (AMX1 and AMX0) 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.5 cycles 2.5 cycles 1 cycle 2 cycles 2.5 cycles 3.5 cycles 4.5 cycles 5.5 cycles 2-cycle (no wait) external wait disabled 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled 2-cycle (no wait) external wait disabled 3-cycle (1 wait) external wait disabled 4-cycle (2 wait) external wait enabled 5-cycle (3 wait) external wait enabled No idle cycles 1 idle cycle Burst disabled DRAM high-speed page mode enabled Access DRAM by RAS up mode Access DRAM by RAS down mode Byte (8-bit) Word (16-bit) 9 bit 10 bit 11 bit 12 bit (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) Description (initial value) Rev.5.00 Sep. 27, 2007 Page 613 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Refresh Timer Control/Status Register (RTCSR) Bit Item Bit name Initial value H'FFFF862C 8/16/32 15 ― 0 R 7 ― 0 R 14 ― 0 R 6 CMF 0 R/W Name 13 ― 0 R 5 CMIE 0 R/W 12 ― 0 R 4 CKS2 0 R/W Value 0 1 11 ― 0 R 3 CKS1 0 R/W 10 ― 0 R 2 CKS0 0 R/W 9 ― 0 R 1 RFSH 0 R/W 8 ― 0 R 0 RMD 0 R/W R/W Item Bit name Initial value R/W Bit 6 Description Clear condition: After RTCSR is read when CMF is 1, 0 is written in CMF (initial value) Set condition: RTCNT = RTCOR Note: When both RTCNT and RTCOR are in an initialized state (when values have not been rewritten since initialization, and RTCNT has not had its value changed due to a countup), RTCNT and RTCOR match, as both are H'0000, but in this case CMF is not set. Disables an interrupt request caused by CMF (initial value) Enables an interrupt request caused by CMF 0 1 0 1 0 1 0 1 Stops count-up φ/2 φ/8 φ/32 φ/128 φ/512 φ/2048 φ/4096 Do not refresh DRAM Refresh DRAM CAS-before-RAS refresh Self-refresh (initial value) (initial value) (initial value) Compare Match Flag (CMF) 5 Compare Match Interrupt Enable (CMIE) Clock Select (CKS2 to CKS0) 0 0 1 4 to 2 0 1 1 0 1 1 0 Refresh Control (RFSH) Refresh Mode (RMD) 0 1 0 1 Rev.5.00 Sep. 27, 2007 Page 614 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers BSC Refresh Timer Counter (RTCNT) Bit Item Bit name Initial value H'FFFF862E 8/16/32 15 ― 0 R 14 ― 0 R 13 ― 0 R 12 ― 0 R 11 ― 0 R 10 ― 0 R 9 ― 0 R 8 ― 0 R 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Refresh Time Constant Register (RTCOR) Bit Item Bit name Initial value H'FFFF8630 8/16/32 15 ― 0 R 14 ― 0 R 13 ― 0 R 12 ― 0 R 11 ― 0 R 10 ― 0 R 9 ― 0 R 8 ― 0 R 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.5.00 Sep. 27, 2007 Page 615 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers DMAC DMA Source Address Registers 0, 1 (SAR0, SAR1) H'FFFF86C0 (Channel 0) H'FFFF86D0 (Channel 1) Bit Item Bit name Initial value 16/32 31 ― 30 ― 29 ― 28 ― 27 ― 26 ― 25 ― 24 ― 23 ― ................................... ................................... ................................... ................................... 0 ― R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA Destination Address Registers 0, 1 (DAR0, DAR1) H'FFFF86C4 (Channel 0) H'FFFF86D4 (Channel 1) Bit 16/32 Item Bit name Initial value 31 ― 30 ― 29 ― 28 ― 27 ― 26 ― 25 ― 24 ― 23 ― ................................... ................................... ................................... ................................... 0 ― R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1) H'FFFF86C8 (Channel 0) H'FFFF86D8 (Channel 1) Bit 16/32 Item Bit name Initial value 31 ― 0 R 15 ― 30 ― 0 R 14 ― 29 ― 0 R 13 ― 28 ― 0 R 12 ― 27 ― 0 R 11 ― 26 ― 0 R 10 ― 25 ― 0 R 9 ― 24 ― 0 R 8 ― 23 ― 0 R 7 ― 22 ― 0 R 6 ― 21 ― 0 R 5 ― 20 ― 0 R 4 ― 19 ― 0 R 3 ― 18 ― 0 R 2 ― 17 ― 0 R 1 ― 16 ― 0 R 0 ― R/W Item Bit name Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.5.00 Sep. 27, 2007 Page 616 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers DMAC DMA Channel Control Registers 0, 1 (CHCR0, CHCR1) H'FFFF86CC (Channel 0) H'FFFF86DC (Channel 1) Bit Item Bit name Initial value 8/16/32 31 ― 0 R 23 ― 0 R 15 DM1 0 R/W 7 ― 0 R 30 ― 0 R 22 ― 0 R 14 DM0 0 R/W 6 DS 0 R/W Name 29 ― 0 R 21 ― 0 R 13 SM1 0 R/W 5 TM 0 R/W 28 ― 0 R 20 ― 0 R 12 SM0 0 R/W 4 TS1 0 R/W Value 0 1 0 1 0 1 0 0 1 27 ― 0 R 19 ― 0 R 11 RS3 0 R/W 3 TS0 0 R/W 26 ― 0 R 18 RL 0 R/W 10 RS2 0 R/W 2 IE 0 R/W 25 ― 0 R 17 AM 0 R/W 9 RS1 0 R/W 1 TE 0 R/(W) 24 ― 0 R 16 AL 0 R/W 8 RS0 0 R/W 0 DE 0 R/W R/W Item Bit name Initial value R/W Item Bit name Initial value R/W Item Bit name Initial value R/W Bit 18 17 16 15, 14 Description Output DRAK with active high Output DRAK with active low Outputs DACK during read cycle Outputs DACK during write cycle Active high output Active low output Destination address fixed (initial value) Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Destination address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) (Setting prohibited) (initial value) (initial value) (initial value) Request Check Level (RL) Acknowledge Mode (AM) Acknowledge Level (AL) Destination Address Mode 1, 0 (DM1 and DM0) 1 0 1 Rev.5.00 Sep. 27, 2007 Page 617 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers DMAC Bit 13, 12 Name Source Address Mode 1, 0 (SM1 and SM0) 0 Value 0 1 Description Source address fixed (initial value) Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) Source address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) (Setting prohibited) 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 6 5 4, 3 DREQ Select (DS) Transfer Mode (TM) Transfer Size 1, 0 (TS1, TS0) 0 1 2 Interrupt Enable (IE) 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 External request, dual address mode (initial value) (Prohibited) External request, single address mode. External address space → external device. External request, single address mode. External device → external address space. Auto-request (Prohibited) MTUTGI0A MTUTGI1A MTUTGI2A (Prohibited) (Prohibited) A/D ADI SCI0TXI0 RXI0 SCI1TXI1 RXI1 Low-level detection Falling-edge detection Cycle steal mode Burst mode Specifies byte size (8 bits) Specifies word size (16 bits) Specifies longword size (32 bits) (Prohibited) Interrupt request not generated after DMATCR—specified transfer count (initial value) Interrupt request enabled on completion of DMATCR specified number of transfers (initial value) (initial value) (initial value) 1 0 1 11 to 8 Resource Select 3 to 0 (RS3 to RS0) 0 0 0 1 Rev.5.00 Sep. 27, 2007 Page 618 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers DMAC Bit 1 Name Transfer End Flag (TE) Value 0 Description DMATCR—specified transfer count not ended (initial value) Clear condition: 0 write after TE = 1 read, Power-on reset, standby mode DMATCR specified number of transfers completed Operation of the corresponding channel disabled (initial value) Operation of the corresponding channel enabled 1 0 DMAC Enable (DE) 0 1 DMAC Operation Register (DMAOR) Bit Item Bit name Initial value H'FFFF86B0 8/16/32 15 ― 0 R 7 ― 0 R * 14 ― 0 R 6 ― 0 R 13 ― 0 R 5 ― 0 R 12 ― 0 R 4 ― 0 R 11 ― 0 R 3 ― 0 R 10 ― 0 R 2 AE 0 R/(W) 9 ― 0 R 1 NMIF 0 R/(W)* 8 ― 0 R 0 DME 0 R/W* R/W Item Bit name Initial value R/W Note: 0 write only is valid after 1 is read. Bit 2 Name Address Error Flag (AE) Value 0 1 Description No address error, DMA transfer enabled (initial value) Clearing condition: Write AE = 0 after reading AE = 1 Address error, DMA transfer disabled Setting condition: Address error due to DMAC No NMI interrupt, DMA transfer enabled (initial value) Clearing condition: Write NMIF = 0 after reading NMIF =1 NMI has occurred, DMC transfer prohibited Set condition: NMI interrupt occurrence Disable operation on all channels Enable operation on all channels (initial value) 1 NMI Flag (NMIF) 0 1 0 DMAC Master Enable (DME) 0 1 Rev.5.00 Sep. 27, 2007 Page 619 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Control Register 0 (TCR0) Bit Item Bit name Initial value H'FFFF8260 8/16/32 7 CCLR2 0 R/W Name 6 CCLR1 0 R/W 5 CCLR0 0 R/W Value 0 0 0 1 1 0 1 1 0 0 1 1 0 1 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W Description 1 TPSC1 0 R/W 0 TPSC0 0 R/W R/W Bit 7 to 5 Counter Clear 2 to 0 (CCLR2 to CCLR0) TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input captur TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync.*1 TCNT clear disabled TCNT is cleared by TGRC compare-match or input capture*2 TCNT is cleared by TGRD compare-match or input capture*2 Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync*1 Count on rising edges Count on falling edges Internal clock: count with φ/1 Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input External clock: count with the TCLKC pin input External clock: count with the TCLKD pin input (initial value) (initial value) 4, 3 Clock Edge 1, 0 (CKEG1 and CKEG0)*4 Timer Prescaler 2 to 0 (TPSC2 to TPSC0) 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 X*3 Count on both rising and falling edges 2 to 0 1 0 Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization. 2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because the buffer registers have priority and compare-match/input captures do not occur. 3. X: 0 or 1, don't care. 4. Internal clock edge selection is effective when the input clock is φ/4 or slower. These settings are ignored when φ/1, or the overflow/underflow of another channel is selected for the input clock. Rev.5.00 Sep. 27, 2007 Page 620 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Mode Register 0 (TMDR0) Bit Item Bit name Initial value H'FFFF8261 8/16/32 7 ― 1 R 6 ― 1 R Name 5 BFB 0 R/W 4 BFA 0 R/W Value 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W R/W Bit 5 4 3 to 0 Description TGRB operates normally TGRA operates normally Normal operation Reserved (do not set) PWM mode 1 PWM mode 2 Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) (initial value) (initial value) (initial value) TGRB and TGRD buffer operation TGRA and TGRC buffer operation Buffer Operation B (BFB) Buffer Operation A (BFA) Modes 3 to 0 (MD3 to MD0) Rev.5.00 Sep. 27, 2007 Page 621 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer I/O Control Register 0H (TIOR0H) Bit Item Bit name Initial value H'FFFF8262 8/16/32 7 IOB3 0 R/W Name 6 IOB2 0 R/W 5 IOB1 0 R/W Value 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W Description 1 IOA1 0 R/W 0 IOA0 0 R/W R/W Bit 7 to 4 I/O Control B3 to B0 (IOB3 to IOB0) TGR0B is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch TGR0B is Capture input source is the an input TIOC0B pin capture register Capture input source is channel 1/ count clock Input capture on rising edge Input capture on falling edge Input capture on both edges Input capture on TCNT1 count up/count down Rev.5.00 Sep. 27, 2007 Page 622 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Bit 3 to 0 Name I/O Control A3 to A0 (IOA3 to IOA0) 0 Value 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Capture input source is channel 1/ count clock Input capture on TCNT1 count up/count down TGR0A is Capture input source is the an input TIOC0A pin capture register Description TGR0A is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch Input capture on rising edge Input capture on falling edge Input capture on both edges Rev.5.00 Sep. 27, 2007 Page 623 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer I/O Control Register 0L (TIOR0L) Bit Item Bit name Initial value H'FFFF8263 8/16/32 7 IOD3 0 R/W Name 6 IOD2 0 R/W 5 IOD1 0 R/W Value 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W Description 1 IOC1 0 R/W 0 IOC0 0 R/W R/W Bit 7 to 4 I/O Control D3 to D0 (IOD3 to IOD0) TGR0D is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch TGR0D is Capture input source is the an input TIOC0D pin capture register Capture input source is channel 1/ count clock Input capture on rising edge Input capture on falling edge Input capture on both edges Input capture on TCNT1 count up/count down Rev.5.00 Sep. 27, 2007 Page 624 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Bit 3 to 0 Name I/O Control C3 to C0 (IOC3 to IOC0) 0 Value 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 Notes: 0 1 0 1 0 1 0 Capture input source is channel 1/ count clock Input capture on TCNT1 count up/count down TGR0C is Capture input source is the an input TIOC0C pin capture register Description TGR0C is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch Input capture on rising edge Input capture on falling edge Input capture on both edges 1 1. When the BFB bit of TMDR0 is set to 1 and TGR0D is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. 2. When the BFA bit of TMDR0 is set to 1 and TGR0C is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. Rev.5.00 Sep. 27, 2007 Page 625 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Interrupt Enable Register 0 (TIER0) Bit Item Bit name Initial value H'FFFF8264 8/16/32 7 TTGE 0 R/W 6 ― 0 R Name 5 ― 0 R 4 TCIEV 0 R/W Value 0 1 0 1 0 1 3 TGIED 0 R/W 2 TGIEC 0 R/W Description 1 TGIEB 0 R/W 0 TGIEA 0 R/W R/W Bit 7 4 3 A/D Conversion Start Request Enable (TTGE) Overflow Interrupt Enable (TCIEV) TGR Interrupt Enable D (TGIED) Disable A/D conversion start requests Disable TCFV interrupt requests (TCIV) Enable TCFV interrupt requests (TCIV) (initial value) (initial value) Enable A/D conversion start request generation Disable interrupt requests (TGID) due to the TGFD bit (initial value) Enable interrupt requests (TGID) due to the TGFD bit Disable interrupt requests (TGIC) due to the TGFC bit (initial value) Enable interrupt requests (TGIC) due to the TGFC bit Disable interrupt requests (TGIB) due to the TGFB bit (initial value) Enable interrupt requests (TGIB) due to the TGFB bit Disable interrupt requests (TGIA) due to the TGFA bit (initial value) Enable interrupt requests (TGIA) due to the TGFA bit 2 TGR Interrupt Enable C (TGIEC) 0 1 1 TGR Interrupt Enable B (TGIEB) 0 1 0 TGR Interrupt Enable A (TGIEA) 0 1 Rev.5.00 Sep. 27, 2007 Page 626 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Status Register 0 (TSR0) Bit Item Bit name Initial value H'FFFF8265 8/16/32 7 ― 1 R * 6 ― 1 R 5 ― 0 R 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* R/W Note: Only 0 writes to clear the flags are possible. Bit 4 Name Overflow Flag (TCFV) Value 0 1 Description Clear condition: With TCFV = 1, a 0 write to TCFV after reading it (initial value) Set condition: When the TCNT value overflows (H'FFFF → H'0000) (initial value) Clear condition: With TGFD = 1, a 0 write to TGFD following a read (initial value) Set conditions: • When TGRD is functioning as an output compare register (TCNT = TGRD) • When TGRD is functioning as input capture (the TCNT value is sent to TGRD by the input capture signal) Clear condition: With TGFC = 1, a 0 write to TGFC following a read (initial value) Set conditions: • When TGRC is functioning as an output compare register (TCNT = TGRC) • When TGRC is functioning as input capture (the TCNT value is sent to TGRC by the input capture signal) Clear condition: With TGFB = 1, a 0 write to TGFB following a read (initial value) Set conditions: • When TGRB is functioning as an output compare register (TCNT = TGRB) • When TGRB is functioning as input capture (the TCNT value is sent to TGRB by the input capture signal) 3 Input Capture/Output Compare Flag D (TGFD) 0 1 2 Input Capture/Output Compare Flag C (TGFC) 0 1 1 Input Capture/Output Compare Flag B (TGFB) 0 1 Rev.5.00 Sep. 27, 2007 Page 627 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Bit 0 Name Input Capture/Output Compare Flag A (TGFA) Value 0 1 Description Clear condition: With TGFA = 1, a 0 write to TGFA following a read* (initial value) Set conditions: • When TGRA is functioning as an output compare register (TCNT = TGRA) • When TGRA is functioning as input capture (the TCNT value is sent to TGRA by the input capture signal) Note: * Cleared by DMAC transfer due to TGFA. Timer Counters 0 (TCNT0) Bit Item Bit name Initial value H'FFFF8266 16/32 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Timer General Register 0 (TGR0) H'FFFF8268 (0A) H'FFFF826A (0B) H'FFFF826C (0C) H'FFFF826E (0D) Bit 16/32 Item Bit name Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.5.00 Sep. 27, 2007 Page 628 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Control Register 1 (TCR1) Bit Item Bit name Initial value H'FFFF8280 8/16/32 7 ― 0 R 6 CCLR1 0 R/W Name 5 CCLR0 0 R/W 4 CKEG1 0 R/W Value 0 0 0 1 1 0 1 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W R/W Bit 7 to 5 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync*1 Count on rising edges Count on falling edges Count on both rising and falling edges Internal clock: count with φ/1 Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input Internal clock: count with φ/256 (initial value) (initial value) Counter Clear 2 to 0 (Reserved*2, CCLR1, CCLR0) 4, 3 Clock Edge 1, 0 (CKEG1, CKEG0)*5 4 0 1 0 1 X* 3 0 1 0 1 0 1 0 1 1 0 2 to 0* Timer Prescaler 2 to 0 (TPSC2 to TPSC0) 0 1 0 Notes: 1. 2. 3. 4. 5. 1 Count with the TCNT2 overflow/underflow Setting the SYNC bit of the TSYR to 1 sets the synchronization. The bit 7 of channels 1 is reserved. It always reads 0, and cannot be modified. X: 0 or 1, don't care. These settings are ineffective when channel 1 is in phase counting mode. Internal clock edge selection is effective when the input clock is φ/4 or slower. These settings are ignored when φ/1, or the overflow/underflow of another channel is selected for the input clock. Rev.5.00 Sep. 27, 2007 Page 629 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Mode Register 1 (TMDR1) Bit Item Bit name Initial value H'FFFF8281 8/16/32 7 ― 1 R 6 ― 1 R Name 5 ― 0 R 4 ― 0 R Value 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W R/W Bit 3 to 0 Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) (Initial value) Modes 3 to 0 (MD3 to MD0) Rev.5.00 Sep. 27, 2007 Page 630 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer I/O Control Register 1 (TIOR1) Bit Item Bit name Initial value H'FFFF8282 8/16/32 7 IOB3 0 R/W Name 6 IOB2 0 R/W 5 IOB1 0 R/W Value 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W Description 1 IOA1 0 R/W 0 IOA0 0 R/W R/W Bit 7 to 4 I/O Control B3 to B0 (IOB3 to IOB0) TGR1B is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematc Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematc TGR1B is Capture input an output source is the compare TIOC1B pin register Capture input source TGR0C compare/match input capture Input capture on rising edge Input capture on falling edge Input capture on both edges Input capture on channel 0/TGR0C comparematch/input capture generation Rev.5.00 Sep. 27, 2007 Page 631 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Bit 3 to 0 Name I/O Control A3 to A0 (IOA3 to IOA0) 0 Value 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Capture input source TGR0A compare/match input capture Input capture on channel 0/TGR0A comparematch/input capture generation TGR1A is Capture input source is the an input TIOC1A pin capture register Description TGR1A is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch Input capture on rising edge Input capture on falling edge Input capture on both edges Rev.5.00 Sep. 27, 2007 Page 632 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Interrupt Enable Register 1 (TIER1) Bit Item Bit name Initial value H'FFFF8284 8/16/32 7 TTGE 0 R/W 6 ― 1 R Name 5 TCIEU 0 R/W 4 TCIEV 0 R/W Value 0 1 0 1 0 1 0 1 3 ― 0 R 2 ― 0 R Description 1 TGIEB 0 R/W 0 TGIEA 0 R/W R/W Bit 7 5 4 1 A/D Conversion Start Request Enable (TTGE) Underflow Interrupt Enable (TCIEU) Overflow Interrupt Enable (TCIEV) TGR Interrupt Enable B (TGIEB) Disable A/D conversion start requests Disable UDF interrupt requests (TCIU) Enable UDF interrupt requests (TCIU) Disable TCFV interrupt requests (TCIV) Enable TCFV interrupt requests (TCIV) (initial value) (initial value) (initial value) Enable A/D conversion start request generation Disable interrupt requests (TGIB) due to the TGFB bit (initial value) Enable interrupt requests (TGIB) due to the TGFB bit Disable interrupt requests (TGIA) due to the TGFA bit (initial value) Enable interrupt requests (TGIA) due to the TGFA bit 0 TGR Interrupt Enable A (TGIEA) 0 1 Rev.5.00 Sep. 27, 2007 Page 633 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Status Register 1 (TSR1) Bit Item Bit name Initial value H'FFFF8285 8/16/32 7 TCFD 1 R/W * 6 ― 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 ― 0 R 2 ― 0 R 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* R/W Note: Only 0 writes to clear the flags are possible. Bit 7 5 Name Count Direction Flag (TCFD) Underflow Flag (TCFU) Value 0 1 0 1 TCNT counts down TCNT counts up Description (initial value) Clear condition: With TCFU = 1, a 0 write to TCFU after reading it (initial value) Set condition: When the TCNT value underflows (H'0000 → H'FFFF) Clear condition: With TCFV = 1, a 0 write to TCFV after reading it (initial value) Set condition: When the TCNT value overflows (H'FFFF → H'0000) Clear condition: With TGFB = 1, a 0 write to TGFB following a read (initial value) Set conditions: • When TGRB is functioning as an output compare register (TCNT = TGRB) • When TGRB is functioning as input capture (the TCNT value is sent to TGRB by the input capture signal) Clear condition: With TGFA = 1, a 0 write to TGFA following a read* (initial value) Set conditions: • When TGRA is functioning as an output compare register (TCNT = TGRA) • When TGRA is functioning as input capture (the TCNT value is sent to TGRA by the input capture signal) 4 Overflow Flag (TCFV) 0 1 1 Input Capture/Output Compare Flag B (TGFB) 0 1 0 Input Capture/Output Compare Flag A (TGFA) 0 1 Note: * Cleared by DMAC transfer due to TGFA. Rev.5.00 Sep. 27, 2007 Page 634 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Counters 1 (TCNT1) Bit Item Bit name Initial value H'FFFF8286 16/32 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Timer General Register 1 (TGR1) H'FFFF8288 (1A) H'FFFF828A (1B) Bit 16/32 Item Bit name Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.5.00 Sep. 27, 2007 Page 635 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Control Register 2 (TCR2) Bit Item Bit name Initial value H'FFFF82A0 8/16/32 7 ― 0 R 6 CCLR1 0 R/W Name 5 CCLR0 0 R/W 4 CKEG1 0 R/W Value 0 0 0 1 1 0 1 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W R/W Bit 7 to 5 Description TCNT clear disabled (initial value) TCNT is cleared by TGRA compare-match or input capture TCNT is cleared by TGRB compare-match or input capture Synchronizing clear: TCNT is cleared in synchronization with clear of other channel counters operating in sync*1 Count on rising edges Count on falling edges Count on both rising and falling edges Internal clock: count with φ/1 Internal clock: count with φ/4 Internal clock: count with φ/16 Internal clock: count with φ/64 External clock: count with the TCLKA pin input External clock: count with the TCLKB pin input External clock: count with the TCLKC pin input (initial value) (initial value) Counter Clear 2 to 0 (Reserved*2, CCLR1, CCLR0) 4, 3 Clock Edge 1, 0 (CKEG1 and CKEG0)*5 4 0 1 0 1 X* 3 0 1 0 1 0 1 0 1 1 0 2 to 0* Timer Prescaler 2 to 0 (TPSC2 to TPSC0) 0 1 0 Notes: 1. 2. 3. 4. 5. 1 Internal clock: count with φ/1024 Setting the SYNC bit of the TSYR to 1 sets the synchronization. The bit 7 of channels 2 is reserved. It always reads 0, and cannot be modified. X: 0 or 1, don't care. These settings are ineffective when channel 2 is in phase counting mode. Internal clock edge selection is effective when the input clock is φ/4 or slower. These settings are ignored when φ/1 is selected for the input clock. Rev.5.00 Sep. 27, 2007 Page 636 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Mode Register 2 (TMDR2) Bit Item Bit name Initial value H'FFFF82A1 8/16/32 7 ― 1 R 6 ― 1 R Name 5 ― 0 R 4 ― 0 R Value 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W R/W Bit 3 to 0 Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) Reserved (do not set) (initial value) Modes 3 to 0 (MD3 to MD0) Rev.5.00 Sep. 27, 2007 Page 637 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer I/O Control Register 2 (TIOR2) Bit Item Bit name Initial value H'FFFF82A2 8/16/32 7 IOB3 0 R/W Name 6 IOB2 0 R/W 5 IOB1 0 R/W Value 0 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W Description 1 IOA1 0 R/W 0 IOA0 0 R/W R/W Bit 7 to 4 I/O Control B3 to B0 (IOB3 to IOB0) TGR2B is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch TGR2B is Capture input an input source is the capture TIOC2B pin register Input capture on rising edge Input capture on falling edge Input capture on both edges Input capture on rising edge Input capture on falling edge Input capture on both edges Rev.5.00 Sep. 27, 2007 Page 638 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Bit 3 to 0 Name I/O Control A3 to A0 (IOA3 to IOA0) 0 Value 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Input capture on rising edge Input capture on falling edge Input capture on both edges TGR2A is Capture input source is the an input TIOC2A pin capture register Description TGR2A is Output disabled (initial value) an output Initial output is 0 Output 0 on compare-match compare Output 1 on compare-match register Toggle output on comparematch Output disabled Initial output is 1 Output 0 on compare-match Output 1 on compare-match Toggle output on comparematch Input capture on rising edge Input capture on falling edge Input capture on both edges Rev.5.00 Sep. 27, 2007 Page 639 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Interrupt Enable Register 2 (TIER2) Bit Item Bit name Initial value H'FFFF82A4 8/16/32 7 TTGE 0 R/W 6 ― 1 R Name 5 TCIEU 0 R/W 4 TCIEV 0 R/W Value 0 1 0 1 0 1 0 1 3 ― 0 R 2 ― 0 R Description 1 TGIEB 0 R/W 0 TGIEA 0 R/W R/W Bit 7 5 4 1 A/D Conversion Start Request Enable (TTGE) Underflow Interrupt Enable (TCIEU) Overflow Interrupt Enable (TCIEV) TGR Interrupt Enable B (TGIEB) Disable A/D conversion start requests Disable UDF interrupt requests (TCIU) Enable UDF interrupt requests (TCIU) Disable TCFV interrupt requests (TCIV) Enable TCFV interrupt requests (TCIV) (initial value) (initial value) (initial value) Enable A/D conversion start request generation Disable interrupt requests (TGIB) due to the TGFB bit (initial value) Enable interrupt requests (TGIB) due to the TGFB bit Disable interrupt requests (TGIA) due to the TGFA bit (initial value) Enable interrupt requests (TGIA) due to the TGFA bit 0 TGR Interrupt Enable A (TGIEA) 0 1 Rev.5.00 Sep. 27, 2007 Page 640 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Status Register 2 (TSR2) Bit Item Bit name Initial value H'FFFF82A5 8/16/32 7 TCFD 1 R * 6 ― 1 R 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 ― 0 R 2 ― 0 R 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* R/W Note: Only 0 writes to clear the flags are possible. Bit 7 5 Name Count Direction Flag (TCFD) Underflow Flag (TCFU) Value 0 1 0 1 TCNT counts down TCNT counts up Description (initial value) Clear condition: With TCFU = 1, a 0 write to TCFU after reading it (initial value) Set condition: When the TCNT value underflows (H'0000 → H'FFFF) Clear condition: With TCFV = 1, a 0 write to TCFV after reading it (initial value) Set condition: When the TCNT value overflows (H'FFFF → H'0000) Clear condition: With TGFB = 1, a 0 write to TGFB following a read (initial value) Set conditions: • When TGRB is functioning as an output compare register (TCNT = TGRB) • When TGRB is functioning as input capture (the TCNT value is sent to TGRB by the input capture signal) Clear condition: With TGFA = 1, a 0 write to TGFA following a read* (initial value) Set conditions: • When TGRA is functioning as an output compare register (TCNT = TGRA) • When TGRA is functioning as input capture (the TCNT value is sent to TGRA by the input capture signal) 4 Overflow Flag (TCFV) 0 1 1 Input Capture/Output Compare Flag B (TGFB) 0 1 0 Input Capture/Output Compare Flag A (TGFA) 0 1 Note: * Cleared by DMAC transfer due to TGFA. Rev.5.00 Sep. 27, 2007 Page 641 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Counters 2 (TCNT2) Bit Item Bit name Initial value H'FFFF82A6 16/32 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Timer General Register 2 (TGR2) H'FFFF82A8 (2A) H'FFFF82AA (2B) Bit 16/32 Item Bit name Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Timer Start Register (TSTR) Bit Item Bit name Initial value H'FFFF8240 8/16/32 7 ― 0 R 6 ― 0 R Name 5 ― 0 R Value 0 1 4 ― 0 R 3 ― 0 R 2 CST2 0 R/W Description 1 CST1 0 R/W 0 CST0 0 R/W R/W Bit 2 to 0 Note: Counter Start 2 to 0 (CST2 to CST0) TCNTn count is halted TCNTn count (initial value) n = 2 to 0 If 0 is written to the CST bit during operation with the TIOC pin in output status, the counter stops, but the TIOC pin output compare output level is maintained. If a write is done to the TIOR register while the CST bit is a 0, the pin output level is updated to the established initial output value. Rev.5.00 Sep. 27, 2007 Page 642 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers MTU Timer Synchro Register (TSYR) Bit Item Bit name Initial value H'FFFF8241 8/16/32 7 ― 0 R 6 ― 0 R Name 5 ― 0 R Value 0 4 ― 0 R 3 ― 0 R 2 SYNC2 0 R/W Description 1 SYNC1 0 R/W 0 SYNC0 0 R/W R/W Bit 2 to 0 Timer Synchronization 2 to 0 (SYNC2 to SYNC0) Timer counter (TCNTn) independent operation (TCNTn preset/clear unrelated to other channels) (initial value) Timer counter synchronous operation*1 TCNTn synchronous preset/ synchronous clear*2 possible 1 Notes: n = 2 to 0 1. Minimum of two channel SYNC bits must be set to 1 for synchronous operation. 2. TCNT counter clear sources (CCLR2 to CCLR0 bits of the TCR register) must be set in addition to the SYNC bit in order to have clear synchronization. Rev.5.00 Sep. 27, 2007 Page 643 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers WDT Timer Counter (TCNT) H'FFFF8610 (Write)*1 H'FFFF8611 (Read)*2 Bit Item Bit name Initial value ― 7 0 6 0 5 0 4 0 3 0 2 0 R/W 1 0 R/W 0 0 R/W R/W R/W R/W R/W R/W R/W Notes: 1. Write by word transfer. It cannot be written in byte or longword. 2. Read by byte transfer. It cannot be read in word or longword. Timer Control/Status Register (TCSR) Bit Item Bit name Initial value H'FFFF8610 ― 7 OVF 0 6 WT/IT 0 5 TME 0 4 ― 0 3 ― 0 2 CKS2 0 1 CKS1 0 0 CKS0 0 R/W Note: * R/(W)* R/W R/W R R R/W R/W R/W The TCSR differs from other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for details. Bit 7 Name Overflow Flag (OVF) Value 0 1 Description No overflow of TCNT in interval timer mode (initial value) Cleared by reading OVF, then writing 0 in OVF TCNT overflow in the interval timer mode Interval timer mode: interval timer interrupt request to the CPU when TCNT overflows (initial value) Watchdog timer mode: WDTOVF signal output externally when TCNT overflows*1 Timer disabled: TCNT is initialized to H'00 and count-up stops (initial value) Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. 6 Timer Mode Select (WT/IT) 0 1 5 Timer Enable (TME) 0 1 Rev.5.00 Sep. 27, 2007 Page 644 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers WDT Description Bit 2 to 0 Name Clock Select 2 to 0 (CKS2 to CKS0) 0 Value 0 1 1 0 1 Notes: 0 1 0 1 0 1 0 φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 Clock Source Overflow Interval*2 (φ = 28.7 MHz) 573.4 μs 1.1 ms 2.3 ms 4.6 ms 9.2 ms 36.7 ms (Initial value) 17.9 μs 1 φ/8192 73.4 ms 1. Section 11.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in the watchdog timer mode. 2. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. H'FFFF8612 (Write) H'FFFF8613 (Read) Bit ― Reset Control/Status Register (RSTCSR) Item Bit name Initial value 7 WOVF 0 6 RSTE 0 5 ― 0 4 ― 1 3 ― 1 R 2 ― 1 R 1 ― 1 R 0 ― 1 R R/W Note: * Bit 7 R/(W)* R/W R R Only 0 can be written in bit 7 to clear the flag. Name Watchdog Timer Overflow Flag (WOVF) Value 0 Description No TCNT overflow in watchdog timer mode (initial value) Cleared when software reads WOVF, then writes 0 in WOVF Set by TCNT overflow in watchdog timer mode Not reset when TCNT overflows (initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. Reset when TCNT overflows 1 6 Reset Enable (RSTE) 0 1 Rev.5.00 Sep. 27, 2007 Page 645 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Receive Data Register (RDR) H'FFFF81A5 (Channel 0) H'FFFF81B5 (Channel 1) Bit Item Bit name Initial value 8/16 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R R/W Transmit Data Register (TDR) H'FFFF81A3 (Channel 0) H'FFFF81B3 (Channel 1) Bit 8/16 Item Bit name Initial value 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W R/W Rev.5.00 Sep. 27, 2007 Page 646 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Serial Mode Register (SMR) H'FFFF81A0 (Channel 0) H'FFFF81B0 (Channel 1) Bit Item Bit name Initial value 8/16 7 C/A 0 R/W 6 CHR 0 R/W Name 5 PE 0 R/W Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W Description 1 CKS1 0 R/W 0 CKS0 0 R/W R/W Bit 7 6 5 4 3 2 1, 0 Communication Mode (C/A) Character Length (CHR) Parity Enable (PE) Parity Mode (O/E) Stop Bit Length (STOP) Multiprocessor Mode (MP) Clock Select 1 and 0 (CKS1 and CKS0) Asynchronous mode Clocked synchronous mode Eight-bit data Seven-bit data*1 Parity bit not added or checked Parity bit added and checked*2 Even parity*3 Odd parity*4 One stop bit*5 Two stop bits*6 Multiprocessor function disabled Multiprocessor format selected φ φ/4 φ/16 (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) (initial value) Notes: 1. 2. 3. 4. 5. 6. 1 φ/64 When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. In transmitting, a single bit of 1 is added at the end of each transmitted character. In transmitting, two bits of 1 are added at the end of each transmitted character. Rev.5.00 Sep. 27, 2007 Page 647 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Serial Control Register (SCR) H'FFFF81A2 (Channel 0) H'FFFF81B2 (Channel 1) Bit Item Bit name Initial value 8/16 7 TIE 0 R/W 6 RIE 0 R/W Name 5 TE 0 R/W Value 0 1 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W Description 1 CKE1 0 R/W 0 CKE0 0 R/W R/W Bit 7 Transmit Interrupt Enable (TIE) Receive Interrupt Enable (RIE) Transmit-data-empty interrupt request (TXI) is disabled *1 (initial value) Transmit-data-empty interrupt request (TXI) is enabled Receive-data-full interrupt (RXI) and receive-error interrupt (initial value) (ERI) requests are disabled*2 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Transmitter disabled*3 Transmitter enabled*4 Receiver disabled*5 Receiver enabled*6 Multiprocessor interrupts are disabled (initial value) (normal receive operation) MPIE is cleared when the MPIE bit is cleared to 0, or the multiprocessor bit (MPB) is set to 1 in receive data. Multiprocessor interrupts are enabled*7 Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. Transmit-end interrupt (TEI) requests are disabled*8 (initial value) Transmit-end interrupt (TEI) requests are enabled*8 (initial value) (initial value) 6 0 1 5 4 3 Transmit Enable (TE) Receive Enable (RE) Multiprocessor Interrupt Enable (MPIE) 0 1 0 1 0 1 2 Transmit-End Interrupt Enable (TEIE) 0 1 Rev.5.00 Sep. 27, 2007 Page 648 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Description Bit 1, 0 Name Clock Enable 1 and 0 (CKE1 and CKE0)*9 Value 0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined)*10 Internal clock, SCK pin used for clock output*11 External clock, SCK pin used for clock input*12 Clock synchronous mode Internal clock, SCK pin used for synchronous clock output*10 Internal clock, SCK pin used for synchronous clock output External clock, SCK pin used for synchronous clock input 0 1 1 1 0 1 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. External clock, SCK pin used External clock, SCK pin used for synchronous clock input for clock input*12 The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format in the SMR before setting TE to 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. Select the receive format in the SMR before setting RE to 1. The SCI does not transfer receive data from the RSR to the RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCR are set to 1), and allows the FER and ORER bits to be set. The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. Initial value. The output clock frequency is the same as the bit rate. The input clock frequency is 16 times the bit rate. Rev.5.00 Sep. 27, 2007 Page 649 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Serial Status Register (SSR) H'FFFF81A4 (Channel 0) H'FFFF81B4 (Channel 1) Bit Item Bit name Initial value 8/16 7 TDRE 1 R/(W)* * 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W R/W Note: The only value that can be written is a 0 to clear the flag. Bit 7 Name Transmit Data Register Empty (TDRE) Value 0 Description TDR contains valid transmit data Clearing conditions: • When 0 is written to TDRE after reading TDRE = 1 • When DMAC writes data in TDR TDR does not contain valid transmit data (initial value) Setting conditions: • Power-on reset or standby mode • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR RDR does not contain valid received data (initial value) Clearing conditions: • Power-on reset or standby mode • When 0 is written to RDRF after reading RDRF = 1 • When DMAC reads data from RDR RDR contains valid received data Setting condition: When serial reception ends normally and receive data is transferred from RSR to RDR 1 6 Receive Data Register Full (RDRF) 0 1 Rev.5.00 Sep. 27, 2007 Page 650 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Bit 5 Name Overrun Error (ORER) Value 0 Description Receiving is in progress or has ended normally*1 (initial value) Clearing conditions: • Power-on reset or standby mode • When 0 is written to ORER after reading ORER = 1 A receive overrun error occurred Setting condition: When the next serial reception is completed while RDRF = 1*2 Receiving is in progress or has ended normally*3 (initial value) Clearing conditions: • Power-on reset or standby mode • When 0 is written to FER after reading FER = 1 A receive framing error occurred*4 Setting condition: When at the end of an SCI receive operation the final stop bit of the receive data is checked and its value*4 is 0 Receiving is in progress or has ended normally*5 (initial value) Clearing conditions: • Power-on reset or standby mode • When 0 is written to PER after reading PER = 1 A receive parity error occurred*6 Setting condition: PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) 1 4 Framing Error (FER) 0 1 3 Parity Error (PER) 0 1 Rev.5.00 Sep. 27, 2007 Page 651 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Bit 2 Name Transmit End (TEND) Value 0 Description Transmission is in progress Clearing conditions: • When 0 is written to TDRE after reading TDRE = 1 • When DMAC writes data in TDR End of transmission (initial value) Clearing conditions: • Power-on reset or standby mode • When the TE bit in SCR is 0 • When TDRE = at transmission of the last bit of a 1-byte serial transmit character Multiprocessor bit value in receive data is 0*7 (initial value) Multiprocessor bit value in receive data is 1 Multiprocessor bit value in transmit data is 0 (initial value) 1 1 0 Notes: Multiprocessor Bit (MPB) Multiprocessor Bit Transfer (MPBT) 0 1 0 1 Multiprocessor bit value in transmit data is 1 1. The ORER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the clock synchronous mode, serial transmitting is disabled. 3. The FER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 4. When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. In addition, serial transmission cannot continue in clock synchronous mode. 5. The PER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 6. When a parity error occurs, the SCI transfers the receive data into the RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. In addition, serial transmission cannot continue in clock synchronous mode. 7. If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. Rev.5.00 Sep. 27, 2007 Page 652 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers SCI Bit Rate Register (BRR) H'FFFF81A1 (Write) H'FFFF81B1 (Read) Bit Item Bit name Initial value 8/16 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W R/W Rev.5.00 Sep. 27, 2007 Page 653 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers A/D (SH7014) A/D Data Registers A to H (ADDRA to ADDRH) H'FFFF83F0 H'FFFF83F2 H'FFFF83F4 H'FFFF83F6 H'FFFF83F8 H'FFFF83FA H'FFFF83FC H'FFFF83FE Bit Item Bit name Initial value 8/16 15 ― 0 R 14 ― 0 R 13 ― 0 R 12 ― 0 R 11 ― 0 R 10 ― 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W A/D Control/Status Register (ADCSR) Bit Item Bit name Initial value H'FFFF83E0 8/16 7 ADF 0 R/(W)* * 6 ADIE 0 R/W 5 ADST 0 R/W 4 CKS 0 R/W 3 GRP 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W R/W Note: Only 0 can be written to bit 7 to clear the flag. Bit 7 Name A/D End Flag (ADF) Value 0 Description Clear conditions: (initial value) • With ADF = 1, by reading the ADF flag then writing 0 in ADF • When the DMAC is activated by an ADI interrupt Set conditions: • Single mode: When A/D conversion ends after conversion for all designated channels* • Scan mode: After one round of A/D conversion for all specified channels Disables interrupt requests (ADI) after A/D conversion ends (initial value) Enables interrupt requests (ADI) after A/D conversion ends 1 6 A/D Interrupt Enable (ADIE) 0 1 Rev.5.00 Sep. 27, 2007 Page 654 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers A/D (SH7014) Bit 5 Name A/D Start (ADST) Value 0 1 Description A/D conversion halted (initial value) • Single mode: Start A/D conversion. Automatically cleared to 0 after conversion for the designated channel ends. • Scan mode: Start A/D conversion. Continuous conversion until 0 cleared by software. Conversion time = 40 states (high speed A/D converter standard clock = φ/2) (initial value) Conversion time = 80 states (when φ/4 is selected) Select mode Group mode Select mode (GRP = 0) Group mode (GRP = 1) 0 0 1 1 0 1 Note: * 0 1 0 1 0 1 0 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 (Initial value) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN0 to AN4 AN0 to AN5 AN0 to AN6 AN0 to AN7 (initial value) 4 Clock Select (CKS) 0 1 3 2 to 0 Group Mode (GRP) Channel Select 2 to 0 (CH2 to CH0) 0 1 During buffer operation, this is not set until operation of the specified buffer has ended. Rev.5.00 Sep. 27, 2007 Page 655 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers A/D (SH7014) A/D Control Register (ADCR) Bit Item Bit name Initial value H'FFFF83E1 8/16 7 ― 0 R 6 PWR 0 R/W Name 5 TRGS1 0 R/W Value 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 4 TRGS0 0 R/W 3 SCAN 0 R/W 2 DSMP 0 R/W Description 1 BUFE1 0 R/W 0 BUFE0 0 R/W R/W Bit 6 5, 4 Power (PWR) Timer Trigger Select 1, 0 (TRGS1, TRGS0) Low power conversion mode High speed start mode Enable A/D conversion start by software (initial value) (initial value) Enables A/D conversion start by MTU conversion start trigger Reserved Single mode Scan mode Normal sampling operation Simultaneous sampling operation Normal operation ADDRA and ADDRB buffer operation: conversion result → ADDRA → ADDRB ADDRA and ADDRC, also ADDRB and ADDRD buffer operation: conversion result 1 → ADDRA → ADDRC, conversion result 2 → ADDRB → ADDRD (ADDRC and ADDRD are buffer registers) ADDRA to ADDRD buffer operation: conversion result → ADDRA → ADDRB → ADDRC → ADDRD (ADDRB to ADDRD are buffer registers) (initial value) (initial value) (initial value) 3 2 1, 0 Scan Mode (SCAN) Simultaneous Sampling (DSMP) Buffer Enable 1, 0 (BUFE1, BUFE0) 1 Rev.5.00 Sep. 27, 2007 Page 656 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers A/D (SH7016, SH7017) A/D Data Register A to D (ADDRA to ADDRD) H'FFFF8420 H'FFFF8422 H'FFFF8424 H'FFFF8426 Bit Item Bit name Initial value 8/16 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 ― 0 R 4 ― 0 R 3 ― 0 R 2 ― 0 R 1 ― 0 R 0 ― 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W A/D Control/Status Register (ADCSR) Bit Item Bit name Initial value H'FFFF8428 8/16 7 ADF 0 R/(W)* * 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W R/W Note: Only 0 can be written to bit 7 to clear the flag. Bit 7 Name A/D End Flag (ADF) Value 0 Description Clear conditions: (initial value) 1. Writing 0 to ADF after reading ADF with ADF =1 2. When registers of the mid-speed converter are accessed after the DMAC is activated by ADI interrupt Set conditions: 1. Single mode: When A/D conversion is complete 2. Scan mode: When A/D conversion of all designated channels are complete Disables interrupt request (ADI) due to completion of A/D conversion (initial value) Enables interrupt request (ADI) due to completion of A/D conversion 1 6 A/D Interrupt Enable (ADIE) 0 1 Rev.5.00 Sep. 27, 2007 Page 657 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers A/D (SH7016, SH7017) Bit 5 Name A/D Start (ADST) Value 0 1 Description A/D conversion halted (initial value) 1. Single mode: Starts A/D conversion. Automatically clears to 0 when conversion of the designated channel is complete 2. Scan mode: Starts A/D conversion. Continuous conversion until cleared to 0 by the software Single mode Scan mode Conversion time = 266 states (max) (initial value) Conversion time = 134 states (max) Single Mode 0 0 1 1 0 1 0 1 0 1 0 1 0 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 (Initial value) Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 (initial value) 4 3 2 to 0 Scan Mode (SCAN) Clock Select (CKS) Channel select 2 to 0 (CH2 to CH0) 0 1 0 1 A/D Control Register (ADCR) Bit Item Bit name Initial value H'FFFF8429 8/16 7 TRGE 0 R/W 6 ― 1 R Name 5 ― 1 R Value 0 1 4 ― 1 R 3 ― 1 R 2 ― 1 R Description 1 ― 1 R 0 ― 1 R R/W Bit 7 Trigger Enable (TRGE) Disables A/D conversion start of MTU trigger (initial value) Starts A/D conversion on MTU trigger Rev.5.00 Sep. 27, 2007 Page 658 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers CMT Compare Match Timer Start Register (CMSTR) Bit Item Bit name Initial value H'FFFF83D0 8/16/32 15 ― 0 R 7 ― 0 R 14 ― 0 R 6 ― 0 R Name 13 ― 0 R 5 ― 0 R 12 ― 0 R 4 ― 0 R Value 0 1 0 1 11 ― 0 R 3 ― 0 R 10 ― 0 R 2 ― 0 R Description 9 ― 0 R 1 STR1 0 R/W 8 ― 0 R 0 STR0 0 R/W R/W Item Bit name Initial value R/W Bit 1 0 Count Start 1 (STR1) Count Start 0 (STR0) CMCNT1 count operation halted CMCNT1 count operation CMCNT0 count operation halted CMCNT0 count operation (initial value) (initial value) Compare Match Timer Control/Status Register (CMCSR) H'FFFF83D2 (Channel 0) H'FFFF83D8 (Channel 1) Bit 8/16/32 Item Bit name Initial value 15 ― 0 R 7 CMF 0 R/(W)* * 14 ― 0 R 6 CMIE 0 R/W 13 ― 0 R 5 ― 0 R 12 ― 0 R 4 ― 0 R 11 ― 0 R 3 ― 0 R 10 ― 0 R 2 ― 0 R 9 ― 0 R 1 CKS1 0 R/W 8 ― 0 R 0 CKS0 0 R/W R/W Item Bit name Initial value R/W Note: The only value that can be written is a 0 to clear the flag. Bit 7 Name Compare Match Flag (CMF) Value 0 Description CMCNT and CMCOR values have not matched Clear condition: Write a 0 to CMF after reading a 1 from it (initial value) CMCNT and CMCOR values have matched Compare match interrupts (CMI) disabled Compare match interrupts (CMI) enabled (initial value) 1 6 Compare Match Interrupt Enable (CMIE) 0 1 Rev.5.00 Sep. 27, 2007 Page 659 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers CMT Bit 1, 0 Name Clock Select 1, 0 (CKS1, CKS0) Value 0 0 1 1 0 1 0 1 φ/8 φ/32 φ/128 φ/512 Description (initial value) Compare Match Timer Counter (CMCNT) H'FFFF83D4 (Channel 0) H'FFFF83DA (Channel 1) Bit 8/16/32 Item Bit name Initial value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Compare Match Timer Constant Register (CMCOR) H'FFFF83D6 (Channel 0) H'FFFF83DC (Channel 1) Bit 8/16/32 Item Bit name Initial value 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev.5.00 Sep. 27, 2007 Page 660 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port A I/O Register L (PAIORL) H'FFFF8386 H'FFFF8387 Bit Item Bit name Initial value 8/16/32 15 PA15IOR 0 R/W 7 PA7IOR 0 R/W * 14 0 R/W 6 PA6IOR 0 R/W 13 0 R/W 5 PA5IOR 0 R/W 12 0 R/W 4 PA4IOR 0 R/W 11 0 R/W 3 PA3IOR 0 R/W 10 0 R/W 2 PA2IOR 0 R/W 9 PA9IOR 0 R/W 1 PA1IOR 0 R/W 8 PA8IOR 0 R/W 0 PA0IOR 0 R/W PA14IOR* PA13IOR* PA12IOR* PA11IOR* PA10IOR* R/W Item Bit name Initial value R/W Note: Reserved bit on the SH7014. H'FFFF838C H'FFFF838D Bit 8/16/32 Port A Control Register L1 (PACRL1) Item Bit name Initial value 15 ― 0 R 7 ― 0 14 PA15MD 0(1)*1 R/W 6 PA15MD*2 0 13 ― 0 R 5 ― 0 12 PA15MD*2 0 R/W 4 PA15MD*2 0 11 ― 0 R 3 PA9MD1 0 R/W 10 PA15MD*2 0 R/W 2 PA9MD0 0 R/W 9 ― 0 R 1 PA8MD1 0 R/W 8 PA15MD*2 0 R/W 0 PA8MD0 0 R/W R/W Item Bit name Initial value R/W R R/W R R/W Notes: 1. Bit 14 is initialized to 1 in extended mode. 2. Reserved bit on the SH7014. Rev.5.00 Sep. 27, 2007 Page 661 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Bit 14 Name PA15 Mode (PA15MD) Value 0 1 12 PA14 Mode (PA14MD) 0 1 10 PA13 Mode (PA13MD) 0 1 8 PA12 Mode (PA12MD) 0 1 6 PA11 Mode (PA11MD) 0 1 4 PA10 Mode (PA10MD) 0 1 3, 2 PA9 Mode 1, 0 (PA9MD1 and PA9MD0) 0 1 1, 0 PA8 Mode 1, 0 (PA8MD1 and PA8MD0) 0 1 0 1 0 1 0 1 0 1 Description General input/output (PA15) (single chip mode initial value) Clock output (CK) (extended mode initial value) General input/output (PA14) (RD in on-chip ROM invalid mode) General input/output (PA13) (WRH in on-chip ROM invalid mode) Most significant side write output (WRH) (PA13 in single chip mode) General input/output (PA12) (WRL in on-chip ROM invalid mode) Least significant side write output (WRL) (PA12 in single chip mode) General input/output (PA11) (CS1 in on-chip ROM invalid mode) General input/output (PA10) (CS0 in on-chip ROM invalid mode) General input/output (PA9) MTU timer clock input (TCLKD) Interrupt request input (IRQ3) Reserved General input/output (PA8) MTU timer clock input (TCLKC) Interrupt request input (IRQ2) Reserved (initial value) (initial value) (initial value) (initial value) Read output (RD) (PA14 in single chip mode) (initial value) Chip select output (CS1) (PA11 in single chip mode) (initial value) (initial value) Chip select output (CS0) (PA10 in single chip mode) Rev.5.00 Sep. 27, 2007 Page 662 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port A Control Register L2 (PACRL2) H'FFFF838E H'FFFF838F Bit Item Bit name Initial value 8/16/32 15 PA7MD1 0 R/W 7 ― 0 R 14 PA7MD0 0 R/W 6 PA3MD 0 R/W Name 13 PA6MD1 0 R/W 5 PA2MD1 0 R/W Value 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 12 PA6MD0 0 R/W 4 PA2MD0 0 R/W 11 PA5MD1 0 R/W 3 ― 0 R 10 PA5MD0 0 R/W 2 PA1MD 0 R/W Description 9 ― 0 R 1 ― 0 R 8 PA4MD 0 R/W 0 PA0MD 0 R/W R/W Item Bit name Initial value R/W Bit 15, 14 PA7 Mode 1, 0 (PA7MD1 and PA7MD0) General input/output (PA7) MTU timer clock input (TCLKB) (initial value) Chip select output (CS3) (PA7 in single-chip mode) Reserved General input/output (PA6) MTU timer clock input (TCLKA) Chip select output (CS2) (PA6 in single-chip mode) Reserved General input/output (PA5) Serial clock input/output (SCK1) DMA transfer request received input (DREQ1) (PA5 in single-chip mode) Interrupt request input (IRQ1) General input/output (PA4) Transmit data output (TxD1) General input/output (PA3) Receive data input (RxD1) (initial value) (initial value) (initial value) (initial value) (initial value) 13, 12 PA6 Mode 1, 0 (PA6MD1 and PA6MD0) 0 11, 10 PA5 Mode 1, 0 (PA5MD1 and PA5MD0) 0 8 6 5, 4 PA4 Mode (PA4MD) PA3 Mode (PA3MD) PA2 Mode 1, 0 (PA2MD1 and PA2MD0) 0 1 0 1 0 1 0 1 0 1 General input/output (PA2) Serial clock input/output (SCK0) DMA transfer request received input (DREQ0) (PA2 in single-chip mode) Interrupt request input (IRQ0) Rev.5.00 Sep. 27, 2007 Page 663 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Bit 2 0 Name PA1 Mode (PA1MD) PA0 Mode (PA0MD) Value 0 1 0 1 Description General input/output (PA1) Transmit data output (TxD0) General input/output (PA0) Receive data input (RxD0) (initial value) (initial value) Port B I/O Register (PBIOR) H'FFFF8394 H'FFFF8395 Bit 8/16/32 Item Bit name Initial value 15 ― 0 R 7 PB7IOR 0 R/W 14 ― 0 R 6 PB6IOR 0 R/W 13 ― 0 R 5 PB5IOR 0 R/W 12 ― 0 R 4 PB4IOR 0 R/W 11 ― 0 R 3 PB3IOR 0 R/W 10 ― 0 R 2 PB2IOR 0 R/W 9 PB9IOR 0 R/W 1 PB1IOR* 0 R/W 8 PB8IOR 0 R/W 0 PB0IOR* 0 R/W R/W Item Bit name Initial value R/W Note: * Reserved bit on the SH7014. Rev.5.00 Sep. 27, 2007 Page 664 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port B Control Register 1 (PBCR1) H'FFFF8398 H'FFFF8399 Bit Item Bit name Initial value 8/16/32 15 ― 0 R 7 ― 0 R 14 ― 0 R 6 ― 0 R Name 13 ― 0 R 5 ― 0 R Value 0 1 0 1 0 1 0 1 1 0 1 12 ― 0 R 4 ― 0 R 11 ― 0 R 3 PB9MD1 0 R/W 10 ― 0 R 2 PB9MD0 0 R/W Description 9 ― 0 R 1 PB8MD1 0 R/W 8 ― 0 R 0 PB8MD0 0 R/W R/W Item Bit name Initial value R/W Bit 3, 2 PB9 Mode 1, 0 (PB9MD1 and PB9MD0) General input/output (PB9) Interrupt request input (IRQ7) (initial value) Address output (A21) (PB9 in single-chip mode) Reserved General input/output (PB8) Interrupt request input (IRQ6) Address output (A20) (PB8 in single-chip mode) Wait state request input (WAIT) (PB8 in single-chip mode) (initial value) 1, 0 PB8 Mode 1, 0 (PB8MD1 and PB8MD0) 0 Rev.5.00 Sep. 27, 2007 Page 665 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port B Control Register 2 (PBCR2) H'FFFF839A H'FFFF839B Bit Item Bit name Initial value 8/16/32 15 PB7MD1 0 R/W 7 PB3MD1 0 R/W 14 PB7MD0 0 R/W 6 PB3MD0 0 R/W 13 PB6MD1 0 R/W 5 PB2MD1 0 R/W 12 PB6MD0 0 R/W 4 PB2MD0 0 R/W 11 PB5MD1 0 R/W 3 ― 0 R 10 PB5MD0 0 R/W 2 PB1MD* 0 R/W 9 PB4MD1 0 R/W 1 ― 0 R 8 PB4MD0 0 R/W 0 PB0MD* 0 R/W R/W Item Bit name Initial value R/W Note: Bit 15, 14 * Reserved bit on the SH7014. Name PB7 Mode 1, 0 (PB7MD1 and PB7MD0) Value 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 Reserved Address output (A19) (PB7 in single-chip mode) Reserved General input/output (PB6) Reserved Address output (A18) (PB6 in single-chip mode) Reserved General input/output (PB5) Interrupt request input (IRQ3) Reserved Read/write output (RDWR) General input/output (PB4) Interrupt request input (IRQ2) Reserved Column address strobe (CASH) (PB4 in single-chip mode) General input/output (PB3) Interrupt request input (IRQ1) Reserved Column address strobe (CASL) (PB3 in single-chip mode) (initial value) (initial value) (initial value) (initial value) Description General input/output (PB7) (initial value) 13, 12 PB6 Mode 1, 0 (PB6MD1 and PB6MD0) 0 11, 10 PB5 Mode 1, 0 (PB5MD1 and PB5MD0) 0 9, 8 PB4 Mode 1, 0 (PB4MD1 and PB4MD0) 0 7, 6 PB3 Mode 1, 0 (PB3MD1 and PB3MD0) 0 1 0 1 0 1 Rev.5.00 Sep. 27, 2007 Page 666 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Bit 5, 4 Name PB2 Mode 1, 0 (PB2MD1 and PB2MD0) Value 0 1 2 PB1 Mode (PB1MD) 0 1 0 PB0 Mode (PB0MD) 0 1 0 1 0 1 Description General input/output (PB2) Interrupt request input (IRQ0) Reserved Row address strobe (RAS) (PB2 in single-chip mode) General input/output (PB1) (A17 in on-chip ROM invalid mode) General input/output (PB0) (A16 in on-chip ROM invalid mode) (initial value) (initial value) Address output (A17) (PB1 in single chip mode) (initial value) Address output (A16) (PB0 in single chip mode) Port C I/O Register (PCIOR) (SH7016, SH7017) H'FFFF8396 H'FFFF8397 Bit 8/16/32 Item 15 Bit name Initial value 14 PC14IOR 0 R/W 6 PC6IOR 0 R/W 13 PC13IOR 0 R/W 5 PC5IOR 0 R/W 12 PC12IOR 0 R/W 4 PC4IOR 0 R/W 11 PC11IOR 0 R/W 3 PC3IOR 0 R/W 10 PC10IOR 0 R/W 2 PC2IOR 0 R/W 9 PC9IOR 0 R/W 1 PC1IOR 0 R/W 8 PC8IOR 0 R/W 0 PC0IOR 0 R/W PC15IOR 0 R/W 7 PC7IOR 0 R/W R/W Item Bit name Initial value R/W Rev.5.00 Sep. 27, 2007 Page 667 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port C Control Register (PCCR) (SH7016, SH7017) H'FFFF839C H'FFFF839D Bit Item Bit name Initial value 8/16/32 15 PC15MD 0 R/W 7 PC7MD 0 R/W 14 PC14MD 0 R/W 6 PC6MD 0 R/W Name 13 PC13MD 0 R/W 5 PC5MD 0 R/W 12 PC12MD 0 R/W 4 PC4MD 0 R/W Value 0 1 11 PC11MD 0 R/W 3 PC3MD 0 R/W 10 PC10MD 0 R/W 2 PC2MD 0 R/W Description 9 PC9MD 0 R/W 1 PC1MD 0 R/W 8 PC8MD 0 R/W 0 PC0MD 0 R/W R/W Item Bit name Initial value R/W Bit 15 PC15 Mode (PC15MD) General input/output (PC15) (A15 in on-chip ROM invalid mode) General input/output (PC14) (A14 in on-chip ROM invalid mode) General input/output (PC13) (A13 in on-chip ROM invalid mode) General input/output (PC12) (A12 in on-chip ROM invalid mode) General input/output (PC11) (A11 in on-chip ROM invalid mode) General input/output (PC10) A10 in on-chip ROM invalid mode) General input/output (PC9) (A9 in on-chip ROM invalid mode) (initial value) Address output (A15) (PC15 in single chip mode) (initial value) 14 PC14 Mode (PC14MD) 0 1 Address output (A14) (PC14 in single chip mode) (initial value) 13 PC13 Mode (PC13MD) 0 1 Address output (A13) (PC13 in single chip mode) (initial value) 12 PC12 Mode (PC12MD) 0 1 Address output (A12) (PC12 in single chip mode) (initial value) 11 PC11 Mode (PC11MD) 0 1 Address output (A11) (PC11 in single chip mode) (initial value) 10 PC10 Mode (PC10MD) 0 1 Address output (A10) (PC10 in single chip mode) (initial value) 9 PC9 Mode (PC9MD) 0 1 Address output (A9) (PC9 in single chip mode) Rev.5.00 Sep. 27, 2007 Page 668 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Bit 8 Name PC8 Mode (PC8MD) Value 0 1 7 PC7 Mode (PC7MD) 0 1 6 PC6 Mode (PC6MD) 0 1 5 PC5 Mode (PC5MD) 0 1 4 PC4 Mode (PC4MD) 0 1 3 PC3 Mode (PC3MD) 0 1 2 PC2 Mode (PC2MD) 0 1 1 PC1 Mode (PC1MD) 0 1 0 PC0 Mode (PC0MD) 0 1 Description General input/output (PC8) A8 in on-chip ROM invalid mode) General input/output (PC7) (A7 in on-chip ROM invalid mode) General input/output (PC6) (A6 in on-chip ROM invalid mode) General input/output (P5) (A5 in on-chip ROM invalid mode) General input/output (PC4) (A4 in on-chip ROM invalid mode) General input/output (PC3) (A3 in on-chip ROM invalid mode) General input/output (PC2) (A2 in on-chip ROM invalid mode) General input/output (PC1) (A1 in on-chip ROM invalid mode) General input/output (PC0) (A0 in on-chip ROM invalid mode) (initial value) Address output (A8) (PC8 in single chip mode) (initial value) Address output (A7) (PC7 in single chip mode) (initial value) Address output (A6) (PC6 in single chip mode) (initial value) Address output (A5) (PC5 in single chip mode) (initial value) Address output (A4) (PC4 in single chip mode) (initial value) Address output (A3) (PC3 in single chip mode) (initial value) Address output (A2) (PC2 in single chip mode) (initial value) Address output (A1) (PC1 in single chip mode) (initial value) Address output (A0) (PC0 in single chip mode) Port D I/O Register L (PDIORL) (SH7016, SH7017) H'FFFF83A6 H'FFFF83A7 Bit 8/16/32 Item Bit name Initial value 15 PD15IOR 0 R/W 7 PD7IOR 0 R/W 14 PD14IOR 0 R/W 6 PD6IOR 0 R/W 13 PD13IOR 0 R/W 5 PD5IOR 0 R/W 12 PD12IOR 0 R/W 4 PD4IOR 0 R/W 11 PD11IOR 0 R/W 3 PD3IOR 0 R/W 10 PD10IOR 0 R/W 2 PD2IOR 0 R/W 9 PD9IOR 0 R/W 1 PD1IOR 0 R/W 8 PD8IOR 0 R/W 0 PD0IOR 0 R/W R/W Item Bit name Initial value R/W Rev.5.00 Sep. 27, 2007 Page 669 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port D Control Register L (PDCRL) (SH7016, SH7017) H'FFFF83AC H'FFFF83AD Bit Item Bit name Initial value 8/16/32 15 PD15MD 0 R/W 7 PD7MD 0 R/W 14 PD14MD 0 R/W 6 PD6MD 0 R/W Name 13 PD13MD 0 R/W 5 PD5MD 0 R/W 12 PD12MD 0 R/W 4 PD4MD 0 R/W Value 0 1 11 PD11MD 0 R/W 3 PD3MD 0 R/W 10 PD10MD 0 R/W 2 PD2MD 0 R/W Description 9 PD9MD 0 R/W 1 PD1MD 0 R/W 8 PD8MD 0 R/W 0 PD0MD 0 R/W R/W Item Bit name Initial value R/W Bit 15 PD15 Mode (PD15MD) General input/output (PD15) (D15 in on-chip ROM invalid mode) General input/output (PD14) (D14 in on-chip ROM invalid mode) General input/output (PD13) (D13 in on-chip ROM invalid mode) General input/output (PD12) (D12 in on-chip ROM invalid mode) General input/output (PD11) (D11 in on-chip ROM invalid mode) General input/output (PD10) (D10 in on-chip ROM invalid mode) General input/output (PD9) (D9 in on-chip ROM invalid mode) (initial value) Data input/output (D15) (PD15 in single chip mode) (initial value) 14 PD14 Mode (PD14MD) 0 1 Data input/output (D14) (PD14 in single chip mode) (initial value) 13 PD13 Mode (PD13MD) 0 1 Data input/output (D13) (PD13 in single chip mode) (initial value) 12 PD12 Mode (PD12MD) 0 1 Data input/output (D12) (PD12 in single chip mode) (initial value) 11 PD11 Mode (PD11MD) 0 1 Data input/output (D11) (PD11 in single chip mode) (initial value) 10 PD10 Mode (PD10MD) 0 1 Data input/output (D10) (PD10 in single chip mode) (initial value) 9 PD9 Mode (PD9MD) 0 1 Data input/output (D9) (PD9 in single chip mode) Rev.5.00 Sep. 27, 2007 Page 670 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Bit 8 Name PD8 Mode (PD8MD) Value 0 1 7 PD7 Mode (PD7MD) 0 1 6 PD6 Mode (PD6MD) 0 1 5 PD5 Mode (PD5MD) 0 1 4 PD4 Mode (PD4MD) 0 1 3 PD3 Mode (PD3MD) 0 1 2 PD2 Mode (PD2MD) 0 1 1 PD1 Mode (PD1MD) 0 1 0 PD0 Mode (PD0MD) 0 1 Description General input/output (PD8) (D8 in on-chip ROM invalid mode) General input/output (PD7) (D7 in on-chip ROM invalid mode) General input/output (PD6) (D6 in on-chip ROM invalid mode) General input/output (PD5) (D5 in on-chip ROM invalid mode) General input/output (PD4) (D4 in on-chip ROM invalid mode) General input/output (PD3) (D3 in on-chip ROM invalid mode) General input/output (PD2) (D2 in on-chip ROM invalid mode) General input/output (PD1) (D1 in on-chip ROM invalid mode) General input/output (PD0) (D0 in on-chip ROM invalid mode) (initial value) Data input/output (D8) (PD8 in single chip mode) (initial value) Data input/output (D7) (PD7 in single chip mode) (initial value) Data input/output (D6) (PD6 in single chip mode) (initial value) Data input/output (D5) (PD5 in single chip mode) (initial value) Data input/output (D4) (PD4 in single chip mode) (initial value) Data input/output (D3) (PD3 in single chip mode) (initial value) Data input/output (D2) (PD2 in single chip mode) (initial value) Data input/output (D1) (PD1 in single chip mode) (initial value) Data input/output (D0) (PD0 in single chip mode) Rev.5.00 Sep. 27, 2007 Page 671 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port E I/O Register (PEIOR) H'FFFF83B4 H'FFFF83B5 Bit Item Bit name Initial value 8/16/32 15 PE15IOR 0 R/W 7 PE7IOR 0 R/W 14 PE14IOR 0 R/W 6 PE6IOR 0 R/W 13 PE13IOR 0 R/W 5 PE5IOR 0 R/W 12 PE12IOR 0 R/W 4 PE4IOR 0 R/W 11 PE11IOR 0 R/W 3 PE3IOR 0 R/W 10 PE10IOR 0 R/W 2 PE2IOR 0 R/W 9 PE9IOR 0 R/W 1 PE1IOR 0 R/W 8 PE8IOR 0 R/W 0 PE0IOR 0 R/W R/W Item Bit name Initial value R/W Port E Control Register 1 (PECR1) H'FFFF83B8 H'FFFF83B9 Bit 8/16/32 Item Bit name Initial value 15 PE15MD1 0 R/W 7 ― 0 R 14 PE15MD0 0 R/W 6 ― 0 R Name 13 PE14MD1 0 R/W 5 ― 0 R Value 0 1 0 1 0 1 12 PE14MD0 0 R/W 4 ― 0 R 11 ― 0 R 3 ― 0 R 10 ― 0 R 2 ― 0 R Description 9 ― 0 R 1 ― 0 R 8 ― 0 R 0 ― 0 R R/W Item Bit name Initial value R/W Bit 15, 14 PE15 Mode 1, 0 (PE15MD1 and PE15MD0) Input/output (PE15) Reserved DMA request received output (DACK1) (PE15 in single-chip mode) Reserved Input/output (PE14) Reserved DMA request received output (DACK0) (PE14 in single-chip mode) Address hold output (AH) (PE14 in single-chip mode) (initial value) 13, 12 PE14 Mode 1, 0 (PE14MD1 and PE14MD0) 0 1 0 1 0 1 (initial value) Rev.5.00 Sep. 27, 2007 Page 672 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Port E Control Register 2 (PECR2) H'FFFF83BA H'FFFF83BB Bit Item Bit name Initial value 8/16/32 15 ― 0 R 7 PE3MD1 0 R/W 14 PE7MD 0 R/W 6 PE3MD0 0 R/W Name 13 ― 0 R 5 PE2MD1 0 R/W Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 12 PE6MD 0 R/W 4 PE2MD0 0 R/W 11 ― 0 R 3 PE1MD1 0 R/W 10 PE5MD 0 R/W 2 PE1MD0 0 R/W Description 9 ― 0 R 1 PE0MD1 0 R/W 8 PE4MD 0 R/W 0 PE0MD0 0 R/W R/W Item Bit name Initial value R/W Bit 14 12 10 8 7, 6 PE7 Mode (PE7MD) PE6 Mode (PE6MD) PE5 Mode (PE5MD) PE4 Mode (PE4MD) PE3 Mode 1, 0 (PE3MD1 and PE3MD0) General input/output (PE7) General input/output (PE6) General input/output (PE5) General input/output (PE4) General input/output (PE3) DREQ1 request received output (DRAK1) (PE3 in single-chip mode) Reserved General input/output (PE2) DREQ1 request received input (PE2 in single-chip mode) Reserved (initial value) (initial value) (initial value) (initial value) (initial value) MTU input capture input/output compare output (TIOC2B) MTU input capture input/output compare output (TIOC2A) MTU input capture input/output compare output (TIOC1B) MTU input capture input/output compare output (TIOC1A) MTU input capture input/output compare output (TIOC0D) 5, 4 PE2 Mode 1, 0 (PE2MD1 and PE2MD0) 0 1 0 1 0 1 (initial value) MTU input capture input/output compare output (TIOC0C) Rev.5.00 Sep. 27, 2007 Page 673 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers PFC Bit 3, 2 Name PE1 Mode 1, 0 (PE1MD1 and PE1MD0) Value 0 1 0 1 0 1 1, 0 PE0 Mode 1, 0 (PE0MD1 and PE0MD0) 0 1 0 1 0 1 Description General input/output (PE1) DREQ0 request received output (DRAK0) (PE1 in single-chip mode) Reserved General input/output (PE0) DREQ0 request received output (DRAK0) (PE0 in single-chip mode) Reserved (initial value) MTU input capture input/output compare output (TIOC0A) (initial value) MTU input capture input/output compare output (TIOC0B) Rev.5.00 Sep. 27, 2007 Page 674 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers I/O Port A Data Register L (PADRL) H'FFFF8382 H'FFFF8383 Bit Item Bit name Initial value 8/16/32 15 PA15DR 0 R/W 7 PA7DR 0 R/W 14 PA14DR* 0 R/W 6 PA6DR 0 R/W 13 PA13DR* 0 R/W 5 PA5DR 0 R/W 12 PA12DR* 0 R/W 4 PA4DR 0 R/W 11 PA11DR* 0 R/W 3 PA3DR 0 R/W 10 PA10DR* 0 R/W 2 PA2DR 0 R/W 9 PA9DR 0 R/W 1 PA1DR 0 R/W 8 PA8DR 0 R/W 0 PA0DR 0 R/W R/W Item Bit name Initial value R/W Note: * Reserved bit on the SH7014. Port B Data Register (PBDR) H'FFFF8390 H'FFFF8391 Bit 8/16/32 Item Bit name Initial value 15 ― 0 R 7 PB7DR 0 R/W 14 ― 0 R 6 PB6DR 0 R/W 13 ― 0 R 5 PB5DR 0 R/W 12 ― 0 R 4 PB4DR 0 R/W 11 ― 0 R 3 PB3DR 0 R/W 10 ― 0 R 2 DB2DR 0 R/W 9 PB9DR 0 R/W 1 PB1DR* 0 R/W 8 PB8DR 0 R/W 0 PB0DR* 0 R/W R/W Item Bit name Initial value R/W Note: * Reserved bit on the SH7014. Rev.5.00 Sep. 27, 2007 Page 675 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers I/O Port C Data Register (PCDR) (SH7016, SH7017) H'FFFF8392 H'FFFF8393 Bit Item Bit name Initial value 8/16/32 15 PC15DR 0 R/W 7 PC7DR 0 R/W 14 PC14DR 0 R/W 6 PC6DR 0 R/W 13 PC13DR 0 R/W 5 PC5DR 0 R/W 12 PC12DR 0 R/W 4 PC4DR 0 R/W 11 PC11DR 0 R/W 3 PC3DR 0 R/W 10 PC10DR 0 R/W 2 PC2DR 0 R/W 9 PC9DR 0 R/W 1 PC1DR 0 R/W 8 PC8DR 0 R/W 0 PC0DR 0 R/W R/W Item Bit name Initial value R/W Port D Data Register L (PDDRL) (SH7016, SH7017) H'FFFF83A2 H'FFFF83A3 Bit 8/16/32 Item Bit name Initial value 15 PD15DR 0 R/W 7 PD7DR 0 R/W 14 PD14DR 0 R/W 6 PD6DR 0 R/W 13 PD13DR 0 R/W 5 PD5DR 0 R/W 12 PD12DR 0 R/W 4 PD4DR 0 R/W 11 PD11DR 0 R/W 3 PD3DR 0 R/W 10 PD10DR 0 R/W 2 PD2DR 0 R/W 9 PD9DR 0 R/W 1 PD1DR 0 R/W 8 PD8DR 0 R/W 0 PD0DR 0 R/W R/W Item Bit name Initial value R/W Port E Data Register (PEDR) H'FFFF83B0 H'FFFF83B1 Bit 8/16/32 Item Bit name Initial value 15 PE15DR 0 R/W 7 PE7DR 0 R/W 14 PE14DR 0 R/W 6 PE6DR 0 R/W 13 PE13DR 0 R/W 5 PE5DR 0 R/W 12 PE12DR 0 R/W 4 PE4DR 0 R/W 11 PE11DR 0 R/W 3 PE3DR 0 R/W 10 PE10DR 0 R/W 2 PE2DR 0 R/W 9 PE9DR 0 R/W 1 PE1DR 0 R/W 8 PE8DR 0 R/W 0 PE0DR 0 R/W R/W Item Bit name Initial value R/W Rev.5.00 Sep. 27, 2007 Page 676 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers I/O Port F Data Register (PFDR) Bit Item Bit name Initial value H'FFFF83B3 8 7 PF7DR * R * 6 PF6DR * R 5 PF5DR * R 4 PF4DR * R 3 PF3DR * R 2 PF2DR * R 1 PF1DR * R 0 PF0DR * R R/W Note: Initial values are dependent on the status of the pins at the time of the reads. Rev.5.00 Sep. 27, 2007 Page 677 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers FLASH Flash Memory Control Register 1 (FLMCR1) Bit Item Bit name Initial value H'FFFF8580 8 7 FWE 1/0 R 6 SWE 0 R/W Name 5 ESU 0 R/W 4 PSU 0 R/W Value 0 1 3 EV 0 R/W 2 PV 0 R/W Description 1 E 0 R/W 0 P 0 R/W R/W Bit 7 Flash Write Enable Bit (FWE) When a low level is input to the FWP pin (hardware-protected state) When a high level is input to the FWP pin Writes disabled Writes enabled Setting condition: When FWE = 1 Erase setup cleared (initial value) Erase setup Setting condition: When FWE = 1 and SWE = 1 Program setup cleared (initial value) Program setup Setting condition: When FWE = 1 and SWE = 1 Erase-verify mode cleared Transition to erase-verify mode Program-verify mode cleared (initial value) Transition to program-verify mode Setting condition: When FWE = 1 and SWE = 1 Erase mode cleared (initial value) Transition to erase mode Setting condition: When FWE = 1, SWE = 1, and ESU =1 Program mode cleared (initial value) Transition to program mode Setting condition: When FWE = 1, SWE = 1, and PSU =1 (initial value) (initial value) 6 Software Write Enable Bit (SWE) 0 1 5 Erase Setup Bit (ESU) 0 1 4 Program Setup Bit (PSU) 0 1 3 2 Erase-Verify (EV) Program-Verify (PV) 0 1 0 1 1 Erase (E) 0 1 0 Program (P) 0 1 Rev.5.00 Sep. 27, 2007 Page 678 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers FLASH Flash Memory Control Register 2 (FLMCR2) Bit Item Bit name Initial value H'FFFF8581 8 7 FLER 0 R 6 — 0 R Name 5 — 0 R Value 0 4 — 0 R 3 — 0 R 2 — 0 R Description 1 — 0 R 0 — 0 R R/W Bit 7 Flash Memory Error (FLER) Flash memory is operating normally. Flash memory program/erase protection (error protection) is disabled. Clearing condition: Power-on reset (initial value) An error has occurred during flash memory programming/erasing. Flash memory program/erase protection (error protection) is enabled. Setting condition: See section 18.8.3, Error Protection. 1 Erase Block Register 1 (EBR1) Bit Item Bit name Initial value H'FFFF8582 8 7 EB7 0 R/W 6 EB6 0 R/W Name 5 EB5 0 R/W 4 EB4 0 R/W Value 0 1 3 EB3 0 R/W 2 EB2 0 R/W Description 1 EB1 0 R/W 0 EB0 0 R/W R/W Bit 7 to 0 EB7 to EB0 Corresponding block is erase-protected (initial value) Corresponding block is not erase-protected Rev.5.00 Sep. 27, 2007 Page 679 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers FLASH RAM Emulation Register (RAMER) Bit Item Bit name Initial value H'FFFF8628 8/16/32 15 — 0 R 7 — 0 R 14 — 0 R 6 — 0 R Name 13 — 0 R 5 — 0 R 12 — 0 R 4 — 0 R Value 0 11 — 0 R 3 — 0 R 10 — 0 R 2 RAMS 0 R/W Description 9 — 0 R 1 RAM1 0 R/W 8 — 0 R 0 RAM0 0 R/W R/W Item Bit name Initial value R/W Bit 2 RAM Select (RAMS) Emulation not selected Program/erase-protection of all flash memory blocks is disabled (initial value) Emulation selected Program/erase-protection of all flash memory blocks is enabled 1 Bit2 RAMS 0 1 1 1 1 Legend: Bit1 RAM1 * 0 0 1 1 Bit0 RAM0 * 0 1 0 1 Address H'FFF800 to H'FFFBFF H'01F000 to H'01F3FF H'01F400 to H'01F7FF H'01F800 to H'01FBFF H'01FC00 to H'01FFFF EB4 (1 kB) EB5 (1 kB) EB6 (1 kB) EB7 (1 kB) Block Name RAM area 1 kB *: Don't care Rev.5.00 Sep. 27, 2007 Page 680 of 716 REJ09B0398-0500 Appendix A On-Chip Supporting Module Registers Power-Down State Standby Control Register (SBYCR) Bit Item Bit name Initial value H'FFFF8614 8/16/32 7 SBY 0 R/W 6 HIZ 0 R/W Name 5 ― 0 R Value 0 1 4 ― 1 R 3 ― 1 R 2 ― 1 R Description 1 ― 1 R 0 ― 1 R R/W Bit 7 Standby (SBY) Executing SLEEP instruction puts the LSI into sleep mode (initial value) Executing SLEEP instruction puts the LSI into standby mode Holds pin status while in standby mode (initial value) Keeps pin at high impedance while in standby mode 6 Port High Impedance (HIZ) 0 1 Rev.5.00 Sep. 27, 2007 Page 681 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams Appendix B I/O Port Block Diagrams PAR RES PAn/RXDm R Q PAnDR D C PAW Standby Q HIZ SCI RXDm Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Notes: n = 0, 3 m = 0, 1 Figure B.1 PAn/RXm Block Diagram Rev.5.00 Sep. 27, 2007 Page 682 of 716 REJ09B0398-0500 Internal data bus PFC Q PAnMD Q PAnIOR SBYCR Appendix B I/O Port Block Diagrams PAn/SCKm/DREQm/IRQm RES Q PAnDR D C PAW Standby Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Notes: n = 2, 5 m = 0, 1 Figure B.2 PAn/SCKm/DREQm/IRQm Block Diagram Rev.5.00 Sep. 27, 2007 Page 683 of 716 REJ09B0398-0500 Internal data bus PAR SCKmOUT PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Q HIZ INTC IRQm DMAC DREQm SCI SCKmIN Appendix B I/O Port Block Diagrams PA6/TCLKA/CS2, PA7/TCLKB/CS3 RES R Q PAnDR D C PAW Standby Q HIZ MTU TCLKA, TCLKB Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Note: n = 6, 7 Figure B.3 PA6/TCLKA/CS2, PA7/TCLKB/CS3 (SH7014, Mask) Block Diagram Rev.5.00 Sep. 27, 2007 Page 684 of 716 REJ09B0398-0500 Internal data bus PAR CS2, CS3 PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Appendix B I/O Port Block Diagrams On-chip flash memory WE PAR Internal data bus PA7/TCLKB/CS3 Programmer mode RES Q PA7DR D C PAW CS3 PFC Q PA7MD0 Q PA7MD1 Q PA7IOR SBYCR Standby Q HIZ MTU TCLKB Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Figure B.4 PA7/TCLKB/CS3 Block Diagram (F-ZTAT Version) Rev.5.00 Sep. 27, 2007 Page 685 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PA8/TCLKC/IRQ2, PA9/TCLKD/IRQ3 RES R Q PAnDR D C PAW Internal data bus PAR PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ MTU TCLKC, TLCKD INTC IRQ2, IRQ3 Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Note: n = 8, 9 Figure B.5 PAn/TCLKm/IRQx Block Diagram (SH7014, Mask) Rev.5.00 Sep. 27, 2007 Page 686 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams On-chip flash memory OE, CE PAR Internal data bus PA8/TCLKC/IRQ2 PA9/TCLKD/IRQ3 Programmer mode RES Q PAnDR D C PAW PFC Q PAnMD0 Q PAnMD1 Q PAnIOR SBYCR Standby Q HIZ MTU TCLKC,D INTC IRQ2,IRQ3 Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Note: n = 8, 9 Figure B.6 PAn/TCLKm/IRQx Block Diagram (F-ZTAT Version) Rev.5.00 Sep. 27, 2007 Page 687 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams RES PAn/TXDm R Q PAnDR D C PAW Standby Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Notes: n = 1, 4 m = 0, 1 Figure B.7 PAn/TXDm Block Diagram Rev.5.00 Sep. 27, 2007 Page 688 of 716 REJ09B0398-0500 Internal data bus TXDm PFC Q PAnMD Q PAnIOR SBYCR Q HIZ PAR Appendix B I/O Port Block Diagrams RES PA15/CK R Q PA15DR D C PAW Standby Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Note: * SH7016, SH7017 only Figure B.8 PA15/CK Block Diagram Rev.5.00 Sep. 27, 2007 Page 689 of 716 REJ09B0398-0500 Internal data bus PAR CK Single-chip mode* MCU mode 2 MCU mode 1 MCU mode 0 PFC Q PA15MD Q PA15IOR SBYCR Q HIZ Appendix B I/O Port Block Diagrams PAn/XXX RES R Q PAnDR D C PAW Bus right release Standby Legend: PAR: Port A read signal PAW: Port A write signal RES: Reset signal Note: n = 10 to 14 Figure B.9 PAn/XXX Block Diagram (SH7016, SH7017) Rev.5.00 Sep. 27, 2007 Page 690 of 716 REJ09B0398-0500 Internal data bus CS0, CS1, WRL, WRH, RD Single-chip mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Q PAnMD Q PAnIOR SBYCR Q HIZ PAR Appendix B I/O Port Block Diagrams On-chip flash memory* A16 PBR Programmer mode PB0/A16 RES R Q PB0DR D C PBW Internal data bus A16 Single-chip mode MCU mode 0 MCU mode 1 MCU mode 2 Bus right release PFC Q PB0MDO Q PB0IOR Standby SBYCR Q HIZ Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Note: * F-ZTAT version only Figure B.10 PB0/A16 Block Diagram (SH7016, SH7017) Rev.5.00 Sep. 27, 2007 Page 691 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams RES R PB1/A17 Q PB1DR D C PBW Internal data bus A17 Single-chip mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Q PB1MD Q PB1IOR Standby SBYCR Q HIZ PBR Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.11 PB1/A17 Block Diagram (SH7016, SH7017) Rev.5.00 Sep. 27, 2007 Page 692 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams RES R PBn/Am Q PBnDR D C PBW Am PFC Q PBnMD0 Q PBnMD1 Internal data bus Q PBnIOR SBYCR Standby Q HIZ PBR Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Notes: n = 6, 7 m = 18, 19 Figure B.12 PBn/Am Block Diagram Rev.5.00 Sep. 27, 2007 Page 693 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams RES PBn/IRQm/CASx Q PBnDR D C PBW CASL,CASH PFC Q PBnMD0 Q PBnMD1 Internal data bus Q PBnIOR SBYCR Standby Q HIZ INTC IRQm PBR Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Notes: n = 3, 4 m = 1, 2 Figure B.13 PBn/IRQm/CASx Block Diagram Rev.5.00 Sep. 27, 2007 Page 694 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams RES PB8/IRQ6/A20/WAIT Q PB8DR D C PBW A20 PFC Q PB8MD0 Q PB8MD1 Internal data bus Q PB8IOR SBYCR Standby Q HIZ BSC WAIT INTC IRQ6 PBR Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.14 PB8/IRQ6/A20/WAIT Block Diagram Rev.5.00 Sep. 27, 2007 Page 695 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams RES PB9/IRQ7/A21 Q PB9DR D C PBW A21 PFC Q PB9MD0 Q PB9MD1 Internal data bus PBR Q PB9IOR SBYCR Standby Q HIZ INTC IRQ7 Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Figure B.15 PB9/IRQ7/A21 Block Diagram Rev.5.00 Sep. 27, 2007 Page 696 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PBR RES PBn/IRQm/XXXX Q PBnDR D C PBW RAS,RDWR PFC Q PBnMD0 Q PBnMD1 Internal data bus Q PBnIOR SBYCR Standby Q HIZ INTC IRQm Legend: PBR: Port B read signal PBW: Port B write signal RES: Reset signal Notes: n = 2, 5 m = 0, 3 Figure B.16 PBn/IRQm/XXXX Block Diagram Rev.5.00 Sep. 27, 2007 Page 697 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams On-chip flash memory* An PCR Programmer mode PCn/An RES R Q PCnDR D C PCW Internal data bus An Single-chip mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Q PCnMD Q PCnIOR Standby SBYCR Q HIZ Legend: PCR: Port C read signal PCW: Port C write signal RES: Reset signal Notes: n = 0 to 15 * F-ZTAT version only Figure B.17 PCn/An Block Diagram Rev.5.00 Sep. 27, 2007 Page 698 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams On-chip flash memory* Dn PDR Programmer mode RES R Q PDnDR D C PDW PDn/Dn Internal data bus Dn Dout Single-chip mode MCU mode 0 MCU mode 1 MCU mode 2 PFC Q PDnMD0 Q PDnIOR Standby SBYCR Q HIZ SLEEP Din Legend: PDR: Port D read signal PDW: Port D write signal RES: Reset signal Dout: Data bus output timing signal Din: Data bus input timing signal Notes: n = 0 to 15 * F-ZTAT version only Figure B.18 PDn/Dn Block Diagram (SH7016, SH7017) Rev.5.00 Sep. 27, 2007 Page 699 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PER RES PEn Q PEnDR D C PEW PFC Q PEnIOR SBYCR Standby Legend: PER: Port E read signal PEW: Port E write signal RES: Reset signal Note: n = 8 to 13 Q HIZ Figure B.19 PEn Block Diagram Rev.5.00 Sep. 27, 2007 Page 700 of 716 REJ09B0398-0500 Internal data bus Appendix B I/O Port Block Diagrams PE14/DACK0/AH RES Q PE14DRD C PEW Internal data bus PER DRAK0 AH PFC Q PE14MD0 Q PE14MD1 Q PE14IOR SBYCR Standby Legend: PER: Port E read signal PEW: Port E write signal RES: Reset signal Q HIZ Figure B.20 PE14/DACK0/AH Block Diagram Rev.5.00 Sep. 27, 2007 Page 701 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PER RES PE15/DACK1 Q PE15DRD C PEW DRAK1 PFC Q PE15MD0 Q PE15MD1 Internal data bus Q PE15IOR SBYCR Standby Q HIZ Legend: PER: Port E read signal PEW: Port E write signal RES: Reset signal Figure B.21 PE15/DACK1 Block Diagram Rev.5.00 Sep. 27, 2007 Page 702 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PER Internal data bus RES PEn/TIOCXX Q PEnDR C D PEW TIOC1A, TIOC1B, TIOC2A, TIOC2B PFC Q PEnMD Q PEnIOR SBYCR Standby Q HIZ MTU TIOC1A, TIOC1B, TIOC2A, TIOC2B Legend: PER: Port E read signal PEW: Port E write signal RES: Reset signal Note: n = 4 to 7 Figure B.22 PEn/TIOCXX Block Diagram Rev.5.00 Sep. 27, 2007 Page 703 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PER Internal data bus PEn/TIOCXX/DRAKm RES Q PEnDR C D PEW TIOC0B TIOC0D DRAKm PFC Q PEnMD0 Q PEnMD1 Q PEnIOR SBYCR Standby Q HIZ MTU Legend: PER: Port E read signal PEW: Port E write signal RES: Reset signal Notes: n = 1, 3 m = 0, 1 TIOC0B TIOC0D Figure B.23 PEn/TIOCXX/DRAKm Block Diagram Rev.5.00 Sep. 27, 2007 Page 704 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PER Internal data bus PEn/TIOCXX/DREQm RES Q PEnDR D C PEW TIOC0A TIOC0C PFC Q PEnMD0 Q PEnMD1 Q PEnIOR Standby SBYCR Q HIZ MTU TIOC0A TIOC0C DMA DREQm Legend: PER: Port E read signal PEW: Port E write signal RES: Reset signal Notes: n = 0, 2 m = 0, 1 Figure B.24 PEn/TIOCXX/DREQm Block Diagram Rev.5.00 Sep. 27, 2007 Page 705 of 716 REJ09B0398-0500 Appendix B I/O Port Block Diagrams PFR PFn/ANn Internal data bus Standby SBYCR Q HIZ AD ANn Legend: PFR: Port F read signal Note: n = 0 to 7 Figure B.25 PFn/ANn Block Diagram Rev.5.00 Sep. 27, 2007 Page 706 of 716 REJ09B0398-0500 Appendix C Pin States Appendix C Pin States C.1 Pin States Pin States in Reset, and Power-Down Modes Pin modes Pin Function Class Clock System control Pin Name CK RES WDTOVF Interrupt NMI IRQ0 to IRQ3, IRQ6, IRQ7 Address bus Data bus Bus control A0 to A21 D0 to D15 WAIT RDWR, RAS CASH, CASL RD CS0, CS1 CS2, CS3 WRH, WRL AH DMAC DACK0, DACK1 DRAK0, DRAK1 DREQ0, DREQ1 MTU TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B TCLKA to TCLKD SCI SCK0, SCK1 TXD0, TXD1 RXD0, RXD1 A/D converter AN0 to AN7 Reset Power-On O I O I Z O Z Z Z Z H H Z H Z Z Z Z Z Power-Down Standby H* I O I Z Z Z Z O O Z Z Z Z Z O* O* Z K* 1 1 1 1 Table C.1 Sleep O I O I I O I/O I H H H H H H L O O I I/O Z Z Z Z Z Z Z O* Z Z 1 I I/O O I I Rev.5.00 Sep. 27, 2007 Page 707 of 716 REJ09B0398-0500 Appendix C Pin States Pin modes Pin Function Class I/O Port Pin Name PA0 to PA9, PA15 PB0 to PB9 PC0 to PC15 PD0 to PD15 PE0 to PE15* PF0 to PF7 2 Reset Power-On Z Power-Down Standby K* 1 Sleep K Z Z I Legend: I: Input O: Output H: High-level output L: Low-level output Z: High impedance K: Input pin with high impedance, output pin mode maintained. Notes: 1. If the standby control register port high-impedence bits are set to 1, output pins become high impedence. 2. When an emulator is used, PE9 and PE11 to PE15 become high-impedance in standby mode. Rev.5.00 Sep. 27, 2007 Page 708 of 716 REJ09B0398-0500 Appendix C Pin States C.2 Pin States of Bus Related Signals Pin Settings for On-Chip Peripheral Modules On-Chip Peripheral Module 16-Bit Space Table C.2 Pin Name CS0 to CS3 RAS* 1 2 On-Chip ROM On-Chip (SH7016/17 only) RAM H H H H H L R W H ⎯ H ⎯ H ⎯ Address Hi-Z Hi-Z H H H H H L H H H H H H Address Hi-Z Hi-Z Lower 8-Bit Space Upper Byte Byte H H H H H L H H H H H H Address Hi-Z Hi-Z H H H H H L H H H H H H Address Hi-Z Hi-Z H H H H H L H H H H H H Address Hi-Z Hi-Z Word/ Longword H H H H H L H H H H H H Address Hi-Z Hi-Z CASH* CASL* RDWR AH RD WRH WRL 2 R W R W A21 to A0 D15 to D8 D7 to D0 Legend: R: Read W: Write Notes: 1. L asserted in RAS down state or refresh state. 2. L asserted in refresh state. Rev.5.00 Sep. 27, 2007 Page 709 of 716 REJ09B0398-0500 Appendix C Pin States Table C.3 Pin Settings for Normal External Space Normal External Space 16-Bit Space Pin Name CS0 to CS2 CS3 RAS* 1 2 8-Bit Space Valid H H H H H L R W L H H H H L Address Hi-Z Data Upper Word Valid H H H H H L L H H L H H Address Data Hi-Z Lower Word Valid H H H H H L L H H H H L Address Hi-Z Data Word/Longword Valid H H H H H L L H H L H L Address Data Data CASH* CASL* RDWR AH RD WRH WRL 2 R W R W A21 to A0 D15 to D8 D7 to D0 Legend: R: Read W: Write Valid: Chip select signal corresponding with accessed area is low; chip select signal in other cases is high. Notes: 1. L asserted in RAS down state or refresh state. 2. L asserted in refresh state. Rev.5.00 Sep. 27, 2007 Page 710 of 716 REJ09B0398-0500 Appendix C Pin States Table C.4 Pin Settings for Multiplex I/O Space Multiplex I/O Space 16-Bit Space Pin Name CS0 to CS2 CS3 RAS* 1 2 8-Bit Space H L H H H H Valid R W L H H H H L Address Hi-Z Upper Byte H L H H H H Valid L H H L H H Address Address/Data Lower Byte H L H H H H Valid L H H H H L Address Address Address/Data Word/Longword H L H H H H Valid L H H L H L Address Address/Data Address/Data CASH* CASL* RDWR AH RD WRH WRL 2 R W R W A21 to A0 D15 to D8 D7 to D0 Address/Data Address Legend: R: Read W: Write Valid: High output in accordance with AH timing Notes: 1. L asserted in RAS down mode or refresh mode. 2. L asserted in refresh mode. Rev.5.00 Sep. 27, 2007 Page 711 of 716 REJ09B0398-0500 Appendix C Pin States Table C.5 Pin Settings for DRAM Space DRAM Space 16-Bit Space Pin Name CS0 to CS3 RAS* 1 2 8-Bit Space H Valid H Valid R W H L L R W L H H H H L Address Hi-Z Data Upper Word H Valid Valid H H L L L H H L H H Address Data Hi-Z Lower Word H Valid H Valid H L L L H H H H L Address Hi-Z Data Word/Longword H Valid Valid Valid H L L L H H L H L Address Data Data CASH* CASL* RDWR AH RD WRH WRL 2 R W R W A21 to A0 D15 to D8 D7 to D0 Legend: R: Read W: Write Valid: Asserted (low) at a timing determined by the DRAM access strobe waveform Notes: 1. L asserted in RAS down mode or refresh mode. 2. L asserted in refresh mode. Rev.5.00 Sep. 27, 2007 Page 712 of 716 REJ09B0398-0500 Appendix D Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Appendix D Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM of the mask-ROM version and FZTAT version differ as follows. Status Register FLMCR1 Bit FWE F-ZTAT Version 0: Application software running 1: Programming Mask-ROM Version 0: Is not read out 1: Application software running Note: This difference applies to all the F-ZTAT versions and all the mask-ROM versions that have different ROM size. Rev.5.00 Sep. 27, 2007 Page 713 of 716 REJ09B0398-0500 Appendix E Product Code Lineup Appendix E Product Code Lineup Table E.1 SH7014, SH7016, and SH7017 Product Code Lineup Product Code HD6417014F28 HD6417014RF28 SH7016 SH7017 Mask ROM version F-ZTAT version HD6437016F28 HD64F7017F28 Mark Code HD6417014F28 HD6417014RF28 HD6437016(***)F28 HD64F7017 Package (Package code) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) 112-pin QFP (FP-112) Product Type SH7014 Note: (***) is the ROM code. Rev.5.00 Sep. 27, 2007 Page 714 of 716 REJ09B0398-0500 Appendix F Package Dimensions Appendix F Package Dimensions Package dimensions of the SH7014, SH7016, SH7017 (FP-112) are shown in figure F.1. JEITA Package Code P-QFP112-20x20-0.65 RENESAS Code PRQP0112JA-A Previous Code FP-112/FP-112V MASS[Typ.] 2.4g HD *1 D 57 84 85 56 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section 112 29 Reference Dimension in Millimeters Symbol 1 ZD 28 F θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A AA bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 20 20 2.70 22.9 23.2 23.5 22.9 23.2 23.5 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 8˚ 0˚ 0.65 0.13 0.10 1.23 1.23 0.5 0.8 1.1 1.6 Min ZE A2 Figure F.1 Package Dimensions (FP-112) Rev.5.00 Sep. 27, 2007 Page 715 of 716 REJ09B0398-0500 A c Appendix F Package Dimensions Rev.5.00 Sep. 27, 2007 Page 716 of 716 REJ09B0398-0500 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7014, SH7016, SH7017F-ZTATTM Publication Date: 1st Edition, September 1997 Rev.5.00, September 27, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: (21) 5877-1818, Fax: (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: 2265-6688, Fax: 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: (2) 2715-2888, Fax: (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: 6213-0200, Fax: 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: (2) 796-3115, Fax: (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: 7955-9390, Fax: 7955-9510 Colophon 6.0 SH7014, SH7016, SH7017F-ZTAT Hardware Manual TM 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan