SH7106

REJ09B0069-0100 32 SH7108, SH7109 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7108 Series SH7108 Group SH7108 SH7106 SH7104 SH7101 SH7109 Group SH7109 SH7107 SH7105 HD6437108 HD6437106 HD6437104 HD6437101 HD6437109 HD6437107 HD6437105 Rev.1.00 Revision Date: Sep. 18, 2008 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.1.00 Sep. 18, 2008 Page ii of xxxiv REJ09B0069-0100 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.1.00 Sep. 18, 2008 Page iii of xxxiv REJ09B0069-0100 Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • • CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev.1.00 Sep. 18, 2008 Page iv of xxxiv REJ09B0069-0100 Preface The SH7108 Series single-chip RISC microprocessor integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. Target users: This manual was written for users who will be using the SH7108 Series MicroComputer Unit (MCU) in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7108 Series MCU to the above users. Refer to the SH-1, SH-2, SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: • Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification SH7108 (80-pin version) On-Chip ROM Classification SH7108 SH7106 SH7104 SH7101 SH7109 (100-pin version) SH7109 SH7107 SH7105 Masked ROM version (ROM: 128 kbytes) Masked ROM version (ROM: 64 kbytes) Masked ROM version (ROM: 256 kbytes) Masked ROM version (ROM: 32 kbytes) Masked ROM version (ROM: 128 kbytes) Masked ROM version (ROM: 64 kbytes) Masked ROM version (ROM: 256 kbytes) Part No. HD6437108 HD6437106 HD6437104 HD6437101 HD6437109 HD6437107 HD6437105 In this manual, the product abbreviations are used to distinguish products. For example, 80-pin products are collectively referred to as the SH7108, an abbreviation of the basic type's classification code, and 100-pin products are referred to as the SH7109. Rev.1.00 Sep. 18, 2008 Page v of xxxiv REJ09B0069-0100 • The typical product The HD6437108 is taken as the typical product for the descriptions in this manual. Accordingly, when using an HD6437101, HD6437104, HD6437105, HD6437106, HD6437109, or HD6437107 simply replace the HD6437108 in those references where no differences between products are pointed out with HD6437101, HD6437104, HD6437105, HD6437106, HD6437109, or HD6437107. Where differences are indicated, be aware that each specification applies to the products as indicated. • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the SH-1, SH-2, SH-DSP Software Manual. • In order to understand the details of a register when the user knows its name Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bit names, and initial values of the registers are summarized in Appendix A, On-chip I/O Register. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Bit order: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7108 Series Manuals: Document Title SH7108, SH7109 Group Hardware Manual SH-1, SH-2, SH-DSP Software Manual ADE No. This manual REJ09B0171 Rev.1.00 Sep. 18, 2008 Page vi of xxxiv REJ09B0069-0100 Users Manuals for Development Tools: Document Title C/C++ Compiler, Assembler, Optimized Linkage Editor Users Manual Simulator Debugger (for Windows) Users Manual Simulator Debugger (for UNIX) Users Manual High-performance Embedded Workshop Users Manual ADE No. REJ10B0047 ADE-702-186 ADE-702-149 REJ10J1737 Application Notes: Document Title C/C++ Compiler Edition ADE No. REJ05B0463 Rev.1.00 Sep. 18, 2008 Page vii of xxxiv REJ09B0069-0100 All trademarks and registered trademarks are the property of their respective owners. Rev.1.00 Sep. 18, 2008 Page viii of xxxiv REJ09B0069-0100 Contents Section 1 Overview........................................................................................... 1.1 1.2 1.3 1.4 1.5 1.6 1 Features ............................................................................................................................. 1 Internal Block Diagram..................................................................................................... 3 Pin Assignment ................................................................................................................. 5 Pin Functions .................................................................................................................... 7 Differences from SH7046 Group ...................................................................................... 12 Differences from SH7047 Group ...................................................................................... 13 Section 2 CPU................................................................................................... 15 2.1 2.2 Features ............................................................................................................................. Register Configuration ...................................................................................................... 2.2.1 General Registers (Rn)......................................................................................... 2.2.2 Control Registers ................................................................................................. 2.2.3 System Registers .................................................................................................. 2.2.4 Initial Values of Registers.................................................................................... Data Formats ..................................................................................................................... 2.3.1 Data Format in Registers...................................................................................... 2.3.2 Data Formats in Memory ..................................................................................... 2.3.3 Immediate Data Format ....................................................................................... Instruction Features........................................................................................................... 2.4.1 RISC-Type Instruction Set................................................................................... 2.4.2 Addressing Modes ............................................................................................... 2.4.3 Instruction Format................................................................................................ Instruction Set ................................................................................................................... 2.5.1 Instruction Set by Classification .......................................................................... Processing States............................................................................................................... 2.6.1 State Transitions................................................................................................... 15 15 17 17 18 18 19 19 19 19 20 20 22 26 28 28 42 42 2.3 2.4 2.5 2.6 Section 3 MCU Operating Modes..................................................................... 45 3.1 3.2 3.3 Selection of Operating Modes........................................................................................... Input/Output Pins .............................................................................................................. Explanation of Operating Modes ...................................................................................... 3.3.1 Mode 0 (MCU Extended Mode 0) ....................................................................... 3.3.2 Mode 1 (MCU Extended Mode 1) ....................................................................... 3.3.3 Mode 2 (MCU Extended Mode 2) ....................................................................... 3.3.4 Mode 3 (Single-Chip Mode) ................................................................................ 3.3.5 Clock Mode.......................................................................................................... Address Map ..................................................................................................................... 45 46 47 47 47 47 47 47 48 3.4 Rev.1.00 Sep. 18, 2008 Page ix of xxxiv REJ09B0069-0100 3.5 Initial State of This LSI..................................................................................................... 54 Section 4 Clock Pulse Generator ....................................................................... 55 4.1 Oscillator........................................................................................................................... 4.1.1 Connecting a Crystal Resonator........................................................................... 4.1.2 External Clock Input Method............................................................................... Function for Detecting the Oscillator Halt........................................................................ Usage Notes ...................................................................................................................... 4.3.1 Note on Crystal Resonator ................................................................................... 4.3.2 Notes on Board Design ........................................................................................ 55 55 56 57 57 57 57 4.2 4.3 Section 5 Exception Processing......................................................................... 59 5.1 Overview........................................................................................................................... 5.1.1 Types of Exception Processing and Priority ........................................................ 5.1.2 Exception Processing Operations......................................................................... 5.1.3 Exception Processing Vector Table ..................................................................... Resets ................................................................................................................................ 5.2.1 Types of Reset ..................................................................................................... 5.2.2 Power-On Reset ................................................................................................... 5.2.3 Manual Reset ....................................................................................................... Address Errors .................................................................................................................. 5.3.1 The Cause of Address Error Exception................................................................ 5.3.2 Address Error Exception Processing.................................................................... Interrupts........................................................................................................................... 5.4.1 Interrupt Sources.................................................................................................. 5.4.2 Interrupt Priority Level ........................................................................................ 5.4.3 Interrupt Exception Processing ............................................................................ Exceptions Triggered by Instructions ............................................................................... 5.5.1 Types of Exceptions Triggered by Instructions ................................................... 5.5.2 Trap Instructions .................................................................................................. 5.5.3 Illegal Slot Instructions ........................................................................................ 5.5.4 General Illegal Instructions.................................................................................. Cases when Exception Sources Are Not Accepted ........................................................... 5.6.1 Immediately after a Delayed Branch Instruction ................................................. 5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ Stack Status after Exception Processing Ends .................................................................. Usage Notes ...................................................................................................................... 5.8.1 Value of Stack Pointer (SP) ................................................................................. 5.8.2 Value of Vector Base Register (VBR) ................................................................. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 59 59 60 61 63 63 63 64 65 65 66 66 66 67 67 67 67 68 68 69 69 69 69 70 71 71 71 71 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Rev.1.00 Sep. 18, 2008 Page x of xxxiv REJ09B0069-0100 Section 6 Interrupt Controller (INTC) .............................................................. 73 6.1 6.2 6.3 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 6.3.1 Interrupt Control Register 1 (ICR1) ..................................................................... 6.3.2 Interrupt Control Register 2 (ICR2) ..................................................................... 6.3.3 IRQ Status Register (ISR).................................................................................... 6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) ............................ Interrupt Sources ............................................................................................................... 6.4.1 External Interrupts ............................................................................................... 6.4.2 On-Chip Peripheral Module Interrupts ................................................................ Interrupt Exception Processing Vectors Table.................................................................. Interrupt Operation............................................................................................................ 6.6.1 Interrupt Sequence ............................................................................................... 6.6.2 Stack after Interrupt Exception Processing .......................................................... Interrupt Response Time ................................................................................................... 73 75 75 76 77 79 80 82 82 83 84 87 87 89 90 6.4 6.5 6.6 6.7 Section 7 Bus State Controller (BSC)............................................................... 93 7.1 7.2 7.3 7.4 7.5 Features ............................................................................................................................. Input/Output Pins .............................................................................................................. Register Configuration ...................................................................................................... Address Map ..................................................................................................................... Register Descriptions ........................................................................................................ 7.5.1 Bus Control Register 1 (BCR1) ........................................................................... 7.5.2 Bus Control Register 2 (BCR2) ........................................................................... 7.5.3 Wait Control Register 1 (WCR1)......................................................................... 7.6 Accessing External Space ................................................................................................. 7.6.1 Basic Timing........................................................................................................ 7.6.2 Wait State Control................................................................................................ 7.6.3 CS Assert Period Extension ................................................................................. 7.7 Waits between Access Cycles ........................................................................................... 7.7.1 Prevention of Data Bus Conflicts......................................................................... 7.7.2 Simplification of Bus Cycle Start Detection ........................................................ 7.8 Bus Arbitration.................................................................................................................. 7.9 Memory Connection Example .......................................................................................... 7.10 On-chip Peripheral I/O Register Access ........................................................................... 7.11 Cycles in which Bus Is not Released ................................................................................ 7.12 CPU Operation when Program Is in External Memory..................................................... 93 95 95 96 102 102 104 105 106 106 107 109 110 110 110 111 112 113 113 113 Rev.1.00 Sep. 18, 2008 Page xi of xxxiv REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU)............................................115 8.1 8.2 8.3 Features............................................................................................................................. Input/Output Pins .............................................................................................................. Register Descriptions ........................................................................................................ 8.3.1 Timer Control Register (TCR)............................................................................. 8.3.2 Timer Mode Register (TMDR) ............................................................................ 8.3.3 Timer I/O Control Register (TIOR) ..................................................................... 8.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 8.3.5 Timer Status Register (TSR)................................................................................ 8.3.6 Timer Counter (TCNT)........................................................................................ 8.3.7 Timer General Register (TGR) ............................................................................ 8.3.8 Timer Start Register (TSTR) ............................................................................... 8.3.9 Timer Synchro Register (TSYR) ......................................................................... 8.3.10 Timer Output Master Enable Register (TOER) ................................................... 8.3.11 Timer Output Control Register (TOCR) .............................................................. 8.3.12 Timer Gate Control Register (TGCR) ................................................................. 8.3.13 Timer Subcounter (TCNTS) ................................................................................ 8.3.14 Timer Dead Time Data Register (TDDR)............................................................ 8.3.15 Timer Period Data Register (TCDR) ................................................................... 8.3.16 Timer Period Buffer Register (TCBR)................................................................. 8.3.17 Bus Master Interface ............................................................................................ Operation .......................................................................................................................... 8.4.1 Basic Functions.................................................................................................... 8.4.2 Synchronous Operation........................................................................................ 8.4.3 Buffer Operation .................................................................................................. 8.4.4 Cascaded Operation ............................................................................................. 8.4.5 PWM Modes ........................................................................................................ 8.4.6 Phase Counting Mode.......................................................................................... 8.4.7 Reset-Synchronized PWM Mode......................................................................... 8.4.8 Complementary PWM Mode............................................................................... Interrupt Sources............................................................................................................... 8.5.1 Interrupts and Priorities........................................................................................ 8.5.2 A/D Converter Activation.................................................................................... Operation Timing.............................................................................................................. 8.6.1 Input/Output Timing ............................................................................................ 8.6.2 Interrupt Signal Timing........................................................................................ Usage Notes ...................................................................................................................... 8.7.1 Module Standby Mode Setting ............................................................................ 8.7.2 Input Clock Restrictions ...................................................................................... 115 119 120 122 126 127 145 147 149 150 150 151 153 154 155 157 157 157 158 158 158 158 163 165 168 169 175 181 184 209 209 211 211 211 216 218 218 218 8.4 8.5 8.6 8.7 Rev.1.00 Sep. 18, 2008 Page xii of xxxiv REJ09B0069-0100 8.7.3 8.7.4 8.7.5 8.7.6 8.7.7 8.7.8 8.7.9 8.7.10 8.7.11 8.7.12 8.7.13 8.7.14 8.7.15 8.7.16 8.7.17 8.7.18 8.8 8.9 Caution on Period Setting .................................................................................... Contention between TCNT Write and Clear Operations ..................................... Contention between TCNT Write and Increment Operations.............................. Contention between TGR Write and Compare Match ......................................... Contention between Buffer Register Write and Compare Match ........................ Contention between TGR Read and Input Capture.............................................. Contention between TGR Write and Input Capture............................................. Contention between Buffer Register Write and Input Capture ............................ TCNT2 Write and Overflow/Underflow Contention in Cascade Connection...... Counter Value during Complementary PWM Mode Stop ................................... Buffer Operation Setting in Complementary PWM Mode .................................. Reset Sync PWM Mode Buffer Operation and Compare Match Flag ................. Overflow Flags in Reset Sync PWM Mode ......................................................... Contention between Overflow/Underflow and Counter Clearing........................ Contention between TCNT Write and Overflow/Underflow............................... Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode.......................................................................... 8.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode.......................................................................................................... 8.7.20 Interrupts in Module Standby Mode .................................................................... 8.7.21 Simultaneous Input Capture of TCNT-1 and TCNT-2 in Cascade Connection............................................................................................. MTU Output Pin Initialization .......................................................................................... 8.8.1 Operating Modes.................................................................................................. 8.8.2 Reset Start Operation ........................................................................................... 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. ................ 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. ................................................................................. Port Output Enable (POE)................................................................................................. 8.9.1 Features................................................................................................................ 8.9.2 Pin Configuration................................................................................................. 8.9.3 Register Descriptions ........................................................................................... 8.9.4 Operation ............................................................................................................. 8.9.5 Usage Note........................................................................................................... 219 219 220 221 222 223 225 226 226 227 228 228 229 230 231 232 232 232 232 233 233 233 234 235 261 261 263 263 268 270 Section 9 Watchdog Timer ............................................................................... 271 9.1 9.2 9.3 Features ............................................................................................................................. Input/Output Pin................................................................................................................ Register Descriptions ........................................................................................................ 9.3.1 Timer Counter (TCNT)........................................................................................ 271 272 272 273 Rev.1.00 Sep. 18, 2008 Page xiii of xxxiv REJ09B0069-0100 9.4 9.5 9.6 9.3.2 Timer Control/Status Register (TCSR)................................................................ 9.3.3 Reset Control/Status Register (RSTCSR) ............................................................ Operation .......................................................................................................................... 9.4.1 Watchdog Timer Mode ........................................................................................ 9.4.2 Interval Timer Mode............................................................................................ 9.4.3 Clearing Software Standby Mode ........................................................................ 9.4.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ Interrupt Source ................................................................................................................ Usage Notes ...................................................................................................................... 9.6.1 Notes on Register Access..................................................................................... 9.6.2 TCNT Write and Increment Contention .............................................................. 9.6.3 Changing CKS2 to CKS0 Bit Values .................................................................. 9.6.4 Changing between Watchdog Timer/Interval Timer Modes................................ 9.6.5 System Reset by WDTOVF Signal...................................................................... 9.6.6 Internal Reset in Watchdog Timer Mode............................................................. 9.6.7 Manual Reset in Watchdog Timer Mode............................................................. 9.6.8 Notes on Using WDTOVF Pin ............................................................................ 273 275 276 276 277 278 278 279 279 279 279 281 281 281 282 282 282 282 Section 10 Serial Communication Interface (SCI) ............................................283 10.1 Features............................................................................................................................. 10.2 Input/Output Pins .............................................................................................................. 10.3 Register Descriptions ........................................................................................................ 10.3.1 Receive Shift Register (RSR) .............................................................................. 10.3.2 Receive Data Register (RDR) .............................................................................. 10.3.3 Transmit Shift Register (TSR) ............................................................................. 10.3.4 Transmit Data Register (TDR)............................................................................. 10.3.5 Serial Mode Register (SMR) ............................................................................... 10.3.6 Serial Control Register (SCR).............................................................................. 10.3.7 Serial Status Register (SSR) ................................................................................ 10.3.8 Serial Direction Control Register (SDCR)........................................................... 10.3.9 Bit Rate Register (BRR) ...................................................................................... 10.4 Operation in Asynchronous Mode .................................................................................... 10.4.1 Data Transfer Format........................................................................................... 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................ 10.4.3 Clock.................................................................................................................... 10.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 10.4.5 Data Transmission (Asynchronous Mode)........................................................... 10.4.6 Serial Data Reception (Asynchronous Mode)...................................................... Rev.1.00 Sep. 18, 2008 Page xiv of xxxiv REJ09B0069-0100 283 285 285 286 286 286 286 287 288 290 292 292 301 301 303 304 305 306 308 10.5 Multiprocessor Communication Function......................................................................... 10.5.1 Multiprocessor Serial Data Transmission ............................................................ 10.5.2 Multiprocessor Serial Data Reception.................................................................. 10.6 Operation in Clocked Synchronous Mode ........................................................................ 10.6.1 Clock.................................................................................................................... 10.6.2 SCI Initialization (Clocked Synchronous Mode) ................................................. 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 10.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 10.7 Interrupt Sources ............................................................................................................... 10.7.1 Interrupts in Normal Serial Communication Interface Mode............................... 10.8 Usage Notes ...................................................................................................................... 10.8.1 TDR Write and TDRE Flag ................................................................................. 10.8.2 Module Standby Mode Setting ............................................................................ 10.8.3 Break Detection and Processing (Asynchronous Mode Only)............................. 10.8.4 Sending Break Signal (Asynchronous Mode Only) ............................................. 10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..................................................................... 10.8.6 Cautions on Clocked Synchronous External Clock Mode ................................... 10.8.7 Caution on Clocked Synchronous Internal Clock Mode...................................... 312 314 315 318 318 318 319 322 324 326 326 327 327 327 327 327 328 328 328 Section 11 A/D Converter................................................................................. 329 11.1 Features ............................................................................................................................. 11.2 Input/Output Pins .............................................................................................................. 11.3 Register Descriptions ........................................................................................................ 11.3.1 A/D Data Registers 0 to 19 (ADDR0 to ADDR19) ............................................. 11.3.2 A/D Control/Status Registers_0 to 2 (ADCSR_0 to ADCSR_2)......................... 11.3.3 A/D Control Registers_0 to 2 (ADCR_0 to ADCR_2) ........................................ 11.3.4 A/D Trigger Select Register (ADTSR) ................................................................ 11.4 Operation........................................................................................................................... 11.4.1 Single Mode......................................................................................................... 11.4.2 Continuous Scan Mode ........................................................................................ 11.4.3 Single-Cycle Scan Mode...................................................................................... 11.4.4 Input Sampling and A/D Conversion Time.......................................................... 11.4.5 A/D Converter Activation by MTU or MMT ...................................................... 11.4.6 External Trigger Input Timing ............................................................................. 11.5 Interrupt Source................................................................................................................. 11.6 Definitions of A/D Conversion Accuracy ......................................................................... 11.7 Usage Notes ...................................................................................................................... 329 331 332 333 334 335 337 338 338 339 341 342 343 343 344 345 347 Rev.1.00 Sep. 18, 2008 Page xv of xxxiv REJ09B0069-0100 11.7.1 11.7.2 11.7.3 11.7.4 11.7.5 11.7.6 Module Standby Mode Setting ............................................................................ Permissible Signal Source Impedance ................................................................. Influences on Absolute Accuracy ........................................................................ Range of Analog Power Supply and Other Pin Settings ...................................... Notes on Board Design ........................................................................................ Notes on Noise Countermeasures ........................................................................ 347 347 347 348 348 348 Section 12 Compare Match Timer (CMT) ........................................................351 12.1 Features............................................................................................................................. 12.2 Register Descriptions ........................................................................................................ 12.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 12.2.2 Compare Match Timer Control/Status Registers_0 and 1 (CMCSR_0, CMCSR_1) ..................................................................................... 12.2.3 Compare Match Timer Counters_0 and 1 (CMCNT_0, CMCNT_1) .................. 12.2.4 Compare Match Timer Constant Registers_0 and 1 (CMCOR_0, CMCOR_1) .................................................................................... 12.3 Operation .......................................................................................................................... 12.3.1 Cyclic Count Operation ....................................................................................... 12.3.2 CMCNT Count Timing........................................................................................ 12.4 Interrupts........................................................................................................................... 12.4.1 Interrupt Sources.................................................................................................. 12.4.2 Compare Match Flag Set Timing......................................................................... 12.4.3 Compare Match Flag Clear Timing ..................................................................... 12.5 Usage Notes ...................................................................................................................... 12.5.1 Contention between CMCNT Write and Compare Match................................... 12.5.2 Contention between CMCNT Word Write and Incrementation .......................... 12.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 351 352 352 353 354 354 354 354 355 355 355 355 356 357 357 358 359 Section 13 Motor Management Timer (MMT) .................................................361 13.1 Features............................................................................................................................. 13.2 Input/Output Pins .............................................................................................................. 13.3 Register Descriptions ........................................................................................................ 13.3.1 Timer Mode Register (MMT_TMDR) ................................................................ 13.3.2 Timer Control Register (TCNR) .......................................................................... 13.3.3 Timer Status Register (MMT_TSR) .................................................................... 13.3.4 Timer Counter (MMT_TCNT) ............................................................................ 13.3.5 Timer Buffer Registers (TBR) ............................................................................. 13.3.6 Timer General Registers (TGR)........................................................................... 13.3.7 Timer Dead Time Counter (TDCNT) .................................................................. 13.3.8 Timer Dead Time Data Register (MMT_TDDR) ................................................ Rev.1.00 Sep. 18, 2008 Page xvi of xxxiv REJ09B0069-0100 361 363 363 365 366 367 368 368 368 368 368 13.4 13.5 13.6 13.7 13.8 13.3.9 Timer Period Buffer Register (TPBR) ................................................................. 13.3.10 Timer Period Data Register (TPDR).................................................................... Operation........................................................................................................................... 13.4.1 Sample Setting Procedure .................................................................................... 13.4.2 Output Protection Functions ................................................................................ Interrupt Sources ............................................................................................................... Operation Timing.............................................................................................................. 13.6.1 Input/Output Timing ............................................................................................ 13.6.2 Interrupt Signal Timing........................................................................................ Usage Notes ...................................................................................................................... 13.7.1 Module Standby Mode Setting ............................................................................ 13.7.2 Notes on MMT Operation.................................................................................... Port Output Enable (POE)................................................................................................. 13.8.1 Features................................................................................................................ 13.8.2 Input/Output Pins ................................................................................................. 13.8.3 Register Description............................................................................................. 13.8.4 Operation ............................................................................................................. 13.8.5 Usage Note........................................................................................................... 368 369 369 370 378 379 379 379 382 383 383 383 386 386 387 387 390 391 Section 14 Pin Function Controller (PFC)........................................................ 393 14.1 Register Descriptions ........................................................................................................ 14.1.1 Port A I/O Register L (PAIORL) ......................................................................... 14.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)................................. 14.1.3 Port B I/O Register (PBIOR) ............................................................................... 14.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2) ...................................... 14.1.5 Port D I/O Register L (PDIORL) ......................................................................... 14.1.6 Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2)............................ 14.1.7 Port E I/O Registers L and H (PEIORL and PEIORH)........................................ 14.1.8 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) ....... 14.2 Usage Note........................................................................................................................ 409 409 409 416 417 419 419 421 421 427 Section 15 I/O Ports .......................................................................................... 429 15.1 Port A ................................................................................................................................ 15.1.1 Register Description............................................................................................. 15.1.2 Port A Data Register L (PADRL) ........................................................................ 15.2 Port B ................................................................................................................................ 15.2.1 Register Description............................................................................................. 15.2.2 Port B Data Register (PBDR) .............................................................................. 15.3 Port D ................................................................................................................................ 15.3.1 Register Description............................................................................................. 429 430 431 432 433 433 434 434 Rev.1.00 Sep. 18, 2008 Page xvii of xxxiv REJ09B0069-0100 15.3.2 Port D Data Register L (PDDRL) ........................................................................ 15.4 Port E ................................................................................................................................ 15.4.1 Register Descriptions ........................................................................................... 15.4.2 Port E Data Registers H and L (PEDRH and PEDRL) ........................................ 15.5 Port F................................................................................................................................. 15.5.1 Register Description............................................................................................. 15.5.2 Port F Data Register (PFDR) ............................................................................... 15.6 Port G................................................................................................................................ 15.6.1 Register Description............................................................................................. 15.6.2 Port G Data Register (PGDR).............................................................................. 435 436 437 438 440 441 441 442 442 442 Section 16 Masked ROM ..................................................................................445 16.1 Usage Note........................................................................................................................ 446 Section 17 RAM ................................................................................................447 17.1 Usage Note........................................................................................................................ 447 Section 18 Power-Down Modes ........................................................................449 18.1 Input/Output Pins .............................................................................................................. 18.2 Register Descriptions ........................................................................................................ 18.2.1 Standby Control Register (SBYCR) .................................................................... 18.2.2 System Control Register (SYSCR) ...................................................................... 18.2.3 Module Standby Control Registers 1 and 2 (MSTCR1 and MSTCR2) ............... 18.3 Operation .......................................................................................................................... 18.3.1 Sleep Mode .......................................................................................................... 18.3.2 Software Standby Mode....................................................................................... 18.3.3 Hardware Standby Mode ..................................................................................... 18.3.4 Module Standby Mode......................................................................................... 18.4 Usage Notes ...................................................................................................................... 18.4.1 I/O Port Status...................................................................................................... 18.4.2 Current Consumption during Oscillation Stabilization Wait Period.................... 18.4.3 On-Chip Peripheral Module Interrupt.................................................................. 18.4.4 Writing to MSTCR1 and MSTCR2 ..................................................................... 452 452 453 454 454 456 456 457 460 461 462 462 462 462 462 Section 19 List of Registers...............................................................................463 19.1 Register Addresses (Address Order)................................................................................. 463 19.2 Register Bits...................................................................................................................... 471 19.3 Register States in Each Operating Mode........................................................................... 479 Rev.1.00 Sep. 18, 2008 Page xviii of xxxiv REJ09B0069-0100 Section 20 Electrical Characteristics ................................................................ 485 20.1 Absolute Maximum Ratings ............................................................................................. 20.2 DC Characteristics ............................................................................................................ 20.3 AC Characteristics ............................................................................................................ 20.3.1 Test Conditions for AC Characteristics ............................................................... 20.3.2 Clock Timing ....................................................................................................... 20.3.3 Control Signal Timing ......................................................................................... 20.3.4 Bus Timing .......................................................................................................... 20.3.5 Multifunction Timer Pulse Unit (MTU) Timing.................................................. 20.3.6 I/O Port Timing.................................................................................................... 20.3.7 Watchdog Timer (WDT) Timing ......................................................................... 20.3.8 Serial Communication Interface (SCI) Timing .................................................... 20.3.9 Motor Management Timer (MMT) Timing ......................................................... 20.3.10 Output Enable (POE) Timing .............................................................................. 20.3.11 A/D Converter Timing ......................................................................................... 20.4 A/D Converter Characteristics .......................................................................................... 485 486 491 491 492 494 497 501 502 503 504 506 507 507 509 Appendix A Pin States ...................................................................................... 511 Appendix B Product Code Lineup.................................................................... 515 Appendix C Package Dimensions..................................................................... 517 Index ......................................................................................................... 519 Rev.1.00 Sep. 18, 2008 Page xix of xxxiv REJ09B0069-0100 Rev.1.00 Sep. 18, 2008 Page xx of xxxiv REJ09B0069-0100 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of SH7108/SH7106/SH7104/SH7101 ............................. Figure 1.2 Internal Block Diagram of SH7109/SH7107/SH7105............................................ Figure 1.3 SH7108/SH7106/SH7104/SH7101 Pin Assignment .............................................. Figure 1.4 SH7109/SH7107/SH7105 Pin Assignment ............................................................ Section 2 CPU Figure 2.1 CPU Internal Registers ........................................................................................... Figure 2.2 Data Format in Registers ........................................................................................ Figure 2.3 Data Formats in Memory ....................................................................................... Figure 2.4 Transitions between Processing States ................................................................... Section 3 MCU Operating Modes Figure 3.1 Address Map of SH7108 ........................................................................................ Figure 3.2 Address Map of SH7106 ........................................................................................ Figure 3.3 Address Map of SH7104 ........................................................................................ Figure 3.4 Address Map of SH7101 ........................................................................................ Figure 3.5 Address Map for Operating Modes of SH7109...................................................... Figure 3.6 Address Map for Operating Modes of SH7107...................................................... Figure 3.7 Address Map for Operating Modes of SH7105...................................................... Section 4 Clock Pulse Generator Figure 4.1 Block Diagram of the Clock Pulse Generator ........................................................ Figure 4.2 Connection of the Crystal Resonator (Example) .................................................... Figure 4.3 Crystal Resonator Equivalent Circuit ..................................................................... Figure 4.4 Example of External Clock Connection ................................................................. Figure 4.5 Cautions for Oscillator Circuit System Board Design............................................ Figure 4.6 Recommended External Circuitry Around the PLL ............................................... Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram ............................................................................................. Figure 6.2 Control of IRQ3 to IRQ0 Interrupts ....................................................................... Figure 6.3 Interrupt Sequence Flowchart................................................................................. Figure 6.4 Stack after Interrupt Exception Processing ............................................................ Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt Is Accepted................ 3 4 5 6 16 19 19 42 48 49 50 51 52 53 54 55 56 56 57 58 58 74 83 88 89 91 Section 7 Bus State Controller (BSC) Figure 7.1 BSC Block Diagram............................................................................................... 94 Rev.1.00 Sep. 18, 2008 Page xxi of xxxiv REJ09B0069-0100 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Address Format ...................................................................................................... Basic Timing of External Space Access................................................................. Wait State Timing of External Space Access (Software Wait Only) ..................... Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State) ........................................ Figure 7.6 CS Assert Period Extension Function .................................................................... Figure 7.7 Example of Idle Cycle Insertion at Same Space Consecutive Access.................... Figure 7.8 Bus Mastership Release Procedure ........................................................................ Figure 7.9 Example of 8-Bit Data Bus Width ROM Connection ............................................ Figure 7.10 One Bus Cycle........................................................................................................ Section 8 Multifunction Timer Pulse Unit (MTU) Figure 8.1 Block Diagram of TPU .......................................................................................... Figure 8.2 Complementary PWM Mode Output Level Example ............................................ Figure 8.3 Example of Counter Operation Setting Procedure ................................................. Figure 8.4 Free-Running Counter Operation ........................................................................... Figure 8.5 Periodic Counter Operation.................................................................................... Figure 8.6 Example of Setting Procedure for Waveform Output by Compare Match............. Figure 8.7 Example of 0 Output/1 Output Operation .............................................................. Figure 8.8 Example of Toggle Output Operation .................................................................... Figure 8.9 Example of Input Capture Operation Setting Procedure ........................................ Figure 8.10 Example of Input Capture Operation ..................................................................... Figure 8.11 Example of Synchronous Operation Setting Procedure ......................................... Figure 8.12 Example of Synchronous Operation....................................................................... Figure 8.13 Compare Match Buffer Operation.......................................................................... Figure 8.14 Input Capture Buffer Operation ............................................................................. Figure 8.15 Example of Buffer Operation Setting Procedure.................................................... Figure 8.16 Example of Buffer Operation (1) ........................................................................... Figure 8.17 Example of Buffer Operation (2) ........................................................................... Figure 8.18 Cascaded Operation Setting Procedure .................................................................. Figure 8.19 Example of Cascaded Operation (2)....................................................................... Figure 8.20 Example of PWM Mode Setting Procedure ........................................................... Figure 8.21 Example of PWM Mode Operation (1) .................................................................. Figure 8.22 Example of PWM Mode Operation (2) .................................................................. Figure 8.23 Example of PWM Mode Operation (3) .................................................................. Figure 8.24 Example of Phase Counting Mode Setting Procedure............................................ Figure 8.25 Example of Phase Counting Mode 1 Operation ..................................................... Figure 8.26 Example of Phase Counting Mode 2 Operation ..................................................... Figure 8.27 Example of Phase Counting Mode 3 Operation ..................................................... Figure 8.28 Example of Phase Counting Mode 4 Operation ..................................................... Rev.1.00 Sep. 18, 2008 Page xxii of xxxiv REJ09B0069-0100 96 106 107 108 109 110 112 112 113 118 155 159 159 160 161 161 162 162 163 164 165 166 166 166 167 168 169 169 172 172 173 174 175 176 177 178 179 Figure 8.29 Phase Counting Mode Application Example.......................................................... Figure 8.30 Procedure for Selecting the Reset-Synchronized PWM Mode............................... Figure 8.31 Reset-Synchronized PWM Mode Operation Examplex (When the TOCR’s OLSN = 1 and OLSP = 1) ...................................................... Figure 8.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode ................... Figure 8.33 Example of Complementary PWM Mode Setting Procedure................................. Figure 8.34 Complementary PWM Mode Counter Operation................................................... Figure 8.35 Example of Complementary PWM Mode Operation ............................................. Figure 8.36 Example of PWM Cycle Updating......................................................................... Figure 8.37 Example of Data Update in Complementary PWM Mode ..................................... Figure 8.38 Example of Initial Output in Complementary PWM Mode (1).............................. Figure 8.39 Example of Initial Output in Complementary PWM Mode (2).............................. Figure 8.40 Example of Complementary PWM Mode Waveform Output (1) .......................... Figure 8.41 Example of Complementary PWM Mode Waveform Output (2) .......................... Figure 8.42 Example of Complementary PWM Mode Waveform Output (3) .......................... Figure 8.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) ... Figure 8.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) ... Figure 8.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) ... Figure 8.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) ... Figure 8.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) ... Figure 8.48 Example of Toggle Output Waveform Synchronized with PWM Output.............. Figure 8.49 Counter Clearing Synchronized with Another Channel ......................................... Figure 8.50 Example of Output Phase Switching by External Input (1).................................... Figure 8.51 Example of Output Phase Switching by External Input (2).................................... Figure 8.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)... Figure 8.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)... Figure 8.54 Count Timing in Internal Clock Operation............................................................. Figure 8.55 Count Timing in External Clock Operation ........................................................... Figure 8.56 Count Timing in External Clock Operation (Phase Counting Mode)..................... Figure 8.57 Output Compare Output Timing (Normal Mode/PWM Mode).............................. Figure 8.58 Output Compare Output Timing (Complementary PWM Mode/ Reset Synchronous PWM Mode) ........................................................................... Figure 8.59 Input Capture Input Signal Timing......................................................................... Figure 8.60 Counter Clear Timing (Compare Match) ............................................................... Figure 8.61 Counter Clear Timing (Input Capture) ................................................................... Figure 8.62 Buffer Operation Timing (Compare Match) .......................................................... Figure 8.63 Buffer Operation Timing (Input Capture) .............................................................. Figure 8.64 TGI Interrupt Timing (Compare Match) ................................................................ Figure 8.65 TGI Interrupt Timing (Input Capture) .................................................................... Figure 8.66 TCIV Interrupt Setting Timing............................................................................... 180 183 184 187 189 191 192 194 196 197 198 199 200 200 201 201 202 202 203 204 205 206 206 207 207 211 212 212 213 213 214 214 215 215 215 216 216 217 Rev.1.00 Sep. 18, 2008 Page xxiii of xxxiv REJ09B0069-0100 Figure 8.67 Figure 8.68 Figure 8.69 Figure 8.70 Figure 8.71 Figure 8.72 Figure 8.73 Figure 8.74 TCIU Interrupt Setting Timing............................................................................... Timing for Status Flag Clearing by the CPU ......................................................... Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. Contention between TCNT Write and Clear Operations........................................ Contention between TCNT Write and Increment Operations ................................ Contention between TGR Write and Compare Match ........................................... Contention between Buffer Register Write and Compare Match (Channel 0) ....... Contention between Buffer Register Write and Compare Match (Channels 3 and 4).................................................................................................. Figure 8.75 Contention between TGR Read and Input Capture ................................................ Figure 8.76 Contention between TGR Write and Input Capture ............................................... Figure 8.77 Contention between Buffer Register Write and Input Capture............................... Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection.. Figure 8.79 Counter Value during Complementary PWM Mode Stop ..................................... Figure 8.80 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode.............. Figure 8.81 Reset Sync PWM Mode Overflow Flag ................................................................. Figure 8.82 Contention between Overflow and Counter Clearing ............................................ Figure 8.83 Contention between TCNT Write and Overflow ................................................... Figure 8.84 Error Occurrence in Normal Mode, Recovery in Normal Mode............................ Figure 8.85 Error Occurrence in Normal Mode, Recovery in PWM Mode 1............................ Figure 8.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 2............................ Figure 8.87 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode............... Figure 8.88 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode.... Figure 8.89 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode ............................................................................ Figure 8.90 Error Occurrence in PWM Mode 1, Recovery in Normal Mode............................ Figure 8.91 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 ........................... Figure 8.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 ........................... Figure 8.93 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode............... Figure 8.94 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode.... Figure 8.95 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode ............................................................................ Figure 8.96 Error Occurrence in PWM Mode 2, Recovery in Normal Mode............................ Figure 8.97 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 ........................... Figure 8.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 ........................... Figure 8.99 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode............... Figure 8.100 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode............... Figure 8.101 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1............... Figure 8.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2............... 217 218 219 220 220 221 222 223 224 225 226 227 228 229 230 231 231 236 237 237 238 239 240 241 242 242 243 244 245 246 247 247 248 249 250 250 Rev.1.00 Sep. 18, 2008 Page xxiv of xxxiv REJ09B0069-0100 Figure 8.103 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode ............................................................................................ Figure 8.104 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode ......................................................................................................... Figure 8.105 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 ......................................................................................................... Figure 8.106 Error Occurrence in Complementary PWM Mode, Recovery in ComplementaryPWM Mode .................................................................................. Figure 8.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode ................................................................................. Figure 8.108 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode ............................................................................ Figure 8.109 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode ..................................................................................... Figure 8.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1..................................................................................... Figure 8.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode ............................................................. Figure 8.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode........................................................ Figure 8.113 POE Block Diagram............................................................................................... Figure 8.114 Low-Level Detection Operation............................................................................. Figure 8.115 Output-Level Detection Operation ......................................................................... Figure 8.116 Falling Edge Detection Operation .......................................................................... Section 9 Watchdog Timer Figure 9.1 Block Diagram of WDT ......................................................................................... Figure 9.2 Operation in Watchdog Timer Mode...................................................................... Figure 9.3 Operation in Interval Timer Mode.......................................................................... Figure 9.4 Timing of Setting OVF........................................................................................... Figure 9.5 Timing of Setting WOVF....................................................................................... Figure 9.6 Writing to TCNT and TCSR .................................................................................. Figure 9.7 Writing to RSTCSR................................................................................................ Figure 9.8 Contention between TCNT Write and Increment................................................... Figure 9.9 Example of System Reset Circuit Using WDTOVF Signal ................................... 251 252 253 254 255 256 257 258 259 260 262 268 269 270 272 277 277 278 279 280 280 281 282 Section 10 Serial Communication Interface (SCI) Figure 10.1 Block Diagram of SCI............................................................................................ 284 Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ............................................................................................ 301 Rev.1.00 Sep. 18, 2008 Page xxv of xxxiv REJ09B0069-0100 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... Figure 10.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)............................................................................................ Figure 10.5 Sample SCI Initialization Flowchart ...................................................................... Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) ................................................... Figure 10.7 Sample Serial Transmission Flowchart .................................................................. Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .............................................................................................. Figure 10.9 Sample Serial Reception Data Flowchart (1) ......................................................... Figure 10.9 Sample Serial Reception Data Flowchart (2) ......................................................... Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H’AA to Receiving Station A)........................................... Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart ......................................... Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).......................................................................... Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)......................................... Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)......................................... Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) ............... Figure 10.15 Sample SCI Initialization Flowchart ...................................................................... Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ................... Figure 10.17 Sample Serial Transmission Flowchart .................................................................. Figure 10.18 Example of SCI Operation in Reception ................................................................ Figure 10.19 Sample Serial Reception Flowchart ....................................................................... Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ....... Section 11 A/D Converter Figure 11.1 Block Diagram of A/D Converter (For One Module) ............................................ Figure 11.2 Example of Continuous Scan Mode Operation (when Three Channels, AN8 to AN10, Are Selected) ................................................................................. Figure 11.3 A/D Conversion Timing......................................................................................... Figure 11.4 External Trigger Input Timing ............................................................................... Figure 11.5 Definitions of A/D Conversion Accuracy .............................................................. Figure 11.6 Definitions of A/D Conversion Accuracy .............................................................. Figure 11.7 Example of Analog Input Circuit ........................................................................... Figure 11.8 Example of Analog Input Protection Circuit.......................................................... Figure 11.9 Analog Input Pin Equivalent Circuit ...................................................................... 303 304 305 306 307 308 310 311 313 314 315 316 317 318 319 320 321 322 323 325 330 340 342 344 346 346 347 349 349 Section 12 Compare Match Timer (CMT) Figure 12.1 CMT Block Diagram.............................................................................................. 351 Rev.1.00 Sep. 18, 2008 Page xxvi of xxxiv REJ09B0069-0100 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Counter Operation .................................................................................................. Count Timing ......................................................................................................... CMF Set Timing..................................................................................................... Timing of CMF Clear by CPU ............................................................................... CMCNT Write and Compare Match Contention.................................................... CMCNT Word Write and Increment Contention ................................................... CMCNT Byte Write and Increment Contention..................................................... 354 355 356 356 357 358 359 Section 13 Motor Management Timer (MMT) Figure 13.1 Block Diagram of MMT......................................................................................... Figure 13.2 Sample Operating Mode Setting Procedure ........................................................... Figure 13.3 Example of TCNT Count Operation ...................................................................... Figure 13.4 Examples of Counter and Register Operations....................................................... Figure 13.5 Example of PWM Waveform Generation .............................................................. Figure 13.6 Example of TCNT Counter Clearing...................................................................... Figure 13.7 Example of Toggle Output Waveform Synchronized with PWM Cycle................ Figure 13.8 Count Timing ......................................................................................................... Figure 13.9 TCNT Counter Clearing Timing ............................................................................ Figure 13.10 TDCNT Operation Timing ..................................................................................... Figure 13.11 Buffer Operation Timing........................................................................................ Figure 13.12 TGI Interrupt Timing.............................................................................................. Figure 13.13 Timing of Status Flag Clearing by CPU................................................................. Figure 13.14 Contention between Buffer Register Write and Compare Match........................... Figure 13.15 Contention between Compare Register Write and Compare Match....................... Figure 13.16 Writing into Timer General Registers (When One Cycle is Not Output)............... Figure 13.17 Block Diagram of POE........................................................................................... Figure 13.18 Low Level Detection Operation ............................................................................. Section 15 I/O Ports Figure 15.1 Port A (SH7108)..................................................................................................... Figure 15.2 Port A (SH7109)..................................................................................................... Figure 15.3 Port B (SH7108)..................................................................................................... Figure 15.4 Port B (SH7109)..................................................................................................... Figure 15.5 Port D (SH7109)..................................................................................................... Figure 15.6 Port E (SH7108) ..................................................................................................... Figure 15.7 Port E (SH7109) ..................................................................................................... Figure 15.8 Port F (SH7108) ..................................................................................................... Figure 15.9 Port F (SH7109) ..................................................................................................... Figure 15.10 Port G (SH7108)..................................................................................................... 362 370 371 373 376 377 378 379 380 380 381 382 382 383 384 385 387 391 429 430 432 432 434 436 437 440 440 442 Rev.1.00 Sep. 18, 2008 Page xxvii of xxxiv REJ09B0069-0100 Section 16 Masked ROM Figure 16.1 Masked ROM Block Diagram (SH7106/SH7107)................................................. 445 Figure 16.2 Masked ROM Block Diagram (SH7108/SH7109)................................................. 445 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Power-Down Modes Mode Transition Diagram ...................................................................................... 451 NMI Timing in Software Standby Mode................................................................ 460 Transition Timing to Hardware Standby Mode...................................................... 461 Section 20 Electrical Characteristics Figure 20.1 Output Load Circuit ............................................................................................... Figure 20.2 System Clock Timing............................................................................................. Figure 20.3 EXTAL Clock Input Timing .................................................................................. Figure 20.4 Oscillation Settling Time ....................................................................................... Figure 20.5 Reset Input Timing................................................................................................. Figure 20.6 Reset Input Timing................................................................................................. Figure 20.7 Interrupt Signal Input Timing................................................................................. Figure 20.8 Interrupt Signal Output Timing .............................................................................. Figure 20.9 Bus Release Timing ............................................................................................... Figure 20.10 Basic Cycle (No Waits).......................................................................................... Figure 20.11 Basic Cycle (One Software Wait) .......................................................................... Figure 20.12 Basic Cycle (Two Software Waits + Waits by WAIT Signal) ............................... Figure 20.13 MTU Input/Output Timing..................................................................................... Figure 20.14 MTU Clock Input Timing ...................................................................................... Figure 20.15 I/O Port Input/Output Timing................................................................................. Figure 20.16 Watchdog Timer Timing ........................................................................................ Figure 20.17 Input Clock Timing ................................................................................................ Figure 20.18 SCI Input/Output Timing ....................................................................................... Figure 20.19 MMT Input/Output Timing .................................................................................... Figure 20.20 POE Input/Output Timing ...................................................................................... Figure 20.21 External Trigger Input Timing ............................................................................... 491 493 493 493 495 495 496 496 496 498 499 500 501 502 502 503 505 505 506 507 508 Appendix C Package Dimensions Figure C.1 FP-80Q ................................................................................................................... 517 Figure C.2 FP-100M ................................................................................................................ 518 Rev.1.00 Sep. 18, 2008 Page xxviii of xxxiv REJ09B0069-0100 Tables Section 1 Overview Table 1.1 Pin Functions.......................................................................................................... 7 Table 1.2 Differences from SH7046 Group ........................................................................... 12 Table 1.3 Differences from SH7047 Group ........................................................................... 13 Section 2 CPU Table 2.1 Initial Values of Registers ...................................................................................... 18 Table 2.2 Sign Extension of Word Data................................................................................. 20 Table 2.3 Delayed Branch Instructions .................................................................................. 21 Table 2.4 T Bit ....................................................................................................................... 21 Table 2.5 Immediate Data Accessing ..................................................................................... 21 Table 2.6 Absolute Address Accessing .................................................................................. 22 Table 2.7 Displacement Accessing......................................................................................... 22 Table 2.8 Addressing Modes and Effective Addresses .......................................................... 23 Table 2.9 Instruction Formats................................................................................................. 26 Table 2.10 Classification of Instructions.................................................................................. 29 Table 2.11 Symbols Used in Instruction Code, Operation, and Execution States Tables ........ 32 Table 2.12 Data Transfer Instructions ...................................................................................... 33 Table 2.13 Arithmetic Operation Instructions.......................................................................... 35 Table 2.14 Logic Operation Instructions.................................................................................. 37 Table 2.15 Shift Instructions .................................................................................................... 38 Table 2.16 Branch Instructions................................................................................................. 39 Table 2.17 System Control Instructions ................................................................................... 40 Section 3 MCU Operating Modes Table 3.1 Selection of Operating Modes ................................................................................ 45 Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode............................... 46 Table 3.3 Pin Configuration ................................................................................................... 46 Section 4 Clock Pulse Generator Table 4.1 Damping Resistance Values ................................................................................... 56 Table 4.2 Crystal Resonator Characteristics........................................................................... 56 Section 5 Exception Processing Table 5.1 Types of Exception Processing and Priority........................................................... Table 5.2 Timing for Exception Source Detection and Start of Exception Processing .......... Table 5.3 Exception Processing Vector Table........................................................................ Table 5.4 Calculating Exception Processing Vector Table Addresses ................................... 59 60 61 62 Rev.1.00 Sep. 18, 2008 Page xxix of xxxiv REJ09B0069-0100 Table 5.5 Table 5.6 Table 5.7 Table 5.8 Table 5.9 Table 5.10 Table 5.11 Reset Status ............................................................................................................ Bus Cycles and Address Errors .............................................................................. Interrupt Sources .................................................................................................... Interrupt Priority..................................................................................................... Types of Exceptions Triggered by Instructions...................................................... Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction.......................................................... Stack Status after Exception Processing Ends........................................................ 63 65 66 67 68 69 70 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration ................................................................................................... 75 Table 6.2 Interrupt Exception Processing Vectors and Priorities........................................... 84 Table 6.3 Interrupt Response Time ........................................................................................ 90 Section 7 Bus State Controller (BSC) Table 7.1 Pin Configuration ................................................................................................... 95 Table 7.2 Address Map .......................................................................................................... 97 Table 7.3 Access to Internal I/O Registers ............................................................................. 113 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.1 MTU Functions ...................................................................................................... Table 8.2 Pin Configuration ................................................................................................... Table 8.3 CCLR0 to CCLR2 (Channels 0, 3, and 4).............................................................. Table 8.4 CCLR0 to CCLR2 (Channels 1 and 2)................................................................... Table 8.5 TPSC0 to TPSC2 (Channel 0)................................................................................ Table 8.6 TPSC0 to TPSC2 (Channel 1)................................................................................ Table 8.7 TPSC0 to TPSC2 (Channel 2)................................................................................ Table 8.8 TPSC0 to TPSC2 (Channels 3 and 4)..................................................................... Table 8.9 MD0 to MD3.......................................................................................................... Table 8.10 TIORH_0 (Channel 0)............................................................................................ Table 8.11 TIORH_0 (Channel 0)............................................................................................ Table 8.12 TIORL_0 (Channel 0) ............................................................................................ Table 8.13 TIORL_0 (Channel 0) ............................................................................................ Table 8.14 TIOR_1 (Channel 1)............................................................................................... Table 8.15 TIOR_1 (Channel 1)............................................................................................... Table 8.16 TIOR_2 (Channel 2)............................................................................................... Table 8.17 TIOR_2 (channel 2) ............................................................................................... Table 8.18 TIORH_3 (Channel 3)............................................................................................ Table 8.19 TIORH_3 (Channel 3)............................................................................................ Table 8.20 TIORL_3 (Channel 3) ............................................................................................ Rev.1.00 Sep. 18, 2008 Page xxx of xxxiv REJ09B0069-0100 116 119 123 123 124 124 125 125 127 129 130 131 132 133 134 135 136 137 138 139 Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 8.25 Table 8.26 Table 8.27 Table 8.28 Table 8.29 Table 8.30 Table 8.31 Table 8.32 Table 8.33 Table 8.34 Table 8.35 Table 8.36 Table 8.37 Table 8.38 Table 8.39 Table 8.40 Table 8.41 Table 8.42 Table 8.43 Table 8.44 Table 8.45 TIORL_3 (Channel 3) ............................................................................................ TIORH_4 (Channel 4)............................................................................................ TIORH_4 (Channel 4)............................................................................................ TIORL_4 (Channel 4) ............................................................................................ TIORL_4 (Channel 4) ............................................................................................ Output Level Select Function................................................................................. Output Level Select Function................................................................................. Output Level Select Function................................................................................. Register Combinations in Buffer Operation........................................................... Cascaded Combinations ......................................................................................... PWM Output Registers and Output Pins................................................................ Phase Counting Mode Clock Input Pins................................................................. Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... Output Pins for Reset-Synchronized PWM Mode.................................................. Register Settings for Reset-Synchronized PWM Mode ......................................... Output Pins for Complementary PWM Mode ........................................................ Register Settings for Complementary PWM Mode................................................ Registers and Counters Requiring Initialization..................................................... MTU Interrupts ...................................................................................................... Mode Transition Combinations.............................................................................. Pin Configuration ................................................................................................... Pin Combinations ................................................................................................... 140 141 142 143 144 154 155 157 165 168 171 175 176 177 178 179 181 181 185 186 193 210 234 263 263 Section 9 Watchdog Timer Table 9.1 Pin Configuration ................................................................................................... 272 Table 9.2 WDT Interrupt Source (in Interval Timer Mode)................................................... 279 Section 10 Serial Communication Interface (SCI) Table 10.1 Pin Configuration ................................................................................................... Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0..................... Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode)............................................................................................ Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................. 285 293 294 294 295 295 296 297 Rev.1.00 Sep. 18, 2008 Page xxxi of xxxiv REJ09B0069-0100 Table 10.6 Table 10.6 Table 10.6 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)................. BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)................. BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3)................. BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4)................. Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Serial Transfer Formats (Asynchronous Mode) ..................................................... SSR Status Flags and Receive Data Handling........................................................ SCI Interrupt Sources ............................................................................................. 298 298 299 299 300 302 309 326 Section 11 A/D Converter Table 11.1 Pin Configuration ................................................................................................... Table 11.2 Channel Select List................................................................................................. Table 11.3 A/D Conversion Time (Single Mode) .................................................................... Table 11.4 A/D Conversion Time (Scan Mode)....................................................................... Table 11.5 A/D Converter Interrupt Source ............................................................................. Table 11.6 Analog Pin Specifications ...................................................................................... 331 335 343 343 344 349 Section 13 Motor Management Timer (MMT) Table 13.1 Pin Configuration ................................................................................................... 363 Table 13.2 Initial Values of TBRU to TBRW and Initial Output ............................................ 375 Table 13.3 Relationship between A/D Conversion Start Timing and Operating Mode ........... 378 Table 13.4 MMT Interrupt Sources.......................................................................................... 379 Table 13.5 Pin Configuration ................................................................................................... 387 Section 14 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Pin Function Controller (PFC) SH7108 Multiplexed Pins (Port A) ........................................................................ SH7108 Multiplexed Pins (Port B)......................................................................... SH7108 Multiplexed Pins (Port E)......................................................................... SH7108 Multiplexed Pins (Port F) ......................................................................... SH7108 Multiplexed Pins (Port G) ........................................................................ SH7109 Multiplexed Pins (Port A) ........................................................................ SH7109 Multiplexed Pins (Port B)......................................................................... SH7109 Multiplexed Pins (Port D) ........................................................................ SH7109 Multiplexed Pins (Port E)......................................................................... SH7109 Multiplexed Pins (Port F) ......................................................................... SH7108 Pin Functions in Each Operating Mode.................................................... SH7109 Pin Functions in Each Operating Mode (1) .............................................. SH7109 Pin Functions in Each Operating Mode (2) .............................................. 393 394 394 395 395 396 397 397 398 399 400 403 406 Rev.1.00 Sep. 18, 2008 Page xxxii of xxxiv REJ09B0069-0100 Section 15 I/O Ports Table 15.1 Port A Data Register L (PADRL) Read/Write Operations..................................... Table 15.2 Port B Data Register (PBDR) Read/Write Operations ........................................... Table 15.3 Port D Data Register L (PDDRL) Read/Write Operations..................................... Table 15.4 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations..... Table 15.5 Port F Data Register (PFDR) Read/Write Operations ............................................ Table 15.6 Port G Data Register (PGDR) Read/Write Operations........................................... 432 434 435 439 442 443 Section 18 Power-Down Modes Table 18.1 Internal Operating States in Each Mode................................................................. 450 Table 18.2 Pin Configuration ................................................................................................... 452 Section 20 Table 20.1 Table 20.2 Table 20.2 Table 20.3 Table 20.4 Table 20.5 Table 20.6 Table 20.7 Table 20.8 Table 20.9 Table 20.10 Table 20.11 Table 20.12 Table 20.13 Table 20.14 Electrical Characteristics Absolute Maximum Ratings................................................................................... DC Characteristics (1) ............................................................................................ DC Characteristics (2) ............................................................................................ Permitted Output Current Values ........................................................................... Clock Timing.......................................................................................................... Control Signal Timing............................................................................................ Bus Timing............................................................................................................. Multifunction Timer Pulse Unit (MTU) Timing .................................................... I/O Port Timing ...................................................................................................... Watchdog Timer (WDT) Timing ........................................................................... Serial Communication Interface (SCI) Timing ...................................................... Motor Management Timer (MMT) Timing............................................................ Output Enable (POE) Timing................................................................................. A/D Converter Timing ........................................................................................... A/D Converter Characteristics ............................................................................... 485 486 487 490 492 494 497 501 502 503 504 506 507 507 509 Appendix A Pin States Table A.1 Pin States ................................................................................................................ 511 Table A.2 Pin States (1) .......................................................................................................... 513 Table A.2 Pin States (2) .......................................................................................................... 513 Rev.1.00 Sep. 18, 2008 Page xxxiii of xxxiv REJ09B0069-0100 Rev.1.00 Sep. 18, 2008 Page xxxiv of xxxiv REJ09B0069-0100 Section 1 Overview Section 1 Overview The SH7108 Series single-chip RISC microprocessor integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The SH7108 Series CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as realtime control, which demands high speeds. In addition, the SH7108 Series includes on-chip peripheral functions necessary for system configuration, such as ROM, RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. As the on-chip ROM, only masked ROM version is available. However, when F-ZTAT (Flexible Zero Turn Around Time) version is required, the SH7046F (80 pins) or SH7047F (100 pins) can be used. 1.1 Features • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture ⎯ Instruction length: 16-bit fixed length for improved code efficiency ⎯ Load-store architecture (basic operations are executed between registers) ⎯ Sixteen 32-bit general registers ⎯ Five-stage pipeline ⎯ On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two to four cycles ⎯ C language-oriented 62 basic instructions • Various peripheral functions ⎯ Multifunction timer/pulse unit (MTU) ⎯ Motor management timer(MMT) ⎯ Compare match timer (CMT) ⎯ Watchdog timer (WDT) ⎯ Asynchronous or clocked synchronous serial communication interface (SCI) ⎯ 10-bit A/D converter ⎯ Clock pulse generator Rev.1.00 Sep. 18, 2008 Page 1 of 522 REJ09B0069-0100 Section 1 Overview • On-chip memory ROM Mask ROM version Model HD6437108 HD6437106 HD6437104 HD6437101 HD6437109 HD6437107 HD6437105 ROM 128 kbytes 64 kbytes 256 kbytes 32 kbytes 128 kbytes 64 kbytes 256 kbytes RAM 4 kbytes 4 kbytes 8 kbytes 2 kbytes 4 kbytes 4 kbytes 8 kbytes Remarks • Maximum operating frequency and operating temperature range Maximum Operating Frequency (MHz) (System Clock (φ) and Peripheral Operating Temperature Range (°C) Clock (Pφ)) (50, 25) or (40, 40) -20 to +75 Model HD6437108F50/HD6437106F50 HD6437104F50/HD6437101F50 HD6437109F50/HD6437107F50/ HD6437105F50 HD6437108FW50/HD6437106FW50 HD6437104FW50/HD6437101FW50 HD6437109FW50/HD6437107FW50/ HD6437105FW50 HD6437101F40 HD6437101FW40 (50, 25) or (40, 40) -40 to +85 (40, 40) (40, 40) -40 to +75 -40 to +85 • I/O ports Model HD6437108/HD6437106 HD6437104/HD6437101 HD6437109/HD6437107/HD6437105 No. of I/O Pins 42 53 No. of Input-only Pins 12 16 • Supports various power-down states • Compact package Model HD6437108/HD6437106/ HD6437104/HD6437101 HD6437109/HD6437107/ HD6437105 Package QFP-80 QFP-100 (Code) FP-80Q FP-100M Body Size 14.0 14.0 Pin Pitch 0.65 mm 0.50 mm × 14.0 mm × 14.0 mm Rev.1.00 Sep. 18, 2008 Page 2 of 522 REJ09B0069-0100 Section 1 Overview 1.2 Internal Block Diagram PA2/IRQ0/PCIO/SCK2 PA11/ADTRG/SCK3 PA8/TCLKC/RxD3 PA6/TCLKA/RxD2 PA9/TCLKD/TxD3 PA7/TCLKB/TxD2 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PB3/IRQ1/POE1 PA0/POE0/RxD2 PA1/POE1/TxD2 PB2/IRQ0/POE0 PA5/IRQ1/SCK3 PA15/POE6 PA14/POE5 PA13/POE4 PA10/SCK2 RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCL PLLCAP PLLVss Vcc VCL VCL Vcc Vcc Vcc Vss Vss Vss Vss AVcc AVcc AVss AVss Compare match timer (x 2 channels) A/D converter Watchdog timer Serial communication interface (x 2 channels) Masked ROM 256 kbytes/128 kbytes/ 64 kbytes/32 kbytes PA3/RxD3 PA4/TxD3 PA12 RAM 8 kbytes/4 kbytes/ 2 kbytes PG3/AN19 PG2/AN18 PG1/AN17 PG0/AN16 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PE21/PWOB PE20/PVOB PE19/PUOB PE18/PWOA PE17/PVOA PE16/PUOA PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D PE10/TIOC3C/TxD2 PE9/TIOC3B PE8/TIOC3A/SCK2 PE7/TIOC2B/RxD2 PE6/TIOC2A/SCK3 PE5/TIOC1B/TxD3 PE4/TIOC1A/RxD3 PE3/TIOC0D PE2/TIOC0C PE1/TIOC0B PE0/TIOC0A Figure 1.1 Internal Block Diagram of SH7108/SH7106/SH7104/SH7101 Rev.1.00 Sep. 18, 2008 Page 3 of 522 REJ09B0069-0100 PLL CPU Interrupt controller Bus state controller Multifunction timer pulse unit Motor management timer (x 1 channel) : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Section 1 Overview PA2/IRQ0/A2/PCIO/SCK2 PA7/TCLKB/WAIT/TxD2 PA15/CK/POE6/BACK PA6/TCLKA/RD/RxD2 PA0/A0/POE0/RxD2 PA11/ADTRG/SCK3 PA1/A1/POE1/TxD2 PA5/IRQ1/A5/SCK3 PA13/POE4/BREQ PA8/TCLKC/RxD3 PA9/TCLKD/TxD3 PA10/CS0/SCK2 PB5/IRQ3/POE3/CK PB4/IRQ2/POE2 PB3/IRQ1/POE1 PA14/RD/POE5 PA3/A3/RxD3 PA4/A4/TxD3 PA12/WRL PB2/IRQ0/POE0 PB1/A17 RES WDTOVF HSTBY MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVCL PLLCAP PLLVss VCL VCL Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss AVcc AVcc AVss AVss Motor management timer (x 1 channel) Compare match timer (x 2 channels) A/D converter Watchdog timer Serial communication interface (x 2 channels) Masked ROM 256 kbytes/ 128 kbytes/64 kbytes RAM 8 kbytes/4 kbytes P L L CPU Interrupt controller Bus state controller Multifunction timer pulse unit PD8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 PD3/D3 PD2/D2/SCK2 PD1/D1/TxD2 PD0/D0/RxD2 PE21/PWOB/A15 PE20/PVOB/A14 PE19/PUOB/A13 PE18/PWOA/A12 PE17/PVOA/WAIT/A11 PE16/PUOA/A10 PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D PE10/TIOC3C/TxD2/WRL PE9/TIOC3B PE8/TIOC3A/SCK2 PE7/TIOC2B/RxD2/A9 PE6/TIOC2A/SCK3/A8 PE5/TIOC1B/TxD3/A7 PE4/TIOC1A/RxD3/A6 PE3/TIOC0D PE2/TIOC0C PE1/TIOC0B PE0/TIOC0A/CS0 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 PB0/A16 : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Figure 1.2 Internal Block Diagram of SH7109/SH7107/SH7105 Rev.1.00 Sep. 18, 2008 Page 4 of 522 REJ09B0069-0100 1.3 Pin Assignment PA1/POE1/TxD2 VCL PA0/POE0/RxD2 Vss Vcc Vcc RES NMI MD3 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 QFP-80 (Top view) Figure 1.3 SH7108/SH7106/SH7104/SH7101 Pin Assignment PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RxD3 PE5/TIOC1B/TxD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RxD2 PE8/TIOC3A/SCK2 PE9/TIOC3B Vss PE10/TIOC3C/TxD2 Vcc PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA PE17/PVOA PE18/PWOA PE19/PUOB 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PA2/IRQ0/PCIO/SCK2 PA3/RxD3 PA4/TxD3 PA5/IRQ1/SCK3 PA6/TCLKA/RxD2 PA7/TCLKB/TxD2 PA8/TCLKC/RxD3 PA9/TCLKD/TxD3 PA10/SCK2 PA11/ADTRG/SCK3 PA12 PA13/POE4 PA14/POE5 PA15/POE6 PB2/IRQ0/POE0 PB3/IRQ1/POE1 PB4/IRQ2/POE2 Vcc PB5/IRQ3/POE3 Vss AVss PF8/AN8 AVcc PF9/AN9 PF10/AN10 PF11/AN11 PG0/AN16 PG1/AN17 PG2/AN18 PG3/AN19 PF12/AN12 PF13/AN13 PF14/AN14 AVcc PF15/AN15 AVss Vss PE21/PWOB VCL PE20/PVOB Rev.1.00 Sep. 18, 2008 Page 5 of 522 REJ09B0069-0100 Section 1 Overview Section 1 Overview Note: * PD2/D2/SCK2 PD0/D0/RxD2 PD1/D1/TxD2 PLLCAP RES PD4/D4 PD5/D5 PD6/D6 PD7/D7 PD3/D3 HSTBY PLLVCL PD8 VCL EXTAL MD0 NMI MD1 MD2 MD3 XTAL VSS VCC VCC 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 99 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PLLVSS 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 WDTOVF PE0/TIOC0A/CS0 PE1/TIOC0B PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RxD3/A6 PE5/TIOC1B/TxD3/A7 PE6/TIOC2A/SCK3/A8 PE7/TIOC2B/RxD2/A9 PE8/TIOC3A/SCK2 ASEBRKAK* PE9/TIOC3B VSS PE10/TIOC3C/TxD2/WRL VCC VCC PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA/A10 PE17/PVOA/WAIT/A11 PE18/PWOA/A12 PE19/PUOB/A13 PA0/A0/POE0/RxD2 VSS PA1/A1/POE1/TxD2 VCC PA2/IRQ0/A2/PCIO/SCK2 PA3/A3/RxD3 PA4/A4/TxD3 PA5/IRQ1/A5/SCK3 PA6/TCLKA/RD/RxD2 PA7/TCLKB/WAIT/TxD2 PA8/TCLKC/RxD3 PA9/TCLKD/TxD3 PA10/CS0/SCK2 PA11/ADTRG/SCK3 PA12/WRL PA13/POE4/BREQ PA14/RD/POE5 PA15/CK/POE6/BACK PB0/A16 PB1/A17 PB2/IRQ0/POE0 PB3/IRQ1/POE1 VCC PB4/IRQ2/POE2 PB5/IRQ3/POE3/CK ASEBRKAK: Rev.1.00 Sep. 18, 2008 Page 6 of 522 REJ09B0069-0100 Vcc fixed Enabled QFP-100 (Top view) Handling procedure Pull-up Pull-down Vss fixed Enabled Enabled Enabled NC Enabled 26 27 28 29 30 VCL VSS AVSS PE20/PVOB/A14 PE21/PWOB/A15 31 32 33 34 35 36 37 38 39 40 41 42 43 AVCC PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 44 45 46 47 48 49 50 Figure 1.4 SH7109/SH7107/SH7105 Pin Assignment VSS AVSS AVCC PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 Section 1 Overview 1.4 Table 1.1 Type Power Supply Pin Functions Pin Functions Symbol VCC I/O Input Name Power supply Function Power supply pins. Connect all these pins to the system power supply. The chip does not operate normally when some of these pins are open. Ground pins. Connect all these pins to the system power supply (0 V). The chip does not operate normally when some of these pins are open. External capacitance pins for internal power-down power supply. Connect these pins to VSS via a 0.47 µF (–10%/+100%) capacitor (placed close to the pin). External capacitance pin for internal power-down power supply for an on-chip PLL oscillator. Connect this pin to PLLVSS via a 0.47 µF (–10%/+100%) capacitor (placed close to the pin). On-chip PLL oscillator ground pin. External capacitance pin for an on-chip PLL oscillator. This is an NC (no connection) pin in the SH7105. VSS Input Ground VCL Output Power supply for internal power-down Power supply for PLL Clock PLLVCL Output PLLVSS PLLCAP Input Input Ground for PLL Capacitance for PLL EXTAL Input External clock For connection to a crystal resonator. An external clock can be supplied from the EXTAL pin. For examples of crystal resonator connection and external clock input, see section 4, Clock Pulse Generator. Crystal For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 4, Clock Pulse Generator. Supplies the system clock to external devices. XTAL Input CK Output System clock Rev.1.00 Sep. 18, 2008 Page 7 of 522 REJ09B0069-0100 Section 1 Overview Type Symbol I/O Input Name Set the mode Function Set the operating mode. Inputs at these pins should not be changed during operation. Pin for the flash memory. This pin is only used in the flash memory version. Writing or erasing of flash memory can be protected. This pin becomes the VCC pin for the masked ROM version. When this pin is driven low, the chip becomes to power-on reset state. When this pin is driven low, the chip becomes to manual reset state. When this pin is driven low, the chip shifts to standby mode. Operating MD3 to MD0 mode control FWP Input Protection against write operation into flash memory Power-on reset Manual reset Standby System control RES MRES HSTBY WDTOVF Input Input Input Output Watchdog Output signal for the watchdog timer timer overflow overflow. If this pin need to be pulleddown, use the resistor larger than 1 MΩ to pull the pin down. Bus request Bus request acknowledge Driven low when an external device request the bus to be released. Indicates that the bus is released to the external device. The device output the BREQ signal controls the bus after it has received the BACK signal. BREQ BACK Input Output Interrupts NMI Input Non-maskable Non-maskable interrupt pin. If this pin is interrupt not used, it should be fixed high or low. Interrupt request 3 to 0 These pins request a maskable interrupt. One of the level input or edge input can be selected. In case of the edge input, one of the rising edge, falling edge, or both can be selected. IRQ3 to IRQ0 Input IRQOUT Output Interrupt Shows that an interrupt cause has request output occurred. It is informed of an interrupt even when the bus is released. Address bus Data bus These pins output addresses. 8-bit bidirectional bus. Address bus A17 to A0 Data bus D7 to D0 Output I/O Rev.1.00 Sep. 18, 2008 Page 8 of 522 REJ09B0069-0100 Section 1 Overview Type Bus control Symbol CS0 RD WRL WAIT I/O Output Output Output Input Input Name Chip select 0 Read Write to lower byte Wait Function Chip-select signal for external memory or devices. Indicates reading of data from external devices. Indicates that lower eight bits (bits 7 to 0) of external data are to be written. Inserts waits to the bus cycle for accessing an external space. Multifunction TCLKA timer pulse TCLKB unit (MTU) TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B External clock These pins input an external clock. input for MTU timer MTU input The TGRA_0 to TGRD_0 input capture capture/output input/output compare output/PWM output compare pins. (channel 0) MTU input The TGRA_1 and TGRB_1 input capture capture/output input/output compare output/PWM output compare pins. (channel 1) MTU input The TGRA_2 and TGRB_2 input capture capture/output input/output compare output/PWM output compare pins. (channel 2) MTU input The TGRA_3 to TGRD_3 input capture capture/output input/output compare output/PWM output compare pins. (channel 3) MTU input The TGRA_4 to TGRD_4 input capture capture/output input/output compare output/PWM output compare pins. (channel 4) Input/ output Input/ output TIOC2A TIOC2B Input/ output TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Input/ output Input/ output Rev.1.00 Sep. 18, 2008 Page 9 of 522 REJ09B0069-0100 Section 1 Overview Type Serial communication interface (SCI) Symbol TxD2 TxD3 RxD2 RxD3 SCK2 SCK3 I/O Output Input Input/ output Output Output Output Output Output Output Input/ output Input Name Transmit data Receive data Serial clock U-phase of PWM U-phase of PWM V-phase of PWM V-phase of PWM W-phase of PWM W-phase of PWM PWM control Function Data output pins. Data input pins. Clock input/output pins. U-phase output pin for 6-phase nonoverlap PWM waveforms. U-phase output pin for 6-phase nonoverlap PWM waveforms. V-phase output pin for 6-phase nonoverlap PWM waveforms. V-phase output pin for 6-phase nonoverlap PWM waveforms. W-phase output pin for 6-phase nonoverlap PWM waveforms. W-phase output pin for 6-phase nonoverlap PWM waveforms. Counter clear input pin by external input or output pin, or toggle output pin synchronized with PWM period. Input pins for the signal to request the output pins of MTU or MMT to become high impedance state. Analog input pins. Motor PUOA management timer PUOB (MMT) PVOA PVOB PWOA PWOB PCIO Output control for MTU and MMT A/D converter POE6 to POE0 Port output control AN19 to AN0 Input ADTRG Input Analog input pins Input of trigger Pin for input of an external trigger to start A/D conversion. for A/D conversion Analog power supply Power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Connect all AVCC pins to the power supply. The chip does not operate normally when some of these pins are open. AVCC Input Rev.1.00 Sep. 18, 2008 Page 10 of 522 REJ09B0069-0100 Section 1 Overview Type A/D converter Symbol AVSS I/O Input Name Function Analog ground The ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Connect all AVSS pins to the system power supply. The chip does not operate normally when some of these pins are open. General purpose port General purpose port General purpose port General purpose port General purpose port General purpose port 16-bit general-purpose input/output pins. 6-bit general-purpose input/output pins. 9-bit general-purpose input/output pins. 22-bit general-purpose input/output pins. 16-bit general-purpose input/output pins. 4-bit general-purpose input/output pins. I/O ports PA15 to PA0 Input/ output PB5 to PB0 PD8 to PD0 Input/ output Input/ output PE21 to PE0 Input/ output PF15 to PF0 PG3 to PG0 Input Input Rev.1.00 Sep. 18, 2008 Page 11 of 522 REJ09B0069-0100 Section 1 Overview 1.5 Table 1.2 Item Differences from SH7046 Group Differences from SH7046 Group SH7046F Incorporated ⎯ PA3/POE4/RxD3 PA3/POE5/RxD3 PA5/IRQ1/POE6/SCK3 PA8/TCLKC/IRQ2/RxD3 PA9/TCLKC/IRQ3/RxD3 PA12/UBCTRG PE16/PUOA/UBCTRG SH7108/SH7106/SH7104/SH7101 Not incorporated Register RAMER deleted PA3/RxD3 PA4/TxD3 PA5/IRQ1/SCK3 PA8/TCLKC/RxD3 PA9/TCLKD/TxD3 PA12 PE16/PUOA Masked ROM: 256 kbytes/128 kbytes/64 kbytes/32 kbytes 8 kbytes/4 kbytes/2 kbytes 10 to 50 MHz DTC, UBC BSC I/O ports, PFC ROM RAM Operating frequency Flash: 256 kbytes 12 kbytes 4 to 50 MHz Rev.1.00 Sep. 18, 2008 Page 12 of 522 REJ09B0069-0100 Section 1 Overview 1.6 Table 1.3 Item Differences from SH7047 Group Differences from SH7047 Group SH7047F Incorporated ⎯ PA3/A3/POE4/RxD3 PA4/A4/POE5/TxD3 PA5/IRQ1/A5/POE6/SCK3 PA8/TCLKC/IRQ2/RxD3 PA9/TCLKD/IRQ3/TxD3 PA10/CS0/RD/TCK/SCK2 PA12/WRL/UBCTRG/TDI PA13/POE4/TDO/BREQ PA14/RD/POE5/TMS PA15/CK/POE6/TRST/BACK PB0/A16/HTxD1 PB1/A17/HRxD1/SCK4 PB2/IRQ0/POE0/RxD4 PB3/IRQ1/POE1/TxD4 PB4/IRQ2/POE2/SCK4 PD0/D0/RxD2/AUDATA0 PD1/D1/TxD2/AUDATA1 PD2/D2/SCK2/AUDATA2 PD3/D3/AUDATA3 PD4/D4/AUDRST PD5/D5/AUDMD PD6/D6/AUDCK PD7/D7/AUDSYNC PD8/UBCTRG PE16/PUOA/UBCTRG/A10 PE19/PUOB/RxD4/A13 PE20/PVOB/TxD4/A14 PE21/PWOB/SCK4/A15 SH7109/SH7107/SH7105 Not incorporated Register RAMER deleted PA3/A3/RxD3 PA4/A4/TxD3 PA5/IRQ1/A5/SCK3 PA8/TCLKC/RxD3 PA9/TCLKD/TxD3 PA10/CS0/SCK2 PA12/WRL PA13/POE4/BREQ PA14/RD/POE5 PA15/CK/POE6/BACK PB0/A16 PB1/A17 PB2/IRQ0/POE0 PB3/IRQ1/POE1 PB4/IRQ2/POE2 PD0/D0/RxD2 PD1/D1/TxD2 PD2/D2/SCK2 PD3/D3 PD4/D4 PD5/D5 PD6/D6 PD7/D7 PD8 PE16/PUOA/A10 PE19/PUOB/A13 PE20/PVOB/A14 PE21/PWOB/A15 Rev.1.00 Sep. 18, 2008 Page 13 of 522 REJ09B0069-0100 DTC, UBC, AUD, H-UDI, HCAN2, SCI (channel 4) BSC I/O ports, PFC Section 1 Overview Item ROM RAM Operating frequency SH7047F Flash: 256 kbytes 12 kbytes 4 to 50 MHz SH7109/SH7107/SH7105 Masked ROM: 256 kbytes/128 kbytes/64 kbytes 8 kbytes/4 kbytes 10 to 50 MHz Rev.1.00 Sep. 18, 2008 Page 14 of 522 REJ09B0069-0100 Section 2 CPU Section 2 CPU 2.1 Features • General-register architecture ⎯ Sixteen 32-bit general registers • Sixty-two basic instructions • Eleven addressing modes ⎯ Register direct [Rn] ⎯ Register indirect [@Rn] ⎯ Register indirect with post-increment [@Rn+] ⎯ Register indirect with pre-decrement [@-Rn] ⎯ Register indirect with displacement [@disp:4,Rn] ⎯ Register indirect with index [@R0, Rn] ⎯ GBR indirect with displacement [@disp:8,GBR] ⎯ GBR indirect with index [@R0,GBR] ⎯ Program-counter relative with displacement [@disp:8,PC] ⎯ Program-counter relative [disp:8/disp:12/Rn] ⎯ Immediate [#imm:8] 2.2 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. CPUS200A_010020030200 Rev.1.00 Sep. 18, 2008 Page 15 of 522 REJ09B0069-0100 Section 2 CPU General registers (Rn) 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0 Status register (SR) 31 9 8765 43 210 M Q I3 I2 I1 I0 ST Global base register (GBR) 31 GBR 0 Vector base register (VBR) 31 VBR 0 Multiply-accumulate register (MAC) 31 MACH MACL 0 Procedure register (PR) 31 PR 0 Program counter (PC) 31 PC 0 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 CPU Internal Registers Rev.1.00 Sep. 18, 2008 Page 16 of 522 REJ09B0069-0100 Section 2 CPU 2.2.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. 2.2.2 Control Registers The control registers consist of three 32-bit registers: status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Status Register (SR): Bit Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 6 5 4 3, 2 M Q I3 I2 I1 I0 — Undefined R/W Undefined R/W 1 1 1 1 All 0 R/W R/W R/W R/W R/W Reserved These bits are always read as 0. The write value should always be 0. 1 0 S T Undefined R/W Undefined R/W S Bit Used by the MAC instruction. T Bit The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. Rev.1.00 Sep. 18, 2008 Page 17 of 522 REJ09B0069-0100 Used by the DIV0U, DIV0S, and DIV1 instructions. Used by the DIV0U, DIV0S, and DIV1 instructions. Interrupt Mask Bits 31 to 10 — Section 2 CPU Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. Vector Base Register (VBR): Indicates the base address of the exception processing vector area. 2.2.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-andaccumulate operations. Procedure Register (PR): Registers to store the return address from a subroutine procedure. Program Counter (PC): Registers to indicate the sum of current instruction addresses and four, that is, the address of the second instruction after the current instruction. 2.2.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I3 to I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Classification General registers Rev.1.00 Sep. 18, 2008 Page 18 of 522 REJ09B0069-0100 Section 2 CPU 2.3 2.3.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 Longword 0 Figure 2.2 Data Format in Registers 2.3.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword 23 Byte Address m + 3 Address m + 2 15 Byte Word 7 Byte 0 Figure 2.3 Data Formats in Memory 2.3.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Rev.1.00 Sep. 18, 2008 Page 19 of 522 REJ09B0069-0100 Section 2 CPU Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.4 2.4.1 Instruction Features RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per State: The microprocessor can execute basic instructions in one state using the pipeline system. One state is 25 ns at 40 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data. Table 2.2 Sign Extension of Word Data Description Example of Conventional CPU ADD.W #H'1234,R0 CPU of This LSI MOV.W ADD .DATA.W @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD H'1234 instruction. Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. This reduces the disturbance of the pipeline control in case of branch instructions. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Rev.1.00 Sep. 18, 2008 Page 20 of 522 REJ09B0069-0100 Section 2 CPU Table 2.3 BRA ADD Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Conventional CPU ADD.W BRA R1,R0 TRGET TRGET R1,R0 CPU of This LSI Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations are executed in one to two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to three states. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four states. T Bit: The T bit in the status register changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Table 2.4 CMP/GE BT BF ADD CMP/EQ BT T Bit Description T bit is set when R0 ≥ R1. The program branches to TRGET0 when R0 ≥ R1 and to TRGET1 when R0 < R1. Example of Conventional CPU CMP.W BGE BLT R1,R0 TRGET0 TRGET1 #1,R0 TRGET R1,R0 TRGET0 TRGET1 #−1,R0 #0,R0 TRGET CPU of This LSI T bit is not changed by ADD. T bit is SUB.W set when R0 = 0. The program BEQ branches if R0 = 0. Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Table 2.5 Immediate Data Accessing CPU of This LSI MOV MOV.W .DATA.W 32-bit immediate MOV.L .DATA.L #H'12,R0 @(disp,PC),R0 ................. H'1234 @(disp,PC),R0 ................. H'12345678 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 Classification 8-bit immediate 16-bit immediate MOV.L #H'12345678,R0 Note: @(disp, PC) accesses the immediate data. Rev.1.00 Sep. 18, 2008 Page 21 of 522 REJ09B0069-0100 Section 2 CPU Absolute Address: When data is accessed by absolute address, the value in the absolute address is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect register addressing mode. Table 2.6 Absolute Address Accessing CPU of This LSI MOV.L MOV.B .DATA.L @(disp,PC),R1 @R1,R0 .................. H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0 Classification Absolute address 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the displacement value is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect indexed register addressing mode. Table 2.7 Displacement Accessing CPU of This LSI MOV.W MOV.W .DATA.W @(disp,PC),R0 @(R0,R1),R2 .................. H'1234 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement 2.4.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Rev.1.00 Sep. 18, 2008 Page 22 of 522 REJ09B0069-0100 Section 2 CPU Table 2.8 Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Equation Rn The effective address is register Rn. (The operand — is the contents of register Rn.) @Rn The effective address is the contents of register Rn. Rn Rn Addressing Mode Direct register addressing Indirect register addressing Rn Post-increment indirect register addressing @Rn+ The effective address is the contents of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn Rn (After the instruction executes) Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction is executed with Rn after this calculation) Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Pre-decrement indirect register addressing @-Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn – 1/2/4 1/2/4 – Rn – 1/2/4 Indirect register addressing with displacement @(disp:4, The effective address is the sum of Rn and a 4-bit Rn) displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4 Rev.1.00 Sep. 18, 2008 Page 23 of 522 REJ09B0069-0100 Section 2 CPU Addressing Mode Indirect indexed register addressing Instruction Format Effective Address Calculation @(R0, Rn) The effective address is the sum of Rn and R0. Rn + R0 Rn + R0 Equation Rn + R0 Indirect GBR addressing with displacement @(disp:8, The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is GBR) zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) × 1/2/4 + GBR + disp × 1/2/4 Byte: GBR + disp Word: GBR + disp × 2 Longword: GBR + disp × 4 Indirect indexed @(R0, GBR addressing GBR) The effective address is the sum of GBR value and GBR + R0 R0. GBR + R0 GBR + R0 Indirect PC addressing with displacement @(disp:8, The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is PC) zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) × 2/4 (for longword) PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 Word: PC + disp × 2 Longword: PC & H'FFFFFFFC + disp × 4 + Rev.1.00 Sep. 18, 2008 Page 24 of 522 REJ09B0069-0100 Section 2 CPU Addressing Mode PC relative addressing Instruction Format Effective Address Calculation disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). PC disp (sign-extended) × 2 + PC + disp × 2 Equation PC + disp × 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC disp (sign-extended) × 2 + PC + disp × 2 PC + disp × 2 Rn The effective address is the sum of the register PC PC + Rn and Rn. PC + Rn PC + Rn Immediate addressing #imm:8 #imm:8 #imm:8 The 8-bit immediate data (imm) for the TST, AND, — OR, and XOR instructions is zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, — and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. — Rev.1.00 Sep. 18, 2008 Page 25 of 522 REJ09B0069-0100 Section 2 CPU 2.4.3 Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Table 2.9 Instruction Formats Source Operand — 0 xxxx xxxx xxxx xxxx Instruction Formats 0 format 15 Destination Operand — Example NOP n format 15 xxxx nnnn xxxx xxxx 0 — Control register or system register Control register or system register nnnn: Direct register nnnn: Direct register nnnn: Indirect predecrement register Control register or system register Control register or system register — — MOVT STS Rn MACH,Rn STC.L SR,@-Rn LDC Rm,SR m format 15 xxxx mmmm xxxx xxxx 0 mmmm: Direct register mmmm: Indirect post-increment register mmmm: Indirect register mmmm: PC relative using Rm LDC.L @Rm+,SR JMP BRAF @Rm Rm Rev.1.00 Sep. 18, 2008 Page 26 of 522 REJ09B0069-0100 Section 2 CPU Instruction Formats nm format 15 xxxx nnnn mmmm xxxx 0 Source Operand mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiplyand-accumulate) nnnn*: Indirect post-increment register (multiplyand-accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register Destination Operand nnnn: Direct register nnnn: Indirect register MACH, MACL Example ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rn),R0 md format 15 xxxx xxxx mmmm dddd 0 mmmmdddd: Indirect register with displacement nd4 format 15 xxxx xxxx 0 nnnn dddd R0 (Direct register) nnnndddd: Indirect register with displacement mmmm: Direct register mmmmdddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register MOV.B R0,@(disp,Rn) nmd format 15 0 xxxx nnnn mmmm dddd MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Rev.1.00 Sep. 18, 2008 Page 27 of 522 REJ09B0069-0100 Section 2 CPU Instruction Formats d format 15 xxxx xxxx dddd dddd 0 Source Operand dddddddd: Indirect GBR with displacement Destination Operand R0 (Direct register) Example MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR) MOVA @(disp,PC),R0 BF BRA label label R0 (Direct register) dddddddd: Indirect GBR with displacement dddddddd: PC relative with displacement — d12 format 15 xxxx dddd dddd dddd 0 R0 (Direct register) dddddddd: PC relative dddddddddddd: PC relative — (label = disp + PC) MOV.L @(disp,PC),Rn nd8 format 15 xxxx nnnn dddd dddd 0 dddddddd: PC relative with displacement iiiiiiii: Immediate nnnn: Direct register i format 15 xxxx 0 xxxx iiii iiii Indirect indexed GBR R0 (Direct register) — nnnn: Direct register AND.B #imm,@(R0,GBR) AND TRAPA ADD #imm,R0 #imm #imm,Rn iiiiiiii: Immediate iiiiiiii: Immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. 2.5 2.5.1 Instruction Set Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Rev.1.00 Sep. 18, 2008 Page 28 of 522 REJ09B0069-0100 Section 2 CPU Table 2.10 Classification of Instructions Operation Classification Types Code Function Data transfer 5 MOV Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check 33 No. of Instructions 39 MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond Comparison DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG NEGC SUB SUBC SUBV Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-length multiply-and-accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Rev.1.00 Sep. 18, 2008 Page 29 of 522 REJ09B0069-0100 Section 2 CPU Operation Classification Types Code Function Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure No. of Instructions 14 14 11 Rev.1.00 Sep. 18, 2008 Page 30 of 522 REJ09B0069-0100 Section 2 CPU Operation Classification Types Code Function System control 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Transition to power-down mode Store control register data Store system register data Trap exception handling No. of Instructions 31 142 The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Rev.1.00 Sep. 18, 2008 Page 31 of 522 REJ09B0069-0100 Section 2 CPU Table 2.11 Symbols Used in Instruction Code, Operation, and Execution States Tables Item Instruction Format Described in mnemonic. OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement*2 mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ⋅ ⋅ ⋅ 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted*1 Value of T bit after instruction is executed. An em-dash (—) in the column means no change. Instruction code Described in MSB ↔ LSB order Outline of the Operation →, ← (xx) M/Q/T & | ^ ~ n Execution states T bit — — Notes: 1. Instruction execution states: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) equals to the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details, refer the SH-1/SH-2/SH-DSP Software Manual. Rev.1.00 Sep. 18, 2008 Page 32 of 522 REJ09B0069-0100 Section 2 CPU Data Transfer Instructions Table 2.12 Data Transfer Instructions Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit — — — — — — — — — — — — — — — — — — — — — — — Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@–Rn Rm,@–Rn Rm,@–Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 Operation #imm → Sign extension → Rn (disp × 2 + PC) → Sign extension → Rn (disp × 4 + PC) → Rn Rm → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → Sign extension → Rn (Rm) → Sign extension → Rn (Rm) → Rn Rn–1 → Rn, Rm → (Rn) Rn–2 → Rn, Rm → (Rn) Rn–4 → Rn, Rm → (Rn) (Rm) → Sign extension → Rn,Rm + 1 → Rm (Rm) → Sign extension → Rn,Rm + 2 → Rm (Rm) → Rn,Rm + 4 → Rm R0 → (disp + Rn) R0 → (disp × 2 + Rn) Rm → (disp × 4 + Rn) (disp + Rm) → Sign extension → R0 (disp × 2 + Rm) → Sign extension → R0 (disp × 4 + Rm) → Rn Rm → (R0 + Rn) Rev.1.00 Sep. 18, 2008 Page 33 of 522 REJ09B0069-0100 Section 2 CPU Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 Operation Rm → (R0 + Rn) Rm → (R0 + Rn) (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Rn R0 → (disp + GBR) R0 → (disp × 2 + GBR) R0 → (disp × 4 + GBR) (disp + GBR) → Sign extension → R0 (disp × 2 + GBR) → Sign extension → R0 (disp × 4 + GBR) → R0 disp × 4 + PC → R0 T → Rn Rm → Swap bottom two bytes → Rn Rm → Swap two consecutive words → Rn Rm: Middle 32 bits of Rn → Rn Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit — — — — — — — — — — — — — — — — R0,@(disp,GBR) 11000000dddddddd R0,@(disp,GBR) 11000001dddddddd R0,@(disp,GBR) 11000010dddddddd @(disp,GBR),R0 11000100dddddddd @(disp,GBR),R0 11000101dddddddd @(disp,GBR),R0 11000110dddddddd @(disp,PC),R0 Rn 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101 SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev.1.00 Sep. 18, 2008 Page 34 of 522 REJ09B0069-0100 Section 2 CPU Arithmetic Operation Instructions Table 2.13 Arithmetic Operation Instructions Execution States 1 1 1 1 1 1 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010101 0100nnnn00010001 0010nnnnmmmm1100 Operation Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, Carry → T Rn + Rm → Rn, Overflow → T If R0 = imm, 1 → T If Rn = Rm, 1 → T T Bit — — Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 — If Rn ≥ Rm with unsigned 1 data, 1 → T If Rn ≥ Rm with signed data, 1 → T 1 If Rn > Rm with unsigned 1 data, 1 → T If Rn > Rm with signed data, 1 → T If Rn > 0, 1 → T If Rn ≥ 0, 1 → T If Rn and Rm have an equivalent byte, 1→T Single-step division (Rn ÷ Rm) MSB of Rn → Q, MSB of Rm → M, M ^ Q → T 0 → M/Q/T 1 1 1 1 CMP/STR Rm,Rn DIV1 DIV0S DIV0U Rm,Rn Rm,Rn 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 1 1 1 DMULS.L Rm,Rn 2 to 4* Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rev.1.00 Sep. 18, 2008 Page 35 of 522 REJ09B0069-0100 Section 2 CPU Instruction DMULU.L Rm,Rn Instruction Code 0011nnnnmmmm0101 Operation Execution States T Bit — DT Rn 0100nnnn00010000 EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 Unsigned operation of 2 to 4* Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rn – 1 → Rn, when Rn 1 is 0, 1 → T. When Rn is nonzero, 0 → T 1 Byte in Rm is signextended → Rn Word in Rm is signextended → Rn Byte in Rm is zeroextended → Rn Word in Rm is zeroextended → Rn Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits Rn × Rm → MACL, 32 × 32 → 32 bits Signed operation of Rn × Rm → MACL 16 × 16 → 32 bits Unsigned operation of Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn 0 – Rm – T → Rn, Borrow → T Rn – Rm → Rn Rn – Rm – T → Rn, Borrow → T Rn – Rm → Rn, Underflow → T 1 1 1 Comparison result — — — — @Rm+,@Rn+ 0000nnnnmmmm1111 3/ — (2 to 4)* MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 3/(2)* — MUL.L MULS.W Rm,Rn Rm,Rn 0000nnnnmmmm0111 0010nnnnmmmm1111 2 to 4* 1 to 3* — — MULU.W Rm,Rn 0010nnnnmmmm1110 1 to 3* — NEG NEGC SUB SUBC SUBV Note: * Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 1 1 1 1 1 — Borrow — Borrow Overflow The normal number of execution states is shown. (The number in parentheses is the number of states when there is contention with the preceding or following instructions.) Rev.1.00 Sep. 18, 2008 Page 36 of 522 REJ09B0069-0100 Section 2 CPU Logic Operation Instructions Table 2.14 Logic Operation Instructions Execution States 1 1 3 1 1 1 3 4 1 1 Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) @Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 0010nnnnmmmm1000 11001000iiiiiiii 11001100iiiiiiii 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) If (Rn) is 0, 1 → T; 1 → MSB of (Rn) Rn & Rm; if the result is 0, 1 → T R0 & imm; if the result is 0, 1 → T T Bit — — — — — — — Test result Test result Test result Test result — — — (R0 + GBR) & imm; if the 3 result is 0, 1 → T Rn ^ Rm → Rn R0 ^ imm → R0 1 1 (R0 + GBR) ^ imm → (R0 3 + GBR) Rev.1.00 Sep. 18, 2008 Page 37 of 522 REJ09B0069-0100 Section 2 CPU Shift Instructions Table 2.15 Shift Instructions Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T T ← Rn ← 0 MSB → Rn → T T ← Rn ← 0 0 → Rn → T Rn2 → Rn Rn8 → Rn Rn16 → Rn Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MSB LSB MSB LSB MSB LSB MSB LSB — — — — — — SHLL16 Rn SHLR16 Rn Rev.1.00 Sep. 18, 2008 Page 38 of 522 REJ09B0069-0100 Section 2 CPU Branch Instructions Table 2.16 Branch Instructions Execution States 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 Instruction BF label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 Operation If T = 0, disp × 2 + PC → PC; if T = 1, nop Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop If T = 1, disp × 2 + PC → PC; if T = 0, nop Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop Delayed branch, disp × 2 + PC → PC Delayed branch, Rm + PC → PC Delayed branch, PC → PR, disp × 2 + PC → PC Delayed branch, PC → PR, Rm + PC → PC Delayed branch, Rm → PC Delayed branch, PC → PR, Rm → PC Delayed branch, PR → PC T Bit — — — — — — — — — — — BF/S label BT label BT/S label BRA label BRAF Rm BSR label BSRF Rm JMP JSR RTS Note: * @Rm @Rm One state when the program does not branch. Rev.1.00 Sep. 18, 2008 Page 39 of 522 REJ09B0069-0100 Section 2 CPU System Control Instructions Table 2.17 System Control Instructions Execution States 1 1 1 1 1 3 3 3 1 1 1 Instruction CLRT CLRMAC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS STS.L SR,Rn GBR,Rn VBR,Rn SR,@–Rn GBR,@–Rn VBR,@–Rn MACH,Rn MACL,Rn PR,Rn MACH,@–Rn Rm,SR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 Operation 0→T 0 → MACH, MACL Rm → SR Rm → GBR Rm → VBR (Rm) → SR, Rm + 4 → Rm (Rm) → GBR, Rm + 4 → Rm (Rm) → VBR, Rm + 4 → Rm Rm → MACH Rm → MACL Rm → PR (Rm) → MACL, Rm + 4 → Rm (Rm) → PR, Rm + 4 → Rm No operation Delayed branch, stack area → PC/SR 1→T Sleep SR → Rn GBR → Rn VBR → Rn Rn – 4 → Rn, SR → (Rn) Rn – 4 → Rn, GBR → (Rn) Rn – 4 → Rn, VBR → (Rn) MACH → Rn MACL → Rn PR → Rn Rn – 4 → Rn, MACH → (Rn) T Bit 0 — LSB — — LSB — — — — — — — — — — 1 — — — — — — — — — — — (Rm) → MACH, Rm + 4 → Rm 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1 1 Rev.1.00 Sep. 18, 2008 Page 40 of 522 REJ09B0069-0100 Section 2 CPU Instruction STS.L STS.L TRAPA Note: MACL,@–Rn PR,@–Rn #imm * Instruction Code 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation Rn – 4 → Rn, MACL → (Rn) Rn – 4 → Rn, PR → (Rn) Execution States 1 1 T Bit — — — PC/SR → stack area, (imm × 4 8 + VBR) → PC The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory → register) equals to the register used by the next instruction. Rev.1.00 Sep. 18, 2008 Page 41 of 522 REJ09B0069-0100 Section 2 CPU 2.6 2.6.1 Processing States State Transitions The CPU has five processing states: reset, exception processing, bus release, program execution, and power-down. Figure 2.4 shows the transitions between the states. From nay state when and =0 =1 and From nay state when = 0, =1 = 0, =0 =1 Power-on reset state =0 Manual reset state =1 = 1, When an internal power-on reset by WDT or internal manual reset by WDT occurs =1 Reset state Bus request released Exception processing state Bus request released Bus request released Exception processing source occurs Exception processing endws Bus release state Bus request generated Bus request generated Bus request released Program execution state SSBY bit set SSBY bit cleared for SLEEP instruction for SLEEP instruction Sleep mode Software standby mode Hardware standby mode Power-down mode From any state when = 0 and =0 Figure 2.4 Transitions between Processing States Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is entered. When the HSTBY pin is driven high and the RES pin level goes low, the power-on reset state is entered. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU’s processing state flow. Rev.1.00 Sep. 18, 2008 Page 42 of 522 REJ09B0069-0100 Section 2 CPU For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. If the HSTBY pin is driven low when the RES pin is low, the CPU will enter the hardware standby mode. Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them. Rev.1.00 Sep. 18, 2008 Page 43 of 522 REJ09B0069-0100 Section 2 CPU Rev.1.00 Sep. 18, 2008 Page 44 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four operating modes and four clock modes. The operating mode is determined by the settings of MD3 to MD0, and FWP pins. Do not change these pins during LSI operation (while power is on). Do not set these pins in the other way than the combination shown in table 3.1. Table 3.1 Selection of Operating Modes Pin Settings Product Type SH7108 Mode Mode No. FWP MD3 MD2 MD1 MD0 Name Mode 0 1 x x 0 0 MCU extended mode 0 MCU extended mode 1 MCU extended mode 2 BusWidth SH7106 SH7104 On-Chip of CS0 SH7101 ROM Space Disabled 8 bits ⎯ SH7109 SH7107 SH7105 Support ed ⎯ Mode 1* 1 x x 0 1 Disabled ⎯ ⎯ Mode 2 1 x x 1 0 Enabled Set by BCR1 in BSC ⎯ ⎯ Support ed Mode 3 1 x x 1 1 Single-chip Enabled mode Support Support ed ed Notes: The symbol x means “Don’t care”. * This mode cannot be used for this LSI. There are two modes as the MCU operating modes: MCU extended mode and single-chip mode. The clock mode is selected by the input of MD2 and MD3 pins. Rev.1.00 Sep. 18, 2008 Page 45 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode Pin Settings MD3 0 0 1 1 Note: * MD2 0 1 0 1 Maximum Operating Clock Frequency 12.5 MHz (Input clock × 1*, maximum of input clock: 12.5 MHz) 25 MHz (Input clock × 2*, maximum of input clock: 12.5 MHz) 40 MHz (Input clock × 4*, maximum of input clock: 10 MHz) 50 MHz (Input clock × 4 for system clock, Input clock × 2 for peripheral clock, maximum of input clock: 12.5 MHz) The frequencies for the system and peripheral module clocks are the same. 3.2 Input/Output Pins Table 3.3 describes the configuration of operating mode related pins. Table 3.3 Pin Name MD0 MD1 MD2 MD3 FWP Pin Configuration Input/Output Input Input Input Input Input Function Designates operating mode through the level applied to this pin Designates operating mode through the level applied to this pin Designates clock mode through the level applied to this pin Designates clock mode through the level applied to this pin Pin for the hardware protection against programming/erasing the on-chip flash memory Rev.1.00 Sep. 18, 2008 Page 46 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes 3.3 3.3.1 Explanation of Operating Modes Mode 0 (MCU Extended Mode 0) The CS0 space becomes an external memory space with 8-bit bus width in mode 0. This mode is not supported in the SH7108/SH7106/SH7104/SH7101. 3.3.2 Mode 1 (MCU Extended Mode 1) This mode is not supported in this LSI. 3.3.3 Mode 2 (MCU Extended Mode 2) The on-chip ROM is enabled and the CS0 space can be used in mode 2. This mode is not supported in the SH7108/SH7106/SH7104/SH7101. 3.3.4 Mode 3 (Single-Chip Mode) All ports can be used in mode 3, however the external address cannot be used. The SH7108/SH7106/SH7104/SH7101 supports only this mode. 3.3.5 Clock Mode The input waveform frequency can be used as is, doubled, or quadrupled as system clock frequency in mode 0 to mode 3. Rev.1.00 Sep. 18, 2008 Page 47 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes 3.4 Address Map The address map for the operating modes are shown in figures 3.1 to 3.6. ROM: 128 kbytes, RAM: 4 kbytes Mode 3 H'00000000 On-chip ROM H'0001FFFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFF000 On-chip RAM H'FFFFFFFF Figure 3.1 Address Map of SH7108 Rev.1.00 Sep. 18, 2008 Page 48 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes ROM: 64 kbytes, RAM: 4 kbytes Mode 3 H'00000000 On-chip ROM H'0000FFFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFF000 On-chip RAM H'FFFFFFFF Figure 3.2 Address Map of SH7106 Rev.1.00 Sep. 18, 2008 Page 49 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes ROM: 256 kbytes, RAM: 8 kbytes Mode 3 H'00000000 On-chip ROM H'0003FFFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFE000 On-chip RAM H'FFFFFFFF Figure 3.3 Address Map of SH7104 Rev.1.00 Sep. 18, 2008 Page 50 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes ROM: 32 kbytes, RAM: 2 kbytes Mode 3 H'00000000 On-chip ROM H'00007FFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFF800 On-chip RAM H'FFFFFFFF Figure 3.4 Address Map of SH7101 Rev.1.00 Sep. 18, 2008 Page 51 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes ROM: 128 kbytes, RAM: 4 kbytes Mode 0 H'00000000 H'00000000 On-chip ROM CS0 space H'0001FFFF H'00020000 H'0003FFFF H'00040000 H'001FFFFF H'00200000 CS0 space Reserved H'0023FFFF H'00240000 Reserved H'FFFF7FFF On-chip peripheral I/O registers H'FFFFBFFF H'FFFFC000 H'FFFF8000 H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers Reserved H'0001FFFF Mode 2 H'00000000 On-chip ROM Mode 3 Reserved H'FFFFEFFF H'FFFFF000 On-chip RAM H'FFFFFFFF H'FFFFFFFF H'FFFFEFFF H'FFFFF000 Reserved H'FFFFF000 On-chip RAM H'FFFFFFFF On-chip RAM Figure 3.5 Address Map for Operating Modes of SH7109 Rev.1.00 Sep. 18, 2008 Page 52 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes ROM: 64 kbytes, RAM: 4 kbytes Mode 0 H'00000000 H'00000000 On-chip ROM CS0 space H'0000FFFF H'00010000 H'0003FFFF H'00040000 H'001FFFFF H'00200000 CS0 space Reserved H'0023FFFF H'00240000 Reserved H'FFFF7FFF On-chip peripheral I/O registers H'FFFFBFFF H'FFFFC000 H'FFFF8000 H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers Reserved H'0000FFFF Mode 2 H'00000000 On-chip ROM Mode 3 Reserved H'FFFFEFFF H'FFFFF000 On-chip RAM H'FFFFFFFF H'FFFFFFFF H'FFFFEFFF H'FFFFF000 Reserved H'FFFFF000 On-chip RAM H'FFFFFFFF On-chip RAM Figure 3.6 Address Map for Operating Modes of SH7107 Rev.1.00 Sep. 18, 2008 Page 53 of 522 REJ09B0069-0100 Section 3 MCU Operating Modes ROM: 256 kbytes, RAM: 8 kbytes Mode 0 H'00000000 H'00000000 Mode 2 H'00000000 Mode 3 CS0 space On-chip ROM On-chip ROM H'0003FFFF H'00040000 H'0003FFFF H'00040000 H'001FFFFF H'00200000 CS0 space Reserved H'0023FFFF H'00240000 Reserved Reserved H'0003FFFF H'FFFF7FFF On-chip peripheral I/O registers H'FFFFBFFF H'FFFFC000 Reserved H'FFFFDFFF H'FFFFE000 On-chip RAM H'FFFF8000 H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers Reserved H'FFFFDFFF H'FFFFE000 On-chip RAM H'FFFFE000 On-chip RAM H'FFFFFFFF H'FFFFFFFF H'FFFFFFFF Figure 3.7 Address Map for Operating Modes of SH7105 3.5 Initial State of This LSI In this LSI, some on-chip modules are set to the module standby state as its initial state for power down. Therefore, to operate those modules, it is necessary to clear module standby state. For details, refer to section 18, Power-Down Modes. Rev.1.00 Sep. 18, 2008 Page 54 of 522 REJ09B0069-0100 Section 4 Clock Pulse Generator Section 4 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and peripheral clock (Pφ) to generate the internal clock (φ/2 to φ/8192, Pφ/2 to Pφ/1024). The CPG consists of an oscillator, PLL circuit, and pre-scaler. A block diagram of the clock pulse generator is shown in figure 4.1. The frequency from the oscillator can be modified by the PLL circuit. PLLCAP EXTAL Oscillator XTAL PLL circuit Clock divider (× 1/2) Pre-scaler MD2 MD3 Pre-scaler Clock mode control circuitry φ φ/2 to φ/8192 Pφ/2 to Pφ/1024 Pφ Within the LSI Figure 4.1 Block Diagram of the Clock Pulse Generator 4.1 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.1. Use an AT-cut parallel-resonance type crystal resonator that has a resonance frequency of 4 to 12.5 MHz. It is recommended to consult crystal dealer concerning the compatibility of the crystal resonator and the LSI. CPG0110B_000020020700 Rev.1.00 Sep. 18, 2008 Page 55 of 522 REJ09B0069-0100 Section 4 Clock Pulse Generator CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 18 to 22 pF (Recommended value) Figure 4.2 Connection of the Crystal Resonator (Example) Table 4.1 Damping Resistance Values 4 500 8 200 10 0 12.5 0 Frequency (MHz) Rd (Ω) Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.2. CL L XTAL C0 Rs EXTAL AT-cut parallel-resonance type Figure 4.3 Crystal Resonator Equivalent Circuit Table 4.2 Crystal Resonator Characteristics 4 120 7 8 80 7 10 60 7 12.5 50 7 Frequency (MHz) Rs max (Ω) C0 max (pF) 4.1.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it in standby mode. During operation, make the external input clock frequency 4 to 12.5 MHz. When leaving the XTAL pin open, make sure the stray capacitance is less than 10 pF. Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing standby mode, in order to ensure the PLL stabilization time. Rev.1.00 Sep. 18, 2008 Page 56 of 522 REJ09B0069-0100 Section 4 Clock Pulse Generator EXTAL XTAL Open state External clock input Figure 4.4 Example of External Clock Connection 4.2 Function for Detecting the Oscillator Halt This CPG can detect a clock halt and automatically cause the timer pins to become highimpedance when any system abnormality causes the oscillator to halt. That is, when a change of EXTAL has not been detected, the high-current 12 pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT, PE16/PUOA, PE17/PVOA, PE18/PWOA, PE19/PUOB, PE20/PVOB, PE21/PWOB) are set to high-impedance regardless of PFC setting. Even in standby mode, these 12 pins become high-impedance regardless of PFC setting. These pins enter the normal state after standby mode is released. When abnormalities that halt the oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI operations, including these 12 pins, become undefined even when the oscillator operation starts again. 4.3 4.3.1 Usage Notes Note on Crystal Resonator A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user’s board design. Since the resonator circuit component values depend on the resonator itself, floating capacitances in the application circuit, and other factors, we recommend consulting with the resonator manufacturer to determine the circuit component values used. Ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 4.3.2 Notes on Board Design Measures against radiation noise are taken in this LSI. If radiation noise needs to be further reduced, usage of a multi-layer printed circuit board with ground planes is recommended. Rev.1.00 Sep. 18, 2008 Page 57 of 522 REJ09B0069-0100 Section 4 Clock Pulse Generator When using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 4.5 Cautions for Oscillator Circuit System Board Design A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVCL and PLLVSS circuit against VCC and VSS circuit from the board power-supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. R1: 3kΩ PLLCAP PLLVCL CPB = 0.47 μF* PLLVSS C1: 470 pF VCC CB = 0.47 μF* VSS (Values are recommended values.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry Around the PLL Electromagnetic waves are radiated from an LSI in operation. This LSI has an electromagnetic peak in the harmonics band whose primary frequency is determined by the lower frequency between the system clock (φ) and peripheral clock (Pφ). For example, when φ = 50 MHz and Pφ = 40 MHz, the primary frequency is 40 MHz. If this LSI is used adjacent to a device sensitive to electromagnetic interference, e.g. FM/VHF band receiver, a printed circuit board of more than four layers with planes exclusively for system ground is recommended. Rev.1.00 Sep. 18, 2008 Page 58 of 522 REJ09B0069-0100 Section 5 Exception Processing Section 5 Exception Processing 5.1 5.1.1 Overview Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority. Table 5.1 Exception Reset Address error Interrupt Types of Exception Processing and Priority Source Power-on reset Manual reset CPU address error NMI IRQ On-chip peripheral modules: • • • • • • Priority High Multifunction timer pulse unit (MTU) A/D converter 0 and 1 (A/D0, A/D1) Compare match timer 0 and 1 (CMT0, CMT1) Watchdog timer (WDT) Input/output port (I/O) (MTU) Serial communication interface 2 and 3 (SCI2 and SCI3) • Motor management timer (MMT) • A/D converter 2 (A/D2) • Input/output port (I/O) (MMT) Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay 1 2 branch instruction* or instructions that rewrite the PC* ) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, and BRAF. Rev.1.00 Sep. 18, 2008 Page 59 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.1.2 Exception Processing Operations The exception processing sources are detected and the processing starts according to the timing shown in table 5.2. Table 5.2 Exception Reset Timing for Exception Source Detection and Start of Exception Processing Source Power-on reset Manual reset Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high or when WDT overflows. Starts when the MRES pin changes from low to high. Detected when instruction is decoded and starts when the execution of the previous instruction is completed. Trap instruction General illegal instructions Illegal slot instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. Address error Interrupts Instructions When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Processing Vector Table, for more information. H'00000000 is then written to the vector base register (VBR) , and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR’s interrupt mask bits (I3 to I0). For address error and instruction exception processing, the I3 to I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. Rev.1.00 Sep. 18, 2008 Page 60 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) CPU address error (Reserved by system) Interrupts (Reserved by system) NMI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : 31 Trap instruction (user vector) 32 : 63 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 H'00000038 to H'0000003B H'0000003C to H'0000003F : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF Rev.1.00 Sep. 18, 2008 Page 61 of 522 REJ09B0069-0100 Exception Sources Power-on reset Section 5 Exception Processing Exception Sources Interrupts IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Vector Numbers 64 65 66 67 68 69 70 71 Vector Table Address Offset H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F H'00000120 to H'00000123 : H'000003FC to H'000003FF On-chip peripheral module* 72 : 255 Note: * The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller, and table 6.2, Interrupt Exception Sources, Vector Addresses and Priorities. Table 5.4 Calculating Exception Processing Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) × 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Rev.1.00 Sep. 18, 2008 Page 62 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.2 5.2.1 Resets Types of Reset Resets have the highest priority of any exception source. There are two types of resets: manual resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset Status WDT Overflow MRES ⎯ Overflow ⎯ ⎯ High Low Internal Status On-Chip Peripheral Module Initialized Initialized Type Power-on reset Manual reset RES Low High High CPU/INTC Initialized Initialized Initialized PFC, IO Port Initialized Not initialized Not initialized Not initialized 5.2.2 Power-On Reset Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a poweron reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 25 tcyc when the clock circuit is running. During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset status. In the power-on reset status, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU will then operate as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception processing vector table are set in PC and SP, then the program begins executing. Rev.1.00 Sep. 18, 2008 Page 63 of 522 REJ09B0069-0100 Section 5 Exception Processing Be certain to always perform power-on reset processing when turning the system power on. Power-On Reset by WDT: When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and the WDT’s TCNT overflows, the LSI becomes to be a poweron reset state. The pin function controller (PFC) registers and I/O port registers are not initialized by the reset signal generated by the WDT (these registers are initialized only by a power-on reset from outside of the chip). If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When WDT-initiated power-on reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, then the program begins executing. 5.2.3 Manual Reset When the RES pin is high and the MRES pin is driven low, the LSI enters a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least 25 tcyc. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters manual reset status in the middle of a bus cycle, manual reset exception processing does not start until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus cycle ends. (Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets. Rev.1.00 Sep. 18, 2008 Page 64 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.3 5.3.1 Address Errors The Cause of Address Error Exception Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Instruction fetched from external memory space when in single chip mode Data read/write CPU Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* External memory space accessed when in single chip mode Note: * Address Errors None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) Address error occurs Address error occurs See section 7, Bus State Controller (BSC) for more information on the on-chip peripheral module space. Rev.1.00 Sep. 18, 2008 Page 65 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends, the current instruction finishes, and then address error exception processing starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The start address of the exception service routine is fetched from the exception processing vector table that corresponds to the occurred address error, and the program starts executing from that address. The jump in this case is not a delayed branch. 5.4 5.4.1 Interrupts Interrupt Sources Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, IRQ, and on-chip peripheral modules. Table 5.7 Type NMI IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) IRQ0 to IRQ3 pins (external input) Multifunction timer pulse unit Compare match timer A/D converter (A/D0 and A/D1) A/D converter (A/D2) Serial communication interface Watchdog timer Motor management timer Input/output port Number of Sources 1 4 23 2 2 1 8 1 2 2 Each interrupt source is allocated a different vector number and vector table offset. See section 6, Interrupt Controller (INTC), and table 6.2, Interrupt Exception Sources, Vector Addresses and Priorities, for more information on vector numbers and vector table address offsets. Rev.1.00 Sep. 18, 2008 Page 66 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.4.2 Interrupt Priority Level The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception processing according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the INTC’s interrupt priority registers A, D to K (IPRA, IPRD to IPRK) as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.4, Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK), for more information on IPRA, IPRD to IPRK. Table 5.8 Type NMI IRQ On-chip peripheral module Interrupt Priority Priority Level 16 0 to 15 Comment Fixed priority level. Cannot be masked. Set with interrupt priority registers A, D to K (IPRA, IPRD to IPRK). 5.4.3 Interrupt Exception Processing When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) in the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.6, Interrupt Operation, for more information on the interrupt exception processing. 5.5 5.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Rev.1.00 Sep. 18, 2008 Page 67 of 522 REJ09B0069-0100 Section 5 Exception Processing Table 5.9 Type Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that rewrite the PC Comment ⎯ Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF ⎯ Trap instruction Illegal slot instructions General illegal instructions Undefined code anywhere besides in a delay slot 5.5.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start address of the exception service routine from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction, jumps to that address and starts executing the program. This jump is not a delayed branch. 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called ″instruction placed in a delay slot″. When the instruction placed in the delay slot is an undefined code, illegal slot exception processing starts after the undefined code is decoded. Illegal slot exception processing also starts when an instruction that rewrites the program counter (PC) is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception service routine is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump in this case is not a delayed branch. Rev.1.00 Sep. 18, 2008 Page 68 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. 5.6 Cases when Exception Sources Are Not Accepted When an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. In this case, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction* 1 2 Address Error Not accepted Accepted Interrupt Not accepted Not accepted Immediately after an interrupt-disabled instruction* Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 5.6.1 Immediately after a Delayed Branch Instruction When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction placed immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after an Interrupt-Disabled Instruction When an instruction placed immediately after an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors can be accepted. Rev.1.00 Sep. 18, 2008 Page 69 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is shown in table 5.11. Table 5.11 Stack Status after Exception Processing Ends Types Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Stack Status Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits General illegal instruction SP Address of instruction after general illegal instruction 32 bits SR 32 bits Interrupt SP Address of instruction after executed instruction 32 bits SR 32 bits Illegal slot instruction SP Jump destination address of delay branch instruction 32 bits SR 32 bits Rev.1.00 Sep. 18, 2008 Page 70 of 522 REJ09B0069-0100 Section 5 Exception Processing 5.8 5.8.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the value of the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start after the first exception processing is ended. Address errors will also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the service routine for address error exception and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the value of SP is reduced by 4 for both of SR and PC, therefore the value of SP is still not a multiple of four after the stacking. The address value output during stacking is the SP value, so the address itself where the error occurred is output. This means that the write data stacked is undefined. Rev.1.00 Sep. 18, 2008 Page 71 of 522 REJ09B0069-0100 Section 5 Exception Processing Rev.1.00 Sep. 18, 2008 Page 72 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features • 16 levels of interrupt priority • NMI noise canceler function • Occurrence of interrupt can be reported externally (IRQOUT pin) Rev.1.00 Sep. 18, 2008 Page 73 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 MTU CMT MMT A/D SCI WDT I/O Input control CPU request determination Priority determination Comparator Interrupt request SR I3 I2 I1 I0 CPU (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) ICR1 ICR2 ISR IPR IPRA, IPRD to IPRK Module bus Bus interface INTC Legend: MTU: Multifunction timer pulse unit CMT: Compare match timer MMT: Motor management timer A/D: A/D converter SCI: Serial communication interface WDT: I/O: ICR1, ICR2: ISR: IPRA, IPRD to IPRK: SR: Watchdog timer I/O port (Port output controller) Interrupt control register IRQ status register Interrupt priority level setting registers A, D to K Status register Figure 6.1 INTC Block Diagram Rev.1.00 Sep. 18, 2008 Page 74 of 522 REJ09B0069-0100 Internal bus Section 6 Interrupt Controller (INTC) 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin Pin Configuration Abbreviation NMI IRQ0 to IRQ3 IRQOUT I/O Input Input Output Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals Output of notification signal when an interrupt has occurred 6.3 Register Descriptions The interrupt controller has the following registers. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Interrupt control register 1 (ICR1) • Interrupt control register 2 (ICR2) • IRQ status register (ISR) • Interrupt priority register A (IPRA) • Interrupt priority register D (IPRD) • Interrupt priority register E (IPRE) • Interrupt priority register F (IPRF) • Interrupt priority register G (IPRG) • Interrupt priority register H (IPRH) • Interrupt priority register I (IPRI) • Interrupt priority register J (IPRJ) • Interrupt priority register K (IPRK) Rev.1.00 Sep. 18, 2008 Page 75 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin. Bit 15 Bit Name NMIL Initial Value 1/0 R/W R Description NMI Input Level Sets the level of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: NMI input level is low 1: NMI input level is high 14 to 9 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select 0: Interrupt request is detected at falling edge of NMI input 1: Interrupt request is detected at rising edge of NMI input 7 IRQ0S 0 R/W IRQ0 Sense Select Sets the IRQ0 interrupt request detection mode. 0: Interrupt request is detected at low level of IRQ0 input 1: Interrupt request is detected at edge of IRQ0 input (edge direction is selected by ICR2) 6 IRQ1S 0 R/W IRQ1 Sense Select Sets the IRQ1 interrupt request detection mode. 0: Interrupt request is detected at low level of IRQ1 input 1: Interrupt request is detected at edge of IRQ1 input (edge direction is selected by ICR2) 5 IRQ2S 0 R/W IRQ2 Sense Select Sets the IRQ2 interrupt request detection mode. 0: Interrupt request is detected at low level of IRQ2 input 1: Interrupt request is detected at edge of IRQ2 input (edge direction is selected by ICR2) Rev.1.00 Sep. 18, 2008 Page 76 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Bit 4 Bit Name IRQ3S Initial Value 0 R/W R/W Description IRQ3 Sense Select Sets the IRQ3 interrupt request detection mode. 0: Interrupt request is detected at low level of IRQ3 input 1: Interrupt request is detected at edge of IRQ3 input (edge direction is selected by ICR2) 3 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6.3.2 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0 to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the edge detection mode by the sense select bits of IRQ0 to IRQ 3 in the interrupt control register 1 (ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the setting of ICR2 is ignored. Bit 15 14 Bit Name IRQ0ES1 IRQ0ES0 Initial Value 0 0 R/W R/W R/W Description These bits set the IRQ0 interrupt request edge detection mode. 00: Interrupt request is detected at falling edge of IRQ0 input 01: Interrupt request is detected at rising edge of IRQ0 input 10: Interrupt request is detected at both falling and rising edges of IRQ0 input 11: Setting prohibited These bits set the IRQ1 interrupt request edge detection mode. 00: Interrupt request is detected at falling edge of IRQ1 input 01: Interrupt request is detected at rising edge of IRQ1 input 10: Interrupt request is detected at both falling and rising edges of IRQ1 input 11: Setting prohibited 13 12 IRQ1ES1 IRQ1ES0 0 0 R/W R/W Rev.1.00 Sep. 18, 2008 Page 77 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Bit 11 10 Bit Name IRQ2ES1 IRQ2ES0 Initial Value 0 0 R/W R/W R/W Description These bits set the IRQ2 interrupt request edge detection mode. 00: Interrupt request is detected at falling edge of IRQ2 input 01: Interrupt request is detected at rising edge of IRQ2 input 10: Interrupt request is detected at both falling and rising edges of IRQ2 input 11: Setting prohibited 9 8 IRQ3ES1 IRQ3ES0 0 0 R/W R/W These bits set the IRQ3 interrupt request edge detection mode. 00: Interrupt request is detected at falling edge of IRQ3 input 01: Interrupt request is detected at rising edge of IRQ3 input 10: Interrupt request is detected at both falling and rising edges of IRQ3 input 11: Setting prohibited 7 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 78 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.3.3 IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading IRQnF = 1. Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 IRQ0F IRQ1F IRQ2F IRQ3F 0 0 0 0 R/W R/W R/W R/W IRQ0 to IRQ3 Flags These bits display the IRQ0 to IRQ3 interrupt request status. [Setting condition] When interrupt source that is selected by ICR1 and ICR2 has occurred. [Clearing conditions] • • When 0 is written after reading IRQnF = 1 When interrupt exception processing has been executed at high level of IRQn input under the low level detection mode. When IRQn interrupt exception processing has been executed under the edge detection mode of falling edge, rising edge, or both falling and rising edges. • 15 to 8 ⎯ • 3 to 0 ⎯ All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 79 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) Interrupt priority registers are nine 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.2. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups, bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000.) Bit 15 14 13 12 Bit Name IPR15 IPR14 IPR13 IPR12 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) These bits set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 11 10 9 8 IPR11 IPR10 IPR9 IPR8 0 0 0 0 R/W R/W R/W R/W Rev.1.00 Sep. 18, 2008 Page 80 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Bit 7 6 5 4 Bit Name IPR7 IPR6 IPR5 IPR4 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) 3 2 1 0 IPR3 IPR2 IPR1 IPR0 0 0 0 0 R/W R/W R/W R/W These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name. Rev.1.00 Sep. 18, 2008 Page 81 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.4 6.4.1 Interrupt Sources External Interrupts There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Set the IRQ sense select bits (IRQ0S to IRQ3S) of the interrupt control register 1 (ICR1) and the IRQ edge select bit (IRQ0ES[1:0] to IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select low level detection, falling edge detection, or rising edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A (IPRA). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F to IRQ3F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change at the IRQ pin from high to low level. The results of detection for IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F to IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3 to I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of this IRQ3 to IRQ0 interrupts. Rev.1.00 Sep. 18, 2008 Page 82 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) IRQnS IRQnES ISR.IRQnF Selection IRQ pins Level detection Edge detection S Q CPU interrupt request RESIRQn R (Acceptance of IRQn interrupt/Writing 0 after reading IRQnF = 1) Figure 6.2 Control of IRQ3 to IRQ0 Interrupts 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. As a different interrupt vector is assigned to each interrupt source, the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules by setting interrupt priority registers A, D to K (IPRA, IPRD to IPRK). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the onchip peripheral module interrupt that was accepted. Rev.1.00 Sep. 18, 2008 Page 83 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Processing Vectors Table Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. For the details of calculation of vector table address, see table 5.4. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A, D to K (IPRA, IPRD to IPRK). However, the smaller vector number has interrupt source, the higher priority ranking is assigned among two or more interrupt sources specified by the same IPR, and the priority ranking cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order indicated in table 6.2. Table 6.2 Interrupt Source External pin ⎯ ⎯ Interrupts Interrupt Exception Processing Vectors and Priorities Name NMI Reserved by system Reserved by system IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system Vector No. 11 14 15 64 65 66 67 68 69 70 71 72 76 80 84 Vector Table Starting Address H'0000002C H'00000038 H'0000003C H'00000100 H'00000104 H'00000108 H'0000010C H'00000110 H'00000114 H'00000118 H'0000011C H'00000120 H'00000130 H'00000140 H'00000150 IPR ⎯ ⎯ ⎯ IPRA15 to IPRA12 IPRA11 to IPRA8 IPRA7 to IPRA4 IPRA3 to IPRA0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Low Default Priority High ⎯ Reserved by system Reserved by system Reserved by system Reserved by system Rev.1.00 Sep. 18, 2008 Page 84 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Interrupt Source Name Vector No. 88 89 90 91 92 96 97 100 101 104 105 108 109 112 113 114 115 116 120 121 122 123 124 128 to 135 136 137 138 to 143 Vector Table Starting Address H'00000160 H'00000164 H'00000168 H'0000016C H'00000170 H'00000180 H'00000184 H'00000190 H'00000194 H'000001A0 H'000001A4 H'000001B0 H'000001B4 H'000001C0 H'000001C4 H'000001C8 H'000001CC H'000001D0 H'000001E0 H'000001E4 H'000001E8 H'000001EC H'000001F0 H'00000200 to H'0000021C H'00000220 H'00000224 H'00000228 to H'0000023C IPR IPRD15 to IPRD12 Default Priority High MTU channel 0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 MTU channel 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 MTU channel 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 MTU channel 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 MTU channel 4 TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 ⎯ A/D Reserved by system ADI0 ADI1 ⎯ Reserved by system IPRD11 to IPRD8 IPRD7 to IPRD4 IPRD3 to IPRD0 IPRE15 to IPRE12 IPRE11 to IPRE8 IPRE7 to IPRE4 IPRE3 to IPRE0 IPRF15 to IPRF12 IPRF11 to IPRF8 ⎯ IPRG15 to IPRG12 ⎯ Low Rev.1.00 Sep. 18, 2008 Page 85 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Interrupt Source CMT Name CMI0 CMI1 Vector No. 144 148 152 153 156 160 to 167 168 169 170 171 172 173 174 175 176 to 179 180 181 184 188 to 196 200 212 Vector Table Starting Address H'00000240 H'00000250 H'00000260 H'00000264 H'00000270 H'00000290 to H'0000029C H'000002A0 H'000002A4 H'000002A8 H'000002AC H'000002B0 H'000002B4 H'000002B8 H'000002BC H’000002C0 to H'000002CC H'000002D0 H'000002D4 H'000002E0 H'000002F0 to H'00000310 H'00000320 H'00000330 to H'000003DC IPR IPRG7 to IPRG4 IPRG3 to IPRG0 IPRH15 to IPRH12 ⎯ IPRH11 to IPRH8 ⎯ IPRI15 to IPRI12 Default Priority High Watchdog timer ⎯ I/O (MTU) ⎯ SCI channel 2 ITI Reserved by system MTUPOE Reserved by system ERI_2 RXI_2 TXI_2 TEI_2 SCI channel 3 ERI_3 RXI_3 TXI_3 TEI_3 IPRI11 to IPRI8 ⎯ MMT Reserved by system TGIM TGIN IPRI7 to IPRI4 IPRI3 to IPRI0 A/D2 ⎯ I/O (MMT) ⎯ ADI2 Reserved by system MMTPOE Reserved by system IPRJ15 to IPRJ12 ⎯ IPRK15 to IPRK12 ⎯ Low Rev.1.00 Sep. 18, 2008 Page 86 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.6 6.6.1 Interrupt Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, according to the priority levels set in interrupt priority level setting registers A, D to K (IPRA, IPRD to IPRK). Interrupts that have lower-priority than that of the selected interrupt are ignored.* If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority order indicated in table 6.2. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the CPU’s status register (SR). If the request priority level is equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.5). 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR). 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in (5) above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepting, the IRQOUT pin holds low level. 9. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program. This jump is not a delay branch. Note: * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. Rev.1.00 Sep. 18, 2008 Page 87 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Program execution state Interrupt? Yes NMI? Yes No No Level 15 interrupt? Yes Yes I3 to I0 ≤ level 14? No Yes No Level 14 interrupt? Yes I3 to I0 ≤ level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No = low Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 = high Read exception vector table Branch to exception service routine *1 *2 Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU. is the same signal as interrupt request signal to the CPU (see figure 6.1). 1. is output when the request priority level is higher than the level in bits I3 to I0 of SR. Therefore, 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted pin holds low level. and has output an interrupt request to the CPU, the Figure 6.3 Interrupt Sequence Flowchart Rev.1.00 Sep. 18, 2008 Page 88 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always make sure that SP is a multiple of 4. Figure 6.4 Stack after Interrupt Exception Processing Rev.1.00 Sep. 18, 2008 Page 89 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) 6.7 Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an IRQ interrupt is accepted. Table 6.3 Interrupt Response Time Number of States Item Idle cycle Interrupt priority judgment and comparison with SR mask bits Wait for completion of sequence currently being executed by CPU NMI, Peripheral Module 0 or 1 2 IRQ 1 3 Remarks X (≥ 0 ) The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the saving PC and SR, and vector address fetch. Time from start of interrupt 5 + m1 + m2 + m3 exception processing until fetch of first instruction of exception service routine starts Interrupt response time Total: (7 or 8) + m1 + m2 + m3 + X Minimum: 10 Maximum: 12 + 2 (m1 + m2 + m3) + m4 Notes: * 9 + m1 + m2 + m3 + X 12 13 + 2 (m1 + m2 + m3) + m4 0.25 to 0.3 µs at 40 MHz 0.48 µs* at 40 MHz 0.48 µs at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1. m1 to m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev.1.00 Sep. 18, 2008 Page 90 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Interrupt acceptance 5 + m1 + m2 + m3 1 3 3 m1 m2 1 m3 1 Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F D E E MM E M E E F F D E F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt Is Accepted Rev.1.00 Sep. 18, 2008 Page 91 of 522 REJ09B0069-0100 Section 6 Interrupt Controller (INTC) Rev.1.00 Sep. 18, 2008 Page 92 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Section 7 Bus State Controller (BSC) The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry. 7.1 Features The BSC has the following features: • Address space is divided into four spaces (supported only by the SH7109) ⎯ A maximum linear 2-Mbyte bus width for the on-chip ROM enabled mode and a maximum 4-Mbyte bus width for the on-chip ROM disabled mode, as for the CS0 space (8 bits) ⎯ Wait states can be inserted by software for each space ⎯ Wait state insertion with the WAIT pin in external memory space access ⎯ Outputs control signals for each space according to the type of memory connected • On-chip ROM and RAM interfaces ⎯ On-chip ROM and RAM access of 32 bits in 1 state BSC1000C_000020020700 Rev.1.00 Sep. 18, 2008 Page 93 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Figure 7.1 shows the BSC block diagram. Bus interface WAIT BCR1 CS0 Area control unit BCR2 RD Memory control unit WRL BSC Legend: WCR1: Wait control register 1 BCR1: Bus control register 1 BCR2: Bus control register 2 Figure 7.1 BSC Block Diagram Rev.1.00 Sep. 18, 2008 Page 94 of 522 REJ09B0069-0100 Module bus Wait control unit WCR1 Internal bus Section 7 Bus State Controller (BSC) 7.2 Input/Output Pins Table 7.1 lists bus state controller pins of the SH7109. The SH7108 is not equipped with this type of pins. Table 7.1 Name Address bus Data bus Chip select Read Lower byte write Wait Bus request Bus request acknowledge Pin Configuration Abbr. A17 to A0 D7 to D0 CS0 RD WRL WAIT BREQ BACK I/O Output I/O Output Output Output Input Input Output Description Address output 8-bit data bus Chip select signal indicating the area being accessed Strobe signal that indicates the read cycle Strobe signal that indicates a write cycle to the lower 8 bits (D7 to D0) Wait state request signal Bus release request input Bus use enable output 7.3 Register Configuration The following registers are provided for the bus state controller. For details on addresses and states of these registers in each processing, refer to section 19, List of Registers. These registers are used to control wait states, bus width, and interfaces with memories like ROM and SRAM. All registers are 16 bits. • Bus control register 1 (BCR1) • Bus control register 2 (BCR2) • Wait control register 1 (WCR1) Rev.1.00 Sep. 18, 2008 Page 95 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.4 Address Map Figure 7.2 shows the address format used by this LSI. A31 to A24 A23, A22 A21 to A18 A17 A0 Output address: Output from the address pins CS space selection: Decoded, outputs when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS0 space when 00000000 (H'00) Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF) Figure 7.2 Address Format This chip uses 32-bit addresses: • Bits A31 to A24 are used to select the type of space and are not output externally. • Bits A23 and A22 are decoded and output as chip select signals (CS0) for the corresponding areas when bits A31 to A24 are 00000000. • A17 to A0 are output externally. A21 to A18 are not output externally. Table 7.2 shows the address map. Rev.1.00 Sep. 18, 2008 Page 96 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Table 7.2 Address Map Single Chip Mode Size Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0002 FFFF H'0003 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF H'FFFF 8000 to H'FFFF BFFF Reserved Reserved Reserved On-chip peripheral module Reserved Reserved Reserved On-chip peripheral module Reserved On-chip RAM Reserved Reserved Reserved 16 kbytes Reserved Reserved Reserved 16 kbytes 8, 16 bits Space On-chip ROM Memory On-chip ROM SH7105 256 kbytes SH7104 256 kbytes Bus Width 32 bits H'FFFF C000 to H'FFFF CFFF Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF 7FFF H'FFFF F800 to H'FFFF FFFF Reserved Reserved 8 kbytes Reserved Reserved 8 kbytes 32 bits Rev.1.00 Sep. 18, 2008 Page 97 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Size Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0002 FFFF H'0003 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF H'FFFF 8000 to H'FFFF BFFF Reserved Reserved Reserved On-chip peripheral module Reserved Reserved Reserved On-chip peripheral module Reserved On-chip RAM Reserved Reserved Reserved 16 kbytes Reserved Reserved Reserved 16 kbytes Reserved Reserved Space On-chip ROM Memory On-chip ROM SH7109 128 kbytes SH7108 128 kbytes Bus Width 32 bits 8, 16 bits H'FFFF C000 to H'FFFF CFFF Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF 7FFF H'FFFF F800 to H'FFFF FFFF Reserved Reserved Reserved Reserved 32 bits 4 kbytes 4 kbytes Rev.1.00 Sep. 18, 2008 Page 98 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Size Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0002 FFFF H'0003 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF H'FFFF 8000 to H'FFFF BFFF Reserved Reserved Reserved On-chip peripheral module Reserved Reserved Reserved On-chip peripheral module Reserved On-chip RAM Reserved Reserved Reserved 16 kbytes Reserved Reserved Reserved 16 kbytes Space On-chip ROM Memory On-chip ROM SH7107 64 kbytes SH7106 64 kbytes Bus Width 32 bits Reserved Reserved 8, 16 bits H'FFFF C000 to H'FFFF CFFF Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF 7FFF H'FFFF F800 to H'FFFF FFFF Reserved Reserved Reserved Reserved 32 bits 4 kbytes 4 kbytes Note: Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. Rev.1.00 Sep. 18, 2008 Page 99 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0002 FFFF H'0003 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF H'FFFF 8000 to H'FFFF BFFF Space On-chip ROM Memory On-chip ROM Size: SH7101 32 kbytes Reserved Bus Width 32 bits Reserved Reserved Reserved On-chip peripheral module Reserved Reserved Reserved On-chip peripheral module Reserved On-chip RAM Reserved Reserved Reserved 16 kbytes 8, 16 bits H'FFFF C000 to H'FFFF CFFF Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF 7FFF H'FFFF F800 to H'FFFF FFFF Reserved Reserved 32 bits 2 kbytes Rev.1.00 Sep. 18, 2008 Page 100 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) On-Chip ROM Enabled Mode (for SH7109 only) Size Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0002 FFFF H'0003 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF H'FFFF 8000 to H'FFFF BFFF Reserved Reserved Reserved Reserved Reserved CS0 space External space 256 kbytes 256 kbytes 256 kbytes 8 bits Reserved Space* On-chip ROM Memory On-chip ROM SH7105 256 kbytes SH7109 128 kbytes SH7107 Bus Width 64 kbytes 32 bits Reserved Reserved Reserved Reserved Reserved Reserved On-chip On-chip 16 kbytes 16 kbytes 16 kbytes 8, 16 bits peripheral peripheral module module H'FFFF C000 to H'FFFF CFFF Reserved Reserved Reserved Reserved Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF 7FFF H'FFFF F800 to H'FFFF FFFF On-chip RAM Reserved Reserved Reserved 32 bits 8 kbytes 4 kbytes 4 kbytes Rev.1.00 Sep. 18, 2008 Page 101 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) On-Chip ROM Disabled Mode (for SH7109 only) Size Address H'0000 0000 to H'0000 7FFF H'0000 8000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0002 FFFF H'0003 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF H'FFFF 8000 to H'FFFF BFFF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved On-chip On-chip 16 kbytes 16 kbytes 16 kbytes 8, 16 bits peripheral peripheral module module Space* CS0 space Memory External space SH7105 256 kbytes SH7109 256 kbytes SH7107 256 kbytes Bus Width 8 bits H'FFFF C000 to H'FFFF CFFF Reserved Reserved Reserved Reserved Reserved H'FFFF D000 to H'FFFF DFFF On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF 7FFF H'FFFF F800 to H'FFFF FFFF Note: * Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. When in single chip mode, spaces other than those for on-chip ROM, on-chip RAM, and internal peripheral module are not available. On-chip RAM Reserved Reserved Reserved 32 bits 8 kbytes 4 kbytes 4 kbytes 7.5 7.5.1 Register Descriptions Bus Control Register 1 (BCR1) BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control registers and specifies the bus size of the CS0 space. The AOSZ bit of BCR1 is written to during the initialization stage after a power-on reset. Do not change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS0 space until completion of register initialization. Rev.1.00 Sep. 18, 2008 Page 102 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Bit 15 Bit Name ⎯ Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 MMTRWE 1 R/W MMT Read/Write Enable This bit enables MMT control register access. For details, refer to section 13, Motor Management Timer (MMT). 0: MMT control register access is disabled 1: MMT control register access is enabled 13 MTURWE 1 R/W MTU Read/Write Enable This bit enables MTU control register access. For details, refer to section 8, Multifunction Timer Pulse Unit (MTU). 0: MTU control register access is disabled 1: MTU control register access is enabled 12 to 4 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 1 ⎯ All 1 R Reserved These bits are always read as 1. The write value should always be 1. 0 A0SZ 1 R/W CS0 Space Size Specification Specifies the CS0 space bus size when A0LG is 0. In on-chip ROM enabled mode, 0 should be written to this bit to specify a bus size of 8 bits before the CS0 space is accessed. Note: In on-chip ROM disabled mode, the CS0 space bus size is specified by the mode pin. Rev.1.00 Sep. 18, 2008 Page 103 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.5.2 Bus Control Register 2 (BCR2) BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS0 signal assert extension of each CS0 space. Bit Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. CS0 Space Idle Specification between Cycles These bits insert idle cycles when a read access is followed immediately by a write access. 00: No CS0 space idle cycle 01: One CS0 space idle cycle 10: Two CS0 space idle cycles 11: Three CS0 space idle cycles Reserved These bits are always read as 1. The write value should always be 1. CS0 Space Idle Specification for Continuous Access The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CS0 signal when performing consecutive accesses to the same CS space. 0: No CS0 space continuous access idle cycle 1: One CS0 space continuous access idle cycle When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IWO1 and IWO0. Reserved These bits are always read as 1. The write value should always be 1. CS0 Space CS Assert Extension Specification The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal or WRL signal assert period beyond the length of the CS0 signal assert period. 0: No CS0 space CS assert extension inserted 1: CS0 space CS assert extension inserted (one cycle is inserted before and after each bus cycle) 15 to 10 ⎯ 9 8 IW01 IW00 1 1 R/W R/W 7 to 5 ⎯ All 1 R 4 CW0 1 R/W 3 to 1 ⎯ All 1 R 0 SW0 1 R/W Rev.1.00 Sep. 18, 2008 Page 104 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.5.3 Wait Control Register 1 (WCR1) WCR1 is a 16-bit readable/writable register that specifies the number of wait cycles for CS0 space. Bit Bit Name Initial Value All 1 R/W R/W Description Reserved These bits are always read as 1. The write value should always be 1. 3 2 1 0 W03 W02 W01 W00 1 1 1 1 R/W R/W R/W R/W CS0 Space Wait Specification These bits specify the number of waits for CS0 space access. 0000: No wait (external wait input disabled) 0001: One wait (external wait input enabled) . . . 1111: 15 waits (external wait input enabled) 15 to 4 ⎯ Rev.1.00 Sep. 18, 2008 Page 105 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.6 Accessing External Space A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct connections. 7.6.1 Basic Timing External access bus cycles are performed in 2 states. Figure 7.3 shows the basic timing of external space access. T1 CK Address T2 Read Data Write Data Figure 7.3 Basic Timing of External Space Access During a read, irrespective of operand size, all bits (8 bits in this LSI) in the data bus width for the access space (address) accessed by RD signal are fetched by the LSI. During a write, the WRL (bits 7 to 0) signal indicates the byte location to be written. Rev.1.00 Sep. 18, 2008 Page 106 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.6.2 Wait State Control The number of wait states inserted into external space access states can be controlled using the WCR1 settings. The specified number of TW cycles are inserted as software cycles at the timing shown in figure 7.4. T1 CK Address TW T2 Read Data Write Data Figure 7.4 Wait State Timing of External Space Access (Software Wait Only) Rev.1.00 Sep. 18, 2008 Page 107 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) When the wait is specified by software using WCR1, the wait input WAIT signal from outside is sampled. Figure 7.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when the TW state shifts to the T2 state. When using external waits, use a WCR1 setting of 1 state or more in case of extending CS assertion, and 2 states or more otherwise. T1 CK Address TW TW TWo T2 Read Data Write Data Figure 7.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State) Rev.1.00 Sep. 18, 2008 Page 108 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.6.3 CS Assert Period Extension Idle cycles can be inserted to prevent extension of the RD or WRL signal assert period beyond the length of the CS0 signal assert period by setting the SW0 bit of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 7.6. Th and Tf cycles are added respectively before and after the normal cycle. Only CS0 is asserted in these cycles; RD and WRL signals are not. Further, data is extended up to the TF cycle, which is effective for gate arrays and the like, which have slower write operations. Th CK Address T1 T2 Tf Read Data Write Data Figure 7.6 CS Assert Period Extension Function Rev.1.00 Sep. 18, 2008 Page 109 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.7 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time, causing conflict with the next access data. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of the bus cycle start, a wait can be inserted between access cycles during continuous accesses of the same CS0 space by negating the CS0 signal once. 7.7.1 Prevention of Data Bus Conflicts Waits are inserted so that the number of write cycles after read cycle and the number of cycles specified by IW01 and IW00 bits of BCR2 can be inserted. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. 7.7.2 Simplification of Bus Cycle Start Detection For consecutive accesses to the same CS0 space, waits are inserted to provide the number of idle cycles designated by bit CW0 in BCR2. However, in the case of a write cycle after a read, the number of idle cycles inserted will be the larger of the two values designated by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 7.7 shows an example. A continuous access idle is specified for CS0 space, and CS0 space is consecutively write-accessed. T1 CK Address T2 Tidle T1 T2 Data CS0 space access Idle cycle CS0 space access Figure 7.7 Example of Idle Cycle Insertion at Same Space Consecutive Access Rev.1.00 Sep. 18, 2008 Page 110 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.8 Bus Arbitration This LSI has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device. It also has an internal bus master, the CPU. The priority for arbitrate the bus mastership between these bus masters is: Bus request from external device > CPU A bus request by an external device should be input to the BREQ pin. When the BREQ pin is asserted, this LSI releases the bus immediately after the bus cycle being executed is completed. The signal indicating that the bus has been released is output from the BACK pin. However, the bus is not released between the read and write cycles during TAS instruction execution. Bus arbitration is not executed between multiple bus cycles that occur due to the data bus width smaller than access size, for instance, bus cycles in which 8-bit memory is accessed by a longword. The bus may be returned when this LSI is releasing the bus. That is, when interrupt request occurs to be processed. This LSI incorporates the IRQOUT pin for the bus request signal. When the bus must be returned to this LSI, the IRQOUT signal can be asserted. The device that is asserting an external bus-release request negates the BREQ signal to release the bus when the IRQOUT signal is asserted. As a result, the bus is returned to and processed by this LSI. The asserting condition of the IRQOUT pin is that an interrupt source occurs and the interrupt request level is higher than that of interrupt mask bits I3 to I0 in the status register (SR). Figure 7.8 shows the bus mastership release procedure. Rev.1.00 Sep. 18, 2008 Page 111 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) This LSI External device accepted = Low Bus request Strobe pin: high-level output Address, data, strobe pin: high impedance = Low Bus release response confirmation Bus mastership release status Bus mastership acquisition Figure 7.8 Bus Mastership Release Procedure 7.9 Memory Connection Example This LSI 32 k × 8-bit ROM A0 to A14 D0 to D7 A0 to A14 I/O0 to I/O7 Figure 7.9 Example of 8-Bit Data Bus Width ROM Connection Rev.1.00 Sep. 18, 2008 Page 112 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) 7.10 On-chip Peripheral I/O Register Access Internal I/O registers are accessed from the bus state controller, as shown in table 7.3. Table 7.3 Access to Internal I/O Registers MTU, POE 16 bits 1 Internal Module SCI Connected bus width Access cycles 8 bits 2 cyc* INTC 16 bits 2 cyc* 2 PFC, PORT 16 bits 2 cyc* 1 CMT 16 bits 2 cyc* 1 A/D 8 bits 3 cyc* 1 WDT 16 bits 3 cyc* 2 MMT 16 bits 2 cyc* 1 2 cyc* 1 Notes: 1. Converted to the peripheral clock. 2. Converted to the system clock. 7.11 Cycles in which Bus Is not Released One Bus Cycle: The bus is never released during a single bus cycle. For example, in the case of a longword read (or write) in 8-bit normal space, four memory accesses to the 8-bit normal space constitute a single bus cycle, and the bus is never released during this period. Assuming that one memory access requires two states, the bus is not released during an 8-state period. 8 bits 8 bits 8 bits 8 bits Cycles in which bus is not released Figure 7.10 One Bus Cycle 7.12 CPU Operation when Program Is in External Memory In this LSI, two words (equivalent to two instructions) are normally fetched in a single instruction fetch. This is also true when the program is located in external memory, irrespective of whether the external memory bus width is 8 or 16 bits. If the program counter value immediately after the program branched is an odd-word (2n+1) address, or if the program counter value immediately before the program branches is an even-word (2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the respective word instruction. Rev.1.00 Sep. 18, 2008 Page 113 of 522 REJ09B0069-0100 Section 7 Bus State Controller (BSC) Rev.1.00 Sep. 18, 2008 Page 114 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Section 8 Multifunction Timer Pulse Unit (MTU) This LSI has an on-chip multifunction timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 8.1. 8.1 Features • Maximum 16-pulse input/output • Selection of 8 counter input clocks for each channel • The following operations can be set for each channel: ⎯ Waveform output at compare match ⎯ Input capture function ⎯ Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation ⎯ A maximum 12-phase PWM output is possible in combination with synchronous operation • Buffer operation settable for channels 0, 3, and 4 • Phase counting mode settable independently for each of channels 1 and 2 • Cascade connection operation • Fast access via internal 16-bit bus • 23 interrupt sources • Automatic transfer of register data • A/D converter conversion start trigger can be generated • Module standby mode can be set • Positive and negative 3-phase waveforms (6-phase waveforms in total) can be output in complementary or reset synchronous PWM mode by combining channels 3 and 4. • AC synchronous motor (brushless DC motor) can be driven in complementary or reset synchronous PWM mode by combining channels 0, 3, and 4. Chopping or level output can be selected as drive waveform output. TIMMTU0A_010020030200 Rev.1.00 Sep. 18, 2008 Page 115 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.1 Item Count clock MTU Functions Channel 0 Pφ/1 Pφ/4 Pφ/16 Pφ/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture Channel 1 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 TCLKA TCLKB TGRA_1 TGRB_1 — TIOC1A TIOC1B Channel 2 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 — TIOC2A TIOC2B Channel 3 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOC3A TIOC3B TIOC3C TIOC3D TGR compare match or input capture Channel 4 Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D TGR compare match or input capture General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset synchronous PWM mode AC synchronous motor drive mode Phase counting mode — — — — — — — — — — — — — Rev.1.00 Sep. 18, 2008 Page 116 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Item Buffer operation A/D converter start trigger Channel 0 Channel 1 — Channel 2 — TGRA_2 compare match or input capture 4 sources Channel 3 Channel 4 TGRA_0 compare match or input capture 5 sources • Compare match or input capture 0A • Compare match or input capture 0B • Compare match or input capture 0C • Compare match or input capture 0D • Overflow TGRA_1 compare match or input capture 4 sources • Compare match or input capture 1A • Compare match or input capture 1B • Overflow • Underflow TGRA_3 compare match or input capture 5 sources TGRA_4 compare match or input capture 5 sources Interrupt sources • Compare • Compare • Compare match or match or match or input input input capture 2A capture 3A capture 4A • Compare • Compare • Compare match or match or match or input input input capture 3B capture 2B capture 4B • Compare • Overflow • Compare match or match or • Underflow input input capture 3C capture 4C • Compare • Compare match or match or input input capture 3D capture 4D • Overflow • Overflow • Underflow Legend: : Possible — : Not possible Rev.1.00 Sep. 18, 2008 Page 117 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Control logic for channels 3 and 4 Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4C TCI4D TGI4V TIORH TIORL TMDR Channel 4 TSR TIER TCR TGRC TDDR TIORH TOCR TGCR TIER TCR TCNTS TCDR TMDR Channel 2 TSR Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 External clock: TCLKA TCLKB TCLKC TCLKD TOER TCBR TGRD TGRA TGRB TCNT TSYR Module data bus Internal data bus BUS I/F Control logic Common TSTR A/D converter conversion start signal TGRA TIOR Control logic for channel 0 to 2 TIER TCR TGRB TCNT TIORL TMDR Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B Channel 0 TGRC TIORH Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): Timer start register Timer synchro register Timer control register Timer mode register Timer I/O control registers (H, L) TIER TCR TIER: Timer interrupt enable register TSR: Timer status register TCNT: Timer counter TGR (A, B, C, D): Timer general registers (A, B, C, D) Figure 8.1 Block Diagram of TPU Rev.1.00 Sep. 18, 2008 Page 118 of 522 REJ09B0069-0100 TGRD TGRA TGRB TCNT Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR TSR TIER TCR TGRB TCNT Section 8 Multifunction Timer Pulse Unit (MTU) 8.2 Table 8.2 Channel Input/Output Pins Pin Configuration Symbol I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin Common TCLKA TCLKB TCLKC TCLKD 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 TIOC1A TIOC1B 2 TIOC2A TIOC2B 3 TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D Rev.1.00 Sep. 18, 2008 Page 119 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3 Register Descriptions The MTU has the following registers. For details on register addresses and register states during each process, refer to section 19, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Channel 0 • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) • Timer interrupt enable register_0 (TIER_0) • Timer status register_0 (TSR_0) • Timer counter_0 (TCNT_0) • Timer general register A_0 (TGRA_0) • Timer general register B_0 (TGRB_0) • Timer general register C_0 (TGRC_0) • Timer general register D_0 (TGRD_0) Channel 1 • Timer control register_1 (TCR_1) • Timer mode register_1 (TMDR_1) • Timer I/O control register _1 (TIOR_1) • Timer interrupt enable register_1 (TIER_1) • Timer status register_1 (TSR_1) • Timer counter_1 (TCNT_1) • Timer general register A_1 (TGRA_1) • Timer general register B_1 (TGRB_1) Channel 2 • Timer control register_2 (TCR_2) • Timer mode register_2 (TMDR_2) • Timer I/O control register_2 (TIOR_2) • Timer interrupt enable register_2 (TIER_2) • Timer status register_2 (TSR_2) • Timer counter_2 (TCNT_2) Rev.1.00 Sep. 18, 2008 Page 120 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) • Timer general register A_2 (TGRA_2) • Timer general register B_2 (TGRB_2) Channel 3 • Timer control register_3 (TCR_3) • Timer mode register_3 (TMDR_3) • Timer I/O control register H_3 (TIORH_3) • Timer I/O control register L_3 (TIORL_3) • Timer interrupt enable register_3 (TIER_3) • Timer status register_3 (TSR_3) • Timer counter_3 (TCNT_3) • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) Channel 4 • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) • Timer I/O control register H_4 (TIORH_4) • Timer I/O control register L_4 (TIORL_4) • Timer interrupt enable register_4 (TIER_4) • Timer status register_4 (TSR_4) • Timer counter_4 (TCNT_4) • Timer general register A_4 (TGRA_4) • Timer general register B_4 (TGRB_4) • Timer general register C_4 (TGRC_4) • Timer general register D_4 (TGRD_4) Common registers • Timer start register (TSTR) • Timer synchro register (TSYR) Common registers for timers 3 and 4 • Timer output master enable register (TOER) • Timer output control enable register (TOCR) Rev.1.00 Sep. 18, 2008 Page 121 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) • Timer gate control register (TGCR) • Timer cycle data register (TCDR) • Timer dead time data register (TDDR) • Timer subcounter (TCNTS) • Timer cycle buffer register (TCBR) 8.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings should be conducted only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. See tables 8.3 and 8.4 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. Pφ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is Pφ/4 or slower. When Pφ/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges Legend: x: Don’t care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 8.5 to 8.8 for details. Rev.1.00 Sep. 18, 2008 Page 122 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.3 Channel 0, 3, 4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 0 0 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 8.4 Channel 1, 2 CCLR0 to CCLR2 (Channels 1 and 2) Bit 7 Bit 6 2 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0. Writing is ignored. Rev.1.00 Sep. 18, 2008 Page 123 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.5 Channel 0 TPSC0 to TPSC2 (Channel 0) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 8.6 Channel 1 TPSC0 to TPSC2 (Channel 1) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on Pφ/256 Counts on TCNT_2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev.1.00 Sep. 18, 2008 Page 124 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.7 Channel 2 TPSC0 to TPSC2 (Channel 2) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on Pφ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 8.8 Channel 3, 4 TPSC0 to TPSC2 (Channels 3 and 4) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 Internal clock: counts on Pφ/256 Internal clock: counts on Pφ/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Rev.1.00 Sep. 18, 2008 Page 125 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit 7, 6 Bit Name — Initial value All 1 R/W — Description Reserved These bits are always read as 1. The write value should always be 1. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0, and the write value should always be 0. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0, and the write value should always be 0. 0: TGRA and TGRD operate normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 3 to 0 These bits are used to set the timer operating mode. See table 8.9 for details. Rev.1.00 Sep. 18, 2008 Page 126 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.9 Bit 3 MD3 0 MD0 to MD3 Bit 2 MD2 0 Bit 1 MD1 0 1 1 0 1 Bit 0 MD0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 x 0 1 0 1 Description Normal operation Reserved (setting prohibited) PWM mode 1 PWM mode 2* 1 2 2 2 2 3 Phase counting mode 1* Phase counting mode 2* Phase counting mode 3* Phase counting mode 4* 1 0 0 Reset synchronous PWM mode* Reserved (setting prohibited) Reserved (setting prohibited) Reserved (setting prohibited) Complementary PWM mode 1 (transmit at peak)* 3 3 Complementary PWM mode 2 (transmit at trough)* Complementary PWM mode 2 (transmit at peak and 3 trough)* Legend: x: Don’t care Notes: 1. PWM mode 2 can not be set for channels 3 and 4. 2. Phase counting mode can not be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode can not be set for channels 0, 1, and 2. 8.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev.1.00 Sep. 18, 2008 Page 127 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit 7 6 5 4 Bit Name IOB3 IOB2 IOB1 IOB0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control B3 to B0 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 8.10 Table 8.14 Table 8.16 Table 8.18 Table 8.22 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 8.11 Table 8.15 Table 8.17 Table 8.19 Table 8.23 TIORL_0, TIORL_3, TIORL_4 Bit 7 6 5 4 Bit Name IOD3 IOD2 IOD1 IOD0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control D3 to D0 Specify the function of TGRD. When the TGRD is used as a buffer register of the TGRB, this setting is invalid and input capture/output compare is not generated. See the following tables. TIORL_0: Table 8.12 TIORL_3: Table 8.20 TIORL_4: Table 8.24 3 2 1 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 R/W R/W R/W R/W I/O Control C3 to C0 Specify the function of TGRC. When the TGRC is used as a buffer register of the TGRA, this setting is invalid and input capture/output compare is not generated. See the following tables. TIORL_0: Table 8.13 TIORL_3: Table 8.21 TIORL_4: Table 8.25 Rev.1.00 Sep. 18, 2008 Page 128 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.10 TIORH_0 (Channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_0 Function Output compare register TIOC0B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down Legend: x: Don’t care Rev.1.00 Sep. 18, 2008 Page 129 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.11 TIORH_0 (Channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_0 Function Output compare register TIOC0A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: x: Don’t care Rev.1.00 Sep. 18, 2008 Page 130 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.12 TIORL_0 (Channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRD_0 Function Output compare register* TIOC0D Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: x: Don’t care Note: * When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Sep. 18, 2008 Page 131 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.13 TIORL_0 (Channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register* TGRC_0 Function Output compare register* TIOC0C Pin Function Output hold* 1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: x: Don’t care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Sep. 18, 2008 Page 132 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.14 TIOR_1 (Channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRB_1 Function Output compare register TIOC1B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture Legend: x: Don’t care Rev.1.00 Sep. 18, 2008 Page 133 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.15 TIOR_1 (Channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x Input capture register TGRA_1 Function Output compare register TIOC1A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture Legend: x: Don’t care Rev.1.00 Sep. 18, 2008 Page 134 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.16 TIOR_2 (Channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don’t care X Input capture register TGRB_2 Function Output compare register TIOC2B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.1.00 Sep. 18, 2008 Page 135 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.17 TIOR_2 (channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don’t care x Input capture register TGRA_2 Function Output compare register TIOC2A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.1.00 Sep. 18, 2008 Page 136 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.18 TIORH_3 (Channel 3) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don’t care x Input capture register TGRB_3 Function Output compare register TIOC3B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.1.00 Sep. 18, 2008 Page 137 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.19 TIORH_3 (Channel 3) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don’t care x Input capture register TGRA_3 Function Output compare register TIOC3A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.1.00 Sep. 18, 2008 Page 138 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.20 TIORL_3 (Channel 3) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x Input capture 2 register* TGRD_3 Function Output compare register* TIOC3D Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: x: Don’t care Note: * When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Sep. 18, 2008 Page 139 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.21 TIORL_3 (Channel 3) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x Input capture register* TGRC_3 Function Output compare register* TIOC3C Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: x: Don’t care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Sep. 18, 2008 Page 140 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.22 TIORH_4 (Channel 4) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don’t care x Input capture register TGRB_4 Function Output compare register TIOC4B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.1.00 Sep. 18, 2008 Page 141 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.23 TIORH_4 (Channel 4) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 Legend: x: Don’t care x Input capture register TGRA_4 Function Output compare register TIOC4A Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Rev.1.00 Sep. 18, 2008 Page 142 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.24 TIORL_4 (Channel 4) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x Input capture register TGRD_4 Function Output compare register* TIOC4B Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: x: Don’t care Note: * When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Sep. 18, 2008 Page 143 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.25 TIORL_4 (Channel 4) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x Input capture register TGRC_4 Function Output compare register* TIOC4C Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output value retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: x: Don’t care Note: * When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev.1.00 Sep. 18, 2008 Page 144 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU has five TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev.1.00 Sep. 18, 2008 Page 145 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 2 Bit Name TGIEC Initial value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev.1.00 Sep. 18, 2008 Page 146 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU has five TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 3, and 4. In channel 0, bit 7 is reserved. It is always read as 1, and should only be written with 1. 0: TCNT counts down 1: TCNT counts up 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 R/(W) Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and the write value should always be 0. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] • 4 TCFV 0 R/(W) When 0 is written to TCFU after reading TCFU = 1 Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when TCNT-4 is underflowed (H'0001 → H'0000) in complementary PWM mode. [Clearing condition] • When 0 is written to TCFV after reading TCFV = 1 • • Rev.1.00 Sep. 18, 2008 Page 147 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 3 Bit Name TGFD Initial value 0 R/W R/(W) Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and the write value should always be 0. [Setting conditions] • • When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing condition] • 2 TGFC 0 R/(W) When 0 is written to TGFD after reading TGFD = 1 Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and the write value should always be 0. [Setting conditions] • • When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing condition] • When 0 is written to TGFC after reading TGFC = 1 Rev.1.00 Sep. 18, 2008 Page 148 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 1 Bit Name TGFB Initial value 0 R/W R/(W) Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] • • When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing condition] • 0 TGFA 0 R/(W) When 0 is written to TGFB after reading TGFB = 1 Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] • • When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing condition] • When 0 is written to TGFA after reading TGFA = 1 8.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one for each channel. The initial value is H'0000. Access to TCNT in 8-bit units is not allowed. Applications must always access TCNT in 16-bit units. Note that TCNT is initialized to H'0000 by a reset. Rev.1.00 Sep. 18, 2008 Page 149 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.7 Timer General Register (TGR) The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3, and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA— TGRC and TGRB—TGRD. The initial value is H'FFFF. 8.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 6 Bit Name CST4 CST3 Initial value 0 0 R/W R/W R/W Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 CST2 CST1 CST0 0 0 0 R/W R/W R/W Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 and TCNT_0 count operation is stopped 1: TCNT_2 and TCNT_0 performs count operation Rev.1.00 Sep. 18, 2008 Page 150 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.9 Timer Synchro Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7 6 Bit Name SYNC4 SYNC3 Initial value 0 0 R/W R/W R/W Description Timer Synchro 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 151 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 2 1 0 Bit Name SYNC2 SYNC1 SYNC0 Initial value 0 0 0 R/W R/W R/W R/W Description Timer Synchro 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently. TCNT presetting /clearing is unrelated to other channels. 1: TCNT_2 to TCNT_0 performs synchronous operation. TCNT synchronous presetting/synchronous clearing is possible. Rev.1.00 Sep. 18, 2008 Page 152 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.10 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit 7, 6 Bit Name — Initial value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 5 OE4D 0 R/W 4 OE4C 0 R/W 3 OE3D 0 R/W 2 OE4B 0 R/W 1 OE4A 0 R/W 0 OE3B 0 R/W Rev.1.00 Sep. 18, 2008 Page 153 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.11 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit 7 Bit Name — Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 OLSN 0 R/W Output Level Select N This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 8.26 0 OLSP 0 R/W Output Level Select P This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 8.27 Table 8.26 Output Level Select Function Bit 1 Function Compare Match Output OLSN 0 1 Initial Output High level Low level Active Level Low level High level Increment Count High level Low level Decrement Count Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Rev.1.00 Sep. 18, 2008 Page 154 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.27 Output Level Select Function Bit 1 Function Compare Match Output OLSP 0 1 Initial Output High level Low level Active Level Low level High level Increment Count Low level High level Decrement Count High level Low level Figure 8.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3, and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Time Positive phase output Reverse phase output Figure 8.2 Complementary PWM Mode Output Level Example 8.3.12 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Rev.1.00 Sep. 18, 2008 Page 155 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 7 Bit Name — Initial value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are on-output. 0: Level output 1: Reset synchronized PWM/complementary PWM output Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are onoutput. 0: Level output 1: Reset synchronized PWM/complementary PWM output External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is carried out by external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings). Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 8.28. 6 BDC 0 R/W 5 N 0 R/W 4 P 0 R/W 3 FB 0 R/W 2 1 0 WF VF UF 0 0 0 R/W R/W R/W Rev.1.00 Sep. 18, 2008 Page 156 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.28 Output Level Select Function Function Bit 2 WF 0 Bit 1 VF 0 Bit 0 UF 0 1 1 0 1 1 0 0 1 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B TIOC3D TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF W Phase U Phase OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF 8.3.13 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value is H'0000. Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. 8.3.14 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value is H'FFFF. Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 8.3.15 Timer Period Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value is H'FFFF. Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. Rev.1.00 Sep. 18, 2008 Page 157 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.3.16 Timer Period Buffer Register (TCBR) The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value is H'FFFF. Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 8.3.17 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register (TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. 8.4 8.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always set the MTU external pins function using the pin function controller (PFC). Counter Operation When one of bits CST0 to CST4 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Example of Count Operation Setting Procedure: Figure 8.3 shows an example of the count operation setting procedure. Rev.1.00 Sep. 18, 2008 Page 158 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Operation selection Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Periodic counter Select counter clearing source Select output compare register Set period [2] [3] [4] [5] Start count operation Figure 8.3 Example of Counter Operation Setting Procedure Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 8.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 8.4 Free-Running Counter Operation Rev.1.00 Sep. 18, 2008 Page 159 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 8.5 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software TGF Figure 8.5 Periodic Counter Operation Waveform Output by Compare Match The MTU can perform 0, 1, or toggle output from the corresponding output pin using compare match. Example of Setting Procedure for Waveform Output by Compare Match: Figure 8.6 shows an example of the setting procedure for waveform output by compare match Rev.1.00 Sep. 18, 2008 Page 160 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 8.6 Example of Setting Procedure for Waveform Output by Compare Match Examples of Waveform Output Operation: Figure 8.7 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB No change No change Time No change No change 1 output 0 output Figure 8.7 Example of 0 Output/1 Output Operation Figure 8.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. Rev.1.00 Sep. 18, 2008 Page 161 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle output Toggle output Figure 8.8 Example of Toggle Output Operation Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, φ/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if φ/1 is selected. Example of Input Capture Operation Setting Procedure: Figure 8.9 shows an example of the input capture operation setting procedure. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Select input capture input [1] Start count [2] Figure 8.9 Example of Input Capture Operation Setting Procedure Rev.1.00 Sep. 18, 2008 Page 162 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Example of Input Capture Operation: Figure 8.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 8.10 Example of Input Capture Operation 8.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Rev.1.00 Sep. 18, 2008 Page 163 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Example of Synchronous Operation Setting Procedure: Figure 8.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 8.11 Example of Synchronous Operation Setting Procedure Example of Synchronous Operation: Figure 8.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. Rev.1.00 Sep. 18, 2008 Page 164 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) For details of PWM modes, see section 8.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Time Figure 8.12 Example of Synchronous Operation 8.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 8.29 shows the register combinations used in buffer operation. Table 8.29 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 4 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 Rev.1.00 Sep. 18, 2008 Page 165 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 8.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 8.13 Compare Match Buffer Operation • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 8.14. Input capture signal Buffer register Timer general register TCNT Figure 8.14 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 8.15 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Select TGR function [1] Start count [3] Figure 8.15 Example of Buffer Operation Setting Procedure Rev.1.00 Sep. 18, 2008 Page 166 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Examples of Buffer Operation: • When TGR is an output compare register Figure 8.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 8.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 8.16 Example of Buffer Operation (1) • When TGR is an input capture register Figure 8.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev.1.00 Sep. 18, 2008 Page 167 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'0532 H'09FB H'0F07 TGRC Figure 8.17 Example of Buffer Operation (2) 8.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 8.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 8.30 Cascaded Combinations Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2 Rev.1.00 Sep. 18, 2008 Page 168 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Example of Cascaded Operation Setting Procedure: Figure 8.18 shows an example of the setting procedure for cascaded operation. Cascaded operation [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Set cascading Start count [2] Figure 8.18 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 8.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 8.19 Example of Cascaded Operation (2) 8.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. Rev.1.00 Sep. 18, 2008 Page 169 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) There are two PWM modes, as described below. • PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. • PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 8.31. Rev.1.00 Sep. 18, 2008 Page 170 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.31 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A TIOC1A TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev.1.00 Sep. 18, 2008 Page 171 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Example of PWM Mode Setting Procedure: Figure 8.20 shows an example of the PWM mode setting procedure. PWM mode [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [3] [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] Select counter clock [1] Select counter clearing source [2] Select waveform output level Set TGR [4] Start count [6] Figure 8.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 8.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty cycle. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 8.21 Example of PWM Mode Operation (1) Rev.1.00 Sep. 18, 2008 Page 172 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Figure 8.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty cycle levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 8.22 Example of PWM Mode Operation (2) Rev.1.00 Sep. 18, 2008 Page 173 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Figure 8.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty cycle Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle 0% duty cycle TGRB rewritten Time TIOCA Figure 8.23 Example of PWM Mode Operation (3) Rev.1.00 Sep. 18, 2008 Page 174 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 8.32 shows the correspondence between external clock pins and channels. Table 8.32 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 8.24 shows an example of the phase counting mode setting procedure. Phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Select phase counting mode [1] Start count [2] Figure 8.24 Example of Phase Counting Mode Setting Procedure Rev.1.00 Sep. 18, 2008 Page 175 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 8.25 shows an example of phase counting mode 1 operation, and table 8.33 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.25 Example of Phase Counting Mode 1 Operation Table 8.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev.1.00 Sep. 18, 2008 Page 176 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) • Phase counting mode 2 Figure 8.26 shows an example of phase counting mode 2 operation, and table 8.34 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.26 Example of Phase Counting Mode 2 Operation Table 8.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don’t care Don’t care Don’t care Up-count Don’t care Don’t care Don’t care Down-count Rev.1.00 Sep. 18, 2008 Page 177 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) • Phase counting mode 3 Figure 8.27 shows an example of phase counting mode 3 operation, and table 8.35 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.27 Example of Phase Counting Mode 3 Operation Table 8.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don’t care Don’t care Don’t care Up-count Down-count Don’t care Don’t care Don’t care Rev.1.00 Sep. 18, 2008 Page 178 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) • Phase counting mode 4 Figure 8.28 shows an example of phase counting mode 4 operation, and table 8.36 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 8.28 Example of Phase Counting Mode 4 Operation Table 8.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don’t care Down-count Don’t care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev.1.00 Sep. 18, 2008 Page 179 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Phase Counting Mode Application Example: Figure 8.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 + + - TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 8.29 Phase Counting Mode Application Example Rev.1.00 Sep. 18, 2008 Page 180 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 8.37 shows the PWM output pins used. Table 8.38 shows the settings of the registers. Table 8.37 Output Pins for Reset-Synchronized PWM Mode Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3) Table 8.38 Register Settings for Reset-Synchronized PWM Mode Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Rev.1.00 Sep. 18, 2008 Page 181 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 8.30 shows an example of procedure for selecting the reset-synchronized PWM mode. 1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The resetsynchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. 2. Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. 3. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4. Reset TCNT_3 and TCNT_4 to H'0000. 5. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. x ≤ TGRA_3 (x: set value). 6. Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 7. Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM output pins*. Do not set to TMDR_4. 8. Set the enabling/disabling of the PWM waveform output pin in TOER. 9. Set the CST3 bit in the TSTR to 1 to start the count operation. Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = x by setting x = TGRA, i.e., cycle = duty cycle. * PFC registers should be specified before this procedure. Rev.1.00 Sep. 18, 2008 Page 182 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Reset-synchronized PWM mode Stop counting 1 Select counter clock and counter clear source 2 Brushless DC motor control setting 3 Set TCNT 4 Set TGR 5 PWM cycle output enabling, PWM output level setting 6 Set reset-synchronized PWM mode 7 Enable waveform output 8 Start count operation Reset-synchronized PWM mode 9 Figure 8.30 Procedure for Selecting the Reset-Synchronized PWM Mode Rev.1.00 Sep. 18, 2008 Page 183 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Reset-Synchronized PWM Mode Operation: Figure 8.31 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT3 and TCNT4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 8.31 Reset-Synchronized PWM Mode Operation Example (When the TOCR’s OLSN = 1 and OLSP = 1) 8.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as increment/decrement counters. Table 8.39 shows the PWM output pins used. Table 8.40 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Rev.1.00 Sep. 18, 2008 Page 184 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.39 Output Pins for Complementary PWM Mode Channel 3 Output Pin TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D Note: * Description Toggle output synchronized with PWM period (or I/O port) PWM output pin 1 I/O port* PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 3 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2) PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3) Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. Rev.1.00 Sep. 18, 2008 Page 185 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.40 Register Settings for Complementary PWM Mode Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Always readable/writable Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Always readable/writable Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable Access can be enabled or disabled according to the setting of bit 13 (MTURWE) in BSC/BCR1 (bus controller/bus control register 1). Rev.1.00 Sep. 18, 2008 Page 186 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TGRD_3 Figure 8.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode ;; @@ ;;; @@ @ ;; @@ ;;; @@ @@@@ ;;;; @@@@ ;;;; ;; @ ; TGRC_3 TCBR TDDR TGRA_3 TCDR Comparator Match signal TCNT_3 TCNTS TCNT_4 Comparator Match signal TGRA_3 comparematch interrupt TCNT_4 underflow interrupt PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input Output controller TGRB_3 TGRA_4 TGRC_4 TGRD_4 TGRB_4 Temp 1 Temp 2 Temp 3 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by the bus controller) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Rev.1.00 Sep. 18, 2008 Page 187 of 522 REJ09B0069-0100 Output protection circuit Section 8 Multifunction Timer Pulse Unit (MTU) Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 8.33. 1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. 2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. 3. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4. Set the dead time in TCNT_3. Set TCNT_4 to H'0000. 5. Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). 6. Set the output PWM duty cycle in the duty cycle registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. 7. Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. 8. Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 9. Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins*. Do not set in TMDR_4. 10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). 11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Note: * PFC registers should be specified before this procedure. Rev.1.00 Sep. 18, 2008 Page 188 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Complementary PWM mode Stop count operation 1 Counter clock, counter clear source selection 2 Brushless DC motor control setting 3 TCNT setting 4 Inter-channel synchronization setting 5 TGR setting 6 Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting 7 8 9 Enable waveform output 10 Start count operation 11 Figure 8.33 Example of Complementary PWM Mode Setting Procedure Rev.1.00 Sep. 18, 2008 Page 189 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 8.34 illustrates counter operation in complementary PWM mode, and figure 8.35 shows an example of complementary PWM mode operation. Counter Operation: In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT_3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT_4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty cycle is set during the count operation only. Rev.1.00 Sep. 18, 2008 Page 190 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TCNT_3 TCNT_4 TCNTS Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Time TCNTS Figure 8.34 Complementary PWM Mode Counter Operation Register Operation: In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 8.35 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 8.35 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 8.35) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared Rev.1.00 Sep. 18, 2008 Page 191 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS— and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly. Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 TGRA_3 Ta Tb1 Ta Tb2 Ta TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 H'6400 H'0080 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform waveform (Output waveform is active-low) Figure 8.35 Example of Complementary PWM Mode Operation Rev.1.00 Sep. 18, 2008 Page 192 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Initialization: In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). Set the respective initial PWM duty cycle values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 8.41 Registers and Counters Requiring Initialization Register/Counter TGRC_3 TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Set Value 1/2 PWM carrier cycle + dead time Td Dead time Td 1/2 PWM carrier cycle Initial PWM duty cycle value for each phase H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. PWM Output Level Setting: In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in the timer output control register (TOCR). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. Dead Time Setting: In complementary PWM mode, PWM pulses are output with a nonoverlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. Rev.1.00 Sep. 18, 2008 Page 193 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. PWM Cycle Setting: In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGRA_3 set value = TCDR set value + TDDR set value The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the peak, and from the current cycle when performed in the trough. Figure 8.36 illustrates the operation when the PWM cycle is updated at the peak. See the following section, Register data updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 8.36 Example of PWM Cycle Updating Rev.1.00 Sep. 18, 2008 Page 194 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Register Data Updating: In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty cycle and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 8.37 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter peak and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Rev.1.00 Sep. 18, 2008 Page 195 of 522 REJ09B0069-0100 Data update timing: counter peak and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register : Compare register : Buffer register Transfer from temporary register to compare register Counter value Rev.1.00 Sep. 18, 2008 Page 196 of 522 REJ09B0069-0100 Time data2 data2 data2 data3 data3 data3 data4 data4 data5 data5 data4 data6 data6 data6 Section 8 Multifunction Timer Pulse Unit (MTU) TGRA_3 TGRC_4 TGRA_4 H'0000 BR data1 Temp_R data1 Figure 8.37 Example of Data Update in Complementary PWM Mode GR data1 Section 8 Multifunction Timer Pulse Unit (MTU) Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 8.38 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty cycle value is smaller than the TDDR value is shown in figure 8.39. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT3, 4 value TCNT_3 TCNT_4 TGR4_A TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level Complementary PWM mode (TMDR setting) TCNT3, 4 count start (TSTR setting) Figure 8.38 Example of Initial Output in Complementary PWM Mode (1) Rev.1.00 Sep. 18, 2008 Page 197 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGR_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 8.39 Example of Initial Output in Complementary PWM Mode (2) Complementary PWM Mode PWM Output Generation Method: In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 8.40 to 8.42 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In Rev.1.00 Sep. 18, 2008 Page 198 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as shown in figure 8.40. If compare-matches deviate from the a → b → c → d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 8.41, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 8.42, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the positive phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. T1 period TGR3A_3 c TCDR d T2 period T1 period a b a' b' TDDR H'0000 Positive phase Negative phase Figure 8.40 Example of Complementary PWM Mode Waveform Output (1) Rev.1.00 Sep. 18, 2008 Page 199 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) T1 period TGRA_3 c TCDR a b d T2 period T1 period a b TDDR H'0000 Positive phase Negative phase Figure 8.41 Example of Complementary PWM Mode Waveform Output (2) T1 period TGRA_3 T2 period T1 period TCDR a b TDDR c a' H'0000 Positive phase b' d Negative phase Figure 8.42 Example of Complementary PWM Mode Waveform Output (3) Rev.1.00 Sep. 18, 2008 Page 200 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) T1 period TGRA_3 c d T2 period T1 period TCDR a b a' TDDR b' H'0000 Positive phase Negative phase Figure 8.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) T1 period TGRA_3 T2 period T1 period TCDR a b a TDDR b H'0000 Positive phase c d Negative phase Figure 8.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) Rev.1.00 Sep. 18, 2008 Page 201 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) T1 period TGRA_3 c d T2 period T1 period TCDR a b TDDR H'0000 Positive phase Negative phase Figure 8.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 Positive phase Negative phase c b' d a' Figure 8.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) Rev.1.00 Sep. 18, 2008 Page 202 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) T1 period TGRA_3 c ad b T2 period T1 period TCDR TDDR H'0000 Positive phase Negative phase Figure 8.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Complementary PWM Mode 0% and 100% Duty Cycle Output: In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 8.43 to 8.47 show output examples. 100% duty cycle output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty cycle output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 8.48. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. Rev.1.00 Sep. 18, 2008 Page 203 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 8.48 Example of Toggle Output Waveform Synchronized with PWM Output Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 8.49 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. Rev.1.00 Sep. 18, 2008 Page 204 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNTS TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 8.49 Counter Clearing Synchronized with Another Channel Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 8.50 to 8.53 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. Rev.1.00 Sep. 18, 2008 Page 205 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 8.50 Example of Output Phase Switching by External Input (1) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 8.51 Example of Output Phase Switching by External Input (2) Rev.1.00 Sep. 18, 2008 Page 206 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 8.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 8.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) Rev.1.00 Sep. 18, 2008 Page 207 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3 compare-match or a compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the center of the PWM pulse. A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection functions. • Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller’s bus control register 1 (BCR1). The registers and counters concerned are listed in table 8.3. This function enables the CPU to prevent miswriting due to CPU runaway by disabling CPU access to the mode registers, control registers, and counters. • Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 8.9, Port Output Enable (POE), for details. • Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. For details, see section 4.2, Function for Detecting the Oscillator Halt. Rev.1.00 Sep. 18, 2008 Page 208 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.5 8.5.1 Interrupt Sources Interrupts and Priorities There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 8.42 lists the MTU interrupt sources. Rev.1.00 Sep. 18, 2008 Page 209 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Table 8.42 MTU Interrupts Channel Name 0 TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TGI4C TGI4D TCI4V Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TGRC_4 input capture/compare match TGRD_4 input capture/compare match TCNT_4 overflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two each for channels 1 and 2. Rev.1.00 Sep. 18, 2008 Page 210 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU has four underflow interrupts, one each for channels 1 and 2. 8.5.2 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match in each channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D converter at this time, A/D conversion starts. In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 8.6 8.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 8.54 shows TCNT count timing in internal clock operation, and Figure 8.55 shows TCNT count timing in external clock operation (normal mode), and figure 8.56 shows TCNT count timing in external clock operation (phase counting mode). Pφ Internal clock TCNT input clock TCNT N-1 N N+1 N+2 Falling edge Rising edge Figure 8.54 Count Timing in Internal Clock Operation Rev.1.00 Sep. 18, 2008 Page 211 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Pφ External clock TCNT input clock TCNT N-1 N N+1 N+2 Falling edge Rising edge Falling edge Figure 8.55 Count Timing in External Clock Operation Pφ External clock TCNT input clock Falling edge Rising edge Falling edge TCNT N-1 N N+1 Figure 8.56 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 8.57 shows output compare output timing (normal mode and PWM mode) and figure 8.58 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). Rev.1.00 Sep. 18, 2008 Page 212 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Pφ TCNT input clock N N+1 TCNT TGR Compare match signal TIOC pin N Figure 8.57 Output Compare Output Timing (Normal Mode/PWM Mode) Pφ TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 8.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Rev.1.00 Sep. 18, 2008 Page 213 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Input Capture Signal Timing: Figure 8.59 shows input capture signal timing. Pφ Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 8.59 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match/Input Capture: Figure 8.60 shows the timing when counter clearing on compare match is specified, and figure 8.61 shows the timing when counter clearing on input capture is specified. Pφ Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 8.60 Counter Clear Timing (Compare Match) Rev.1.00 Sep. 18, 2008 Page 214 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Pφ Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 8.61 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 8.62 and 8.63 show the timing in buffer operation. Pφ TCNT Compare match signal TGRA, TGRB TGRC, TGRD n n+1 n N N Figure 8.62 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 8.63 Buffer Operation Timing (Input Capture) Rev.1.00 Sep. 18, 2008 Page 215 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 8.64 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. Pφ TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 8.64 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 8.65 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. Pφ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 8.65 TGI Interrupt Timing (Input Capture) Rev.1.00 Sep. 18, 2008 Page 216 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TCFV Flag/TCFU Flag Setting Timing: Figure 8.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 8.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. Pφ TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 8.66 TCIV Interrupt Setting Timing Pφ TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF TCIU interrupt Figure 8.67 TCIU Interrupt Setting Timing Rev.1.00 Sep. 18, 2008 Page 217 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 8.68 shows the timing for status flag clearing by the CPU. TSR write cycle T1 T2 Pφ Address TSR address Write signal Status flag Interrupt request signal Figure 8.68 Timing for Status Flag Clearing by the CPU 8.7 8.7.1 Usage Notes Module Standby Mode Setting MTU operation can be disabled or enabled using the module standby register. The initial setting is for MTU operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 18, Power-Down Modes. 8.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.69 shows the input clock conditions in phase counting mode. Rev.1.00 Sep. 18, 2008 Page 218 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Overlap TCLKA (TCLKC) TCLKB (TCLKD) Phase Phase differdifference Overlap ence Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 8.69 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 8.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where Pφ (N + 1) f : Counter frequency Pφ : Peripheral clock operating frequency N : TGR set value Contention between TCNT Write and Clear Operations 8.7.4 If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 8.70 shows the timing in this case. Rev.1.00 Sep. 18, 2008 Page 219 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TCNT write cycle T1 T2 Pφ Address Write signal Counter clear signal TCNT TCNT address N H'0000 Figure 8.70 Contention between TCNT Write and Clear Operations 8.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 8.71 shows the timing in this case. TCNT write cycle T1 T2 Pφ Address TCNT address Write signal TCNT input clock TCNT N TCNT write data M Figure 8.71 Contention between TCNT Write and Increment Operations Rev.1.00 Sep. 18, 2008 Page 220 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.7.6 Contention between TGR Write and Compare Match When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is generated. Figure 8.72 shows the timing in this case. TGR write cycle T1 T2 Pφ Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address Figure 8.72 Contention between TGR Write and Compare Match Rev.1.00 Sep. 18, 2008 Page 221 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write. Figures 8.73 and 8.74 show the timing in this case. TGR write cycle T1 T2 Pφ Address Write signal Compare match signal Compare match buffer signal Buffer register TGR N M M Buffer register address Buffer register write data Figure 8.73 Contention between Buffer Register Write and Compare Match (Channel 0) Rev.1.00 Sep. 18, 2008 Page 222 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TGR write cycle T1 T2 Pφ Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M TGR N Figure 8.74 Contention between Buffer Register Write and Compare Match (Channels 3 and 4) 8.7.8 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 8.75 shows the timing in this case. Rev.1.00 Sep. 18, 2008 Page 223 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TGR read cycle T1 T2 Pφ Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 8.75 Contention between TGR Read and Input Capture Rev.1.00 Sep. 18, 2008 Page 224 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.7.9 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 8.76 shows the timing in this case. TGR write cycle T1 T2 Pφ Address Write signal Input capture signal TCNT TGR M M TGR address Figure 8.76 Contention between TGR Write and Input Capture Rev.1.00 Sep. 18, 2008 Page 225 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.7.10 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 8.77 shows the timing in this case. Buffer register write cycle T1 T2 Pφ Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address Figure 8.77 Contention between Buffer Register Write and Input Capture 8.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 8.78. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Rev.1.00 Sep. 18, 2008 Page 226 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) TCNT write cycle T1 Pφ Address Write signal TCNT_2 H'FFFE H'FFFF TCNT_2 write data TGR2A_2 to TGR2B_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D P N M M M Disabled H'FFFF N N+1 TCNT_2 address T2 Q P Figure 8.78 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection 8.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 8.79. Rev.1.00 Sep. 18, 2008 Page 227 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Counter operation stop Complementary PWM mode operation Complementary PMW restart Figure 8.79 Counter Value during Complementary PWM Mode Stop 8.7.13 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty cycle setting registers (TGRB_3, TRGA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3’s BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4, while the TCBR functions as the TCDR’s buffer register. 8.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 Rev.1.00 Sep. 18, 2008 Page 228 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 8.80 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3’s BFA and BFB bits set to 1, and TMDR_4’s BFA and BFB bits set to 0. TGRA_3 TCNT3 TGRC_3 Point a Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRB_3, TGRA_4, TGRB_4 Point b TGRD_3, TGRC_4, TGRD_4 H'0000 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 8.80 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode 8.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4’s count clock source and count edge obey the TCR_3 setting. In reset sync PWM mode, with cycle register TGRA_3’s set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, Rev.1.00 Sep. 18, 2008 Page 229 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR’s overflow flag TCFV bit is not set. Figure 8.81 shows a TCFV bit operation example in reset sync PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 8.81 Reset Sync PWM Mode Overflow Flag 8.7.16 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 8.82 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. Rev.1.00 Sep. 18, 2008 Page 230 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Pφ TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV Figure 8.82 Contention between Overflow and Counter Clearing 8.7.17 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 8.83 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 Pφ Address Write signal TCNT address TCNT write data TCNT H'FFFF M TCFV flag Figure 8.83 Contention between TCNT Write and Overflow Rev.1.00 Sep. 18, 2008 Page 231 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to registers TIOR3H, TIOR3L, TIOR4H, and TIOR4L to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronous PWM mode. 8.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode, TIOR should be set to H'00. 8.7.20 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode. 8.7.21 Simultaneous Input Capture of TCNT-1 and TCNT-2 in Cascade Connection When cascade-connected timer counters (TCNT-1 and TCNT-2) are operated, cascade values cannot be captured even if input capture is executed simultaneously with TIOC1A or TIOC1B and TIOC2A or TIOC2B. Rev.1.00 Sep. 18, 2008 Page 232 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.8 8.8.1 MTU Output Pin Initialization Operating Modes The MTU has the following six operating modes. Waveform output is possible in all of these modes. • Normal mode (channels 0 to 4) • PWM mode 1 (channels 0 to 4) • PWM mode 2 (channels 0 to 2) • Phase counting modes 1 to 4 (channels 1 and 2) • Complementary PWM mode (channels 3 and 4) • Reset-synchronous PWM mode (channels 3 and 4) The MTU output pin initialization method for each of these modes is described in this section. 8.8.2 Reset Start Operation The MTU output pins (TIOC*) are initialized low by a reset or in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: Channel number and port notation are substituted for *. Rev.1.00 Sep. 18, 2008 Page 233 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.8.3 Operation in Case of Re-Setting Due to Error During Operation, Etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 8.43. Table 8.43 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29) Legend: Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronous PWM mode The above abbreviations are used in some places in following descriptions. Rev.1.00 Sep. 18, 2008 Page 234 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. • In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. • In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. • In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, and then set buffer mode again. • In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. • When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Pin initialization procedures are described below for the numbered combinations in table 8.43. The active level is assumed to be low. Note: Channel number is substituted for * indicated in this article. Rev.1.00 Sep. 18, 2008 Page 235 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 8.84 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z Figure 8.84 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 236 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 8.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 8.85 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.84. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 8.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) Figure 8.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 Rev.1.00 Sep. 18, 2008 Page 237 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 1 to 10 are the same as in figure 8.84. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 8.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z Figure 8.87 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 8.84. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev.1.00 Sep. 18, 2008 Page 238 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 8.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (normal) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 11 12 14 15 (16) (17) (18) TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.88 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.84. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 239 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 8.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (normal) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 11 12 14 15 16 17 18 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.89 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode 1 to 13 are the same as in figure 8.88. 14. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronous PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 240 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 8.90 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 8.90 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 241 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 8.91 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) • Not initialized (TIOC*B) Figure 8.91 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.90. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 8.92 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z • Not initialized (cycle register) • Not initialized (TIOC*B) Figure 8.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 Rev.1.00 Sep. 18, 2008 Page 242 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 1 to 10 are the same as in figure 8.90. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 8.93 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z • Not initialized (TIOC*B) Figure 8.93 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 8.90. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev.1.00 Sep. 18, 2008 Page 243 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 8.94 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (PWM1) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 18 19 Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 • Not initialized (TIOC3B) • Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 8.94 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.90. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 244 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 8.95 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (PWM1) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 18 19 Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 • Not initialized (TIOC3B) • Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 8.95 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode 1 to 14 are the same as in figure 8.90. 15. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronous PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 245 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 8.96 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 • Not initialized (cycle register) Hi-Z Hi-Z Figure 8.96 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. 4. 5. 6. 7. 8. 9. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 246 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 8.97 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 • Not initialized (cycle register) • Not initialized (TIOC*B) Hi-Z Hi-Z Figure 8.97 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.96. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 8.98 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 • Not initialized (cycle register) • Not initialized (cycle register) Hi-Z Hi-Z Figure 8.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 Rev.1.00 Sep. 18, 2008 Page 247 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 1 to 9 are the same as in figure 8.96. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 8.99 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 PFC TSTR Match Error PFC TSTR TMDR (MTU) (1) occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 • Not initialized (cycle register) Hi-Z Hi-Z Figure 8.99 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 8.96. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 248 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 8.100 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TIOR (PCM) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z Figure 8.100 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 249 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 8.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 • Not initialized (TIOC*B) Hi-Z Hi-Z Figure 8.101 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 8.100. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 8.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 • Not initialized (cycle register) Hi-Z Hi-Z Figure 8.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 Rev.1.00 Sep. 18, 2008 Page 250 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 1 to 9 are the same as in figure 8.100. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 8.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 PFC TSTR Match Error PFC TSTR TMDR (MTU) (1) occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 Hi-Z Hi-Z Figure 8.103 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 8.100. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 251 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 8.104 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.104 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU output becomes the complementary PWM output initial value.) 11. Set normal mode. (MTU output goes low.) 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 252 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 8.105 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z • Not initialized (TIOC3B) • Not initialized (TIOC3D) Figure 8.105 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.104. 11. Set PWM mode 1. (MTU output goes low.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 253 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 8.106 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty cycle settings at the time the counter was stopped). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.106 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.104. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. Rev.1.00 Sep. 18, 2008 Page 254 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 8.107 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty cycle settings). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.104. 11. Set normal mode and make new settings. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 255 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 8.108 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (RPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.108 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in figure 8.104. 11. Set normal mode. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronous PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronous PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 256 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 8.109 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.109 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronous PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The reset-synchronous PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU output becomes the reset-synchronous PWM output initial value.) 11. Set normal mode. (MTU positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 257 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 8.110 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z • Not initialized (TIOC3B) • Not initialized (TIOC3D) Figure 8.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 8.109. 11. Set PWM mode 1. (MTU positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 258 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 8.111 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 8.109. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU output with the PFC. 16. Operation is restarted by TSTR. Rev.1.00 Sep. 18, 2008 Page 259 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) (29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode Figure 8.112 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 Hi-Z Hi-Z Hi-Z Figure 8.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in figure 8.109. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronous PWM waveform is output on compare-match occurrence. Rev.1.00 Sep. 18, 2008 Page 260 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0 to POE3 pin input, depending on the output status of the high-current pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT). It can also simultaneously generate interrupt requests. The high-current pins also become high-impedance regardless of whether these pin functions are selected in cases such as when the oscillator stops or in standby mode. 8.9.1 Features • Each of the POE0 to POE3 input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or Pφ/128 × 16 low-level sampling. • High-current pins can be set to high-impedance state by POE0 to POE3 pin falling-edge or low-level sampling. • High-current pins can be set to high-impedance state when the high-current pin output levels are compared and simultaneous low-level output continues for one cycle or more. • Interrupts can be generated by input-level sampling or output-level comparison results. Rev.1.00 Sep. 18, 2008 Page 261 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 8.113. TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Output level detection circuit Output level detection circuit Output level detection circuit OCSR Highimpedance request control signal Interrupt request (MTUPOE) ICSR1 Input level detection circuit Falling-edge detection circuit Low-level detection circuit POE3 POE2 POE1 POE0 Pφ/8 Pφ/16 Pφ/128 Legend: OCSR: Output level control/status register ICSR1: Input level control/status register Figure 8.113 POE Block Diagram Rev.1.00 Sep. 18, 2008 Page 262 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.9.2 Pin Configuration Table 8.44 Pin Configuration Name Port output enable input pins Abbreviation POE0 to POE3 I/O Input Description Input request signals to make highcurrent pins high-impedance state Table 8.45 shows output-level comparisons with pin combinations. Table 8.45 Pin Combinations Pin Combination PE9/TIOC3B and PE11/TIOC3D I/O Output Description All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. PE12/TIOC4A and PE14/TIOC4C Output PE13/TIOC4B/MRES and PE15/TIOC4D/IRQOUT Output 8.9.3 Register Descriptions The POE has the two registers. The input level control/status register 1 (ICSR1) controls both POE0 to POE3 pin input signal detection and interrupts. The output level control/status register (OCSR) controls both the enable/disable of output comparison and interrupts. Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1) is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Rev.1.00 Sep. 18, 2008 Page 263 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 15 Initial Bit Name value POE3F 0 R/W R/(W)* Description POE3 Flag This flag indicates that a high impedance request has been input to the POE3 pin. [Clearing condition] • By writing 0 to POE3F after reading POE3F = 1 [Setting condition] • When the input set by bits 7 and 6 of ICSR1 occurs at the POE3 pin 14 POE2F 0 R/(W)* POE2 Flag This flag indicates that a high impedance request has been input to the POE2 pin. [Clearing condition] • By writing 0 to POE2F after reading POE2F = 1 [Setting condition] • When the input set by bits 5 and 4 of ICSR1 occurs at the POE2 pin 13 POE1F 0 R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin. [Clearing condition] • By writing 0 to POE1F after reading POE1F = 1 [Setting condition] • When the input set by bits 3 and 2 of ICSR1 occurs at the POE1 pin 12 POE0F 0 R/(W)* POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin. [Clearing condition] • By writing 0 to POE0F after reading POE0F = 1 [Setting condition] • When the input set by bits 1 and 0 of ICSR1 occurs at the POE0 pin Rev.1.00 Sep. 18, 2008 Page 264 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit Initial Bit Name value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 9 — 8 PIE 0 R/W Port Interrupt Enable This bit enables/disables interrupt requests when any of the POE0F to POE3F bits of the ICSR1 are set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 6 POE3M1 POE3M0 0 0 R/W R/W POE3 mode 1 and 0 These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input. 01: Accept request when POE3 input has been sampled for 16 Pφ/8 clock pulses, and all are low level. 10: Accept request when POE3 input has been sampled for 16 Pφ/16 clock pulses, and all are low level. 11: Accept request when POE3 input has been sampled for 16 Pφ/128 clock pulses, and all are low level. 5 4 POE2M1 POE2M0 0 0 R/W R/W POE2 mode 1 and 0 These bits select the input mode of the POE2 pin. 00: Accept request on falling edge of POE2 input. 01: Accept request when POE2 input has been sampled for 16 Pφ/8 clock pulses, and all are low level. 10: Accept request when POE2 input has been sampled for 16 Pφ/16 clock pulses, and all are low level. 11: Accept request when POE2 input has been sampled for 16 Pφ/128 clock pulses, and all are low level. 3 2 POE1M1 POE1M0 0 0 R/W R/W POE1 mode 1 and 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input. 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses, and all are low level. 10: Accept request when POE1 input has been sampled for 16 Pφ/16 clock pulses, and all are low level. 11: Accept request when POE1 input has been sampled for 16 Pφ/128 clock pulses, and all are low level. Rev.1.00 Sep. 18, 2008 Page 265 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 1 0 Initial Bit Name value POE0M1 POE0M0 0 0 R/W R/W R/W Description Note: * POE0 mode 1 and 0 These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input. 01: Accept request when POE0 input has been sampled for 16 Pφ/8 clock pulses, and all are low level. 10: Accept request when POE0 input has been sampled for 16 Pφ/16 clock pulses, and all are low level. 11: Accept request when POE0 input has been sampled for 16 Pφ/128 clock pulses, and all are low level. The write value should always be 0. Output Level Control/Status Register (OCSR): The output level control/status register (OCSR) is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. Bit 15 Bit Name OSF Initial value 0 R/W Description R/(W)* Output Short Flag This flag indicates that any one pair of the three pairs of 2 phase outputs compared have simultaneously become low level outputs. [Clearing condition] • By writing 0 to OSF after reading OSF = 1 [Setting condition] • When any one pair of the three 2-phase outputs simultaneously become low level 14 to 10 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 266 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Bit 9 Bit Name OCE Initial value 0 R/W R/W Description Output Level Compare Enable This bit enables the start of output level comparisons. When setting this bit to 1, pay attention to the output pin combinations shown in table 8.43, Mode Transition Combinations. When 0 is output, the OSF bit is set to 1 at the same time when this bit is set, and output goes to high impedance. Accordingly, bits 15 to 11 and bit 9 of the port E data register (PEDR) are set to 1. For the MTU output comparison, set the bit to 1 after setting the MTU's output pins with the PFC. Set this bit only when using pins as outputs. When the OCE bit is set to 1, if OIE = 0 a highimpedance request will not be issued even if OSF is set to 1. Therefore, in order to have a high-impedance request issued according to the result of the output level comparison, the OIE bit must be set to 1. When OCE = 1 and OIE = 1, an interrupt request will be generated at the same time as the high-impedance request: however, this interrupt can be masked by means of an interrupt controller (INTC) setting. 0: Output level compare disabled 1: Output level compare enabled; makes an output high impedance request when OSF = 1. 8 OIE 0 R/W Output Short Interrupt Enable This bit makes interrupt requests when the OSF bit of the OCSR is set. 0: Interrupt requests disabled 1: Interrupt request enabled 7 to 0 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 267 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) 8.9.4 Operation Input Level Detection Operation If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins become high-impedance state. However, only when the general input/output function or MTU function is selected, the large-current pin is in the high-impedance state. Falling Edge Detection: When a change from high to low level is input to the POE pins. Low-Level Detection: Figure 8.114 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR1. If even one high level is detected during this interval, the low level is not accepted. Furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection. 8/16/128 clock cycles Pφ Sampling clock POE input PE9/ TIOC3B When low level is sampled at all points When high level is sampled at least once High-impedance state* 1 1 2 2 3 16 13 Flag set (POE received) Flag not set Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT) also go to the high-impedance state at the same timing. Figure 8.114 Low-Level Detection Operation Rev.1.00 Sep. 18, 2008 Page 268 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) Output-Level Compare Operation Figure 8.115 shows an example of the output-level compare operation for the combination of PE9/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations. P 0 level overlapping detected PE9/ TIOC3B PE11/ TIOC3D High impedance state Figure 8.115 Output-Level Detection Operation Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-current pins that have become highimpedance due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance state by clearing the OSF flag, always do so only after outputting a high level from the highcurrent pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs can be achieved by setting the MTU internal registers. Rev.1.00 Sep. 18, 2008 Page 269 of 522 REJ09B0069-0100 Section 8 Multifunction Timer Pulse Unit (MTU) POE Timing Figure 8.116 shows an example of timing from POE input to high impedance of pin. Pφ CK falling input Falling edge detected PE9/ TIOC3B High impedance state Note: Other large-current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/ , PE14/TIOC4C, ) also goes to the high impedance state at the same timing PE15/TIOC4D/ Figure 8.116 Falling Edge Detection Operation 8.9.5 Usage Note To set the POE pin as a level detection pin, a high level signal must be firstly input to the POE pin. Rev.1.00 Sep. 18, 2008 Page 270 of 522 REJ09B0069-0100 Section 9 Watchdog Timer Section 9 Watchdog Timer This watchdog timer (WDT) module provides a single, 8-bit timer that can be used to monitor the system. When the counter value is not rewritten due to a system crash (such as an infinite loop) and the counter overflows, an overflow signal (WDTOVF) is output to external circuits. It is also possible to issue an IC internal reset signal at the same time. If this module is not used as a watchdog timer, it can be used as an interval timer. If it is used as an interval timer, the interval timer interrupt (ITI) will be generated each time the counter overflows. The watchdog timer can also be used when standby mode is cleared. Figure 9.1 shows the block timer of the WDT module. The block diagram of the WDT is shown in figure 9.1. 9.1 Features • Selectable from eight counter input clocks • Switchable between watchdog timer mode and interval timer mode • Used to clear software standby mode In watchdog timer mode • Output WDTOVF signal • If the counter overflows, it is possible to select whether this LSI is internally reset or not. In interval timer mode • If the counter overflows, the WDT generates an interval timer interrupt (ITI). WDT0400A_010020030200 Rev.1.00 Sep. 18, 2008 Page 271 of 522 REJ09B0069-0100 Section 9 Watchdog Timer Overflow ITI (interrupt request signal) Interrupt control Clock Clock select WDTOVF Internal reset signal* Reset control φ/2 φ/64 φ/128 φ/256 φ/512 φ/1024 φ/4096 φ/8192 Internal clock sources Internal bus RSTCSR TCNT TSCR Bus interface Module bus WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by making a register setting. Power-on reset or manual reset can be selected. Figure 9.1 Block Diagram of WDT 9.2 Input/Output Pin Table 9.1 shows the pin configuration of the watchdog timer. Table 9.1 Pin Watchdog timer overflow Pin Configuration Abbreviation WDTOVF I/O Output Function Outputs the counter overflow signal in watchdog timer mode Note: The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin down, a resistance of 1 MΩ or higher should be used. 9.3 Register Descriptions The WDT has the following three registers. For details, refer to section 19, List of Registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 9.6.1, Notes on Register Access. Rev.1.00 Sep. 18, 2008 Page 272 of 522 REJ09B0069-0100 Section 9 Watchdog Timer • Timer control/status register (TCSR) • Timer counter (TCNT) • Reset control/status register (RSTCSR) 9.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR. The initial value of TCNT is H'00. 9.3.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* 1 Description Overflow Flag Indicates that TCNT has overflowed in interval timer mode. This bit should only be written with 0 to clear the flag. This flag is not set in watchdog timer mode. [Setting condition] • When TCNT overflows in interval timer mode [Clearing conditions] • • Cleared by reading OVF When 0 is written to the TME bit in interval timer mode 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. 0: Interval timer mode Interval timer interrupt (ITI) request to the CPU when TCNT overflows 1: Watchdog timer mode WDTOVF signal output externally when TCNT 2 overflows* . Rev.1.00 Sep. 18, 2008 Page 273 of 522 REJ09B0069-0100 Section 9 Watchdog Timer Bit 5 Bit Name TME Initial Value 0 R/W R/W Description Timer Enable Enables or disables the timer. 0: Timer disabled TCNT is initialized to H'00 and count-up stops 1: Timer enabled TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. 4, 3 — All 1 R Reserved These bits are always read as 1. The write value should always be 1. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (φ). The overflow frequency for φ = 40 MHz is enclosed in 3 parentheses* . 000: Clock φ/2 (period: 12.8 μs) 001: Clock φ/64 (period: 409.6 μs) 010: Clock φ/128 (period: 0.8 ms) 011: Clock φ/256 (period: 1.6 ms) 100: Clock φ/512 (period: 3.3 ms) 101: Clock φ/1024 (period: 6.6 ms) 110: Clock φ/4096 (period: 26.2 ms) 111: Clock φ/8192 (period: 52.4 ms) Notes: 1. Only 0 can be written after reading 1. 2. Section 9.3.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode. 3. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Rev.1.00 Sep. 18, 2008 Page 274 of 522 REJ09B0069-0100 Section 9 Watchdog Timer 9.3.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W)* Description Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode. [Setting condition] • Set when TCNT overflows in watchdog timer mode [Clearing condition] • 6 RSTE 0 R/W Cleared by reading WOVF, and then writing 0 to WOVF Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows in watchdog timer mode. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 RSTS 0 R/W Reset Select Selects the type of internal reset generated if TCNT overflows in watchdog timer mode. 0: Power-on reset 1: Manual reset 4 to 0 — All 1 R Reserved These bits are always read as 1. The write value should always be 1. Note: * Only 0 can be written, for flag clearing. Rev.1.00 Sep. 18, 2008 Page 275 of 522 REJ09B0069-0100 Section 9 Watchdog Timer 9.4 9.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally. The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 φ clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 φ clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following are not initialized by a WDT reset signal: • POE (port output enable) of MTU registers • PFC (pin function controller) registers • I/O port registers These registers are initialized only by an external power-on reset. Rev.1.00 Sep. 18, 2008 Page 276 of 522 REJ09B0069-0100 Section 9 Watchdog Timer TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written in TCNT WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WOVF = 1 Time WDTOVF signal Internal reset signal* 128 φ clocks 512 φ clocks WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 9.2 Operation in Watchdog Timer Mode 9.4.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter (TCNT) overflows. This function can be used to generate interval timer interrupts at regular intervals. TCNT value Overflow H'FF Overflow Overflow Overflow H'00 WT/ = 0 TME = 1 ITI ITI ITI ITI Time ITI: Interval timer interrupt request generation Figure 9.3 Operation in Interval Timer Mode Rev.1.00 Sep. 18, 2008 Page 277 of 522 REJ09B0069-0100 Section 9 Watchdog Timer 9.4.3 Clearing Software Standby Mode The watchdog timer has a special function to clear software standby mode with an NMI interrupt or IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below. Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to stop the watchdog timer counter before entering software standby mode. The chip cannot enter software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 20.3, AC Characteristics, for the oscillation settling time. Recovery from Software Standby Mode: When an NMI signal or IRQ0 to IRQ3 signals are received in software standby mode, the clock oscillator starts running and TCNT starts incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and software standby mode ends. For details on software standby mode, see section 18, Power-Down Modes. 9.4.4 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested. Figure 9.4 shows this timing. CK TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 9.4 Timing of Setting OVF Rev.1.00 Sep. 18, 2008 Page 278 of 522 REJ09B0069-0100 Section 9 Watchdog Timer 9.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip. Figure 9.5 shows this timing. CK TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 9.5 Timing of Setting WOVF 9.5 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 9.2 Name ITI WDT Interrupt Source (in Interval Timer Mode) Interrupt Source TCNT overflow Interrupt Flag OVF 9.6 9.6.1 Usage Notes Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. Rev.1.00 Sep. 18, 2008 Page 279 of 522 REJ09B0069-0100 Section 9 Watchdog Timer TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 9.6). This transfers the write data from the lower byte to TCNT or TCSR. • Writing to TCNT 15 Address: H'FFFF8610 H'5A 8 7 Write data 0 • Writing to TCSR 15 Address: H'FFFF8610 H'A5 8 7 Write data 0 Figure 9.6 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 9.7. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. • Writing 0 to the WOVF bit 15 Address: H'FFFF8612 H'A5 8 7 H'00 0 • Writing to the RSTE and RSTS bits 15 Address: H'FFFF8612 H'5A 8 7 Write data 0 Figure 9.7 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR, H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR. Rev.1.00 Sep. 18, 2008 Page 280 of 522 REJ09B0069-0100 Section 9 Watchdog Timer 9.6.2 TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented. Figure 9.8 shows this operation. TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 9.8 Contention between TCNT Write and Increment 9.6.3 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0. 9.6.4 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev.1.00 Sep. 18, 2008 Page 281 of 522 REJ09B0069-0100 Section 9 Watchdog Timer 9.6.5 System Reset by WDTOVF Signal If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 9.9. This LSI Reset input Reset signal to entire system Figure 9.9 Example of System Reset Circuit Using WDTOVF Signal 9.6.6 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. 9.6.7 Manual Reset in Watchdog Timer Mode When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. 9.6.8 Notes on Using WDTOVF Pin The WDTOVF pin should not be pulled down. However, if it is necessary to pull this pin down, a resistance of 1 MΩ or higher should be used. Rev.1.00 Sep. 18, 2008 Page 282 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Section 10 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). 10.1 Features • Choice of asynchronous or clocked synchronous serial communication mode • Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. • On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source. • Choice of LSB-first or MSB-first transfer* (except in the case of asynchronous mode 7-bit data) • Four interrupt sources Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive error — that can issue requests. • Module standby mode can be set Asynchronous mode • Data length: 7 or 8 bits • Stop bit length: 1 or 2 bits • Parity: Even, odd, or none • Multiprocessor bit: 1 or 0 • Receive error detection: Parity, overrun, and framing errors • Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCIS200B_010020030200 Rev.1.00 Sep. 18, 2008 Page 283 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors detected Note: * The description in this section are based on LSB-first transfer. Figure 10.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SSR SCR SMR SDCR Transmission/ reception control BRR Pφ Baud rate generator Pφ/8 Pφ/32 Pφ/128 Clock RxD RSR TSR TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register SDCR: Serial direction control register Figure 10.1 Block Diagram of SCI Rev.1.00 Sep. 18, 2008 Page 284 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.2 Input/Output Pins Table 10.1 shows the SCI pin configuration. Table 10.1 Pin Configuration Channel 2 Pin Name* SCK2 RxD2 TxD2 3 SCK3 RxD3 TxD3 Note: * I/O I/O Input Output I/O Input Output Function SCI_2 clock input/output SCI_2 receive data input SCI_2 transmit data output SCI_3 clock input/output SCI_3 receive data input SCI_3 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 10.3 Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each processing, refer to section 19, List of Registers. Channel 2 • Serial mode register_2 (SMR_2) • Bit rate register_2 (BRR_2) • Serial control register_2 (SCR_2) • Transmit data register_2 (TDR_2) • Serial status register_2 (SSR_2) • Receive data register_2 (RDR_2) • Serial direction control register_2 (SDCR_2) Channel 3 • Serial mode register_3 (SMR_3) • Bit rate register_3 (BRR_3) • Serial control register_3 (SCR_3) • Transmit data register_3 (TDR_3) • Serial status register_3 (SSR_3) • Receive data register_3 (RDR_3) • Serial direction control register_3 (SDCR_3) Rev.1.00 Sep. 18, 2008 Page 285 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 10.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 10.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 10.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. Rev.1.00 Sep. 18, 2008 Page 286 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.3.5 Serial Mode Register (SMR) SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. Rev.1.00 Sep. 18, 2008 Page 287 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/8 clock (n = 1) 10: Pφ/32 clock (n = 2) 11: Pφ/128 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 10.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 10.3.9, Bit Rate Register (BRR)). 10.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 10.7, Interrupt Sources. Bit 7 6 Bit Name TIE RIE Initial Value 0 0 R/W R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 10.5, Multiprocessor Communication Function. Rev.1.00 Sep. 18, 2008 Page 288 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Bit 2 1 0 Bit Name TEIE CKE1 CKE0 Initial Value 0 0 0 R/W R/W R/W R/W Description Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. Clock Enable 1 and 0 Selects the clock source and SCK pin function. Asynchronous mode: 00: Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined) 01: Internal clock, SCK pin used for clock output (The output clock frequency is the same as the bit rate) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate) 11: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate) Clocked synchronous mode: 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Rev.1.00 Sep. 18, 2008 Page 289 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] • • • Power-on reset and software standby mode When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Clearing condition] • 6 RDRF 0 R/(W)* When 0 is written to TDRE after reading TDRE = 1 Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] • Power-on reset or software standby mode • When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing conditions] • Power-on reset or software standby mode • When 0 is written to ORER after reading ORER = 1 The ORER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. • • Rev.1.00 Sep. 18, 2008 Page 290 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Bit 4 Bit Name FER Initial Value 0 R/W R/(W)* Description Framing Error [Setting condition] • When the stop bit is 0 [Clearing conditions] • Power-on reset or software standby mode • When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. The FER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 3 PER 0 R/(W)* Parity Error [Setting condition] • When a parity error is detected during reception [Clearing conditions] • Power-on reset or software standby mode • When 0 is written to PER after reading PER = 1 The PER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 2 TEND 1 R Transmit End [Setting conditions] • • • Power-on reset or software standby mode When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character [Clearing condition] • 1 MPB 0 R When 0 is written to TDRE after reading TDRE = 1 Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0, its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT sets the multiprocessor bit value to be added to the transmit data. Note: * Only 0 can be written for flag clearing. Rev.1.00 Sep. 18, 2008 Page 291 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.3.8 Serial Direction Control Register (SDCR) The DIR bit in SDCR selects LSB-first or MSB-first transfer. With an 8-bit data length, LSBfirst/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-first transfer. Bit Bit Name Initial Value All 1 R/W R Description Reserved The write value should always be 1. Operation cannot be guaranteed if 0 is written. 3 DIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: TDR contents are transmitted in LSB-first order Receive data is stored in RDR in LSB-first 1: TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first 2 ⎯ 0 R Reserved The write value should always be 0. Operation cannot be guaranteed if 1 is written. 1 0 ⎯ ⎯ 1 0 R R Reserved This bit is always read as 1, and cannot be modified. Reserved The write value should always be 0. Operation cannot be guaranteed if 1 is written. 7 to 4 ⎯ 10.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 10.2 shows the relationships between the N setting in BRR and the effective bit rate B0 for asynchronous and clocked synchronous modes. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Rev.1.00 Sep. 18, 2008 Page 292 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0 Mode Asynchronous mode (n = 0) Asynchronous mode (n = 1 to 3) Clocked synchronous mode (n = 0) Clocked synchronous mode (n = 1 to 3) Bit Rate B0 = Pφ × 106 32 × 2 2n Error Error (%) = ⎞ ⎞ B0 – 1 × 100 ⎠ ⎠B 1 ⎞ ⎞ B0 – 1 × 100 ⎠ ⎠B 1 × (N + 1) B0 = Pφ × 106 32 × 22n+1 × (N + 1) Pφ × 106 4 × 22n × (N + 1) Pφ × 106 4 × 22n+1 × (N + 1) Error (%) = B0 = — B0 = — Note: B0: B1: N: Pφ: n: Effective bit rate (bit/s) Actual transfer speed according to the register settings Logical bit rate (bit/s) Specified transfer speed of the target system BRR setting for baud rate generator (0 ≤ N ≤ 255) Peripheral clock operating frequency (MHz) Determined by the SMR settings shown in the following tables. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N settings in BRR in clocked synchronous mode. For details, refer to section 10.4.2, Receive Data Sampling Timing and Reception Margin in Asynchronous Mode. Tables 10.5 and 10.7 show the maximum bit rates with external clock input. Rev.1.00 Sep. 18, 2008 Page 293 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 4 n 1 1 1 1 1 0 0 0 0 0 0 0 0 N 140 103 51 25 12 51 25 12 8 6 3 3 2 Error (%) 0.74 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –3.55 –6.99 8.51 0.00 8.51 n 1 1 1 1 0 0 0 0 0 0 0 0 0 N 212 155 77 38 155 77 38 19 12 9 6 5 4 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.16 –2.34 –6.99 0.00 –2.34 n 2 2 2 2 1 1 0 0 0 0 0 0 0 N 70 51 25 12 25 12 51 25 16 12 8 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 2.12 0.16 –3.55 0.00 –6.99 n 2 2 1 1 1 0 0 0 0 0 0 0 0 N 88 64 129 64 32 129 64 32 21 15 10 9 7 10 Error (%) –0.25 0.16 0.16 0.16 –1.36 0.16 0.16 –1.36 –1.36 1.73 –1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 106 77 38 77 38 155 77 38 25 19 12 11 9 12 Error (%) –0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –2.34 0.16 0.00 –2.34 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 14 n 2 2 2 2 1 1 0 0 0 0 0 0 0 N 123 90 45 22 45 22 90 45 29 22 14 13 10 Error (%) 0.23 0.16 –0.93 –0.93 –0.93 –0.93 0.16 –0.93 1.27 –0.93 1.27 0.00 3.57 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 141 103 51 103 51 207 103 51 34 25 16 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 –0.79 0.16 2.12 0.00 0.16 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 159 116 58 116 58 233 116 58 38 28 19 17 14 18 Error (%) –0.12 0.16 –0.69 0.16 –0.69 0.16 0.16 –0.69 0.16 1.02 –2.34 0.00 –2.34 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 177 129 64 129 64 32 129 64 42 32 21 19 15 20 Error (%) –0.25 0.16 0.16 0.16 0.16 –1.36 0.16 0.16 0.94 –1.36 –1.36 0.00 1.73 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 194 142 71 142 71 35 142 71 47 35 23 21 17 22 Error (%) 0.16 0.16 –0.54 0.16 –0.54 –0.54 0.16 –0.54 –0.54 –0.54 –0.54 0.00 –0.54 Rev.1.00 Sep. 18, 2008 Page 294 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 24 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 155 77 51 38 25 23 19 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 –2.34 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 221 162 80 162 80 40 162 80 53 40 26 24 19 25 Error (%) –0.02 –0.15 0.47 –0.15 0.47 –0.76 –0.15 0.47 0.47 –0.76 0.47 0.00 1.73 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 230 168 84 168 84 41 168 84 55 41 27 25 20 26 Error (%) –0.08 0.16 –0.43 0.16 –0.43 0.76 0.16 –0.43 0.76 0.76 0.76 0.00 0.76 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 248 181 90 181 90 45 181 90 60 45 29 27 22 28 Error (%) –0.17 0.16 0.16 0.16 0.16 –0.93 0.16 0.16 –0.39 –0.93 1.27 0.00 –0.93 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 66 194 97 48 97 48 194 97 64 48 32 29 23 30 Error (%) –0.62 0.16 –0.35 –0.35 –0.35 –0.35 0.16 –0.35 0.16 –0.35 –1.36 0.00 1.73 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 32 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 70 207 103 51 103 51 207 103 68 51 34 31 25 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.64 0.16 –0.79 0.00 0.16 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 74 220 110 54 110 51 220 110 73 54 36 33 27 34 Error (%) 0.62 0.16 –0.29 0.62 –0.29 6.42 0.16 –0.29 –0.29 0.62 –0.29 0.00 –1.18 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 79 233 116 58 116 58 234 116 77 58 38 35 28 36 Error (%) –0.12 0.16 0.16 –0.69 0.16 –0.69 –0.27 0.16 0.16 –0.69 0.16 0.00 1.02 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 83 246 123 61 123 61 246 123 81 61 40 37 30 38 Error (%) 0.40 0.16 –0.24 –0.24 –0.24 –0.24 0.16 –0.24 0.57 –0.24 0.57 0.00 –0.24 n 3 3 2 2 1 1 1 0 0 0 0 0 0 N 88 64 129 64 129 64 32 129 86 64 42 39 32 40 Error (%) –0.25 0.16 0.16 0.16 0.16 0.16 –1.36 0.16 –0.22 0.16 0.94 0.00 –1.36 Rev.1.00 Sep. 18, 2008 Page 295 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode) Pφ (MHz) 4 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Maximum Bit Rate (bit/s) 125000 250000 312500 375000 437500 500000 562500 625000 687500 750000 781250 812500 875000 937500 1000000 1062500 1125000 1187500 1250000 Rev.1.00 Sep. 18, 2008 Page 296 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ (MHz) 4 6 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 External Clock (MHz) 1.0000 1.5000 2.0000 2.5000 3.0000 3.5000 4.0000 4.5000 5.0000 5.5000 6.0000 6.2500 6.5000 7.0000 7.5000 8.0000 8.5000 9.0000 9.5000 10.0000 Maximum Bit Rate (bit/s) 62500 93750 125000 156250 187500 218750 250000 281250 312500 343750 375000 390625 406250 437500 468750 500000 531250 562500 593750 625000 Rev.1.00 Sep. 18, 2008 Page 297 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 4 n 2 1 1 1 1 0 0 0 0 0 0 0 — — N 124 249 124 49 24 99 39 19 9 3 1 0 — — n 2 — 1 1 — 0 0 0 0 0 0 — — — 6 N 187 — 187 74 — 149 59 29 14 5 2 — — — n 2 2 1 1 1 1 1 1 0 0 0 0 — — 8 N 249 124 249 99 49 24 9 4 19 7 3 1 — — n — 2 — 1 — 0 0 0 0 0 0 — 0 — 10 N — 155 — 124 — 249 99 49 24 9 4 — 0* — n — 2 — 1 1 — 1 0 0 0 0 0 — — 12 N — 187 — 149 74 — 14 59 29 11 5 2 — — Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 14 n N n 16 N n 18 N n 20 N n 22 N 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 3 2 2 1 — — 0 0 0 0 0 — — — 108 218 108 174 — — 139 69 34 13 6 — — — 3 2 2 2 2 1 1 1 1 1 1 0 — — 124 249 124 49 24 49 19 9 4 1 0 3 — — 3 — 2 1 1 — 0 0 0 0 0 — — — 140 — 140 224 112 — 179 89 44 17 8 — — — 3 — 2 1 1 — 1 0 0 0 0 0 0 0 155 — 155 249 124 — 24 99 49 19 9 4 1 0* 3 — 3 — 1 — 0 0 0 0 0 — — — 171 — 42 — 137 — 219 109 54 21 10 — — — Rev.1.00 Sep. 18, 2008 Page 298 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 24 n 3 — 2 2 1 1 1 1 0 0 0 0 — — N 187 — 187 74 149 74 29 14 59 23 11 5 — — n 3 — 2 — 1 — 0 0 — 0 — — — — 25 N 194 — 194 — 155 — 249 124 — 24 — — — — n 3 3 2 — 1 — — 0 0 0 0 — — — 26 N 202 101 202 — 162 — — 129 64 25 12 — — — n 3 3 2 — 1 — 1 0 0 0 0 0 — — 28 N 218 108 218 — 174 — 34 139 69 27 13 6 — — n 3 3 2 — 1 — — 0 0 0 0 — 0 — 30 N 233 116 233 — 187 — — 149 74 29 14 — 2 — Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4) Operating Frequency Pφ (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 32 n 3 3 2 2 2 2 2 2 1 1 1 1 — — N 249 124 249 99 49 24 9 4 9 3 1 0 — — n — 3 — 2 1 1 — 0 0 0 0 — — — 34 N — 132 — 105 212 105 — 169 84 33 16 — — — n — 3 — 2 1 1 1 0 0 0 0 0 — — 36 N — 140 — 112 224 112 44 179 89 35 17 8 — — n — 3 — 2 1 1 — 0 0 0 0 — — — 38 N — 147 — 118 237 118 — 189 94 37 18 — — — n — 3 — 2 1 1 1 1 0 0 0 0 0 0 40 N — 155 — 124 249 124 49 24 99 39 19 9 3 1 Rev.1.00 Sep. 18, 2008 Page 299 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Legend: —: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Note: Settings with an error of 1% or less are recommended. Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) Pφ (MHz) 4 6 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 External Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 3.6667 4.0000 4.1667 4.3333 4.6667 5.0000 5.3333 5.6667 6.0000 6.3333 6.6667 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 3666666.7 4000000.0 4166666.7 4333333.3 4666666.7 5000000.0 5333333.3 5666666.7 6000000.0 6333333.3 6666666.7 Rev.1.00 Sep. 18, 2008 Page 300 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.4 Operation in Asynchronous Mode Figure 10.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Transmit/receive data 7 or 8 bits Stop bit 1 or 2 bits One unit of transfer data (character or frame) Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 10.4.1 Data Transfer Format Table 10.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 10.5, Multiprocessor Communication Function. Rev.1.00 Sep. 18, 2008 Page 301 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 X 1 0 S 8-bit data MPB STOP 0 X 1 1 S 8-bit data MPB STOP STOP 1 X 1 0 S 7-bit data MPB STOP 1 X 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit X: Don’t care Rev.1.00 Sep. 18, 2008 Page 302 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.3. Thus the reception margin in asynchronous mode is given by formula (1) below. M= 0.5 – 1 (D – 0.5) – – (L – 0.5) F 2N N × 100% .......................... Formula (1) Where M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula below. M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode Rev.1.00 Sep. 18, 2008 Page 303 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.4. The clock must not be stopped during operation. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 10.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev.1.00 Sep. 18, 2008 Page 304 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start transmission [1] Set the clock selection in SCR. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external colck is used. [4] Set PFC of the external pin used. Set RxD input during receiving and TxD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1.* At this time, the TxD, RxD, and SCK pins can be used. The TxD pin is in a mark state during transmitting, and RxD pin is in an idle state for waiting the start bit during receiving. Clear RIE, TIE, TEIE, MPIE, TE, and RE bits in SCR to 0* Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Set data transfer format in SMR Set value in BRR Wait [1] [2] [3] No 1-bit interval elapsed? Yes Set PFC of the external pin used SCK, TxD, RxD Set SCR RIE, TIE, TEIE, and MPIE bits and set SCR TE and RE bits to 1. [4] [5] < Initialization completion> Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 10.5 Sample SCI Initialization Flowchart Rev.1.00 Sep. 18, 2008 Page 305 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.4.5 Data Transmission (Asynchronous Mode) Figure 10.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit, or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 10.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 TxD 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine One frame TXI interrupt request generated TEI interrupt request generated Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev.1.00 Sep. 18, 2008 Page 306 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes No [3] Read TEND flag in SSR No TEND = 1 Yes Break output? Yes Clear DR to 0 [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to select the TxD pin as an output port. No [4] Clear TE bit in SCR to 0; select the TxD pin as an output port with the PFC Figure 10.7 Sample Serial Transmission Flowchart Rev.1.00 Sep. 18, 2008 Page 307 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.4.6 Serial Data Reception (Asynchronous Mode) Figure 10.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 RxD 1 Idle state (mark state) RDRF FER RXI interrupt request generated 1 frame RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ERI interrupt request generated by framing error Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev.1.00 Sep. 18, 2008 Page 308 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Table 10.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.9 shows a sample flowchart for serial data reception. Table 10.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains its state before data reception. Rev.1.00 Sep. 18, 2008 Page 309 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: Set the RxD pin using the PFC. [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to Read ORER, PER, and [2] identify the error. After performing the FER flags in SSR appropriate error processing, ensure that the ORER, PER, and FER flags are Yes all cleared to 0. Reception cannot be PER FER ORER = 1 resumed if any of these flags are set to [3] 1. In the case of a framing error, a No Error processing break can be detected by reading the value of the input port corresponding to (Continued on next page) the RxD pin. Read RDRF flag in SSR No [4] [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. [5] RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 10.9 Sample Serial Reception Data Flowchart (1) Rev.1.00 Sep. 18, 2008 Page 310 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 10.9 Sample Serial Reception Data Flowchart (2) Rev.1.00 Sep. 18, 2008 Page 311 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 10.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev.1.00 Sep. 18, 2008 Page 312 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H’AA to Receiving Station A) Rev.1.00 Sep. 18, 2008 Page 313 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.5.1 Multiprocessor Serial Data Transmission Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission Read TDRE flag in SSR No [2] [1] [1] SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to select the TxD pin as an output port. [4] TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 No No Clear TE bit in SCR to 0; select the TxD pin as an output port with the PFC Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart Rev.1.00 Sep. 18, 2008 Page 314 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.5.2 Multiprocessor Serial Data Reception Figure 10.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 10.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 Data (ID1) MPB D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0 1 RxD 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated ID1 RDR data read If not this station’s ID, and RDRF flag MPIE bit is set to 1 cleared to 0 in again RXI interrupt processing routine RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station’s ID 1 RxD Start bit 0 D0 Data (ID2) D1 D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Data2 Matches this station’s ID, MPIE bit is set to 1 so reception continues, again and data is received in RXI interrupt processing routine (b) Data matches station’s ID Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev.1.00 Sep. 18, 2008 Page 315 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No [1] [1] SCI initialization: Set the RxD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] Yes [3] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Yes Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No Yes RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev.1.00 Sep. 18, 2008 Page 316 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes Clear ORER and FER flags in SSR to 0 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.1.00 Sep. 18, 2008 Page 317 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.6 Operation in Clocked Synchronous Mode Figure 10.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. Data is transferred in 8-bit units. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don’t care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don’t care * Figure 10.14 Data Format in Clocked Synchronous Communication (For LSB-First) 10.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the clock is fixed high. Note, however, that in receive mode only, the sync clock will be output until either an overrun error occurs or the RE bit is cleared to 0. Select the external clock as the clock source to perform reception operations in single character units. 10.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 10.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Rev.1.00 Sep. 18, 2008 Page 318 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or the contents of RDR. Start initialization [1] Set the clock selection in SCR. [2] Set the data transfer format in SMR. Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCR to 0* Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Set data transfer format in SMR Set value in BRR Wait No [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [1] [4] Set PFC of the external pin used. Set RxD input during receiving and TxD output during transmitting. Set SCK input/output according to contents set by the CKE1 and CKE0 bits. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1.* At this time, the TxD, RxD, and SCK pins can be used. The TxD pin is in a mark state during transmitting. When synchronous clock output (clock master) is set during receiving in clocked synchronous mode, outputting clocks from the SCK pin starts. [2] [3] 1-bit interval elapsed? Yes Set PFC of the external pin used SCK, TxD, RxD Set SCR RIE, TIE, and TEIE bits and set SCR TE and RE bits to 1. [4] [5] Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 10.15 Sample SCI Initialization Flowchart 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 10.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI) interrupt request is generated. Because the TXI interrupt routine writes the next transmit data Rev.1.00 Sep. 18, 2008 Page 319 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 10.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev.1.00 Sep. 18, 2008 Page 320 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: Set the TxD pin using the PFC. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Clear TE bit in SCR to 0 No Figure 10.17 Sample Serial Transmission Flowchart Rev.1.00 Sep. 18, 2008 Page 321 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 10.18 Example of SCI Operation in Reception Rev.1.00 Sep. 18, 2008 Page 322 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.19 shows a sample flowchart for serial data reception. Initialization Start reception [1] [1] SCI initialization: Set the RxD pin using the PFC. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. Read ORER flag in SSR Yes [2] ORER = 1 No [3] No [4] SCI status check and receive data read: Error processing Read SSR and check that the RDRF flag is set to 1, then read the receive (Continued below) data in RDR and clear the RDRF flag Read RDRF flag in SSR [4] to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. [5] No All data received? Yes Clear RE bit in SCR to 0 [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 10.19 Sample Serial Reception Flowchart Rev.1.00 Sep. 18, 2008 Page 323 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI initialization. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev.1.00 Sep. 18, 2008 Page 324 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: Set the TxD and RxD pins using the PFC. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR Yes [3] Error processing [4] ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear TE and RE bits in SCR to 0 [5] Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev.1.00 Sep. 18, 2008 Page 325 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.7 10.7.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 10.10 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 10.10 SCI Interrupt Sources Channel 2 Name ERI_2 RXI_2 TXI_2 TEI_2 3 ERI_3 RXI_3 TXI_3 TEI_3 Interrupt Source Receive error Receive data full Transmit data empty Transmission end Receive error Receive data full Transmit data empty Transmission end Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND Rev.1.00 Sep. 18, 2008 Page 326 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.8 10.8.1 Usage Notes TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating transferring of transmit data from TDR into TSR. The SCI sets the TDRE bit to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when the TDRE bit is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that the TDRE bit is set to 1. 10.8.2 Module Standby Mode Setting SCI operation can be disabled or enabled using the module standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 18, Power-Down Modes. 10.8.3 Break Detection and Processing (Asynchronous Mode Only) When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 10.8.4 Sending Break Signal (Asynchronous Mode Only) The TxD pin becomes of the I/O port general I/O pin with the I/O direction and level determined by the port data register (DR) and the port I/O register (IOR) of the pin function controller (PFC). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When the TE bit is cleared to 0, the transmission section is initialized regardless of the present transmission status. Rev.1.00 Sep. 18, 2008 Page 327 of 522 REJ09B0069-0100 Section 10 Serial Communication Interface (SCI) 10.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 10.8.6 Cautions on Clocked Synchronous External Clock Mode 1. Set TE = RE = 1 only when external clock SCK is 1. 2. Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed from 0 to 1. 3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5 to 3.5 Pφ clocks from the rising edge of the SCK input of the D7 bit in RxD, but copying to RDR is not possible. 10.8.7 Caution on Clocked Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 Pφ clocks from the rising edge of the SCK output of the D7 bit in RxD, but copying to RDR is not possible. Rev.1.00 Sep. 18, 2008 Page 328 of 522 REJ09B0069-0100 Section 11 A/D Converter Section 11 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter. The block diagram of the A/D converter is shown in figure 11.1. 11.1 Features • 10-bit resolution • Input channels SH7108: 12 channels (three independent A/D conversion modules) SH7109: 16 channels (two independent A/D conversion modules) • Conversion time: 6.7 µs (at Pφ = 20-MHz operation) or 5.4 µs (at Pφ = 25-MHz operation) per channel • Three operating modes Single mode: Single-channel A/D conversion Continuous scan mode: Repetitive A/D conversion on 1 to 4 channels in the SH7108 and on 1 to 8 channels in the SH7109 Single-cycle scan mode: Continuous A/D conversion on 1 to 4 channels in the SH7108 and on 1 to 8 channels in the SH7109 • Data registers: Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three methods for conversion start Software Conversion start trigger from multifunction timer pulse unit (MTU) or motor management timer (MMT) External trigger signal • Interrupt request: An A/D conversion end interrupt request (ADI) can be generated • Module standby mode can be set ADCMS20B_020020030700 Rev.1.00 Sep. 18, 2008 Page 329 of 522 REJ09B0069-0100 Section 11 A/D Converter Module data bus Internal data bus ADDRm ADCSR AVCC 10-bit D/A AVSS Successive approximations register ADTSR ADDRn ADCR • • • Bus interface + Pφ/4 Pφ/8 Control circuit Pφ/16 Pφ/32 ADI interrupt signal Conversion start trigger from MTU/MMT ANm • Comparator • • • • Multiplexer • Sample-andhold circuit ANn ADTRG Legend: ADCR: A/D control register ADCSR: A/D control/status register ADTSR: A/D trigger select register ADDRm to ADDRn: A/D data registers m to n Note: The register number corresponds to the channel number of the module. (Note that for SH7108: m = 8, n = 19 SH7109: m = 0, n = 15) Figure 11.1 Block Diagram of A/D Converter (For One Module) Rev.1.00 Sep. 18, 2008 Page 330 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.2 Input/Output Pins Table 11.1 summarizes the input pins used by the A/D converter. The SH7108 has three A/D conversion modules and the SH7109 two A/D conversion modules, each of which can be operated independently. The input channels are divided into four channel sets. The analog input pins that can be used differ in each product type, as shown in table 11.1. Table 11.1 Pin Configuration Product Type Module Type Common Pin Name AVCC AVSS ADTRG A/D module 0 (A/D0) AN0 AN1 AN2 AN3 AN8 AN9 AN10 AN11 A/D module 1 (A/D1) AN4 AN5 AN6 AN7 AN12 AN13 AN14 AN15 A/D module 2 (A/D2) AN16 AN17 AN18 AN19 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply and reference voltage Analog block ground and reference voltage A/D external trigger input pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 Analog input pin 16 Analog input pin 17 Analog input pin 18 Analog input pin 19 Group 0 Usable Not usable Group 1 Usable Usable Group 0 Not usable Usable Group 1 Usable Usable Group 0 SH7108 Usable Usable Usable Not usable SH7109 Usable Usable Usable Usable Note: The connected A/D module differs for each pin. The control registers of each module must be set. Rev.1.00 Sep. 18, 2008 Page 331 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.3 Register Descriptions The A/D converter has the following registers. For details on register addresses, refer to section 19, List of Registers. • A/D data register 0 (H/L) (ADDR0) • A/D data register 1 (H/L) (ADDR1) • A/D data register 2 (H/L) (ADDR2) • A/D data register 3 (H/L) (ADDR3) • A/D data register 4 (H/L) (ADDR4) • A/D data register 5 (H/L) (ADDR5) • A/D data register 6 (H/L) (ADDR6) • A/D data register 7 (H/L) (ADDR7) • A/D data register 8 (H/L) (ADDR8) • A/D data register 9 (H/L) (ADDR9) • A/D data register 10 (H/L) (ADDR10) • A/D data register 11 (H/L) (ADDR11) • A/D data register 12 (H/L) (ADDR12) • A/D data register 13 (H/L) (ADDR13) • A/D data register 14 (H/L) (ADDR14) • A/D data register 15 (H/L) (ADDR15) • A/D data register 16 (H/L) (ADDR16) • A/D data register 17 (H/L) (ADDR17) • A/D data register 18 (H/L) (ADDR18) • A/D data register 19 (H/L) (ADDR19) • A/D control/status register_0 (ADCSR_0) • A/D control/status register_1 (ADCSR_1) • A/D control/status register_2 (ADCSR_2) • A/D control register_0 (ADCR_0) • A/D control register_1 (ADCR_1) • A/D control register_2 (ADCR_2) • A/D trigger select register (ADTSR) Rev.1.00 Sep. 18, 2008 Page 332 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.3.1 A/D Data Registers 0 to 19 (ADDR0 to ADDR19) ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is stored in ADDR4.) The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before the lower byte, or read in word unit. The initial value of ADDR is H'0000. Rev.1.00 Sep. 18, 2008 Page 333 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.3.2 A/D Control/Status Registers_0 to 2 (ADCSR_0 to ADCSR_2) ADCSR for each module controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W Description A status flag that indicates the end of A/D conversion. [Setting conditions] • • When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 R/(W)* A/D End Flag [Clearing condition] • 6 ADIE 0 R/W A/D Interrupt Enable The A/D conversion end interrupt (ADI) request is enabled when this bit is set to 1. When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. 5 4 ADM1 ADM0 0 0 R/W R/W A/D Mode 1 and 0 Select the A/D conversion mode. 00: Single mode 01: 4-channel scan mode 10: 8-channel scan mode 11: Setting prohibited When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. For A/D2, the ADM1 bit must be cleared to 0. 3 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1. 2 1 0 Note: CH2 CH1 CH0 * 0 0 0 R/W R/W R/W Channel Select 2 to 0 Select analog input channels. See table 11.2. When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. Only 0 can be written to clear the flag. Rev.1.00 Sep. 18, 2008 Page 334 of 522 REJ09B0069-0100 Section 11 A/D Converter Table 11.2 Channel Select List Analog Input Channels Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 A/D0 AN0 AN1 AN2 AN3 AN8 AN9 AN10 AN11 Single Mode A/D1 AN4 AN5 AN6 AN7 AN12 AN13 AN14 AN15 A/D2 AN16 AN17 AN18 AN19 Setting prohibited A/D0 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 4-Channel Scan Mode*2 A/D1 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 A/D2 AN16 AN16, AN17 AN16 to AN18 AN16 to AN19 Setting prohibited Analog Input Channels Bit 2 CH2 0* 1 Bit 1 CH1 0 Bit 0 CH0 0 1 A/D0 AN0, AN8 8-Channel Scan Mode (Only in SH7109)*2 A/D1 AN4, AN12 AN4, AN5, AN12, AN13 AN4 to AN6, AN12 to AN14 AN4 to AN7, AN12 to AN15 AN0, AN1, AN8, AN9 AN0 to AN2, AN8 to AN10 AN0 to AN3, AN8 to AN11 1 0 1 Notes: 1. In 8-channel scan mode, the CH2 bit must be cleared to 0. 2. Continuous scan mode or single-cycle scan mode can be selected with the ADCS bit. 11.3.3 A/D Control Registers_0 to 2 (ADCR_0 to ADCR_2) ADCR for each module controls A/D conversion started by an external trigger signal and selects the operating clock. Rev.1.00 Sep. 18, 2008 Page 335 of 522 REJ09B0069-0100 Section 11 A/D Converter Bit 7 Bit Name TRGE Initial Value 0 R/W R/W Description Trigger Enable Enables or disables triggering of A/D conversion by ADTRG, an MTU trigger, or an MMT trigger. 0: A/D conversion triggering is disabled 1: A/D conversion triggering is enabled 6 5 CKS1 CKS0 0 0 R/W R/W Clock Select 0 and 1 Select the A/D conversion time. 00: Pφ/32 01: Pφ/16 10: Pφ/8 11: Pφ/4 When changing the A/D conversion time, first clear the ADST bit in the A/D control registers (ADCRs) to 0. CKS[1,0] = b'11 can be set while Pφ ≤ 25 MHz. 4 ADST 0 R/W A/D Start Starts or stops A/D conversion. When this bit is set to 1, A/D conversion is started. When this bit is cleared to 0, A/D conversion is stopped and the A/D converter enters the idle state. In single or single-cycle scan mode, this bit is automatically cleared to 0 when A/D conversion ends on the selected single channel. In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode, hardware standby mode, or module standby mode. 3 ADCS 0 R/W A/D Continuous Scan Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. 0: Single-cycle scan 1: Continuous scan When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. 2 to 0 — All 1 R Reserved These bits are always read as 1. The write value should always be 1. Rev.1.00 Sep. 18, 2008 Page 336 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.3.4 A/D Trigger Select Register (ADTSR) ADTSR enables an A/D conversion started by an external trigger signal. Bit 7, 6 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 TRG2S1 TRG2S0 0 0 R/W R/W AD Trigger 2 Select 1 and 0 Enable the start of A/D conversion by A/D2 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bits in the A/D control registers (ADCRs) to 0. 3 2 TRG1S1 TRG1S0 0 0 R/W R/W AD Trigger 1 Select 1 and 0 Enable the start of A/D conversion by A/D1 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bits in the A/D control registers (ADCRs) to 0. Rev.1.00 Sep. 18, 2008 Page 337 of 522 REJ09B0069-0100 Section 11 A/D Converter Bit 1 0 Bit Name TRG0S1 TRG0S0 Initial Value 0 0 R/W R/W R/W Description AD Trigger 0 Select 1 and 0 Enable the start of A/D conversion by A/D0 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bits in the A/D control registers (ADCRs) to 0. 11.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. The ADST bit can be set at the same time when the operating mode is changed. 11.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU, MMT, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. Rev.1.00 Sep. 18, 2008 Page 338 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.4.2 Continuous Scan Mode In continuous scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum in the SH7108 and eight channels maximum in the SH7109). The operations are as follows. 1. When the ADST bit in ADCR is set to 1 by software, MTU, MMT, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN7). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. Rev.1.00 Sep. 18, 2008 Page 339 of 522 REJ09B0069-0100 Continuous A/D conversion Set*1 Clear*1 Section 11 A/D Converter ADST Clear*1 A/D conversion time Idle A/D conversion A/D conversion ADF Channel 8 (AN8) operation Idle Idle A/D conversion Idle Rev.1.00 Sep. 18, 2008 Page 340 of 522 REJ09B0069-0100 Idle A/D conversion *2 Channel 9 (AN9) operation Idle A/D conversion Idle Channel 10 (AN10) operation Idle Transfer A/D conversion result Channel 11 (AN11) operation ADDR8 A/D conversion result ADDR9 A/D conversion result ADDR10 A/D conversion result Figure 11.2 Example of Continuous Scan Mode Operation (when Three Channels, AN8 to AN10, Are Selected) ADDR11 Notes: 1.↓ means instruction execution by software 2.Data during A/D conversion are ignored. Section 11 A/D Converter 11.4.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (four channels maximum in the SH7108 and eight channels maximum in the SH7109). Operations are as follows. 1. When the ADST bit in ADCR is set to 1 by software, MTU, MMT, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN7). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. 4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. Rev.1.00 Sep. 18, 2008 Page 341 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.4.4 Input Sampling and A/D Conversion Time The A/D converter has an on-chip sample-and-hold circuit for each module. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCR is set to 1, then starts conversion. Figure 11.3 shows the A/D conversion timing. Table 11.3 shows the A/D conversion time. As indicated in figure 11.3, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total conversion time therefore varies within the ranges indicated in table 11.3. In scan mode, the values given in table 11.3 apply to the first conversion time. The values given in table 11.4 apply to the second and subsequent conversions. A/D conversion time (tCONV) Analog input A/D conversion start sampling time(tSPL) delay time(tD) Write cycle A/D synchronization time (Up to (3 states) 59 states) Pφ Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle state Sample-and-hold A/D conversion ADF End of A/D conversion Figure 11.3 A/D Conversion Timing Rev.1.00 Sep. 18, 2008 Page 342 of 522 REJ09B0069-0100 Section 11 A/D Converter Table 11.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. Typ. Max. 31 — — 256 62 — 1055 CKS0 = 1 Min. Typ. Max. 15 — 515 — 128 — 30 — 530 CKS0 = 0 Min. Typ. Max. 7 — 259 — 64 — 14 — 266 CKS1 = 1 CKS0 = 1 Min. Typ. Max. 3 — 131 — 32 — 6 — 134 1024 — Note: All values represent the number of states for Pφ. Table 11.4 A/D Conversion Time (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 1024 (Fixed) 512 (Fixed) 256 (Fixed) 128 (Fixed) 11.4.5 A/D Converter Activation by MTU or MMT The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU or MMT. To activate the A/D converter by the MTU or MMT, set the A/D trigger select register (ADTSR). After this register setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D conversion request from the interval timer of the MTU or MMT occurs. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 11.4.6 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 00 or 01 in ADTSR, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 11.4 shows the timing. Rev.1.00 Sep. 18, 2008 Page 343 of 522 REJ09B0069-0100 Section 11 A/D Converter CK External trigger signal ADST A/D conversion Figure 11.4 External Trigger Input Timing 11.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) upon the completion of A/D conversion. ADI interrupt requests are enabled when the ADIE bit is set to 1 while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. Table 11.5 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF Rev.1.00 Sep. 18, 2008 Page 344 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.6 Definitions of A/D Conversion Accuracy This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 11.5). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 11.6). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 11.6). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 11.6). • Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev.1.00 Sep. 18, 2008 Page 345 of 522 REJ09B0069-0100 Section 11 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 11.5 Definitions of A/D Conversion Accuracy Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 11.6 Definitions of A/D Conversion Accuracy Rev.1.00 Sep. 18, 2008 Page 346 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.7 11.7.1 Usage Notes Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the module standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 18, Power-Down Modes. 11.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 kΩ or less than 3 kΩ. (For details, see table 11.6.) This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance is 1 kΩ or exceeds 3 kΩ, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/μs or greater) (see figure 11.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 11.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e, acting as antennas). This LSI Sensor output impedance of up to 3 kΩ or to 3 kΩ Sensor input Low-pass filter C to 0.1 μF Cin = 15 pF 20 pF A/D converter equivalent circuit 10 kΩ Figure 11.7 Example of Analog Input Circuit Rev.1.00 Sep. 18, 2008 Page 347 of 522 REJ09B0069-0100 Section 11 A/D Converter 11.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ VAN ≤ AVcc. • Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 11.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN19), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 11.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN19), between AVcc and AVss, as shown in figure 11.8. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN19 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN19) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. Rev.1.00 Sep. 18, 2008 Page 348 of 522 REJ09B0069-0100 Section 11 A/D Converter AVCC Rin∗2 ∗1 0.1 mF 100 Ω AN0 to AN19 AVSS Notes: Values are reference values. 1 10 μF 0.01 μF 2 Rin: Input impedance Figure 11.8 Example of Analog Input Protection Circuit Table 11.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min. — — — Max. 20 3 1 Unit. pF kΩ kΩ ≤ 20 MHz 20 to 25 MHz Measurement Condition 10 kΩ AN0 to AN19 To A/D converter 20 pF Note: Values are reference values. Figure 11.9 Analog Input Pin Equivalent Circuit Rev.1.00 Sep. 18, 2008 Page 349 of 522 REJ09B0069-0100 Section 11 A/D Converter Rev.1.00 Sep. 18, 2008 Page 350 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) Section 12 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 12.1 Features • Four types of counter input clock can be selected One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) can be selected independently for each channel. • Interrupt sources A compare match interrupt can be requested independently for each channel. • Module standby mode can be set Figure 12.1 shows a block diagram of the CMT. CMI0 Pφ/32 Pφ/512 Pφ/8 Pφ/128 CMI1 Pφ/32 Pφ/512 Pφ/8 Pφ/128 Control circuit Clock selection Control circuit Clock selection Comparator CMCOR0 CMCSR0 CMCOR1 CMCSR1 CMCNT0 Comparator CMCNT1 CMSTR Module bus CMT Legend: CMSTR: CMCSR: CMCOR: CMCNT: CMI: Bus interface Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 12.1 CMT Block Diagram TIMCMT0A_010020030200 Rev.1.00 Sep. 18, 2008 Page 351 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.2 Register Descriptions The CMT has the following registers. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Compare match timer start register (CMSTR) • Compare match timer control/status register_0 (CMCSR_0) • Compare match timer counter_0 (CMCNT_0) • Compare match timer constant register_0 (CMCOR_0) • Compare match timer control/status register_1 (CMCSR_1) • Compare match timer counter_1 (CMCNT_1) • Compare match timer constant register_1 (CMCOR_1) 12.2.1 Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Selects whether to operate or halt the compare match timer counter_1. 0: CMCNT_1 count operation halted 1: CMCNT_1 count operation 0 STR0 0 R/W Count Start 0 Selects whether to operate or halt the compare match timer counter_0. 0: CMCNT_0 count operation halted 1: CMCNT_0 count operation 15 to 2 ⎯ Rev.1.00 Sep. 18, 2008 Page 352 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.2.2 Compare Match Timer Control/Status Registers_0 and 1 (CMCSR_0, CMCSR_1) CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables or disables interrupts, and sets the clock used for incrementation. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag Indicates whether or not the CMCNT and CMCOR values have matched. 0: CMCNT and CMCOR values have not matched [Clearing condition] • Write 0 to CMF after reading 1 from it 1: CMCNT and CMCOR values have matched 6 CMIE 0 R/W Compare Match Interrupt Enable Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Select the clock input to CMCNT among the four internal clocks obtained by dividing the peripheral clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT begins incrementing with the clock selected by the CKS1 and CKS0 bits. 00: Pφ/8 01: Pφ/32 10: Pφ/128 11: Pφ/512 Note: * Only 0 can be written for flag clearing. 15 to 8 ⎯ Rev.1.00 Sep. 18, 2008 Page 353 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.2.3 Compare Match Timer Counters_0 and 1 (CMCNT_0, CMCNT_1) CMCNT is a 16-bit register used as an up-counter for generating interrupt requests. CMCNT is initialized to H'0000. 12.2.4 Compare Match Timer Constant Registers_0 and 1 (CMCOR_0, CMCOR_1) CMCOR is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is initialized to H'FFFF. 12.3 12.3.1 Operation Cyclic Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag in CMCSR is set to 1. If the CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 12.2 shows the compare match counter operation. CMCNT value Counter cleared by CMCOR compare match CMCOR H'0000 Time Figure 12.2 Counter Operation Rev.1.00 Sep. 18, 2008 Page 354 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.3.2 CMCNT Count Timing One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing. Pφ Internal clock CMCNT input clock CMCNT N-1 N N+1 Figure 12.3 Count Timing 12.4 12.4.1 Interrupts Interrupt Sources The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when the interrupt request flag (CMF) is set to 1 and interrupt enable bit (CMIE) has also been set to 1. When activating CPU interrupts by an interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for details. 12.4.2 Compare Match Flag Set Timing The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and CMCNT match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT matching count value is updated). Consequently, after CMCOR and CMCNT match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 12.4 shows the CMF bit set timing. Rev.1.00 Sep. 18, 2008 Page 355 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) Pφ CMCNT input clock CMCNT CMCOR Compare match signal CMF CMI N N 0 Figure 12.4 CMF Set Timing 12.4.3 Compare Match Flag Clear Timing The CMF bit in CMCSR is cleared by writing 0 to it after reading 1. Figure 12.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 Pφ CMF Figure 12.5 Timing of CMF Clear by CPU Rev.1.00 Sep. 18, 2008 Page 356 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.5 12.5.1 Usage Notes Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 12.6 shows the timing. CMCNT write cycle T1 T2 Pφ Address Internal write signal Compare match signal CMCNT N H' 0000 CMCNT Figure 12.6 CMCNT Write and Compare Match Contention Rev.1.00 Sep. 18, 2008 Page 357 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 12.7 shows the timing. CMCNT write cycle T1 T2 Pφ Address Internal write signal CMCNT input clock CMCNT N M CMCNT write data CMCNT Figure 12.7 CMCNT Word Write and Increment Contention Rev.1.00 Sep. 18, 2008 Page 358 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) 12.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 12.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 T2 Pφ Address Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X CMCNTH Figure 12.8 CMCNT Byte Write and Increment Contention Rev.1.00 Sep. 18, 2008 Page 359 of 522 REJ09B0069-0100 Section 12 Compare Match Timer (CMT) Rev.1.00 Sep. 18, 2008 Page 360 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) Section 13 Motor Management Timer (MMT) The motor management timer (MMT) can output six-phase PWM waveforms with non-overlap times. Figure 13.1 shows a block diagram of the MMT. 13.1 Features • Six-phase PWM waveform output of the triangular wave comparison type with non-overlap times • Non-overlap times generated by timer dead time counters • Toggle output synchronized with PWM period • Counter clearing on an external signal • Generation of a trigger for the start of conversion by the A/D converter is available • Output-off functions • PWM output halted by an external signal • PWM output halted when oscillation stops • Module standby mode can be set PWMMMT1A_020020030700 Rev.1.00 Sep. 18, 2008 Page 361 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) TPDR compare match interrupt 2Td compare match interrupt TPBR MMT_TDDR ×2 Comparators TDCNT0 TPDR Comparators PCIO +2Td Control circuit Pφ to Pφ/1024 PUOA PUOB PVOA PVOB PWOA PWOB A/D start-conversion request signal MMT_TCNT Magnitude comparators TGRWU TGRWD MMT_TMDR TCNR TGRUU TGRUD TGRVU TGRVD +2Td +2Td +2Td +Td +Td +Td TGRW TGRU TGRV TBRU TBRV TBRW MMT_TSR Legend: TGR: TBR: MMT_TDDR: TPDR: TPBR: Td: Timer general register Timer buffer register Timer dead time data register Timer period data register Timer period buffer register Dead time MMT_TMDR: TCNR: MMT_TSR: MMT_TCNT: TDCNT: Pφ: Timer mode register Timer control register Timer status register Timer counter Timer dead time counter Peripheral clock Figure 13.1 Block Diagram of MMT Rev.1.00 Sep. 18, 2008 Page 362 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the MMT. Table 13.1 Pin Configuration Name PCIO I/O I/O Function Counter clear signal input when set as an input by PAIORL; toggle output in synchronization with the PWM cycle when set as an output by PAIORL. PWMU phase output (positive phase) PWMU phase output (negative phase) PWMV phase output (positive phase) PWMV phase output (negative phase) PWMW phase output (positive phase) PWMW phase output (negative phase) PUOA PUOB PVOA PVOB PWOA PWOB Output Output Output Output Output Output 13.3 Register Descriptions The MMT has the following registers. For details on register addresses and the register states during each processing, refer to section 19, List of Registers. • Timer mode register (MMT_TMDR*) • Timer control register (TCNR) • Timer status register (MMT_TSR*) • Timer counter (MMT_TCNT*) • Timer buffer register U (TBRU) • Timer buffer register V (TBRV) • Timer buffer register W (TBRW) • Timer general register UU (TGRUU) • Timer general register VU (TGRVU) • Timer general register WU (TGRWU) • Timer general register U (TGRU) • Timer general register V (TGRV) • Timer general register W (TGRW) • Timer general register UD (TGRUD) • Timer general register VD (TGRVD) Rev.1.00 Sep. 18, 2008 Page 363 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) • Timer general register WD (TGRWD) • Timer dead time counter 0 (TDCNT0) • Timer dead time counter 1 (TDCNT1) • Timer dead time counter 2 (TDCNT2) • Timer dead time counter 3 (TDCNT3) • Timer dead time counter 4 (TDCNT4) • Timer dead time counter 5 (TDCNT5) • Timer dead time data register (MMT_TDDR*) • Timer period buffer register (TPBR) • Timer period data register (TPDR) Note: * In this section, the names of these registers are further abbreviated to TMDR, TSR, TCNT, and TDDR hereafter. Rev.1.00 Sep. 18, 2008 Page 364 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.3.1 Timer Mode Register (MMT_TMDR) MMT_TMDR sets the operating mode and selects the PWM output level. (In this section, the name of this register is abbreviated to TMDR hereafter.) Bit 7 Bit Name ⎯ Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Select the clock input to MMT. 000: Pφ 001: Pφ/4 010: Pφ/16 011: Pφ/64 100: Pφ/256 101: Pφ/1024 11x: Setting prohibited [Legend] x: Don’t care. 3 OLSN 0 R/W Output Level Select N Selects the negative phase output level in the operating modes. 0: Active level is low 1: Active level is high 2 OLSP 0 R/W Output Level Select P Selects the positive phase output level in the operating modes. 0: Active level is low 1: Active level is high 1 0 MD1 MD0 0 0 R/W R/W Mode 3 to 0 Set the timer operating mode. 00: Operation halted 01: Operating mode 1 (Transfer at TCNT = TPDR) 10: Operating mode 2 (Transfer at TCNT = TDDR × 2) 11: Operating mode 3 (Transfer at TCNT = TPDR or TCNT = TDDR × 2) Rev.1.00 Sep. 18, 2008 Page 365 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.3.2 Timer Control Register (TCNR) TCNR controls the enabling or disabling of interrupt requests, selects the enabling or disabling of register access, selects counter operation or halting, and controls the enabling or disabling of toggle output synchronized with the PWM period. Bit 7 Bit Name TTGE Initial Value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables the generation of A/D conversion start requests when the TGFN or TGFM bit in the timer status register (TSR) is set. 0: Disables the request 1: Enables the request Timer Counter Start Selects operation or halting of the timer counter (TCNT) and timer dead time counter (TDCNT). 0: TCNT and TDCNT operation is halted 1: TCNT and TDCNT perform count operations Register Protects Enables or disables the reading of registers other than TSR, and enables or disables the writing to registers other than TBRU to TBRW, TPBR, and TSR. Writes to TCNR itself are also disabled. Note that reset input is necessary in order to write to these registers again. 0: Register access enabled 1: Register access disabled Reserved These bits are always read as 0. The write value should always be 0. TGR Interrupt Enable N Enables or disables interrupt requests by the TGFN bit when the TGFN bit is set to 1 in TSR. 0: Interrupt requests by TGFN bit disabled 1: Interrupt requests by TGFN bit enabled TGR Interrupt Enable M Enables or disables interrupt requests by the TGFM bit when the TGFM bit is set to 1 in TSR. 0: Interrupt requests by TGFM bit disabled 1: Interrupt requests by TGFM bit enabled 6 CST 0 R/W 5 RPRO 0 R/W 4 to 2 ⎯ All 0 R 1 TGIEN 0 R/W 0 TGIEM 0 R/W Rev.1.00 Sep. 18, 2008 Page 366 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.3.3 Timer Status Register (MMT_TSR) MMT_TSR holds status flags. (In this section, the name of this register is abbreviated to TSR hereafter.) Bit 7 Bit Name TCFD Initial Value 1 R/W R Description Count Direction Flag Status flag that indicates the count direction of the TCNT counter. 0: TCNT counts down 1: TCNT counts up 6 to 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGFN 0 R/(W)* Output Compare Flag N Status flag that indicates a compare match between TCNT and 2Td (Td: TDDR value). [Setting condition] • When TCNT = 2Td [Clearing condition] • 0 TGFM 0 R/(W)* When 0 is written to TGFN after reading TGFN = 1 Output Compare Flag M Status flag that indicates a compare match between TCNT and TPDR. [Setting condition] • When TCNT = TPDR [Clearing condition] • Note: * When 0 is written to TGFM after reading TGFM = 1 Only 0 can be written for flag clearing. Rev.1.00 Sep. 18, 2008 Page 367 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.3.4 Timer Counter (MMT_TCNT) MMT_TCNT is a 16-bit counter. The initial value is H'0000. Only 16-bit access can be used on MMT_TCNT; 8-bit access is not possible. (In this section, the name of this register is abbreviated to TCNT hereafter.) 13.3.5 Timer Buffer Registers (TBR) TBR function as 16-bit buffer registers. The MMT has three TBR registers; TBRU, TBRV, and TBRW, each of which has two addresses; a buffer operation address (shown first) and a free operation address (shown second). A value written to the buffer operation address is transferred to the corresponding TGR at the timing set in bits MD1 and MD0 in the timer mode register (TMDR). A value set in the free operation address is transferred to the corresponding TGR immediately. The initial value of TBR is H'FFFF. Only 16-bit access can be used on the TBR registers; 8-bit access is not possible. 13.3.6 Timer General Registers (TGR) TGR function as 16-bit compare registers. The MMT has nine TGR registers, that are compared with the TCNT counter in the operating modes. The initial value of TGR is H'FFFF. Only 16-bit access can be used on the TGR registers; 8-bit access is not possible. 13.3.7 Timer Dead Time Counter (TDCNT) TDCNT is a 16-bit read-only counter. The initial value of TDCNT is H'0000. Only 16-bit access can be used on TDCNT; 8-bit access is not possible. 13.3.8 Timer Dead Time Data Register (MMT_TDDR) MMT_TDDR is a 16-bit register that sets the positive phase and negative phase non-overlap time (dead time). The initial value of MMT_TDDR is H'FFFF. Only 16-bit access can be used on MMT_TDDR; 8-bit access is not possible. (In this section, the name of this register is further abbreviated to TDDR hereafter.) 13.3.9 Timer Period Buffer Register (TPBR) TPBR is a 16-bit register that functions as a buffer register for TPDR. A value of 1/2 the PWM carrier period should be set as the TPBR value. The TPBR value is transferred to TPDR at the transfer timing set in TMDR. The initial value of TPBR is H'FFFF. Only 16-bit access can be used on TPBR; 8-bit access is not possible. Rev.1.00 Sep. 18, 2008 Page 368 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.3.10 Timer Period Data Register (TPDR) TPDR functions as a 16-bit compare register. In the operating modes, the TPDR value is constantly compared with the TCNT counter value, and when they match, the TCNT counter changes its count direction from up to down. The initial value of TPDR is H'FFFF. Only 16-bit access can be used on TPDR; 8-bit access is not possible. 13.4 Operation When the operating mode is selected, a three-phase PWM waveform is output with a non-overlap relationship between the positive and negative phases. The PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are PWM output pins, the PCIO pin (when set to output) functions as a toggle output synchronized with the PWM waveform, and the PCI0 pin (when set to input) functions as the counter clear signal input. The TCNT counter performs up- and down-count operations, whereas the TDCNT counters perform up-count operations. Rev.1.00 Sep. 18, 2008 Page 369 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.4.1 Sample Setting Procedure An example of the operating mode setting procedure is shown in figure 13.2. Clear the CST bit to 0 in the timer control register (TCNR) to halt timer counter operation. Make the operating mode setting while TCNT is halted. Set 2Td (Td: dead time) in TCNT. Halt count operation Set TCNT Set dead time carrier period Set dead time Td in the dead time data register (TDDR), set 1/2 the carrier period in the timer period buffer register (TPBR), and set {TPBR value + 2Td} in the timer period data register (TPDR). Set the output PWM duty cycle {PWM duty cycle initial value – Td} in the free operation addresses of the buffer registers (TBRU, TBRV, TBRW). Set TBR Set PWM output level Set the PWM output level with bits OLSN and OLSP in the timer mode register (TMDR). Set operating mode Set the operating mode in the timer mode register (TMDR). The PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are output pins. Set the external pin functions with the pin function controller (PFC). Set external pin functions Start count operation Set the CST bit to 1 in TCNR to start the count operation. Figure 13.2 Sample Operating Mode Setting Procedure Rev.1.00 Sep. 18, 2008 Page 370 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (1) Count Operation Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter when the CST bit in TCNR is cleared to 0. When the CST bit is set to 1, TCNT counts up to {the value set in TPBR + 2Td}, and then starts counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way. TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD, TGRWD, and 2Td when counting down. TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values. TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of a positive phase compare match output when TCNT is counting down. When they become equal to TDDR they are cleared to 0 and halt. TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of a negative phase compare match output when TCNT is counting up. When they match TDDR they are cleared to 0 and halt. TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No count operation is performed when the TDDR value is 0. Figure 13.3 shows an example of the TCNT count operation. H'FFFF 2Td TPDR TCNT TGRUU TGRU TGRUD Td Td 1/2 period (TPBR) 2Td H'0000 2Td Td Figure 13.3 Example of TCNT Count Operation Rev.1.00 Sep. 18, 2008 Page 371 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (2) Register Operation In the operating modes, four buffer registers and ten compare registers are used. The registers that are constantly compared with the TCNT counter are TGRU, TGRV, and TGRW. In addition, TGRUU, TGRVU, TGRWU, and TPDR are compared with TCNT when TCNT is counting up, and TGRUD, TGRVD, TGRWD are compared with TCNT when TCNT is counting down. The buffer register for TPDR is TPBR; the buffer register for TGRUU, TGRU, and TGRUD is TBRU; the buffer register for TGRVU, TGRV, and TGRVD is TBRV; and the buffer register for TGRWU, TGRW, and TGRWD is TBRW. To change compare register data, the new data should be written to the corresponding buffer register. The buffer registers can be read from or written to at all times. Data written to the buffer operation addresses for TPBR and TBRU to TBRW is transferred at the timing specified by bits MD1 and MD0 in the timer mode register (TMDR). Data written to the free operation addresses for TBRU to TBRW is transferred immediately. After data transfer is completed, the relationship between the compare registers and buffer registers is as follows: TGRU (TGRV, TGRW) value = TBRU (TBRV, TBRW) value + Td (Td: value set in TDDR) TGRUU (TGRVU, TGRWU) value = TBRU (TBRV, TBRW) value + 2Td TGRUD (TGRVD, TGRWD) value = TBRU (TBRV, TBRW) value TPDR value = TPBR value + 2Td The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td. Figure 13.4 shows examples of counter and register operations. Rev.1.00 Sep. 18, 2008 Page 372 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 2 + TGRUU TGRVU TGRWU (TBR + 2Td) Compared during up-count TDDR (Td) TBRU TBRV TBRW (TBR) + TGRU TGRV TGRW (TBR + Td) TCNT Constantly compared TGRUD TGRVD TGRWD (TBR) Compared during down-count (1/2 period + 2Td) TPBR (1/2 period) + TPDR Compared during up-count TCNT TDDR (Td) 2 (2Td) Compared during down-count compare Down-count up-count match compare Up-count match down-count TDDR (Td) Up-count compare match halt TDCNT Figure 13.4 Examples of Counter and Register Operations (3) Initial Settings In the operating modes, there are five registers that require initialization. Make the following register settings before setting the operating mode with bits MD1 and MD0 in the timer mode register (TMDR). Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set {TPBR value + 2Td} in the timer period data register (TPDR). Set {PWM duty initial value – Td} in the free write operation addresses for TBRU to TBRW. Rev.1.00 Sep. 18, 2008 Page 373 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF – 2Td, and the value of TPBR should always be set in the range H'0000 to H'FFFF – 4Td. (4) PWM Output Active Level Setting In the operating modes, the active level of PWM pulses is set with bits OLSN and OLSP in the timer mode register (TMDR). The output level can be set for the three positive phases and the three negative phases of six-phase output. The operating mode must be exited before setting or changing the output level. (5) Dead Time Setting In the operating modes, PWM pulses are output with a non-overlap relationship between the positive and negative phases. This non-overlap time is known as the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The dead time generation waveform is generated by comparing the value set in TDDR with the timer dead time counters (TDCNT) for each phase. The operating mode must be exited before changing the contents of TDDR. (6) PWM Period Setting In the operating modes, 1/2 the PWM pulse period is set in TPBR. The TPBR value should always be set in the range H'0000 to H'FFFF – 4Td. The value set in TPBR is transferred to TPDR at the timing selected with bits MD1 and MD0 in the timer mode register (TMDR). After the transfer, the value in TPDR is {TPBR value + 2Td}. The new PWM period is effective from the next period when data is updated at the TCNT counter peak, and from the same period when data is updated at the trough. (7) Register Updating In the operating modes, buffer registers are used to update compare register data. Update data can be written to a buffer register at all times. The buffer register value is transferred to the compare register at the timing set by bits MD1 and MD0 in the timer mode register (TMDR) (except in the case of a write to the free operation address for TBRU to TBRW, in which case the value is transferred to the corresponding compare register immediately). (8) Initial Output in Operating Modes The initial output in the operating modes is determined by the initial values of TBRU to TBRW. Table 13.2 shows the relationship between the initial value of TBRU to TBRW and the initial output. Rev.1.00 Sep. 18, 2008 Page 374 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) Table 13.2 Initial Values of TBRU to TBRW and Initial Output Initial Output Initial Value of TBRU to TBRW TBR = H'0000 H'0000 < TBR ≤ Td Td < TBR ≤ H'FFFF – 2Td OLSP = 1, OLSN = 1 Positive phase: 1 Negative phase: 0 Positive phase: 0 Negative phase: 0 Positive phase: 0 Negative phase: 1 OLSP = 0, OLSN = 0 Positive phase: 0 Negative phase: 1 Positive phase: 1 Negative phase: 1 Positive phase: 1 Negative phase: 0 (9) PWM Output Generation in Operating Modes In the operating modes, a three-phase PWM waveform is output with a non-overlap relationship between the positive and negative phases. This non-overlap time is called the dead time. The PWM waveform is generated from an output generation waveform generated by ANDing the compare output waveform with the dead time generation waveform. Waveform generation for one phase (the U-phase) is shown here. The V-phase and W-phase waveforms are generated in the same way. (a) Compare Output Waveform The compare output waveform is generated by comparing the values in TCNT and TGR. For compare output waveform U phase A (CMOUA), 0 is output if TGRUU > TCNT in the T1 interval (when TCNT is counting up), and 1 is output if TGRUU ≤ TCNT. In the T2 interval (when TCNT is counting down), 0 is output if TGRU > TCNT, and 1 is output if TGRU ≤ TCNT. For compare output waveform U phase B (CMOUB), 1 is output if TGRU > TCNT in the T1 interval, and 0 is output if TGRU ≤ TCNT. In the T2 interval, 1 is output if TGRUD > TCNT, and 0 is output if TGRUD ≤ TCNT. (b) Dead Time Generation Waveform For dead time generation waveform U phases A (DTGUA) and B (DTGUB), 1 is output as the initial value. TDCNT0 starts counting at the falling edge of CMOUA. DTGUA outputs 0 if TDCNT0 is counting, and 1 otherwise. Rev.1.00 Sep. 18, 2008 Page 375 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) TDCNT1 starts counting at the falling edge of CMOUB. DTGUB outputs 0 if TDCNT1 is counting, and 1 otherwise. (c) Output Generation Waveform Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and DTGUB, and output generation waveform U phase B (OGUB) is generated by ANDing CMOUB and DTGUA. (d) PWM Waveform The PWM waveform is generated by converting the output generation waveform to the output level set in bits OLSN and OLSP in the timer mode register (TMDR). Figure 13.5 shows an example of PWM waveform generation (operating mode 3, OLSN = 1, OLSP = 1). When writing to free operation address TPDR 2Td Compare output waveform Dead time generation waveform Output generation waveform PWM waveform Figure 13.5 Example of PWM Waveform Generation (10) 0% to 100% Duty Cycle Output In the operating modes, PWM waveforms with any duty cycle from 0% to 100% can be output. The output PWM duty cycle is set using the buffer registers (TBRU to TBRW). 100% duty cycle output is performed when the buffer register (TBRU to TBRW) value is set to H'0000. The waveform in this case has positive phase in the 100% on state. 0% duty cycle output Rev.1.00 Sep. 18, 2008 Page 376 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) is performed when a value greater than the TPDR value is set as the buffer register (TBRU to TBRW) value. The waveform in this case has positive phase in the 100% off state. (11) External Counter Clear Function In the operating modes, the TCNT counter can be cleared from an external source. When using the counter clearing function, the port A I/O register L (PAIORL) should be used to set the PCIO pin as an input. On the falling edge of the PCIO pin (when set to input), the TCNT counter is reset to 2Td (the initial setting). It then counts up until it reaches the value in TPDR, then starts counting down. When the count returns to 2Td, TCNT starts counting up again, and this sequence is repeated. Figure 13.6 shows the example for counter clearing. TPDR TCNT 2Td H'0000 PCIO pin (counter clear input) Figure 13.6 Example of TCNT Counter Clearing (12) Toggle Output Synchronized with PWM Cycle In the operating modes, output can be toggled synchronously with the PWM carrier cycle. When outputting the PWM cycle, the pin function controller (PFC) should be used to set the PCIO pin as an output (when set to output). An example of the toggle output waveform is shown in figure 13.7. PWM cycle output is toggled according to the TCNT count direction. The toggle output pin is PCIO (when set to output). The PCIO pin outputs 1 when TCNT is counting up, and 0 when counting down. Rev.1.00 Sep. 18, 2008 Page 377 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) TPDR TCNT 2Td H'0000 PCIO pin (toggle output) Figure 13.7 Example of Toggle Output Waveform Synchronized with PWM Cycle (13) Settings for A/D Conversion Start Requests Requests to start A/D conversion can be set up to be issued when TCNT matches TPDR or 2Td. When the start requests are set up for issue when TCNT matches TPDR, A/D conversion will start at the center of the PWM pulse (the peak value of the TCNT counter). When the start requests are set up for issue when TCNT matches 2Td, A/D conversion will start on the edge of the PWM pulse (the minimum value of the TCNT counter). Requests to start A/D conversion is enabled by setting the TTGE bit in the timer control register (TCNR) to 1. Table 13.3 shows the relationship between A/D conversion start timing and operating mode. Table 13.3 Relationship between A/D Conversion Start Timing and Operating Mode Operating Mode Operating mode 1 (transfer at peak) Operating mode 2 (transfer at trough) Operating mode 3 (transfer at peak and trough) A/D Conversion Start Timing A/D conversion start at trough A/D conversion start at peak A/D conversion start at peak and trough 13.4.2 Output Protection Functions Operating mode output has the following protection functions: • Halting MMT output by external signal The six-phase PWM output pins can be placed in the high-impedance state automatically by inputting a specified external signal. There are three external signal input pins. For details, see section 13.8, Port Output Enable (POE). Rev.1.00 Sep. 18, 2008 Page 378 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) • Halting MMT output when oscillation stops The six-phase PWM output pins are placed in the high-impedance state automatically when stoppage of the clock input is detected. However, pin states are not guaranteed when the clock is restarted. 13.5 Interrupt Sources When the TGFM (TGFN) flag is set to 1 in the timer status register (TSR) by a compare match between TCNT and TPDR (2Td), and if the TGIEM (TGIEN) bit setting in the timer control register (TCNR) is 1, an interrupt is requested. The interrupt request is cleared by clearing the TGF flag to 0. Table 13.4 MMT Interrupt Sources Name TGIMN TGINN Interrupt Source Compare match between TCNT and TPDR Compare match between TCNT and 2Td Interrupt Flag TGFM TGFN The on-chip A/D converter can be activated when TCNT matches TPDR or 2Td. When the TGF flag in the timer status register (TSR) is set to 1 as a result of either match, a request to start A/D conversion is sent to the A/D converter. If the conversion start trigger of the MMT is selected in the A/D converter at that time, A/D conversion starts. 13.6 13.6.1 Operation Timing Input/Output Timing (1) TCNT and TDCNT Count Timing Figure 13.8 shows the TCNT and TDCNT count timing. Pφ TCNT, TDCNT N–3 N–2 N–1 N N+1 N+2 N+3 N+4 Figure 13.8 Count Timing Rev.1.00 Sep. 18, 2008 Page 379 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (2) TCNT Counter Clearing Timing Figure 13.9 shows the timing of TCNT counter clearing by an external signal. Pφ Counter clear signal TCNT N–3 N–2 N–1 N N+1 2Td 2Td + 1 2Td + 2 TDDR Td Figure 13.9 TCNT Counter Clearing Timing (3) TDCNT Operation Timing Figure 13.10 shows the TDCNT operation timing. Pφ CMO TDCNT H'0000 H'0001 . . . . Td – 1 Td H'0000 TDDR Compare match signal DTG TDCNT clear signal Td Legend: CMO: Compare match flag of TGR + TDDR and TCNT DTG: Operation signal of TDCNT Figure 13.10 TDCNT Operation Timing Rev.1.00 Sep. 18, 2008 Page 380 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (4) Buffer Operation Timing Figure 13.11 shows the compare match buffer operation timing. Pφ Compare match signal TCNT N–1 N N–1 .... 2Td + 1 2Td 2Td + 1 2Td + 2 TPDR M0 + 2Td M1 + 2Td M2 + 2Td TPBR M0 M1 M2 TDDR TGRUU, TGRVU, TGRWU TGRU, TGRV, TGRW TGRUD, TGRVD, TGRWD TBRU, TBRV, TBRW L0 Td L0 + 2Td L1 + 2Td L2 + 2Td L0 + Td L0 L1 + Td L1 L2 + Td L2 L1 L2 Figure 13.11 Buffer Operation Timing Rev.1.00 Sep. 18, 2008 Page 381 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.6.2 Interrupt Signal Timing (1) Timing of TGF Flag Setting by Compare Match Figure 13.12 shows the timing of setting of the TGF flag in the timer status register (TSR) on a compare match between TCNT and TPDR, and the timing of the TGI interrupt request signal. The timing is the same for a compare match between TCNT and 2Td. Pφ TCNT N–3 N–2 N–1 N N+1 N+2 N+3 N+4 TPDR Compare match signal N TGF flag TGI interrupt Figure 13.12 TGI Interrupt Timing (2) Status Flag Clearing Timing A status flag is cleared when the CPU reads 1 from the flag, then 0 is written to it. Figure 13.13 shows the timing of status flag clearing by the CPU. TSR write cycle T1 T2 P Address TSR address Write signal Status flag Interrupt request signal Figure 13.13 Timing of Status Flag Clearing by CPU Rev.1.00 Sep. 18, 2008 Page 382 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 13.7 13.7.1 Usage Notes Module Standby Mode Setting MMT operation can be disabled or enabled using the module standby control register. The initial setting is for MMT operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 18, Power-Down Modes. 13.7.2 Notes on MMT Operation Note that the kinds of operation and contention described below occur during MMT operation. (1) Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data transferred is the buffer register write data. Figure 13.14 shows the timing in this case. Buffer register write cycle T1 Pφ Address Buffer register address T2 Write signal Compare match signal Interrupt request signal Buffer register write data Buffer register N M Compare register M Figure 13.14 Contention between Buffer Register Write and Compare Match Rev.1.00 Sep. 18, 2008 Page 383 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (2) Contention between Compare Register Write and Compare Match If a compare match occurs in the T2 state of a compare register (TGR or TPDR) write cycle, the compare register write is not performed, and data is transferred from the buffer register (TBRU, TBRV, TBRW, or TPBR) to the compare register by a buffer operation. Figure 13.15 shows the timing in this case. Compare register write cycle T1 P Address Compare register address T2 Write signal Compare match signal Interrupt request signal Buffer register N Compare register N Figure 13.15 Contention between Compare Register Write and Compare Match (3) Pay Attention to the Notices Below, When a Value is Written into the Timer General Register U (TGRU), Timer General Register V (TGRV), Timer General Register W (TGRW), and in Case of Written into Free Operation Address (*) • In case of counting up: Do not write a value {Previous value of TGRU + Td} into TGRU. • In case of counting down: Do not write a value {Previous value of TGRU - Td} into TGRU. In the same manner to TGRV and TGRW. When a value {Previous value of TGRU + Td} is written (in case of counting down {Previous value of TGRU - Td}), the output of PUOA/PUOB, PVOA/PVOB, PWOA/PWOB (corresponding to U, V, W phase) may not be output for 1 cycle. Figure 15.17 shows the error case. When writing into the buffer operation address, these notes are not relevant. Note: * When addresses, H'FFFF8A1C, H'FFFF8A2C, H'FFFF8A3C are used as register address for TBRU, TBRV, TBRW, respectively. Rev.1.00 Sep. 18, 2008 Page 384 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) TGRU PreviousTGRU Td PreviousTGRU TGRU Td 2Td 2Td Count-up Count down Figure 13.16 Writing into Timer General Registers (When One Cycle is Not Output) (4) Writing Operation into Timer Period Data Register (TPDR) and Timer Dead Time Data Register (TDDR) When MMT is Operating • Do not revise TPDR register when MMT is operating. Always use a buffer-write operation through TPBR register. • Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT), because a value cannot be written into TDCNT, which is compared to a value set in TDDR. (5) Notes on Halting TCNT Counter Operation If TCNT counter operation is halted, a PCM waveform may be output with dead time (non-overlap time) shorter than the value set in the timer dead time register (MMT_TDDR) or no dead time at all (value of 0). To prevent this, use one of the following methods. (a) Set the CST bit in the timer control register (TCNR) to 1 and do not clear it to 0 after MMT counter operation starts. If the CST bit is cleared to 0, do not set it to 1 again. (b) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing and then resetting. (1) Use the pin function controller (PFC) to set the PWM output pin as a general input port. (2) Set the free operation addresses for all the buffer registers (TBRU, TBRV, and TBRW) to H'0000. (3) After the specified dead time duration has elapsed, set TCNR to H'00 and clear the CST bit to 0. (4) Once again, set the CST bit to 1. Rev.1.00 Sep. 18, 2008 Page 385 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (c) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing and then resetting. (1) Clear the CST bit in TCNR to 0 to halt counter operation. (2) Use the pin function controller to set the PWM output pin as a general input port. (3) Clear the MSTP14 bit in module standby control register 2 (MSTCR2) to 0 to transition to module standby mode, and initialize the internal status of MMT. (4) Immediately set the MSTP14 bit to 1 to transition back from module standby mode. Reinitialize MMT and the pin. (5) Set the CST bit in TCNR to 1 to restart counter operation. 13.8 Port Output Enable (POE) The port output enable (POE) circuit enables the MMT’s output pins (POUA, POUB, POVA, POVB, POWA, and POWB) to be placed in the high-impedance state by varying the input to pins POE4 to POE6. An interrupt can also be requested at the same time. In addition, the MMT’s output pins will also enter the high-impedance state in standby mode or when the oscillator halts. 13.8.1 Features The POE circuit has the following features: • Falling edge, Pφ/8 × 16 times, Pφ/16 × 16 times, or Pφ/128 × 16 times low-level sampling can be set for each of input pins POE4 to POE6. • The MMT’s output pins can be placed in the high-impedance state at the falling edge or lowlevel sampling of pins POE4 to POE6. • An interrupt can be generated by input level sampling. Rev.1.00 Sep. 18, 2008 Page 386 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) High impedance request control signal Interrupt request (MMTPOE) ICSR2 Input level detection circuit Falling edge detection circuit Low level detection circuit P /8 P /16 P /128 Figure 13.17 Block Diagram of POE 13.8.2 Input/Output Pins Table13.5 shows the pin configuration of the POE circuit. Table 13.5 Pin Configuration Name Port output enable input pins Abbreviation POE4 to POE6 I/O Input Function Input request signals for placing MMT’s output pins in high-impedance state 13.8.3 Register Description The POE circuit has the following register. • Input level control/status register 2 (ICSR2) Rev.1.00 Sep. 18, 2008 Page 387 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) (1) Input Level Control/Status Register 2 (ICSR2) ICSR2 is a 16-bit readable/writable register that selects the input mode for pins POE4 to POE6, controls enabling or disabling of interrupts, and holds status information. Bit 15 Initial Bit Name Value ⎯ 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 POE6F 0 R/(W)* POE6 Flag Indicates that a high impedance request has been input to the POE6 pin. [Clearing condition] When 0 is written to POE6F after reading POE6F = 1 [Setting condition] • 13 POE5F 0 R/(W)* When the input set by bits 4 and 5 in ICSR2 occurs at the POE6 pin • POE5 Flag Indicates that a high impedance request has been input to the POE5 pin. [Clearing condition] When 0 is written to POE5F after reading POE5F = 1 [Setting condition] • When the input set by bits 2 and 3 in ICSR2 occurs at the POE5 pin • 12 POE4F 0 R/(W)* POE4 Flag Indicates that a high impedance request has been input to the POE4 pin. [Clearing condition] When 0 is written to POE4F after reading POE4F = 1 [Setting condition] • When the input set by bits 0 and 1 in ICSR2 occurs at the POE4 pin • Rev.1.00 Sep. 18, 2008 Page 388 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) Bit Initial Bit Name Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 9 ⎯ 8 PIE 0 R/W Port Interrupt Enable Enables or disables an interrupt request when 1 is set in any of bits POE4F to POE6F in ICSR2. 0: Interrupt request disabled 1: Interrupt request enabled 7, 6 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 4 POE6M1 POE6M0 0 0 R/W R/W POE6 Mode 1 and 0 Select the input mode of the POE6 pin. 00: Request accepted at falling edge of POE6 input 01: POE6 input is sampled for low level 16 times every Pφ/8 clock, and request is accepted when all samples are low level 10: POE6 input is sampled for low level 16 times every Pφ/16 clock, and request is accepted when all samples are low level 11: POE6 input is sampled for low level 16 times every Pφ/128 clock, and request is accepted when all samples are low level 3 2 POE5M1 POE5M0 0 0 R/W R/W POE5 Mode 1 and 0 Select the input mode of the POE5 pin. 00: Request accepted at falling edge of POE5 input 01: POE5 input is sampled for low level 16 times every Pφ/8 clock, and request is accepted when all samples are low level 10: POE5 input is sampled for low level 16 times every Pφ/16 clock, and request is accepted when all samples are low level 11: POE5 input is sampled for low level 16 times every Pφ/128 clock, and request is accepted when all samples are low level Rev.1.00 Sep. 18, 2008 Page 389 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) Bit 1 0 Initial Bit Name Value POE4M1 POE4M0 0 0 R/W R/W R/W Description POE4 Mode 1 and 0 Select the input mode of the POE4 pin. 00: Request accepted at falling edge of POE4 input 01: POE4 input is sampled for low level 16 times every Pφ/8 clock, and request is accepted when all samples are low level 10: POE4 input is sampled for low level 16 times every Pφ/16 clock, and request is accepted when all samples are low level 11: POE4 input is sampled for low level 16 times every Pφ/128 clock, and request is accepted when all samples are low level Note: * Only 0 can be written to clear the flag. 13.8.4 Operation (1) Input Level Detection When the input condition set in ICSR2 occurs on any one of the POE pins, the MMT output pins enter the high-impedance state. • Pins placed in the high-impedance state (the MMT’s output pins) The six pins PWOB, PWOA, PVOB, PVOA, PUOB, and PUOA in the motor management timer (MMT) are placed in the high-impedance state. Note: These pins are in the high-impedance state only when each pin is used as the general input/output function or MMT output pin. (a) Falling Edge Detection When a transition from high- to low-level input occurs on a POE pin (b) Low Level Detection Figure 13.18 shows the low level detection operation. Low level sampling is performed 16 times in succession using the sampling clock set in ICSR2. The input is not accepted if a high level is detected even once among these samples. The timing of entry of the MMT's output pins into the high-impedance state from the sampling clock is the same for falling edge detection and low level detection. Rev.1.00 Sep. 18, 2008 Page 390 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) 8, 16, or 128 clocks P Sampling clock input PUOA High-impedance state [1] [1] [2] [2] [3] [16] Flag set (POE accepted) [13] Flag not set All low-level samples At least one high-level sample Note: The other MMT output pins also enter the high-impedance state at the same timing. Figure 13.18 Low Level Detection Operation (2) Exiting High-Impedance State The MMT output pins that have entered the high-impedance state by the input level detection are released from this state by restoring them to their initial states by means of a power-on reset, or by clearing all the POE flags in ICSR2 (POE4F to POE6F: bits 12 to 14). 13.8.5 Usage Note To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE pin. Rev.1.00 Sep. 18, 2008 Page 391 of 522 REJ09B0069-0100 Section 13 Motor Management Timer (MMT) Rev.1.00 Sep. 18, 2008 Page 392 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Section 14 Pin Function Controller (PFC) The pin function controller (PFC) is composed of those registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 14.1 to 14.10 list the multiplexed pins of this LSI. Tables 14.11 and 14.12 list the pin functions in each operating mode. Table 14.1 SH7108 Multiplexed Pins (Port A) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 (Related (Related (Related (Related (Related (Related Module) Module) Module) Module) Module) Port Module) A PA0 I/O (port) PA1 I/O (port) PA2 I/O (port) PA3 I/O (port) PA4 I/O (port) PA5 I/O (port) PA6 I/O (port) PA7 I/O (port) PA8 I/O (port) PA9 I/O (port) PA10 I/O (port) PA11 I/O (port) PA12 I/O (port) PA13 I/O (port) PA14 I/O (port) PA15 I/O (port) — — — — — — — — — — — — — — IRQ0 input (INTC) — — IRQ1 input (INTC) — — — — — — — — — — — — — — — — — — — — — — — Function 7 (Related Module) Function 8 (Related Module) — POE0 input RxD2 input (port) (SCI) POE1 input TxD2 output — (port) (SCI) PCIO I/O (MMT) — — — RxD2 input (SCI) SCK2 I/O (SCI) RxD3 input (SCI) — — TxD3 output — (SCI) SCK3 I/O (SCI) — — — — — — — — — — — — TCLKA — input (MTU) TCLKB — input (MTU) TCLKC — input (MTU) TCLKD — input (MTU) — — — — — — — ADTRG input (A/D) — TxD2 output — (SCI) RxD3 input (SCI) — TxD3 output — (SCI) SCK2 I/O (SCI) SCK3 I/O (SCI) — — — — — — — — — — POE4 input — (port) POE5 input — (port) POE6 input — (port) Rev.1.00 Sep. 18, 2008 Page 393 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.2 SH7108 Multiplexed Pins (Port B) Port B Function 1 (Related Module) PB2 I/O (port) PB3 I/O (port) PB4 I/O (port) PB5 I/O (port) Function 2 (Related Module) IRQ0 input (INTC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) Function 3 (Related Module) POE0 input (port) POE1 input (port) POE2 input (port) POE3 input (port) Function 4 (Related Module) — — — — Table 14.3 SH7108 Multiplexed Pins (Port E) Port E Function 1 (Related Module) PE0 I/O (port) PE1 I/O (port) PE2 I/O (port) PE3 I/O (port) PE4 I/O (port) PE5 I/O (port) PE6 I/O (port) PE7 I/O (port) PE8 I/O (port) PE9 I/O (port) PE10 I/O (port) PE11 I/O (port) PE12 I/O (port) PE13 I/O (port) PE14 I/O (port) PE15 I/O (port) PE16 I/O (port) PE17 I/O (port) PE18 I/O (port) PE19 I/O (port) PE20 I/O (port) PE21 I/O (port) Function 2 (Related Module) TIOC0A I/O (MTU) TIOC0B I/O (MTU) TIOC0C I/O (MTU) TIOC0D I/O (MTU) TIOC1A I/O (MTU) TIOC1B I/O (MTU) TIOC2A I/O (MTU) TIOC2B I/O (MTU) TIOC3A I/O (MTU) TIOC3B I/O (MTU) TIOC3C I/O (MTU) TIOC3D I/O (MTU) TIOC4A I/O (MTU) TIOC4B I/O (MTU) TIOC4C I/O (MTU) TIOC4D I/O (MTU) PUOA output (MMT) PVOA output (MMT) PWOA output (MMT) PUOB output (MMT) PVOB output (MMT) PWOB output (MMT) Function 3 (Related Module) — — — — RxD3 input (SCI) TxD3 output (SCI) SCK3 I/O (SCI) RxD2 input (SCI) SCK2 I/O (SCI) — TxD2 output (SCI) — — MRES input (INTC) — — — — — — — — Function 4 (Related Module) — — — — — — — — — — — — — — — IRQOUT output (INTC) — — — — — — Rev.1.00 Sep. 18, 2008 Page 394 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.4 SH7108 Multiplexed Pins (Port F) Port F Function 1 (Related Module) PF8 input (port) PF9 input (port) PF10 input (port) PF11 input (port) PF12 input (port) PF13 input (port) PF14 input (port) PF15 input (port) Function 2 (Related Module) AN8 input (A/D-0) AN9 input (A/D-0) AN10 input (A/D-0) AN11 input (A/D-0) AN12 input (A/D-1) AN13 input (A/D-1) AN14 input (A/D-1) AN15 input (A/D-1) Function 3 (Related Module) — — — — — — — — Function 4 (Related Module) — — — — — — — — Table 14.5 SH7108 Multiplexed Pins (Port G) Port G Function 1 (Related Module) PG0 input (port) PG1 input (port) PG2 input (port) PG3 input (port) Function 2 (Related Module) AN16 input (A/D-2) AN17 input (A/D-2) AN18 input (A/D-2) AN19 input (A/D-2) Function 3 (Related Module) — — — — Function 4 (Related Module) — — — — Rev.1.00 Sep. 18, 2008 Page 395 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.6 SH7109 Multiplexed Pins (Port A) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 (Related (Related (Related (Related (Related (Related Port Module) Module) Module) Module) Module) Module) A PA0 I/O (port) PA1 I/O (port) PA2 I/O (port) PA3 I/O (port) PA4 I/O (port) PA5 I/O (port) PA6 I/O (port) PA7 I/O (port) PA8 I/O (port) PA9 I/O (port) PA10 I/O (port) PA11 I/O (port) PA12 I/O (port) PA13 I/O (port) PA14 I/O (port) PA15 I/O (port) — — — — — — — — — — — — — — IRQ0 input (INTC) — — IRQ1 input (INTC) RD output (BSC) A0 output (BSC) A1 output (BSC) A2 output (BSC) A3 output (BSC) A4 output (BSC) A5 output (BSC) — Function 7 (Related Module) Function 8 (Related Module) — POE0 input RxD2 input (port) (SCI) POE1 input TxD2 output — (port) (SCI) PCIO I/O (MMT) — — — RxD2 input (SCI) SCK2 I/O (SCI) RxD3 input (SCI) — — TxD3 output — (SCI) SCK3 I/O (SCI) — — — — — — — — — — — — TCLKA — input (MTU) TCLKB — input (MTU) TCLKC — input (MTU) TCLKD — input (MTU) CS0 output — (BSC) — ADTRG input (A/D) WAIT input — (BSC) — — — — — — — — — — — — — TxD2 output — (SCI) RxD3 input (SCI) — TxD3 output — (SCI) SCK2 I/O (SCI) SCK3 I/O (SCI) — — — — WRL output — (BSC) — RD output (BSC) CK output (CPG) POE4 input — (port) POE5 input — (port) POE6 input — (port) BREQ input — (BSC) — — BACK — output (BSC) Rev.1.00 Sep. 18, 2008 Page 396 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.7 SH7109 Multiplexed Pins (Port B) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 (Related (Related (Related (Related (Related (Related (Related (Related Port Module) Module) Module) Module) Module) Module) Module) Module) B PB0 I/O (port) PB1 I/O (port) PB2 I/O (port) PB3 I/O (port) PB4 I/O (port) PB5 I/O (port) A16 output (BSC) A17 output (BSC) IRQ0 input (INTC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) — — — — — — — — — — — — — — — CK output (CPG) — — — — — — — — — — — — POE0 input — (port) POE1 input — (port) POE2 input — (port) POE3 input — (port) Table 14.8 SH7109 Multiplexed Pins (Port D) Port D Function 1 (Related Module) PD0 I/O (port) PD1 I/O (port) PD2 I/O (port) PD3 I/O (port) PD4 I/O (port) PD5 I/O (port) PD6 I/O (port) PD7 I/O (port) PD8 I/O (port) Function 2 (Related Module) D0 I/O (BSC) D1 I/O (BSC) D2 I/O (BSC) D3 I/O (BSC) D4 I/O (BSC) D5 I/O (BSC) D6 I/O (BSC) D7 I/O (BSC) — Function 3 (Related Module) RxD2 input (SCI) TxD2 output (SCI) SCK2 I/O (SCI) — — — — — — Function 4 (Related Module) — — — — — — — — — Rev.1.00 Sep. 18, 2008 Page 397 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.9 SH7109 Multiplexed Pins (Port E) Port E Function 1 (Related Module) PE0 I/O (port) PE1 I/O (port) PE2 I/O (port) PE3 I/O (port) PE4 I/O (port) PE5 I/O (port) PE6 I/O (port) PE7 I/O (port) PE8 I/O (port) PE9 I/O (port) PE10 I/O (port) PE11 I/O (port) PE12 I/O (port) PE13 I/O (port) PE14 I/O (port) PE15 I/O (port) PE16 I/O (port) PE17 I/O (port) PE18 I/O (port) PE19 I/O (port) PE20 I/O (port) PE21 I/O (port) Function 2 (Related Module) TIOC0A I/O (MTU) TIOC0B I/O (MTU) TIOC0C I/O (MTU) TIOC0D I/O (MTU) TIOC1A I/O (MTU) TIOC1B I/O (MTU) TIOC2A I/O (MTU) TIOC2B I/O (MTU) TIOC3A I/O (MTU) TIOC3B I/O (MTU) TIOC3C I/O (MTU) TIOC3D I/O (MTU) TIOC4A I/O (MTU) TIOC4B I/O (MTU) TIOC4C I/O (MTU) TIOC4D I/O (MTU) PUOA output (MMT) PVOA output (MMT) PWOA output (MMT) PUOB output (MMT) PVOB output (MMT) PWOB output (MMT) Function 3 (Related Module) — — — — RxD3 input (SCI) TxD3 output (SCI) SCK3 I/O (SCI) RxD2 input (SCI) SCK2 I/O (SCI) — TxD2 output (SCI) — — MRES input (INTC) — — — WAIT input (BSC) — — — — Function 4 (Related Module) CS0 output (BSC) — — — A6 output (BSC) A7 output (BSC) A8 output (BSC) A9 output (BSC) — — WRL output (BSC) — — — — IRQOUT output (INTC) A10 output (BSC) A11 output (BSC) A12 output (BSC) A13 output (BSC) A14 output (BSC) A15 output (BSC) Rev.1.00 Sep. 18, 2008 Page 398 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.10 SH7109 Multiplexed Pins (Port F) Port F Function 1 (Related Module) PF0 input (port) PF1 input (port) PF2 input (port) PF3 input (port) PF4 input (port) PF5 input (port) PF6 input (port) PF7 input (port) PF8 input (port) PF9 input (port) PF10 input (port) PF11 input (port) PF12 input (port) PF13 input (port) PF14 input (port) PF15 input (port) Function 2 (Related Module) AN0 input (A/D-0) AN1 input (A/D-0) AN2 input (A/D-0) AN3 input (A/D-0) AN4 input (A/D-1) AN5 input (A/D-1) AN6 input (A/D-1) AN7 input (A/D-1) AN8 input (A/D-0) AN9 input (A/D-0) AN10 input (A/D-0) AN11 input (A/D-0) AN12 input (A/D-1) AN13 input (A/D-1) AN14 input (A/D-1) AN15 input (A/D-1) Function 3 (Related Module) — — — — — — — — — — — — — — — — Function 4 (Related Module) — — — — — — — — — — — — — — — — Rev.1.00 Sep. 18, 2008 Page 399 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.11 SH7108 Pin Functions in Each Operating Mode Pin Name Pin No. SH7108 11, 43, 66 9, 24, 41, 64 22, 62 27, 38 25, 40 1 2 3 4 5 6 7 8 10 12 13 14 15 16 17 18 19 20 21 23 26 28 29 30 31 32 Initial Function Vcc Vss VCL AVcc AVss PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PG3/AN19 PG2/AN18 Single Chip Mode Settable Function by PFC Vcc Vss VCL AVcc AVss PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RxD3 PE5/TIOC1B/TxD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RxD2 PE8/TIOC3A/SCK2 PE9/TIOC3B PE10/TIOC3C/TxD2 PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA PE17/PVOA PE18/PWOA PE19/PUOB PE20/PVOB PE21/PWOB PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PG3/AN19 PG2/AN18 Rev.1.00 Sep. 18, 2008 Page 400 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Pin Name Pin No. SH7108 33 34 35 36 37 39 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 63 65 67 68 69 70 71 72 Initial Function PG1/AN17 PG0/AN16 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PB5 PB4 PB3 PB2 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FWP RES NMI MD3 MD2 MD1 MD0 Single Chip Mode Settable Function by PFC PG1/AN17 PG0/AN16 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PB3/IRQ1/POE1 PB2/IRQ0/POE0 PA15/POE6 PA14/POE5 PA13/POE4 PA12 PA11/ADTRG/SCK3 PA10/SCK2 PA9/TCLKD/TxD3 PA8/TCLKC/RxD3 PA7/TCLKB/TxD2 PA6/TCLKA/RxD2 PA5/IRQ1/SCK3 PA4/TxD3 PA3/RxD3 PA2/IRQ0/PCIO/SCK2 PA1/POE1/TxD2 PA0/POE0/RxD2 FWP RES NMI MD3 MD2 MD1 MD0 Rev.1.00 Sep. 18, 2008 Page 401 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Pin Name Pin No. SH7108 73 74 75 76 77 78 79 80 Initial Function EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0 PE1 Single Chip Mode Settable Function by PFC EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B Rev.1.00 Sep. 18, 2008 Page 402 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.12 SH7109 Pin Functions in Each Operating Mode (1) Pin Name Pin No. SH7109 15, 53, 72, 84 13, 29, 50, 74, 82 27, 77 33, 46 30, 49 1 2 3 4 5 6 7 8 9 10 11 12 14 16 17 18 19 20 21 22 23 24 25 26 28 31 On-Chip ROM Disabled Initial Function Settable Function by PFC Vcc Vss VCL AVcc AVss WDTOVF CS0 PE1 PE2 PE3 A6 A7 A8 A9 PE8 ASEBRKAK PE9 WRL DBGMD PE11 PE12 PE13 PE14 PE15 A10 A11 A12 A13 A14 A15 PF7/AN7 Vcc Vss VCL AVcc AVss WDTOVF CS0 PE1/TIOC0B PE2/TIOC0C PE3/TIOC0D A6 A7 A8 A9 PE8/TIOC3A/SCK2 ASEBRKAK PE9/TIOC3B WRL DBGMD PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT A10 A11 A12 A13 A14 A15 PF7/AN7 On-Chip ROM Enabled Initial Function Settable Function by PFC Vcc Vss VCL AVcc AVss WDTOVF PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 ASEBRKAK PE9 PE10 DBGMD PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PF7/AN7 Vcc Vss VCL AVcc AVss WDTOVF PE0/TIOC0A/CS0 PE1/TIOC0B PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RxD3/A6 PE5/TIOC1B/TxD3/A7 PE6/TIOC2A/SCK3/A8 PE7/TIOC2B/RxD2/A9 PE8/TIOC3A/SCK2 ASEBRKAK PE9/TIOC3B PE10/TIOC3C/TxD2/WRL DBGMD PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA/A10 PE17/PVOA/WAIT/A11 PE18/PWOA/A12 PE19/PUOB/A13 PE20/PVOB/A14 PE21/PWOB/A15 PF7/AN7 Rev.1.00 Sep. 18, 2008 Page 403 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Pin Name Pin No. SH7109 32 34 35 36 37 38 39 40 41 42 43 44 45 47 48 51 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 On-Chip ROM Disabled Initial Function Settable Function by PFC PF15/AN15 PF6/AN6 PF14/AN14 PF5/AN5 PF13/AN13 PF4/AN4 PF12/AN12 PF11/AN11 PF3/AN3 PF10/AN10 PF2/AN2 PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 CK PB4 PB3 PB2 A17 A16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 RD A5 A4 A3 PF15/AN15 PF6/AN6 PF14/AN14 PF5/AN5 PF13/AN13 PF4/AN4 PF12/AN12 PF11/AN11 PF3/AN3 PF10/AN10 PF2/AN2 PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 PB5/IRQ3/POE3/CK PB4/IRQ2/POE2 PB3/IRQ1/POE1 PB2/IRQ0/POE0 A17 A16 PA15/CK/POE6/BACK PA14/RD/POE5 PA13/POE4/BREQ PA12/WRL PA11/ADTRG/SCK3 PA10/CS0/SCK2 PA9/TCLKD/TxD3 PA8/TCLKC/RxD3 PA7/TCLKB/WAIT/TxD2 RD A5 A4 A3 On-Chip ROM Enabled Initial Function Settable Function by PFC PF15/AN15 PF6/AN6 PF14/AN14 PF5/AN5 PF13/AN13 PF4/AN4 PF12/AN12 PF11/AN11 PF3/AN3 PF10/AN10 PF2/AN2 PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 CK PB4 PB3 PB2 PB1 PB0 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PF15/AN15 PF6/AN6 PF14/AN14 PF5/AN5 PF13/AN13 PF4/AN4 PF12/AN12 PF11/AN11 PF3/AN3 PF10/AN10 PF2/AN2 PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 PB5/IRQ3/POE3/CK PB4/IRQ2/POE2 PB3/IRQ1/POE1 PB2/IRQ0/POE0 PB1/A17 PB0/A16 PA15/CK/POE6/BACK PA14/RD/POE5 PA13/POE4/BREQ PA12/WRL PA11/ADTRG/SCK3 PA10/CS0/SCK2 PA9/TCLKD/TxD3 PA8/TCLKC/RxD3 PA7/TCLKB/WAIT/TxD2 PA6/TCLKA/RD/RxD2 PA5/IRQ1/A5/SCK3 PA4/A4/TxD3 PA3/A3/RxD3 Rev.1.00 Sep. 18, 2008 Page 404 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Pin Name Pin No. SH7109 71 73 75 76 78 79 80 81 83 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 On-Chip ROM Disabled Initial Function Settable Function by PFC A2 A1 A0 PD8 D7 D6 D5 D4 FWP HSTBY D3 RES D2 NMI D1 MD3 D0 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss A2 A1 A0 PD8 D7 D6 D5 D4 FWP HSTBY D3 RES D2 NMI D1 MD3 D0 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss On-Chip ROM Enabled Initial Function Settable Function by PFC PA2 PA1 PA0 PD8 PD7 PD6 PD5 PD4 FWP HSTBY PD3 RES PD2 NMI PD1 MD3 PD0 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss PA2/IRQ0/A2/PCIO/SCK2 PA1/A1/POE1/TxD2 PA0/A0/POE0/RxD2 PD8 PD7/D7 PD6/D6 PD5/D5 PD4/D4 FWP HSTBY PD3/D3 RES PD2/D2/SCK2 NMI PD1/D1/TxD2 MD3 PD0/D0/RxD2 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss Rev.1.00 Sep. 18, 2008 Page 405 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Table 14.13 SH7109 Pin Functions in Each Operating Mode (2) Pin Name Pin No. SH7109 15, 53, 72, 84 13, 29, 50, 74, 82 27, 77 33, 46 30, 49 1 2 3 4 5 6 7 8 9 10 11 12 14 16 17 18 19 20 21 22 23 24 25 26 28 31 32 34 Initial Function Vcc Vss VCL Avcc AVss WDTOVF PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 ASEBRKAK PE9 PE10 DBGMD PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PF7/AN7 PF15/AN15 PF6/AN6 Single Chip Mode Settable Function by PFC Vcc Vss VCL Avcc AVss WDTOVF PE0/TIOC0A PE1/TIOC0B PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RxD3 PE5/TIOC1B/TxD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RxD2 PE8/TIOC3A/SCK2 ASEBRKAK PE9/TIOC3B PE10/TIOC3C/TxD2 DBGMD PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA PE17/PVOA PE18/PWOA PE19/PUOB PE20/PVOB PE21/PWOB PF7/AN7 PF15/AN15 PF6/AN6 Rev.1.00 Sep. 18, 2008 Page 406 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Pin Name Pin No. SH7109 35 36 37 38 39 40 41 42 43 44 45 47 48 51 52 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 73 Initial Function PF14/AN14 PF5/AN5 PF13/AN13 PF4/AN4 PF12/AN12 PF11/AN11 PF3/AN3 PF10/AN10 PF2/AN2 PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 PB5 PB4 PB3 PB2 PB1 PB0 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 Single Chip Mode Settable Function by PFC PF14/AN14 PF5/AN5 PF13/AN13 PF4/AN4 PF12/AN12 PF11/AN11 PF3/AN3 PF10/AN10 PF2/AN2 PF9/AN9 PF1/AN1 PF8/AN8 PF0/AN0 PB5/IRQ3/POE3/CK PB4/IRQ2/POE2 PB3/IRQ1/POE1 PB2/IRQ0/POE0 PB1 PB0 PA15/CK/POE6 PA14/POE5 PA13/POE4 PA12 PA11/ADTRG/SCK3 PA10/SCK2 PA9/TCLKD/TxD3 PA8/TCLKC/RxD3 PA7/TCLKB/TxD2 PA6/TCLKA/RxD2 PA5/IRQ1/SCK3 PA4/TxD3 PA3/RxD3 PA2/IRQ0/PCIO/SCK2 PA1/POE1/TxD2 Rev.1.00 Sep. 18, 2008 Page 407 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Pin Name Pin No. SH7109 75 78 79 80 81 83 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Initial Function PA0 PD7 PD6 PD5 PD4 FWP HSTBY PD3 RES PD2 NMI PD1 MD3 PD0 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss Single Chip Mode Settable Function by PFC PA0/POE0/RxD2 PD7 PD6 PD5 PD4 FWP HSTBY PD3 RES PD2/SCK2 NMI PD1/TxD2 MD3 PD0/RxD2 MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss Rev.1.00 Sep. 18, 2008 Page 408 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) 14.1 Register Descriptions The PFC has the following registers. For details on the addresses of the registers and their states during each process, refer to section 19, List of Registers. • Port A I/O register L (PAIORL) • Port A control register L3 (PACRL3) • Port A control register L2 (PACRL2) • Port A control register L1 (PACRL1) • Port B I/O register (PBIOR) • Port B control register 1 (PBCR1) • Port B control register 2 (PBCR2) • Port D I/O register L (PDIORL) • Port D control register L1 (PDCRL1) • Port D control register L2 (PDCRL2) • Port E I/O register H (PEIORH) • Port E I/O register L (PEIORL) • Port E control register H (PECRH) • Port E control register L1 (PECRL1) • Port E control register L2 (PECRL2) 14.1.1 Port A I/O Register L (PAIORL) PAIORL is a 16-bit readable/writable register that sets the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0), SCK2 and SCK3 pins are functioning as inputs/outputs of the SCI, and PCIO pin is functioning as an input/output of the MMT. In other states, PAIORL is disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an input pin if the bit is cleared to 0. The initial value of PAIORL is H'0000. 14.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1) PACRL3 to PACRL1 are 16-bit readable/writable registers that select the functions of the multiplexed pins on port A. Rev.1.00 Sep. 18, 2008 Page 409 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) (1) Port A Control Registers L3 to L1 (PACRL3 to PACRL1) in SH7108 Register PACRL3 PACRL1 PACRL1 Bit 15 15 14 Bit Name PA15MD2 PA15MD1 PA15MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA15 Mode Select the function of the PA15/POE6 pin. 000: PA15 I/O (port) 001: Setting prohibited 010: POE6 input (port) PACRL3 PACRL1 PACRL1 14 13 12 PA14MD2 PA14MD1 PA14MD0 0 0 0 R/W R/W R/W PA14 Mode Select the function of the PA14/POE5 pin. 000: PA14 I/O (port) 001: Setting prohibited 010: POE5 input (port) PACRL3 PACRL1 PACRL1 13 11 10 PA13MD2 PA13MD1 PA13MD0 0 0 0 R/W R/W R/W PA13 Mode Select the function of the PA13/POE4 pin. 000: PA13 I/O (port) 001: Setting prohibited 010: POE4 input (port) PACRL3 PACRL1 PACRL1 12 9 8 PA12MD2 PA12MD1 PA12MD0 0 0 0 R/W R/W R/W PA12 Mode Select the function of the PA12 pin. 000: PA12 I/O (port) 001: Setting prohibited 010: Setting prohibited PACRL3 PACRL1 PACRL1 11 7 6 PA11MD2 PA11MD1 PA11MD0 0 0 0 R/W R/W R/W PA11 Mode Select the function of the PA11/ADTRG/SCK3 pin. 000: PA11 I/O (port) 001: Setting prohibited 010: ADTRG input (A/D) 011: Setting prohibited PACRL3 PACRL1 PACRL1 10 5 4 PA10MD2 PA10MD1 PA10MD0 0 0 0 R/W R/W R/W PA10 Mode Select the function of the PA10/SCK2 pin. 000: PA10 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: SCK2 I/O (SCI) 110: Setting prohibited 111: Setting prohibited 100: Setting prohibited 101: SCK3 I/O (SCI) 110: Setting prohibited 111: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 410 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0 0 Register PACRL3 PACRL1 PACRL1 Bit 9 3 2 Bit Name PA9MD2 PA9MD1 PA9MD0 R/W R/W R/W R/W Description PA9 Mode Select the function of the PA9/TCLKD/TxD3 pin. 000: PA9 I/O (port) 001: TCLKD input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: TxD3 output (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 8 1 0 PA8MD2 PA8MD1 PA8MD0 0 0 0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/RxD3 pin. 000: PA8 I/O (port) 001: TCLKC input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: RxD3 input (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 7 15 14 PA7MD2 PA7MD1 PA7MD0 0 0 0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/TxD2 pin. 000: PA7 I/O (port) 001: TCLKB input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: TxD2 output (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 6 13 12 PA6MD2 PA6MD1 PA6MD0 0 0 0 R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA/RxD2 pin. 000: PA6 I/O (port) 001: TCLKA input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: RxD2 input (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 5 11 10 PA5MD2 PA5MD1 PA5MD0 0 0 0 R/W R/W R/W PA5 Mode Select the function of the PA5/IRQ1/SCK3 pin. 000: PA5 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ1 input (INTC) 100: Setting prohibited 101: Setting prohibited 110: SCK3 I/O (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 4 9 8 PA4MD2 PA4MD1 PA4MD0 0 0 0 R/W R/W R/W PA4 Mode Select the function of the PA4/TxD3 pin. 000: PA4 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: TxD3 output (SCI) 111: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 411 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0 0 Register PACRL3 PACRL2 PACRL2 Bit 3 7 6 Bit Name PA3MD2 PA3MD1 PA3MD0 R/W R/W R/W R/W Description PA3 Mode Select the function of the PA3/RxD3 pin. 000: PA3 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: RxD3 input (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 2 5 4 PA2MD2 PA2MD1 PA2MD0 0 0 0 R/W R/W R/W PA2 Mode Select the function of the PA2/IRQ0/PCIO/SCK2 pin. 000: PA2 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ0 input (INTC) 100: Setting prohibited 101: PCIO I/O (MMT) 110: SCK2 I/O (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 1 3 2 PA1MD2 PA1MD1 PA1MD0 0 0 0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TxD2 pin. 000: PA1 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE1 input (port) 110: TxD2 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 0 1 0 PA0MD2 PA0MD1 PA0MD0 0 0 0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RxD2 pin. 000: PA0 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE0 input (port) 110: RxD2 input (SCI) 111: Setting prohibited Legend: x: Don’t care. Rev.1.00 Sep. 18, 2008 Page 412 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) (2) Port A Control Registers L3 to L1 (PACRL3 to PACRL1) in SH7109 Register PACRL3 PACRL1 PACRL1 Bit 15 15 14 Bit Name PA15MD2 PA15MD1 PA15MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA15 Mode Select the function of the PA15/CK/POE6/BACK pin. 000: PA15 I/O (port) 001: CK output (CPG) 010: POE6 input (port) 011: Setting prohibited PACRL3 PACRL1 PACRL1 14 13 12 PA14MD2 PA15MD1 PA14MD0 0 0 0 R/W R/W R/W PA14 Mode Select the function of the PA14/RD/POE5 pin. 000: PA14 I/O (port) 001: RD output (BSC) 010: POE5 input (port) 011: Setting prohibited PACRL3 PACRL1 PACRL1 13 11 10 PA13MD2 PA13MD1 PA13MD0 0 0 0 R/W R/W R/W PA13 Mode Select the function of the PA13/POE4/BREQ pin. 000: PA13 I/O (port) 001: Setting prohibited 010: POE4 input (port) 011: Setting prohibited PACRL3 PACRL1 PACRL1 12 9 8 PA12MD2 PA12MD1 PA12MD0 0 0 0 R/W R/W R/W PA12 Mode Select the function of the PA12/WRL pin. 000: PA12 I/O (port) 001: WRL output (BSC) 010: Setting prohibited 011: Setting prohibited PACRL3 PACRL1 PACRL1 11 7 6 PA11MD2 PA11MD1 PA11MD0 0 0 0 R/W R/W R/W PA11 Mode Select the function of the PA11/ADTRG/SCK3 pin. 000: PA11 I/O (port) 001: Setting prohibited 010: ADTRG input (A/D) 011: Setting prohibited 100: Setting prohibited 101: SCK3 I/O (SCI) 110: Setting prohibited 111: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 100: Setting prohibited 101: BREQ input (BSC) 110: Setting prohibited 111: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 100: Setting prohibited 101: BACK output (BSC) 110: Setting prohibited 111: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 413 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0 0 Register PACRL3 PACRL1 PACRL1 Bit 10 5 4 Bit Name PA10MD2 PA10MD1 PA10MD0 R/W R/W R/W R/W Description PA10 Mode Select the function of the PA10/CS0/SCK2 pin. 000: PA10 I/O (port) 001: CS0 output (BSC) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: SCK2 I/O (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 9 3 2 PA9MD2 PA9MD1 PA9MD0 0 0 0 R/W R/W R/W PA9 Mode Select the function of the PA9/TCLKD/TxD3 pin. 000: PA9 I/O (port) 001: TCLKD input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: TxD3 output (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL1 PACRL1 8 1 0 PA8MD2 PA8MD1 PA8MD0 0 0 0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/RxD3 pin. 000: PA8 I/O (port) 001: TCLKC input (MTU) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: RxD3 input (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 7 15 14 PA7MD2 PA7MD1 PA7MD0 0 0 0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/WAIT/TxD2 pin. 000: PA7 I/O (port) 001: TCLKB input (MTU) 010: Setting prohibited 011: WAIT input (BSC) 100: Setting prohibited 101: TxD2 output (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 6 13 12 PA6MD2 PA6MD1 PA6MD0 0 0* 0* R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA/RD/RxD2 pin. 000: PA6 I/O (port) 001: TCLKA input (MTU) 010: Setting prohibited 011: RD output (BSC) 100: Setting prohibited 101: RxD2 input (SCI) 110: Setting prohibited 111: Setting prohibited PACRL3 PACRL2 PACRL2 5 11 10 PA5MD2 PA5MD1 PA5MD0 0* 0 0 R/W R/W R/W PA5 Mode Select the function of the PA5/IRQ1/A5/SCK3 pin. 000: PA5 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ1 input (INTC) 100: A5 output (BSC) 101: Setting prohibited 110: SCK3 I/O (SCI) 111: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 414 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0* 0 0 Register PACRL3 PACRL2 PACRL2 Bit 4 9 8 Bit Name PA4MD2 PA4MD1 PA4MD0 R/W R/W R/W R/W Description PA4 Mode Select the function of the PA4/A4/TxD3 pin. 000: PA4 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: A4 output (BSC) 101: Setting prohibited 110: TxD3 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 3 7 6 PA3MD2 PA3MD1 PA3MD0 0* 0 0 R/W R/W R/W PA3 Mode Select the function of the PA3/A3/RxD3 pin. 000: PA3 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: A3 output (BSC) 101: Setting prohibited 110: RxD3 input (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 2 5 4 PA2MD2 PA2MD1 PA2MD0 0* 0 0 R/W R/W R/W PA2 Mode Select the function of the PA2/IRQ0/A2/PCIO/SCK2 pin. 000: PA2 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ0 input (INTC) 100: A2 output (BSC) 101: PCIO I/O (MMT) 110: SCK2 I/O (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 1 3 2 PA1MD2 PA1MD1 PA1MD0 0* 0 0 R/W R/W R/W PA1 Mode Select the function of the PA1/A1/POE1/TxD2 pin. 000: PA1 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: A1 output (BSC) 101: POE1 input (port) 110: TxD2 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 0 1 0 PA0MD2 PA0MD1 PA0MD0 0* 0 0 R/W R/W R/W PA0 Mode Select the function of the PA0/A0/POE0/RxD2 pin. 000: PA0 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: A0 output (BSC) 101: POE0 input (port) 110: RxD2 input (SCI) 111: Setting prohibited Note: * The initial value is 1 in 8-bit external extended mode with the on-chip ROM disabled. Rev.1.00 Sep. 18, 2008 Page 415 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) 14.1.3 Port B I/O Register (PBIOR) PBIOR is a 16-bit readable/writable register that sets the pins on port B as inputs or outputs. Bits PB5IOR to PB0IOR correspond to pins PB5 to PB0 (names of multiplexed pins are here given as port names and pin numbers alone). PBIOR is enabled when port B pins are functioning as general-purpose inputs/outputs (PB5 to PB0). In other states, PBIOR is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an input pin if the bit is cleared to 0. Note that bits 1 and 0 are disabled in the SH7108. Bits 15 to 6 are reserved. These bits are always read as 0. The write value should always be 0. The initial vale of PBIOR is H'0000. Rev.1.00 Sep. 18, 2008 Page 416 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) 14.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2) PBCR1 and PBCR2 are 16-bit readable/writable registers that select the multiplexed pin function of the pins on port B. Note that bit 9 in PBCR1 and bits 3 to 0 in PBCR2 are disabled in the SH7108. (1) Port B Control Registers 1 and 2 (PBCR1 and PBCR2) in SH7108 Register PBCR1 PBCR1 PBCR1 PBCR2 PBCR2 PBCR1 PBCR2 PBCR2 Bit 15, 14 8 to 0 9 15 to 12 3 to 0 13 11 10 Bit Name — — — — — PB5MD2 PB5MD1 PB5MD0 Initial Value All 0 All 0 0 All 0 All 0 0 0 0 R/W R R R R R R/W R/W R/W PB5 Mode Select the function of the PB5/IRQ3/POE3 pin. 000: PB5 I/O (port) 010: POE3 input (port) PBCR1 PBCR2 PBCR2 12 9 8 PB4MD2 PB4MD1 PB4MD0 0 0 0 R/W R/W R/W PB4 Mode Select the function of the PB4/IRQ2/POE2 pin. 000: PB4 I/O (port) 010: POE2 input (port) PBCR1 PBCR2 PBCR2 11 7 6 PB3MD2 PB3MD1 PB3MD0 0 0 0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1 pin. 000: PB3 I/O (port) 010: POE1 input (port) PBCR1 PBCR2 PBCR2 10 5 4 PB2MD2 PB2MD1 PB2MD0 0 0 0 R/W R/W R/W PB2 Mode Select the function of the PB2/IRQ0/POE0 pin. 000: PB2 I/O (port) 010: POE0 input (port) 011: Setting prohibited 001: IRQ0 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ1 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ2 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ3 input (INTC) 1xx: Setting prohibited Description Reserved These bits are always read as 0. The write value should always be 0. Legend: x: Don’t care. Rev.1.00 Sep. 18, 2008 Page 417 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) (2) Port B Control Registers 1 and 2 (PBCR1 and PBCR2) in SH7109 Register PBCR1 PBCR1 PBCR2 PBCR1 PBCR2 PBCR2 Bit 15 to 14 8 to 0 15 to 12 13 11 10 Bit Name — — — PB5MD2 PB5MD1 PB5MD0 Initial Value All 0 All 0 All 0 0*1 0 0* 1 R/W R R R R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. PB5 Mode Select the function of the PB5/IRQ3/POE3/CK pin. 000: PB5 I/O (port) 010: POE3 input (port) 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: IRQ3 input (INTC) 101: CK output (CPG) PBCR1 PBCR2 PBCR2 12 9 8 PB4MD2 PB4MD1 PB4MD0 0 0 0 R/W R/W R/W PB4 Mode Select the function of the PB4/IRQ2/POE2 pin. 000: PB4 I/O (port) 010: POE2 input (port) 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: IRQ2 input (INTC) 101: Setting prohibited PBCR1 PBCR2 PBCR2 11 7 6 PB3MD2 PB3MD1 PB3MD0 0 0 0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1 pin. 000: PB3 I/O (port) 010: POE1 input (port) 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: IRQ1 input (INTC) 101: Setting prohibited PBCR1 PBCR2 PBCR2 10 5 4 PB2MD2 PB2MD1 PB2MD0 0 0 0 R/W R/W R/W PB2 Mode Select the function of the PB2/IRQ0/POE0 pin. 000: PB2 I/O (port) 010: POE0 input (port) 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: IRQ0 input (INTC) 101: Setting prohibited PBCR1 PBCR2 PBCR2 9 3 2 PB1MD2 PB1MD1 PB1MD0 0 0 0*2 R/W R/W R/W PB1 Mode Select the function of the PB1/A17 pin. 000: PB1 I/O (port) 001: A17 output (BSC) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 418 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0*2 Register PBCR2 PBCR2 Bit 1 0 Bit Name PB0MD1 PB0MD0 R/W R/W R/W Description PB0 Mode Select the function of the PB0/A16 pin. 00: PB0 I/O (port) 01: A16 output (BSC) 10: Setting prohibited 11: Setting prohibited Notes: 1. The initial value is 1 in 8-bit external extended mode with on-chip ROM enabled/disabled. 2. The initial value is 1 in 8-bit external extended mode with the on-chip ROM disabled. 14.1.5 Port D I/O Register L (PDIORL) PDIORL is a 16-bit readable/writable register that sets the pins on port D as inputs or outputs. Bits PD8IOR to PD0IOR correspond to pins PD8 to PD0 (names of multiplexed pins are here given as port names and pin numbers alone). PDIORL is enabled when the port D pins are functioning as general-purpose inputs/outputs (PD8 to PD0) and SCK2 pins are functioning as inputs/outputs of the SCI. In other states, PDIORL is disabled. A given pin on port D will be an output pin if the corresponding bit in PDIORL is set to 1, and an input pin if the bit is cleared to 0. Note that PDIORL is disabled in the SH7108. Bits 15 to 9 in PDIORL are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PDIORL is H'0000. 14.1.6 Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2) PDCRL1 and PDCRL2 are 16-bit readable/writable registers that select the multiplexed pin function of the pins on port D. Note that PDCRL1 and PDCRL2 are disabled in the SH7108. Rev.1.00 Sep. 18, 2008 Page 419 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) (1) Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2) in SH7109 Register PDCRL2 PDCRL1 PDCRL2 PDCRL1 Bit 15 to 9 15 to 9 8 8 Bit Name — — PD8MD1 PD8MD0 Initial Value All 0 All 0 0 0 R/W R R R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. PD8 Mode Select the function of the PD8 pin. 00: PD8 I/O (port) 01: Setting prohibited PDCRL2 PDCRL1 7 7 PD7MD1 PD7MD0 0 0*1 R/W R/W PD7 Mode Select the function of the PD7/D7 pin. 00: PD7 I/O (port) 01: D7 I/O (BSC)*2 PDCRL2 PDCRL1 6 6 PD6MD1 PD6MD0 0 0*1 R/W R/W PD6 Mode Select the function of the PD6/D6 pin. 00: PD6 I/O (port) 01: D6 I/O (BSC)*2 PDCRL2 PDCRL1 5 5 PD5MD1 PD5MD0 0 0* 1 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: Setting prohibited R/W R/W PD5 Mode Select the function of the PD5/D5 pin. 00: PD5 I/O (port) 01: D5 I/O (BSC)* 2 10: Setting prohibited 11: Setting prohibited PDCRL2 PDCRL1 4 4 PD4MD1 PD4MD0 0 0*1 R/W R/W PD4 Mode Select the function of the PD4/D4 pin. 00: PD4 I/O (port) 01: D4 I/O (BSC)*2 10: Setting prohibited 11: Setting prohibited PDCRL2 PDCRL1 3 3 PD3MD1 PD3MD0 0 0* 1 R/W R/W PD3 Mode Select the function of the PD3/D3 pin. 00: PD3 I/O (port) 01: D3 I/O (BSC)* 2 10: Setting prohibited 11: Setting prohibited PDCRL2 PDCRL1 2 2 PD2MD1 PD2MD0 0 0*1 R/W R/W PD2 Mode Select the function of the PD2/D2/SCK2 pin. 00: PD2 I/O (port) 01: D2 I/O (BSC)* 2 10: SCK2 I/O (SCI) 11: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 420 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0*1 Register PDCRL2 PDCRL1 Bit 1 1 Bit Name PD1MD1 PD1MD0 R/W R/W R/W Description PD1 Mode Select the function of the PD1/D1/TxD2 pin. 00: PD1 I/O (port) 01: D1 I/O (BSC)*2 10: TxD2 output (SCI) 11: Setting prohibited PDCRL2 PDCRL1 0 0 PD0MD1 PD0MD0 0 0* 1 R/W R/W PD0 Mode Select the function of the PD0/D0/RxD2 pin. 00: PD0 I/O (port) 01: D0 I/O (BSC)* 2 10: RxD2 input (SCI) 11: Setting prohibited Notes: 1. The initial value is 1 in 8-bit external extended mode with the on-chip ROM disabled. 2. When using the external buses, set D7 to D0 at input/output pins. 14.1.7 Port E I/O Registers L and H (PEIORL and PEIORH) PEIORL and PEIORH are 16-bit readable/writable registers that set the pins on port E as inputs or outputs. Bits PE21IOR to PE0IOR correspond to pins PE21 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PE0), TIOC pins are functioning as inputs/outputs of the MTU, and SCK2 and SCK3 pins are functioning as inputs/outputs of the SCI. In other states, PEIORL is disabled. PEIORH is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE21 to PE16). In other states, PEIORH is disabled. A given pin on port E will be an output pin if the corresponding PEIORL or PEIORH bit is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 6 in PEIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial values of PEIORL and PEIORH are H'0000. 14.1.8 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) PECRL1, PECRL2, and PECRH are 16-bit readable/writable registers that select the multiplexed pin function of the pins on port E. Rev.1.00 Sep. 18, 2008 Page 421 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) (1) Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) in SH7108 Register PECRH Bit 15 to 12 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. PECRH PECRH 11 10 PE21MD1 PE21MD0 0 0 R/W R/W PE21 Mode Select the function of the PE21/PWOB pin. 00: PE21 I/O (port) PECRH PECRH 9 8 PE20MD1 PE20MD0 0 0 R/W R/W PE20 Mode Select the function of the PE20/PVOB pin. 00: PE20 I/O (port) PECRH PECRH 7 6 PE19MD1 PE19MD0 0 0 R/W R/W PE19 Mode Select the function of the PE19/PUOB pin. 00: PE19 I/O (port) PECRH PECRH 5 4 PE18MD1 PE18MD0 0 0 R/W R/W PE18 Mode Select the function of the PE18/PWOA pin. 00: PE18 I/O (port) PECRH PECRH 3 2 PE17MD1 PE17MD0 0 0 R/W R/W PE17 Mode Select the function of the PE17/PVOA pin. 00: PE17 I/O (port) PECRH PECRH 1 0 PE16MD1 PE16MD0 0 0 R/W R/W PE16 Mode Select the function of the PE16/PUOA pin. 00: PE16 I/O (port) PECRL1 PECRL1 15 14 PE15MD1 PE15MD0 0 0 R/W R/W PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 00: PE15 I/O (port) 01: TIOC4D I/O (MTU) PECRL1 PECRL1 13 12 PE14MD1 PE14MD0 0 0 R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 00: PE14 I/O (port) 01: TIOC4C I/O (MTU) 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: IRQOUT output (INTC) 10: Setting prohibited 01: PUOA output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PVOA output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PWOA output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PUOB output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PVOB output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PWOB output (MMT) 11: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 422 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0 Register PECRL1 PECRL1 Bit 11 10 Bit Name PE13MD1 PE13MD0 R/W R/W R/W Description PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU) 10: MRES input (INTC) 11: Setting prohibited PECRL1 PECRL1 9 8 PE12MD1 PE12MD0 0 0 R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 00: PE12 I/O (port) 01: TIOC4A I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 7 6 PE11MD1 PE11MD0 0 0 R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 00: PE11 I/O (port) 01: TIOC3D I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 5 4 PE10MD1 PE10MD0 0 0 R/W R/W PE10 Mode Select the function of the PE10/TIOC3C/TxD2 pin. 00: PE10 I/O (port) 01: TIOC3C I/O (MTU) 10: TxD2 output (SCI) 11: Setting prohibited PECRL1 PECRL1 3 2 PE9MD1 PE9MD0 0 0 R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 00: PE9 I/O (port) 01: TIOC3B I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 1 0 PE8MD1 PE8MD0 0 0 R/W R/W PE8 Mode Select the function of the PE8/TIOC3A/SCK2 pin. 00: PE8 I/O (port) 01: TIOC3A I/O (MTU) 10: SCK2 I/O (SCI) 11: Setting prohibited PECRL2 PECRL2 15 14 PE7MD1 PE7MD0 0 0 R/W R/W PE7 Mode Select the function of the PE7/TIOC2B/RxD2 pin. 00: PE7 I/O (port) 01: TIOC2B I/O (MTU) 10: RxD2 input (SCI) 11: Setting prohibited PECRL2 PECRL2 13 12 PE6MD1 PE6MD0 0 0 R/W R/W PE6 Mode Select the function of the PE6/TIOC2A/SCK3 pin. 00: PE6 I/O (port) 01: TIOC2A I/O (MTU) 10: SCK3 I/O (SCI) 11: Setting prohibited PECRL2 PECRL2 11 10 PE5MD1 PE5MD0 0 0 R/W R/W PE5 Mode Select the function of the PE5/TIOC1B/TxD3 pin. 00: PE5 I/O (port) 01: TIOC1B I/O (MTU) 10: TxD3 output (SCI) 11: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 423 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0 Register PECRL2 PECRL2 Bit 9 8 Bit Name PE4MD1 PE4MD0 R/W R/W R/W Description PE4 Mode Select the function of the PE4/TIOC1A/RxD3 pin. 00: PE4 I/O (port) 01: TIOC1A I/O (MTU) 10: RxD3 input (SCI) 11: Setting prohibited PECRL2 PECRL2 7 6 PE3MD1 PE3MD0 0 0 R/W R/W PE3 Mode Select the function of the PE3/TIOC0D pin. 00: PE3 I/O (port) 01: TIOC0D I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 5 4 PE2MD1 PE2MD0 0 0 R/W R/W PE2 Mode Select the function of the PE2/TIOC0C pin. 00: PE2 I/O (port) 01: TIOC0C I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 3 2 PE1MD1 PE1MD0 0 0 R/W R/W PE1 Mode Select the function of the PE1/TIOC0B pin. 00: PE1 I/O (port) 01: TIOC0B I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 1 0 PE0MD1 PE0MD0 0 0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU) 10: Setting prohibited 11: Setting prohibited Rev.1.00 Sep. 18, 2008 Page 424 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) (2) Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) in SH7109 Register PECRH Bit 15 to 12 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. PECRH PECRH 11 10 PE21MD1 PE21MD0 0* 0* R/W R/W PE21 Mode Select the function of the PE21/PWOB/A15 pin. 00: PE21 I/O (port) PECRH PECRH 9 8 PE20MD1 PE20MD0 0* 0* R/W R/W PE20 Mode Select the function of the PE20/PVOB/A14 pin. 00: PE20 I/O (port) 01: PVOB output (MMT) PECRH PECRH 7 6 PE19MD1 PE19MD0 0* 0* R/W R/W PE19 Mode Select the function of the PE19/PUOB/A13 pin. 00: PE19 I/O (port) PECRH PECRH 5 4 PE18MD1 PE18MD0 0* 0* R/W R/W PE18 Mode Select the function of the PE18/PWOA/A12 pin. 00: PE18 I/O (port) PECRH PECRH 3 2 PE17MD1 PE17MD0 0* 0* R/W R/W PE17 Mode Select the function of the PE17/PVOA/WAIT/A11 pin. 00: PE17 I/O (port) PECRH PECRH 1 0 PE16MD1 PE16MD0 0* 0* R/W R/W PE16 Mode Select the function of the PE16/PUOA/A10 pin. 00: PE16 I/O (port) PECRL1 PECRL1 15 14 PE15MD1 PE15MD0 0 0 R/W R/W PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 00: PE15 I/O (port) 01: TIOC4D I/O (MTU) PECRL1 PECRL1 13 12 PE14MD1 PE14MD0 0 0 R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 00: PE14 I/O (port) 01: TIOC4C I/O (MTU) 10: Setting prohibited 11: Setting prohibited 10: Setting prohibited 11: IRQOUT output (INTC) 10: Setting prohibited 01: PUOA output (MMT) 11: A10 output (BSC) 10: WAIT input (BSC) 01: PVOA output (MMT) 11: A11 output (BSC) 10: Setting prohibited 01: PWOA output (MMT) 11: A12 output (BSC) 10: Setting prohibited 01: PUOB output (MMT) 11: A13 output (BSC) 10: Setting prohibited 11: A14 output (BSC) 10: Setting prohibited 01: PWOB output (MMT) 11: A15 output (BSC) Rev.1.00 Sep. 18, 2008 Page 425 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0 0 Register PECRL1 PECRL1 Bit 11 10 Bit Name PE13MD1 PE13MD0 R/W R/W R/W Description PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU) 10: MRES input (INTC) 11: Setting prohibited PECRL1 PECRL1 9 8 PE12MD1 PE12MD0 0 0 R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 00: PE12 I/O (port) 01: TIOC4A I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 7 6 PE11MD1 PE11MD0 0 0 R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 00: PE11 I/O (port) 01: TIOC3D I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 5 4 PE10MD1 PE10MD0 0* 0* R/W R/W PE10 Mode Select the function of the PE10/TIOC3C/TxD2/WRL pin. 00: PE10 I/O (port) 01: TIOC3C I/O (MTU) 10: TxD2 output (SCI) 11: WRL output (BSC) PECRL1 PECRL1 3 2 PE9MD1 PE9MD0 0 0 R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 00: PE9 I/O (port) 01: TIOC3B I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL1 PECRL1 1 0 PE8MD1 PE8MD0 0 0 R/W R/W PE8 Mode Select the function of the PE8/TIOC3A/SCK2 pin. 00: PE8 I/O (port) 01: TIOC3A I/O (MTU) 10: SCK2 I/O (SCI) 11: Setting prohibited PECRL2 PECRL2 15 14 PE7MD1 PE7MD0 0* 0* R/W R/W PE7 Mode Select the function of the PE7/TIOC2B/RxD2/A9 pin. 00: PE7 I/O (port) 01: TIOC2B I/O (MTU) 10: RxD2 input (SCI) 11: A9 output (BSC) PECRL2 PECRL2 13 12 PE6MD1 PE6MD0 0* 0* R/W R/W PE6 Mode Select the function of the PE6/TIOC2A/SCK3/A8 pin. 00: PE6 I/O (port) 01: TIOC2A I/O (MTU) 10: SCK3 I/O (SCI) 11: A8 output (BSC) PECRL2 PECRL2 11 10 PE5MD1 PE5MD0 0* 0* R/W R/W PE5 Mode Select the function of the PE5/TIOC1B/TxD3/A7 pin. 00: PE5 I/O (port) 01: TIOC1B I/O (MTU) 10: TxD3 output (SCI) 11: A7 output (BSC) Rev.1.00 Sep. 18, 2008 Page 426 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Initial Value 0* 0* Register PECRL2 PECRL2 Bit 9 8 Bit Name PE4MD1 PE4MD0 R/W R/W R/W Description PE4 Mode Select the function of the PE4/TIOC1A/RxD3/A6 pin. 00: PE4 I/O (port) 01: TIOC1A I/O (MTU) 10: RxD3 input (SCI) 11: A6 output (BSC) PECRL2 PECRL2 7 6 PE3MD1 PE3MD0 0 0 R/W R/W PE3 Mode Select the function of the PE3/TIOC0D pin. 00: PE3 I/O (port) 01: TIOC0D I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 5 4 PE2MD1 PE2MD0 0 0 R/W R/W PE2 Mode Select the function of the PE2/TIOC0C pin. 00: PE2 I/O (port) 01: TIOC0C I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 3 2 PE1MD1 PE1MD0 0 0 R/W R/W PE1 Mode Select the function of the PE1/TIOC0B pin. 00: PE1 I/O (port) 01: TIOC0B I/O (MTU) 10: Setting prohibited 11: Setting prohibited PECRL2 PECRL2 1 0 PE0MD1 PE0MD0 0* 0* R/W R/W PE0 Mode Select the function of the PE0/TIOC0A/CS0 pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU) 10: Setting prohibited 11: CS0 output (BSC) Note: * The initial value is 1 in 8-bit external extended mode with the on-chip ROM disabled. 14.2 Usage Note In this LSI, individual functions are available as multiplexed functions on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. When the pin function controller (PFC) is used to select a function, only a single pin can be specified for each function. If one function is specified for two or more pins, the function will not work properly. Rev.1.00 Sep. 18, 2008 Page 427 of 522 REJ09B0069-0100 Section 14 Pin Function Controller (PFC) Rev.1.00 Sep. 18, 2008 Page 428 of 522 REJ09B0069-0100 Section 15 I/O Ports Section 15 I/O Ports The SH7108 has five ports: A, B, E, F, and G. Port A is a 16-bit port, port B is a 4-bit port, and port E is a 22-bit port, all supporting both input and output. Port F is an 8-bit port and port G is a 4-bit port, both for input-only. The SH7109 has five ports: A, B, D, E, and F. Port A is a 16-bit port, port B is a 6-bit port, port D is a 9-bit port, and port E is a 22-bit port, all supporting both input and output. Port F is a 16-bit input-only port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. 15.1 Port A Port A in the SH7108 is an input/output port with the 16 pins shown in figure 15.1. PA15 (I/O) / PA14 (I/O) / PA13 (I/O) / PA12 (I/O) PA11 (I/O) / (input) / SCK3 (I/O) (input) (input) (input) PA10 (I/O) / SCK2 (I/O) PA9 (I/O) / TCLKD (input)/ TxD3 (output) Port A PA8 (I/O) / TCLKC (input) / RxD3 (input) PA7 (I/O) / TCLKB (input) / TxD2 (output) PA6 (I/O) / TCLKA (input) / RxD2 (input) PA5 (I/O) / (input) / SCK3 (I/O) PA4 (I/O) / TXD3 (output) PA3 (I/O) / PA2 (I/O) / PA1 (I/O) / PA0 (I/O) / (input) / RxD3 (input) (input) / PCIO (I/O) / SCK2 (I/O) (input) / TxD2 (output) (input) / RxD2 (input) Figure 15.1 Port A (SH7108) Rev.1.00 Sep. 18, 2008 Page 429 of 522 REJ09B0069-0100 Section 15 I/O Ports Port A in the SH7109 is an input/output port with the 16 pins shown in figure 15.2. PA15 (I/O) / CK (output) / PA14 (I/O) / PA13 (I/O) / PA12 (I/O) / PA11 (I/O) / PA10 (I/O) / (output) / (input) / (output) (input) / SCK3 (I/O) (output) / SCK2 (I/O) (input) / (input) (input) (output) PA9 (I/O) / TCLKD (input) / TxD3 (output) Port A PA8 (I/O) / TCLKC (input) / RxD3 (input) PA7 (I/O) / TCLKB (input) / PA6 (I/O) / TCLKA (input) / PA5 (I/O) / (input) / TxD2 (output) (output) / RxD2 (input) (input) / A5 (output) / SCK3 (I/O) PA4 (I/O) / A4 (output) / TxD3 (output) PA3 (I/O) / A3 (output) / RxD3 (input) PA2 (I/O) / (input) / A2 (output) / PCIO (I/O) / SCK2 (I/O) (input) / TxD2 (output) (input) / RxD2 (input) PA1 (I/O) / A1 (output) / PA0 (I/O) / A0 (output) / Figure 15.2 Port A (SH7109) 15.1.1 Register Description Port A is a 16-bit input/output port. Port A has the following register. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Port A data register L (PADRL) Rev.1.00 Sep. 18, 2008 Page 430 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.1.2 Port A Data Register L (PADRL) PADRL is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRL, although that value is written into PADRL, it does not affect the pin state. Table 15.1 summarizes port A data register L read/write operations. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 15.1. Rev.1.00 Sep. 18, 2008 Page 431 of 522 REJ09B0069-0100 Section 15 I/O Ports Table 15.1 Port A Data Register L (PADRL) Read/Write Operations • Bits 15 to 0 PAIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADRL value PADRL value Write Can write to PADRL, but it has no effect on pin state Can write to PADRL, but it has no effect on pin state Value written is output from pin Can write to PADRL, but it has no effect on pin state 15.2 Port B Port B in the SH7108 is an input/output port with the four pins shown in figure 15.3. PB5 (I/O) / PB4 (I/O) / Port B PB3 (I/O) / PB2 (I/O) / (input) / (input) / (input) (input) (input) / (input) / (input) (input) Figure 15.3 Port B (SH7108) Port B in the SH7109 is an input/output port with the six pins shown in figure 15.4. PB5 (I/O) / PB4 (I/O) / Port B PB3 (I/O) / PB2 (I/O) / (input) / (input) / (input) / (input) / (input) / CK (output) (input) (input) (input) PB1 (I/O) / A17 (output) PB0 (I/O) / A16 (output) Figure 15.4 Port B (SH7109) Rev.1.00 Sep. 18, 2008 Page 432 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.2.1 Register Description Port B is a 4-bit input/output port in the SH7108 and a 6-bit input/output port in the SH7109. Port B has the following register. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Port B data register (PBDR) 15.2.2 Port B Data Register (PBDR) PBDR is a 16-bit readable/writable register that stores port B data. In the SH7108, bits PB5DR to PB2DR correspond to pins PB5 to PB2 (multiplexed functions omitted here). In the SH7109, bits PB5DR to PB0DR correspond to pins PB5 to PB0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PBDR is read, the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR, it does not affect the pin state. Table 15.2 summarizes port B data register read/write operations. Bit 15 to 6 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 Note: * PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0/1 0/1 R/W R/W R/W R/W R/W R/W See table 15.2.* See table 15.2. These bits are reserved in the SH7108. They have no corresponding pins. The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 433 of 522 REJ09B0069-0100 Section 15 I/O Ports Table 15.2 Port B Data Register (PBDR) Read/Write Operations • Bits 5 to 0 PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Can write to PBDR, but it has no effect on pin state Can write to PBDR, but it has no effect on pin state Value written is output from pin Can write to PBDR, but it has no effect on pin state 15.3 Port D Port D that can only be used in the SH7109 is an input/output port with the nine pins shown in figure 15.5. PD8 (I/O) PD7 (I/O) / D7 (I/O) PD6 (I/O) / D6 (I/O) PD5 (I/O) / D5 (I/O) Port D PD4 (I/O) / D4 (I/O) PD3 (I/O) / D3 (I/O) PD2 (I/O) / D2 (I/O) / SCK2 (I/O) PD1 (I/O) / D1 (I/O) / TxD2 (output) PD0 (I/O) / D0 (I/O) / RxD2 (input) Figure 15.5 Port D (SH7109) 15.3.1 Register Description Port D has the following register. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Port D data register L (PDDRL) Rev.1.00 Sep. 18, 2008 Page 434 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.3.2 Port D Data Register L (PDDRL) PDDRL is a 16-bit readable/writable register that stores port D data. Bits PD8DR to PD0DR correspond to pins PD8 to PD0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PDDRL, that value is output directly from the pin, and if PDDRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PDDRL is read, the pin state, not the register value, is returned directly. If a value is written to PDDRL, although that value is written into PDDRL, it does not affect the pin state. Table 15.3 summarizes port D data register L read/write operations. Bit 15 to 9 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 8 7 6 5 4 3 2 1 0 PD8DR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W See table 15.3. Table 15.3 Port D Data Register L (PDDRL) Read/Write Operations • Bits 8 to 0 PDIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PDDRL value PDDRL value Write Can write to PDDRL, but it has no effect on pin state Can write to PDDRL, but it has no effect on pin state Value written is output from pin Can write to PDDRL, but it has no effect on pin state Rev.1.00 Sep. 18, 2008 Page 435 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.4 Port E Port E in the SH7108 is an input/output port with the 22 pins shown in figure 15.6. PE21 (I/O) / PWOB (output) PE20 (I/O) / PVOB (output) PE19 (I/O) / PUOB (output) PE18 (I/O) / PWOA (output) PE17 (I/O) / PVOA (output) PE16 (I/O) / PUOA (output) PE15 (I/O) / TIOC4D (I/O) / PE14 (I/O) / TIOC4C (I/O) PE13 (I/O) / TIOC4B (I/O) / Port E PE12 (I/O) / TIOC4A (I/O) PE11 (I/O) / TIOC3D (I/O) PE10 (I/O) / TIOC3C (I/O) / TxD2 (output) PE9 (I/O) / TIOC3B (I/O) PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O) PE7 (I/O) / TIOC2B (I/O) / RxD2 (input) PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O) PE5 (I/O) / TIOC1B (I/O) / TxD3 (output) PE4 (I/O) / TIOC1A (I/O) / RxD3 (input) PE3 (I/O) / TIOC0D (I/O) PE2 (I/O) / TIOC0C (I/O) PE1 (I/O) / TIOC0B (I/O) PE0 (I/O) / TIOC0A (I/O) (input) (output) Figure 15.6 Port E (SH7108) Port E in the SH7109 is an input/output port with the 22 pins shown in figure 15.7. Rev.1.00 Sep. 18, 2008 Page 436 of 522 REJ09B0069-0100 Section 15 I/O Ports PE21 (I/O) / PWOB (output) / A15 (output) PE20 (I/O) / PVOB (output) /A14 (output) PE19 (I/O) / PUOB (output) /A13 (output) PE18 (I/O) / PWOA (output) / A12 (output) PE17 (I/O) / PVOA (output) / (input) / A11 (output) PE16 (I/O) / PUOA (output) / A10 (output) PE15 (I/O) / TIOC4D (I/O) / PE14 (I/O) / TIOC4C (I/O) PE13 (I/O) / TIOC4B (I/O) / Port E PE12 (I/O) / TIOC4A (I/O) PE11 (I/O) / TIOC3D (I/O) PE10 (I/O) / TIOC3C (I/O) / TxD2 (output) / PE9 (I/O) / TIOC3B (I/O) PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O) PE7 (I/O) / TIOC2B (I/O) / RxD2 (input) / A9 (output) PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O) / A8 (output) PE5 (I/O) / TIOC1B (I/O) / TxD3 (output) / A7 (output) PE4 (I/O) / TIOC1A (I/O) / RxD3 (input) / A6 (output) PE3 (I/O) / TIOC0D (I/O) PE2 (I/O) / TIOC0C (I/O) PE1 (I/O) / TIOC0B (I/O) PE0 (I/O) / TIOC0A (I/O) / (output) (output) (input) (output) Figure 15.7 Port E (SH7109) 15.4.1 Register Descriptions Port E has the following registers. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Port E data register H (PEDRH) • Port E data register L (PEDRL) Rev.1.00 Sep. 18, 2008 Page 437 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.4.2 Port E Data Registers H and L (PEDRH and PEDRL) PEDRH and PEDRL are 16-bit readable/writable registers that store port E data. Bits PE21DR to PE0DR correspond to pins PE21 to PE0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PEDRH or PEDRL, that value is output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PEDRH or PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is written into PEDRH or PEDRL it does not affect the pin state. Table 15.4 summarizes port E data register read/write operations. • PEDRH Bit 15 to 6 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 PE21DR PE20DR PE19DR PE18DR PE17DR PE16DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W See table 15.4. Rev.1.00 Sep. 18, 2008 Page 438 of 522 REJ09B0069-0100 Section 15 I/O Ports • PEDRL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 15.4. Table 15.4 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations • Bits 5 to 0 in PEDRH and bits 15 to 0 in PEDRL PEIOR 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state PEDRH or PEDRL value PEDRH or PEDRL value Write Can write to PEDRH or PEDRL, but it has no effect on pin state Can write to PEDRH or PEDRL, but it has no effect on pin state Value written is output from pin (POE pin = high)* High impedance regardless of PEDRH or PEDRL value (POE pin = low)* Can write to PEDRH or PEDRL, but it has no effect on pin state Other than general output Note: * Control by the POE pin is only available for large current-output pins (PE9 and PE11 to PE21). Rev.1.00 Sep. 18, 2008 Page 439 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.5 Port F Port F in the SH7108 is an input-only port with the eight pins shown in figure 15.8. PF15 (input) / AN15 (input) PF14 (input) / AN14 (input) PF13 (input) / AN13 (input) Port F PF12 (input) / AN12 (input) PF11 (input) / AN11 (input) PF10 (input) / AN10 (input) PF9 (input) / AN9 (input) PF8 (input) / AN8 (input) Figure 15.8 Port F (SH7108) Port F in the SH7109 is an input-only port with the 16 pins shown in figure 15.9. PF15 (input) / AN15 (input) PF14 (input) / AN14 (input) PF13 (input) / AN13 (input) PF12 (input) / AN12 (input) PF11 (input) / AN11 (input) PF10 (input) / AN10 (input) PF9 (input) / AN9 (input) Port F PF8 (input) / AN8 (input) PF7 (input) / AN7 (input) PF6 (input) / AN6 (input) PF5 (input) / AN5 (input) PF4 (input) / AN4 (input) PF3 (input) / AN3 (input) PF2 (input) / AN2 (input) PF1 (input) / AN1 (input) PF0 (input) / AN0 (input) Figure 15.9 Port F (SH7109) Rev.1.00 Sep. 18, 2008 Page 440 of 522 REJ09B0069-0100 Section 15 I/O Ports 15.5.1 Register Description Port F is an 8-bit input-only port in the SH7108 and a 16-bit input-only port in the SH7109. Port F has the following register. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Port F data register (PFDR) 15.5.2 Port F Data Register (PFDR) PFDR is a 16-bit read-only register that stores port F data. In the SH7108, bits PF15DR to PF8DR correspond to pins PF15 to PF8 (multiplexed functions omitted here). In the SH7109, bits PF15DR to PF0DR correspond to pins PF15 to PF0 (multiplexed functions omitted here). Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read. Table 15.5 summarizes port F data register read/write operations. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PF15DR PF14DR PF13DR PF12DR PF11DR PF10DR PF9DR PF8DR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial Value 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R R R R R R R R R R R R R R R R Description See table 15.5. See table 15.5.* 2 Notes: 1. Initial values are dependent on the state of the external pins. 2. These bits are reserved in the SH7108. The write value should always be 0. Rev.1.00 Sep. 18, 2008 Page 441 of 522 REJ09B0069-0100 Section 15 I/O Ports Table 15.5 Port F Data Register (PFDR) Read/Write Operations • Bits 15 to 8 in SH7108 and bits 15 to 0 in SH7109 Pin Function General input ANn input Read Pin state 1 Write Ignored (no effect on pin state) Ignored (no effect on pin state) 15.6 Port G Port G that can only be used in the SH7108 is an input-only port with the four pins shown in figure 15.10. PG3 (input) / AN19 (input) PG2 (input) / AN18 (input) Port G PG1 (input) / AN17 (input) PG0 (input) / AN16 (input) Figure 15.10 Port G (SH7108) 15.6.1 Register Description Port G is a 4-bit input-only port. Port G has the following register. For details on register addresses and register states during each processing, refer to section 19, List of Registers. • Port G data register (PGDR) 15.6.2 Port G Data Register (PGDR) PGDR is an 8-bit read-only register that stores port G data. Bits PG3DR to PG0DR correspond to pins PG3 to PG0 (multiplexed functions omitted here). Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read. Table 15.6 summarizes port G data register read/write operations. Rev.1.00 Sep. 18, 2008 Page 442 of 522 REJ09B0069-0100 Section 15 I/O Ports Bit Bit Name Initial Value All 0 0/1* 0/1* 0/1* 0/1* R/W R R R R R Description Reserved These bits are always read as 0. See table 15.6. 7 to 4 — 3 2 1 0 Note: PG3DR PG2DR PG1DR PG0DR * Initial values are dependent on the state of the external pins. Table 15.6 Port G Data Register (PGDR) Read/Write Operations • Bits 3 to 0 Pin Function General input ANn input Read Pin state 1 Write Ignored (no effect on pin state) Ignored (no effect on pin state) Rev.1.00 Sep. 18, 2008 Page 443 of 522 REJ09B0069-0100 Section 15 I/O Ports Rev.1.00 Sep. 18, 2008 Page 444 of 522 REJ09B0069-0100 Section 16 Masked ROM Section 16 Masked ROM This LSI is available with 64 kbytes or 128 kbytes of on-chip masked ROM. The on-chip ROM is connected to the CPU through a 32-bit data bus (figures 16.1 and 16.2). The CPU can access the on-chip ROM in 8, 16, or 32-bit width. Data in the on-chip ROM can always be accessed in one cycle. Internal data bus (32 bits) H'00000000 H'00000004 H'00000001 H'00000005 H'00000002 H'00000006 H'00000003 H'00000007 On-chip ROM H'0000FFFC H'0000FFFD H'0000FFFE H'0000FFFF Figure 16.1 Masked ROM Block Diagram (SH7106/SH7107) Internal data bus (32 bits) H'00000000 H'00000004 H'00000001 H'00000005 H'00000002 H'00000006 H'00000003 H'00000007 On-chip ROM H'0001FFFC H'0001FFFD H'0001FFFE H'0001FFFF Figure 16.2 Masked ROM Block Diagram (SH7108/SH7109) Rev.1.00 Sep. 18, 2008 Page 445 of 522 REJ09B0069-0100 Section 16 Masked ROM The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins FWP and MD3 to MD0 as shown in table 3.1. When the on-chip ROM is used, select mode 2 or mode 3; if not, select mode 0. The on-chip ROM is allocated to addresses H'00000000 to H'0000FFFF of memory area 0 (in the SH7106/SH7107) or H'00000000 to H'0001FFFF of memory area 0 (in the SH7108/SH7109). 16.1 Usage Note • Setting module standby mode For masked ROM, this module can be disabled/enabled by the module standby control register. Masked ROM operation is enabled for the initial value. Accessing masked ROM is disabled by setting module standby mode. For details, refer to section 18, Power-Down Modes. Rev.1.00 Sep. 18, 2008 Page 446 of 522 REJ09B0069-0100 Section 17 RAM Section 17 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU via a 32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the onchip RAM can always be accessed in one cycle, providing high-speed access that makes this RAM ideal for use as a program area, stack area, or data area. The contents of the on-chip RAM are retained in both sleep and software standby modes. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 18.2.2, System Control Register (SYSCR). Product Type SH7108 Type of ROM Masked ROM RAM Capacity 4 kbytes RAM Address H'FFFFF000 to H'FFFFFFFF 17.1 Usage Note • Module Standby Mode Setting RAM can be enabled or disabled by the module standby control register. The initial value enables RAM operation. RAM access is disabled by setting module standby mode. For details, refer to section 18, Power-Down Modes. Rev.1.00 Sep. 18, 2008 Page 447 of 522 REJ09B0069-0100 Section 17 RAM Rev.1.00 Sep. 18, 2008 Page 448 of 522 REJ09B0069-0100 Section 18 Power-Down Modes Section 18 Power-Down Modes In addition to the normal program execution state, this LSI has four power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral functions, and so on. This LSI's power-down modes are as follows: • Sleep mode • Software standby mode • Hardware standby mode • Module standby mode Sleep mode indicates the state of the CPU, and module standby mode indicates the state of the onchip peripheral function (including the bus master other than the CPU). Some of these states can be combined. After a reset, this LSI is in normal operating mode. Table 18.1 lists internal operation states in each mode. Rev.1.00 Sep. 18, 2008 Page 449 of 522 REJ09B0069-0100 Section 18 Power-Down Modes Table 18.1 Internal Operating States in Each Mode Function System clock pulse generator CPU Normal operation Functioning Sleep Functioning Halted (retained) Functioning Module Standby Functioning Functioning Functioning Software Standby Halted Halted (retained) Functioning Hardware Standby Halted Halted (undefined) Halted Instructions Functioning Registers Functioning External interrupts NMI IRQ3 to IRQ0 Peripheral I/O ports functions WDT SCI A/D MTU CMT MMT ROM RAM Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Retained Halted (retained) High impedance Halted (reset) Halted (reset) Halted (reset) Halted (reset) Functioning Functioning Functioning Functioning Halted (reset) Halted (reset) Halted (reset) Retained Retained Retained Notes: "Halted (retained)" means that the operation of the internal state is suspended, although internal register values are retained. "Halted (reset)" means that internal register values and internal state are initialized. In module standby mode, only modules for which a stop setting has been made are halted (reset or retained). 1. There are two types of on-chip peripheral module registers; ones which are initialized in software standby mode and module standby mode, and those not initialized in those modes. For details, refer to section 19.3, Register States in Each Operating Mode. 2. The port high-impedance bit (Hi-Z) in SBYCR sets the state of the I/O ports in software standby mode. For details on the setting, refer to section 18.2.1, Standby Control Register (SBYCR). For the state of pins, refer to appendix A, Pin States. Rev.1.00 Sep. 18, 2008 Page 450 of 522 REJ09B0069-0100 Section 18 Power-Down Modes Program-halted state pin = Low Reset state Hardware standby mode pin = High pin = Low pin = High Program execution state SLEEP instruction SSBY = 0 Sleep mode (main clock) Normal operation mode (main clock) SLEEP instruction External interrupt * SSBY = 1 Software standby mode : Transition after exception handling Notes: * : Power-down mode NMI and IRQ When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. In any state except hardware standby mode, a transition to the reset state occurs when is driven low. In any state, a transition to hardware standby mode occurs when is driven low. Figure 18.1 Mode Transition Diagram Rev.1.00 Sep. 18, 2008 Page 451 of 522 REJ09B0069-0100 Section 18 Power-Down Modes 18.1 Input/Output Pins Table 18.2 lists the pins relating to power-down mode. Table 18.2 Pin Configuration Pin Name HSTBY RES MRES I/O Input Input Input Function Hardware standby input pin Power-on reset input pin Manual reset input pin 18.2 Register Descriptions Registers related to power-down modes are shown below. For details on register addresses and register states during each process, refer to section 19, List of Registers. • Standby control register (SBYCR) • System control register (SYSCR) • Module standby control register 1 (MSTCR1) • Module standby control register 2 (MSTCR2) Rev.1.00 Sep. 18, 2008 Page 452 of 522 REJ09B0069-0100 Section 18 Power-Down Modes 18.2.1 Standby Control Register (SBYCR) SBYCR is an 8-bit readable/writable register that performs software standby mode control. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Specifies the transition mode after executing the SLEEP instruction. 0: Transition to sleep mode after the SLEEP instruction has been executed 1: Transition to software standby mode after the SLEEP instruction has been executed This bit cannot be set to 1 when the watchdog timer (WDT) is operating (when the TME bit in TCSR of the WDT is set to 1). When entering software standby mode, clear the TME bit to 0, stop the WDT, then set the SSBY bit to 1. 6 HIZ 0 R/W Port High-Impedance In software standby mode, this bit selects whether the pin state of the I/O port is retained or changed to highimpedance. 0: In software standby mode, the pin state is retained. 1: In software standby mode, the pin state is changed to high-impedance. The HIZ bit cannot be set to 1 when the TEM bit in TCSR of the WDT is set to 1. When changing the pin state of the I/O port to highimpedance, clear the TEM bit to 0, then set the HIZ bit to 1. 5 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 4 to 1 ⎯ All 1 R Reserved These bits are always read as 1. The write value should always be 1. 0 IRQEL 1 R/W IRQ3 to IRQ0 Enable Enables to clear software standby mode by IRQ interrupts. 0: Software standby mode is cleared. 1: Software standby mode is not cleared. Rev.1.00 Sep. 18, 2008 Page 453 of 522 REJ09B0069-0100 Section 18 Power-Down Modes 18.2.2 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM. Bit 7, 6 Bit Name ⎯ Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled When this bit is cleared to 0, the access to the on-chip RAM is disabled. In this case, an undefined value is returned when reading or fetching the data or instruction from the on-chip RAM, and writing to the on-chip RAM is ignored. When RAME is cleared to 0 to disable the on-chip RAM, an instruction to access the on-chip RAM should not be set next to the instruction to write to SYSCR. If such an instruction is set, normal access is not guaranteed. When RAME is set to 1 to enable the on-chip RAM, an instruction to read SYSCR should be set next to the instruction to write to SYSCR. If an instruction to access the on-chip RAM is set next to the instruction to write to SYSCR, normal access is not guaranteed. 18.2.3 Module Standby Control Registers 1 and 2 (MSTCR1 and MSTCR2) MSTCR is two 16-bit readable/writable registers that perform module standby mode control. Setting a bit to 1, the corresponding module enters module standby mode, while clearing the bit to 0 clears module standby mode. Rev.1.00 Sep. 18, 2008 Page 454 of 522 REJ09B0069-0100 Section 18 Power-Down Modes • MSTCR1 Bit Initial Bit Name Value All 1 R/W R/W Description Reserved These bits are always read as 1. The write value should always be 1. 11 10 9 to 6 MSTP27 MSTP26 ⎯ 0 0 All 0 R/W R/W R On-chip RAM On-chip ROM Reserved These bits are always read as 0. The write value should always be 0. 5, 4 ⎯ All 1 R Reserved These bits are always read as 1. The write value should always be 1. 3 2 1, 0 MSTP19 MSTP18 ⎯ 1 1 All 1 R/W R/W R Serial communication interface 3 (SCI_3) Serial communication interface 2 (SCI_2) Reserved These bits are always read as 1. The write value should always be 1. 15 to 12 ⎯ Rev.1.00 Sep. 18, 2008 Page 455 of 522 REJ09B0069-0100 Section 18 Power-Down Modes • MSTCR2 Bit 15 Bit Name ⎯ Initial Value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. Motor management timer (MMT) Multifunction timer pulse unit (MTU) Compare match timer (CMT) Reserved These bits are always read as 0. The write value should always be 0 Reserved This bit is always read as 1. The write value should always be 1. A/D converter (A/D2) A/D converter (A/D1) A/D converter (A/D0) Reserved These bits are always read as 0. The write value should always be 0. 14 13 12 11 to 8 MSTP14 MSTP13 MSTP12 ⎯ 1 1 1 All 0 R/W R/W R/W R 7 ⎯ 1 R 6 5 4 3 to 0 MSTP6 MSTP5 MSTP4 ⎯ 1 1 1 All 0 R/W R/W R/W R 18.3 18.3.1 Operation Sleep Mode (1) Transition to Sleep Mode If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers are retained. Peripheral functions except the CPU do not stop. (2) Clearing Sleep Mode Sleep mode is cleared by the conditions below. • Clearing by a power-on reset When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven high after the elapse of the specified reset input period, the CPU starts the reset exception handling. Rev.1.00 Sep. 18, 2008 Page 456 of 522 REJ09B0069-0100 Section 18 Power-Down Modes When an internal power-on reset by the WDT occurs, sleep mode is also cleared. • Clearing by a manual reset When the MRES pin is driven low while the RES pin goes high, the CPU shifts to the manual reset state and thus sleep mode is cleared. When an internal manual reset by the WDT occurs, sleep mode is also cleared. 18.3.2 Software Standby Mode (1) Transition to Software Standby Mode A transition is made to software standby mode if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In this mode, the CPU, on-chip peripheral functions, and oscillator, all stop. However, the contents of the CPU's internal registers and on-chip RAM data (when the RAME bit in SYSCR is 0) are retained as long as the specified voltage is supplied. There are two types of onchip peripheral module registers; ones which are initialized by software standby mode, and those not initialized by that mode. For details, refer to section 19.3, Register States in Each Operating Mode. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port either to "retained" or "high-impedance". For the state of pins, refer to appendix A, Pin States. In software standby mode, the oscillator stops and thus power consumption is significantly reduced. Rev.1.00 Sep. 18, 2008 Page 457 of 522 REJ09B0069-0100 Section 18 Power-Down Modes (2) Clearing Software Standby Mode Software standby mode is cleared by the condition below. • Clearing by the NMI interrupt input When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started. This clock pulse is supplied only to the watchdog timer (WDT). After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and the NMI exception handling is started. When clearing software standby mode by the NMI interrupt, set the CKS2 to CKS0 bits so that the WDT overflow period will be longer than the oscillation stabilization time. When software standby mode is cleared by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from standby mode (when the clock is initiated after the oscillation stabilization). When software standby mode is cleared by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). • Clearing by the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset exception handling. • Clearing by the IRQ interrupt input When the IRQEL bit in the standby control register (SBYCR) is set to 1 and when the falling edge or rising edge of the IRQ pin (selected by the IRQ3S to IRQ0S bits in ICR1 of the interrupt controller (INTC) and the IRQ3ES[1:0] to IRQ0ES[1:0] bits in ICR2) is detected, clock oscillation is started.* This clock pulse is supplied only to the watchdog timer (WDT). The IRQ interrupt priority level should be higher than the interrupt mask level set in the status register (SR) of the CPU before the transition to software standby mode. Rev.1.00 Sep. 18, 2008 Page 458 of 522 REJ09B0069-0100 Section 18 Power-Down Modes After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and the IRQ exception handling is started. When clearing software standby mode by the IRQ interrupt, set the CKS2 to CKS0 bits so that the WDT overflow period will be longer than the oscillation stabilization time. When software standby mode is cleared by the falling edge or both edges of the IRQ pin, the IRQ pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). When software standby mode is cleared by the rising edge of the IRQ pin, the IRQ pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). Note: * When the IRQ pin is set to falling-edge detection or both-edge detection, clock oscillation starts at falling-edge detection. When the IRQ pin is set to rising-edge detection, clock oscillation starts at rising-edge detection. Do not set the IRQ pin to low-level detection. (3) Application Example of Software Standby Mode Figure 18.2 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at a rising edge of the NMI pin. In this example, when the NMI pin is driven from high to low while the NMI edge select bit (NMIE) in ICR1 is 0 (falling edge detection), an NMI interrupt is accepted. Then, when the NMIE bit is set to 1 (rising edge detection) in the NMI exception service routine, the SSBY bit in SBYCR is set to 1, and a SLEEP instruction is executed, a transition is made to software standby mode. Software standby mode is cleared by driving the NMI pin from low to high. Rev.1.00 Sep. 18, 2008 Page 459 of 522 REJ09B0069-0100 Section 18 Power-Down Modes Oscillator CK NMI pin NMIE bit SSBY bit LSI state NMI Program exception execution state handling Exception service routine Software standby mode Oscillation WDT start time setting time Oscillation stabilization time NMI exception handling Figure 18.2 NMI Timing in Software Standby Mode 18.3.3 Hardware Standby Mode (1) Transition to Hardware Standby Mode When the HSTBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. As long as the specified voltage is supplied, on-chip RAM data is retained. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the HSTBY pin low. Do not change the state of the mode pins (MD3 to MD0) while the CPU is in hardware standby mode. Rev.1.00 Sep. 18, 2008 Page 460 of 522 REJ09B0069-0100 Section 18 Power-Down Modes (2) Clearing Hardware Standby Mode Hardware standby mode is cleared by means of the HSTBY pin and RES pin. When the HSTBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillation stabilizes. When the RES pin is then driven high, a transition is made to the program execution state via the power-on reset exception handling state. (3) Hardware Standby Mode Timing Figure 18.3 shows a transition-timing example to hardware standby mode. In this example, when the HSTBY pin is driven low, the transition to hardware standby mode is made. Hardware standby mode is cleared when the HSTBY pin is driven high and then the RES pin is driven high after the elapse of the oscillation stabilization time of the clock pulse. Oscillator Oscillation stabilization time Reset exception handling Figure 18.3 Transition Timing to Hardware Standby Mode 18.3.4 Module Standby Mode Module standby mode can be set for individual on-chip peripheral functions. When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module standby mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the module starts operating at the end of the bus cycle. In module standby mode, the internal states of modules are initialized. After reset clearing, the SCI, MTU, MMT, CMT, and A/D converter are in module standby mode. Rev.1.00 Sep. 18, 2008 Page 461 of 522 REJ09B0069-0100 Section 18 Power-Down Modes When an on-chip peripheral module is in module standby mode, read/write access to its registers is disabled. 18.4 18.4.1 Usage Notes I/O Port Status When a transition is made to software standby mode while the port high-impedance bit (HIZ) in SBYCR is cleared to 0, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 18.4.2 Current Consumption during Oscillation Stabilization Wait Period Current consumption increases during the oscillation stabilization wait period. 18.4.3 On-Chip Peripheral Module Interrupt Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the CPU enters module standby mode while an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode. 18.4.4 Writing to MSTCR1 and MSTCR2 MSTCR1 and MSTCR2 should only be written to by the CPU. Rev.1.00 Sep. 18, 2008 Page 462 of 522 REJ09B0069-0100 Section 19 List of Registers Section 19 List of Registers The column “Access Size” shows the number of bits. The column “Access States” shows the number of access states, in units of cycles, of the specified reference clock. B, W, and L in the column represent 8-bit, 16-bit, and 32-bit access, respectively. 19.1 Register Addresses (Address Order) Abbreviation — SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 — SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 — — TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 Register Name — Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 — Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit data register_3 Serial status register_3 Receive data register_3 — — Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 Bits Address — 8 8 8 8 8 8 8 — 8 8 8 8 8 8 8 — — 8 8 8 8 8 8 H'FFFF8000 to H'FFFF81BF H'FFFF81C0 H'FFFF81C1 H'FFFF81C2 H'FFFF81C3 H'FFFF81C4 H'FFFF81C5 H'FFFF81C6 Module — Access Access Size States — — In Pφ cycles B: 2 W: 4 SCI 8, 16 (channel 2) 8 8, 16 8 8, 16 8 8 — Serial direction control register_2 SDCR_2 H'FFFF81C7 to — H'FFFF81CF H'FFFF81D0 H'FFFF81D1 H'FFFF81D2 H'FFFF81D3 H'FFFF81D4 H'FFFF81D5 H'FFFF81D6 H'FFFF81D7 to — H'FFFF81EF H'FFFF81F0 to — H'FFFF81FF H'FFFF8200 H'FFFF8201 H'FFFF8202 H'FFFF8203 H'FFFF8204 H'FFFF8205 SCI 8, 16 (channel 3) 8 8, 16 8 8, 16 8 8 — — — In Pφ cycles B: 2 W: 2 L: 4 Serial direction control register_3 SDCR_3 8, 16, 32 MTU (channels 3 8 and 4) 8, 16 8 8, 16, 32 8 Rev.1.00 Sep. 18, 2008 Page 463 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_3 Timer interrupt enable register_4 Timer output master enable register Timer output control register — Timer gate control register — — Timer counter_3 Timer counter_4 Timer period data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer sub-counter Timer period buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 — Timer start register Timer synchro register — Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Abbreviation TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR — TGCR — — TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 — TSTR TSYR — TCR_0 TMDR_0 TIORH_0 Bits Address 8 8 8 8 8 8 — 8 — — 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 — 8 8 — 8 8 8 H'FFFF8206 H'FFFF8207 H'FFFF8208 H'FFFF8209 H'FFFF820A H'FFFF820B H'FFFF820C H'FFFF820D H'FFFF820E H'FFFF820F H'FFFF8210 H'FFFF8212 H'FFFF8214 H'FFFF8216 H'FFFF8218 H'FFFF821A H'FFFF821C H'FFFF821E H'FFFF8220 H'FFFF8222 H'FFFF8224 H'FFFF8226 H'FFFF8228 H'FFFF822A H'FFFF822C H'FFFF822D H'FFFF822E to H'FFFF823F H'FFFF8240 H'FFFF8241 H'FFFF8242 to H'FFFF825F H'FFFF8260 H'FFFF8261 H'FFFF8262 Module Access Access Size States 8, 16 8 8, 16, 32 8 8, 16 8 — 8 — — 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 — MTU (common) 8, 16 8 — In Pφ cycles B: 2 W: 2 8, 16, 32 In Pφ cycles MTU B: 2 (channel 0) 8 W: 2 8, 16 L: 4 Rev.1.00 Sep. 18, 2008 Page 464 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 — Timer control register_1 Timer mode register_1 Timer I/O control register_1 — Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 — Timer control register_2 Timer mode register_2 Timer I/O control register_2 — Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 — — Interrupt priority register A — Abbreviation TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 — TCR_1 TMDR_1 TIOR_1 — TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 — TCR_2 TMDR_2 TIOR_2 — TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 — — IPRA — Bits Address 8 8 8 16 16 16 16 16 — 8 8 8 — 8 8 16 16 16 — 8 8 8 — 8 8 16 16 16 — — 16 — H'FFFF8263 H'FFFF8264 H'FFFF8265 H'FFFF8266 H'FFFF8268 H'FFFF826A H'FFFF826C H'FFFF826E H'FFFF8270 to H'FFFF827F H'FFFF8280 H'FFFF8281 H'FFFF8282 H'FFFF8283 H'FFFF8284 H'FFFF8285 H'FFFF8286 H'FFFF8288 H'FFFF828A H'FFFF828C to H'FFFF829F H'FFFF82A0 H'FFFF82A1 H'FFFF82A2 H'FFFF82A3 H'FFFF82A4 H'FFFF82A5 H'FFFF82A6 H'FFFF82A8 H'FFFF82AA Module Access Access Size States 8 8, 16, 32 8 16 16, 32 16 16, 32 16 — 8, 16 MTU (channel 1) 8 8 — 8, 16, 32 8 16 16, 32 16 — MTU 8, 16 (channel 2) 8 8 — 8, 16, 32 8 16 16, 32 16 — — 8, 16 — — In φ cycles B: 2 W: 2 L: 4 H'FFFF82AC to — H'FFFF833F H'FFFF8340 to H'FFFF8347 H'FFFF8348 H'FFFF834A to H'FFFF834D INTC Rev.1.00 Sep. 18, 2008 Page 465 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt control register 1 IRQ status register Interrupt priority register I Interrupt priority register J Interrupt priority register K — Interrupt control register 2 — — Port A data register L — Abbreviation IPRD IPRE IPRF IPRG IPRH ICR1 ISR IPRI IPRJ IPRK — ICR2 — — PADRL — Bits Address 16 16 16 16 16 16 16 16 16 16 — 16 — — 16 — H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A H'FFFF835C H'FFFF835E H'FFFF8360 H'FFFF8362 to H'FFFF8365 H'FFFF8366 H'FFFF8368 to H'FFFF837F H'FFFF8380 to H'FFFF8381 H'FFFF8382 H'FFFF8384 to H'FFFF8385 H'FFFF8386 H'FFFF8388 to H'FFFF8389 H’FFFF838A H’FFFF838C H’FFFF838E H’FFFF8390 H’FFFF8392 to H’FFFF8393 H'FFFF8394 H'FFFF8396 to H'FFFF8397 H'FFFF8398 H'FFFF839A Module Access Access Size States 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 — 8, 16 — — I/O — — 8, 16 — — In φ cycles B: 2 W: 2 L: 4 Port A I/O register L — Port A control register L3 Port A control register L1 Port A control register L2 Port B data register — Port B I/O register — Port B control register 1 Port B control register 2 — Port D data register L PAIORL — PACRL3 PACRL1 PACRL2 PBDR — PBIOR — PBCR1 PBCR2 — PDDRL 16 — 16 16 16 16 — 16 — 16 16 — 16 PFC — PFC 8, 16 — 8, 16 8, 16, 32 8, 16 I/O — PFC — PFC 8, 16 — 8, 16, 32 — 8, 16, 32 In φ cycles B: 2 8, 16 W: 2 — L: 4 8, 16 H'FFFF839C to — H'FFFF83A1 H'FFFF83A2 I/O Rev.1.00 Sep. 18, 2008 Page 466 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name — Port D I/O register L — Port D control register L1 Port D control register L2 Port E data register L Port F data register Port E I/O register L Port E I/O register H Port E control register L1 Port E control register L2 Port E control register H Port E data register H Input control/status register 1 Output control/status register Input control/status register 2 — Port G data register Abbreviation — PDIORL — PDCRL1 PDCRL2 PEDRL PFDR PEIORL PEIORH PECRL1 PECRL2 PECRH PEDRH ICSR1 OCSR ICSR2 — PGDR Bits Address — 16 — 16 16 16 16 16 16 16 16 16 16 16 16 16 — 8 Module Access Access Size States — 8, 16 — 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 H'FFFF83A4 to — H'FFFF83A5 H'FFFF83A6 PFC H'FFFF83A8 to — H'FFFF83AB H'FFFF83AC H'FFFF83AE H'FFFF83B0 H'FFFF83B2 H'FFFF83B4 H'FFFF83B6 H'FFFF83B8 H'FFFF83BA H'FFFF83BC H'FFFF83BE H'FFFF83C0 H'FFFF83C2 H'FFFF83C4 MMT I/O MTU PFC I/O PFC 8, 16 8, 16, 32 In Pφ cycles B: 2 8, 16 W: 2 8, 16 L: 4 — 8 — In φ cycles B: 2 W: 2 L: 4 — H'FFFF83C6 to — H'FFFF83CC H'FFFF83CD I/O — Compare match timer start register Compare match timer control/status register_0 Compare match timer counter_0 Compare match timer constant register_0 Compare match timer control/status register_1 Compare match timer counter_1 Compare match timer constant register_1 — — CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 — — 16 16 16 16 16 16 16 — H'FFFF83CE to — H'FFFF83CF H'FFFF83D0 H'FFFF83D2 H'FFFF83D4 H'FFFF83D6 H'FFFF83D8 H'FFFF83DA H'FFFF83DC H'FFFF83DE CMT — 8, 16, 32 In Pφ cycles B: 2 W: 2 8, 16 L: 4 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 — Rev.1.00 Sep. 18, 2008 Page 467 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name — A/D data register 0 A/D data register 1 A/D data register 2 A/D data register 3 A/D data register 4 A/D data register 5 A/D data register 6 A/D data register 7 A/D data register 8 A/D data register 9 A/D data register 10 A/D data register 11 A/D data register 12 A/D data register 13 A/D data register 14 A/D data register 15 A/D data register 16 A/D data register 17 A/D data register 18 A/D data register 19 — A/D control/status register_0 A/D control/status register_1 A/D control/status register_2 — A/D control register_0 A/D control register_1 A/D control register_2 — Abbreviation — ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 — ADCSR_0 ADCSR_1 ADCSR_2 — ADCR_0 ADCR_1 ADCR_2 — Bits Address — 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 — 8 8 8 — 8 8 8 — Module Access Access Size States — — In Pφ cycles B: 3 W: 6 H'FFFF83E0 to — H'FFFF841F H'FFFF8420 H'FFFF8422 H'FFFF8424 H'FFFF8426 H'FFFF8428 H'FFFF842A H'FFFF842C H'FFFF842E H'FFFF8430 H'FFFF8432 H'FFFF8434 H'FFFF8436 H'FFFF8438 H'FFFF843A H'FFFF843C H'FFFF843E H'FFFF8440 H'FFFF8442 H'FFFF8444 H'FFFF8446 H'FFFF8448 to H'FFFF847F H'FFFF8480 H'FFFF8481 H'FFFF8482 H'FFFF8483 to H'FFFF8487 H'FFFF8488 H'FFFF8489 H'FFFF848A H'FFFF848B to H’FFFF860F — A/D 8, 16 A/D (channel 0) 8, 16 8, 16 8, 16 8, 16 A/D (channel 1) 8, 16 8, 16 8, 16 8, 16 A/D (channel 0) 8, 16 8, 16 8, 16 8, 16 A/D (channel 1) 8, 16 8, 16 8, 16 8, 16 A/D (channel 2) 8, 16 8, 16 8, 16 — 8, 16 8 8 — 8, 16 8 8 — Rev.1.00 Sep. 18, 2008 Page 468 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name Timer control/status register Timer counter Timer counter Reset control/status register Reset control/status register Standby control register Abbreviation TCSR TCNT* 1 Bits Address 8 8 8 8 8 8 H'FFFF8610 H'FFFF8610 H'FFFF8611 H'FFFF8612 H'FFFF8613 H'FFFF8614 Module WDT *1: Write cycle *2: Read cycle Powerdown modes — Powerdown modes Access Access Size States 8*2/16*1 16 8 16 8 8 In φ cycles B: 3 — In Pφ cycles B: 3 W: 3 L: 6 In φ cycles B: 3 W: 3 TCNT*2 RSTCSR*1 RSTCSR*2 SBYCR — System control register — SYSCR — 8 H'FFFF8615 to H'FFFF8617 H'FFFF8618 — 8 — — — 16 16 16 16 16 — — — 8 — 8 — 8 — 8 — 16 16 16 16 H'FFFF8619 to H'FFFF861B H'FFFF861C H'FFFF861E H'FFFF8620 H'FFFF8622 H'FFFF8624 H'FFFF8626 H'FFFF8628 to H'FFFF864F H'FFFF8650 to H'FFFF87F3 H'FFFF87F4 H'FFFF87F5 to H'FFFF89FF H'FFFF8A00 H'FFFF8A01 H'FFFF8A02 H'FFFF8A03 H'FFFF8A04 H'FFFF8A05 H'FFFF8A06 H'FFFF8A08 H'FFFF8A0A H'FFFF8A0C MMT — — A/D BSC — 8, 16, 32 8, 16 Module standby control register 1 MSTCR1 Module standby control register 2 MSTCR2 Bus control register 1 Bus control register 2 Wait control register 1 — — — A/D trigger select register — Timer mode register — Timer control register — Timer status register — Timer counter Timer period data register Timer period buffer register Timer dead time data register BCR1 BCR2 WCR1 — — — ADTSR — MMT_TMDR — TCNR — MMT_TSR — MMT_TCNT TPDR TPBR MMT_TDDR 8, 16, 32 In φ cycles B: 3 8, 16 W: 3 8, 16 L: 6 — — — 8 — 8 — 8 — 8 — 16 16, 32 16 16 — — In Pφ cycles B: 3 In Pφ cycles B: 2 W: 2 L: 4 Rev.1.00 Sep. 18, 2008 Page 469 of 522 REJ09B0069-0100 Section 19 List of Registers Register Name — Timer buffer register U_B Timer general register UU Timer general register U Timer general register UD Timer dead time counter 0 Timer dead time counter 1 Timer buffer register U_F — Timer buffer register V_B Timer general register VU Timer general register V Timer general register VD Timer dead time counter 2 Timer dead time counter 3 Timer buffer register V_F — Timer buffer register W_B Timer general register WU Timer general register W Timer general register WD Timer dead time counter 4 Timer dead time counter 5 Timer buffer register W_F — Abbreviation — TBRU_B TGRUU TGRU TGRUD TDCNT0 TDCNT1 TBRU_F — TBRV_B TGRVU TGRV TGRVD TDCNT2 TDCNT3 TBRV_F — TBRW_B TGRWU TGRW TGRWD TDCNT4 TDCNT5 TBRW_F — Bits Address — 16 16 16 16 16 16 16 — 16 16 16 16 16 16 16 — 16 16 16 16 16 16 16 — H'FFFF8A0E to H'FFFF8A0F H'FFFF8A10 H'FFFF8A12 H'FFFF8A14 H'FFFF8A16 H'FFFF8A18 H'FFFF8A1A H'FFFF8A1C H'FFFF8A1E to H'FFFF8A1F H'FFFF8A20 H'FFFF8A22 H'FFFF8A24 H'FFFF8A26 H'FFFF8A28 H'FFFF8A2A H'FFFF8A2C H'FFFF8A2E to H'FFFF8A2F H'FFFF8A30 H'FFFF8A32 H'FFFF8A34 H'FFFF8A36 H'FFFF8A38 H'FFFF8A3A H'FFFF8A3C H'FFFF8A3E to H'FFFF8A4F Module Access Access Size States — 16, 32 16 16, 32 16 16, 32 16 16 — 16, 32 16 16, 32 16 16, 32 16 16 — 16, 32 16 16, 32 16 16, 32 16 16 — Rev.1.00 Sep. 18, 2008 Page 470 of 522 REJ09B0069-0100 Section 19 List of Registers 19.2 Register Bits Addresses and bit names for on-chip peripheral module registers are shown in the following table. 16-bit and 32-bit registers are shown in two or four rows of 8 bits, respectively. Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SDCR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SDCR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 — CCLR2 CCLR2 — — IOB3 IOD3 IOB3 IOD3 TTGE TTGE — — — — CCLR1 CCLR1 — — IOB2 IOD2 IOB2 IOD2 — — — PSYE BDC — CCLR0 CCLR0 BFB BFB IOB1 IOD1 IOB1 IOD1 — — OE4D — N — CKEG1 CKEG1 BFA BFA IOB0 IOD0 IOB0 IOD0 TCIEV TCIEV OE4C — P DIR CKEG0 CKEG0 MD3 MD3 IOA3 IOC3 IOA3 IOC3 TGIED TGIED OE3D — FB — TPSC2 TPSC2 MD2 MD2 IOA2 IOC2 IOA2 IOC2 TGIEC TGIEC OE4B — WF — TPSC1 TPSC1 MD1 MD1 IOA1 IOC1 IOA1 IOC1 TGIEB TGIEB OE4A OLSN VF — TPSC0 TPSC0 MD0 MD0 IOA0 IOC0 IOA0 IOC0 TGIEA TGIEA OE3B OLSP UF MTU (channels 3 and 4) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 — C/A — CHR — PE — O/E DIR STOP — MP — CKS1 — CKS0 SCI (channel 3) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI (channel 2) TCNT_4 TCDR Rev.1.00 Sep. 18, 2008 Page 471 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation TDDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MTU (channels 3 and 4) TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TCFD TCFD CST4 SYNC4 CCLR2 — IOB3 IOD3 TTGE — — — CST3 SYNC3 CCLR1 — IOB2 IOD2 — — — — — — CCLR0 BFB IOB1 IOD1 — — TCFV TCFV — — CKEG1 BFA IOB0 IOD0 TCIEV TCFV TGFD TGFD — — CKEG0 MD3 IOA3 IOC3 TGIED TGFD TGFC TGFC CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC TGFB TGFB CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TGFA TGFA CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA MTU (channel 0) MTU (common) TGRA_0 TGRB_0 Rev.1.00 Sep. 18, 2008 Page 472 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation TGRC_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MTU (channel 0) TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA MTU (channel 1) TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 — — IOB3 TTGE TCFD CCLR1 — IOB2 — — CCLR0 — IOB1 TCIEU TCFU CKEG1 — IOB0 TCIEV TCFV CKEG0 MD3 IOA3 — — TPSC2 MD2 IOA2 — — TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA MTU (channel 2) TGRA_2 TGRB_2 IPRA IRQ0 IRQ2 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 — A/D0,1 CMT0 WDT — IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 — A/D0,1 CMT0 WDT — IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 — A/D0,1 CMT0 WDT — IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 — — CMT1 I/O(MTU) — IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 — — CMT1 I/O(MTU) — IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 — — CMT1 I/O(MTU) — IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 — — CMT1 I/O(MTU) — INTC IPRD MTU0 MTU1 IPRE MTU2 MTU3 IPRF MTU4 — IPRG A/D0,1 CMT0 IPRH WDT — Rev.1.00 Sep. 18, 2008 Page 473 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation ICR1 Bit 7 NMIL IRQ0S Bit 6 — IRQ1S — IRQ1F SCI2 — A/D2 — I/O(MMT) — IRQ0ES0 — PA14DR PA6DR PA14IOR PA6IOR Bit 5 — IRQ2S — IRQ2F SCI2 — A/D2 — I/O(MMT) — IRQ1ES1 — PA13DR PA5DR PA13IOR PA5IOR Bit 4 — IRQ3S — IRQ3F SCI2 — A/D2 — I/O(MMT) — IRQ1ES0 — PA12DR PA4DR PA12IOR PA4IOR Bit 3 — — — — SCI3 MMT — — — — IRQ2ES1 — PA11DR PA3DR PA11IOR PA3IOR Bit 2 — — — — SCI3 MMT — — — — IRQ2ES0 — PA10DR PA2DR PA10IOR PA2IOR Bit 1 — — — — SCI3 MMT — — — — IRQ3ES1 — PA9DR PA1DR PA9IOR PA1IOR PA9MD2 PA1MD2 Bit 0 NMIE — — — SCI3 MMT — — — — IRQ3ES0 — PA8DR PA0DR PA8IOR PA0IOR PA8MD2 PA0MD2 Module INTC ISR — IRQ0F IPRI SCI2 — IPRJ A/D2 — IPRK I/O(MMT) — ICR2 IRQ0ES1 — PADRL PA15DR PA7DR Port A PAIORL PA15IOR PA7IOR PACRL3 PA15MD2 PA14MD2 PA13MD2 PA12MD2 PA11MD2 PA10MD2 PA7MD2 PA6MD2 PA5MD2 PA4MD2 PA3MD2 PA2MD2 PACRL1 PA15MD1 PA15MD0 PA14MD1 PA14MD0 PA13MD1 PA13MD0 PA12MD1 PA12MD0 PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA9MD1 PA5MD1 PA1MD1 — PB3DR — PB3IOR PB3MD2 — PB5MD1 PB1MD1 — PD3DR — PD3IOR — PD3MD0 — PD3MD1 PA9MD0 PA5MD0 PA1MD0 — PB2DR — PB2IOR PB2MD2 — PB5MD0 PB1MD0 — PD2DR — PD2IOR — PD2MD0 — PD2MD1 PA8MD1 PA4MD1 PA0MD1 — PB1DR — PB1IOR PB1MD2 — PB4MD1 PB0MD1 — PD1DR — PD1IOR — PD1MD0 — PD1MD1 PA8MD0 PA4MD0 PA0MD0 — PB0DR — PB0IOR — — PB4MD0 PB0MD0 PD8DR PD0DR PD8IOR PD0IOR PD8MD0 PD0MD0 PD8MD1 PD0MD1 Port D Port B PACRL2 PA7MD1 PA3MD1 PA7MD0 PA3MD0 — — — — — — — PB3MD0 — PD6DR — PD6IOR — PD6MD0 — PD6MD1 PA6MD1 PA2MD1 — PB5DR — PB5IOR PB5MD2 — — PB2MD1 — PD5DR — PD5IOR — PD5MD0 — PD5MD1 PA6MD0 PA2MD0 — PB4DR — PB4IOR PB4MD2 — — PB2MD0 — PD4DR — PD4IOR — PD4MD0 — PD4MD1 PBDR — — PBIOR — — PBCR1 — — PBCR2 — PB3MD1 PDDRL — PD7DR PDIORL — PD7IOR PDCRL1 — PD7MD0 PDCRL2 — PD7MD1 Rev.1.00 Sep. 18, 2008 Page 474 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation PEDRL Bit 7 PE15DR PE7DR Bit 6 PE14DR PE6DR PF14DR PF6DR PE14IOR PE6IOR — — Bit 5 PE13DR PE5DR PF13DR PF5DR PE13IOR PE5IOR — PE21IOR Bit 4 PE12DR PE4DR PF12DR PF4DR PE12IOR PE4IOR — PE20IOR Bit 3 PE11DR PE3DR PF11DR PF3DR PE11IOR PE3IOR — PE19IOR Bit 2 PE10DR PE2DR PF10DR PF2DR PE10IOR PE2IOR — PE18IOR Bit 1 PE9DR PE1DR PF9DR PF1DR PE9IOR PE1IOR — PE17IOR Bit 0 PE8DR PE0DR PF8DR PF0DR PE8IOR PE0IOR — PE16IOR Module Port E PFDR PF15DR PF7DR Port F PEIORL PE15IOR PE7IOR Port E PEIORH — — PECRL1 PE15MD1 PE15MD0 PE14MD1 PE14MD0 PE13MD1 PE13MD0 PE12MD1 PE12MD0 PE11MD1 PE11MD0 PE10MD1 PE10MD0 PE9MD1 PE5MD1 PE1MD1 PE9MD0 PE5MD0 PE1MD0 PE8MD1 PE4MD1 PE0MD1 PE8MD0 PE4MD0 PE0MD0 PECRL2 PE7MD1 PE3MD1 PE7MD0 PE3MD0 — PE6MD1 PE2MD1 — PE6MD0 PE2MD0 — PECRH — PE21MD1 PE21MD0 PE20MD1 PE20MD0 PE19MD1 PE19MD0 PE18MD1 PE18MD0 PE17MD1 PE17MD0 PE16MD1 PE16MD0 PEDRH — — ICSR1 POE3F POE3M1 OCSR OSF — ICSR2 — — PGDR CMSTR — — — CMCSR_0 — CMF CMCNT_0 — — POE2F POE3M0 — — POE6F — — — — — CMIE — PE21DR POE1F POE2M1 — — POE5F POE6M1 — — — — — — PE20DR POE0F POE2M0 — — POE4F POE6M0 — — — — — — PE19DR — POE1M1 — — — POE5M1 PG3DR — — — — — PE18DR — POE1M0 — — — POE5M0 PG2DR — — — — — PE17DR — POE0M1 OCE — — POE4M1 PG1DR — STR1 — CKS1 — PE16DR PIE POE0M0 OIE — PIE POE4M0 PG0DR — STR0 — CKS0 Port G CMT MMT MTU CMCOR_0 CMCSR_1 — CMF — CMIE — — — — — — — — — CKS1 — CKS0 CMCNT_1 CMCOR_1 ADDR0 AD9 AD1 AD8 AD0 AD7 — AD6 — AD5 — AD4 — AD3 — AD2 — A/D Rev.1.00 Sep. 18, 2008 Page 475 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation ADDR1 Bit 7 AD9 AD1 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 Bit 5 AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — AD7 — Bit 4 AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — AD6 — Bit 3 AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — AD5 — Bit 2 AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — AD4 — Bit 1 AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — AD3 — Bit 0 AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — AD2 — Module A/D ADDR2 AD9 AD1 ADDR3 AD9 AD1 ADDR4 AD9 AD1 ADDR5 AD9 AD1 ADDR6 AD9 AD1 ADDR7 AD9 AD1 ADDR8 AD9 AD1 ADDR9 AD9 AD1 ADDR10 AD9 AD1 ADDR11 AD9 AD1 ADDR12 AD9 AD1 ADDR13 AD9 AD1 ADDR14 AD9 AD1 ADDR15 AD9 AD1 ADDR16 AD9 AD1 ADDR17 AD9 AD1 ADDR18 AD9 AD1 ADDR19 AD9 AD1 Rev.1.00 Sep. 18, 2008 Page 476 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation ADCSR_0 ADCSR_1 ADCSR_2 ADCR_0 ADCR_1 ADCR_2 TCSR TCNT RSTCSR SBYCR SYSCR MSTCR1 WOVF SSBY — — — MSTCR2 — — — BCR1 — — — BCR2 — — WCR1 — — ADTSR MMT_TMDR TCNR MMT_TSR MMT_TCNT — — TTGE TCFD RSTE HIZ — — — MSTP14 MSTP6 — RSTS — — — — MSTP13 MSTP5 — — — — — — MSTP12 MSTP4 — — — — CW0 — — TRG2S0 CKS0 — — — — — MSTP27 MSTP19 — — — — — — — — W03 TRG1S1 OLSN — — — — — MSTP26 MSTP18 — — — — — — — — W02 TRG1S0 OLSP — — — — — — — — — — — — IW01 — — W01 TRG0S1 MD1 TGIEN TGFN — IRQEL RAME — — — — — — A0SZ IW00 SW0 — W00 TRG0S0 MD0 TGIEM TGFM A/D MMT — BSC Power-down modes Bit 7 ADF ADF ADF TRGE TRGE TRGE OVF Bit 6 ADIE ADIE ADIE CKS1 CKS1 CKS1 WT/IT Bit 5 ADM1 ADM1 ADM1 CKS0 CKS0 CKS0 TME Bit 4 ADM0 ADM0 ADM0 ADST ADST ADST — Bit 3 — — — ADCS ADCS ADCS — Bit 2 CH2 CH2 CH2 — — — CKS2 Bit 1 CH1 CH1 CH1 — — — CKS1 Bit 0 CH0 CH0 CH0 — — — CKS0 Module A/D WDT MMTRWE MTURWE — — — — — — CKS2 CST — — — — — — TRG2S1 CKS1 RPRO — TPDR TPBR MMT_TDDR TBRU_B TGRUU Rev.1.00 Sep. 18, 2008 Page 477 of 522 REJ09B0069-0100 Section 19 List of Registers Register Abbreviation TGRU Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MMT TGRUD TDCNT0 TDCNT1 TBRU_F TBRV_B TGRVU TGRV TGRVD TDCNT2 TDCNT3 TBRV_F TBRW_B TGRWU TGRW TGRWD TDCNT4 TDCNT5 TBRW_F Rev.1.00 Sep. 18, 2008 Page 478 of 522 REJ09B0069-0100 Section 19 List of Registers 19.3 Register States in Each Operating Mode Hardware Software Module Standby Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Register PowerManual Abbreviation On Reset Reset SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SDCR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SDCR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module SCI (channel 2) SCI (channel 3) MTU (channels 3 and 4) Rev.1.00 Sep. 18, 2008 Page 479 of 522 REJ09B0069-0100 Section 19 List of Registers Register PowerManual Abbreviation On Reset Reset TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Hardware Software Module Standby Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MTU (channels 3 and 4) MTU (common) MTU (channel 0) MTU (channel 1) MTU (channel 2) Rev.1.00 Sep. 18, 2008 Page 480 of 522 REJ09B0069-0100 Section 19 List of Registers Register PowerManual Abbreviation On Reset Reset TCNT_2 TGRA_2 TGRB_2 IPRA IPRD IPRE IPRF IPRG IPRH ICR1 ISR IPRI IPRJ IPRK ICR2 PADRL PAIORL PACRL3 PACRL1 PACRL2 PBDR PBIOR PBCR1 PBCR2 PDDRL PDIORL PDCRL1 PDCRL2 PEDRL PFDR PEIORL PEIORH PECRL1 PECRL2 PECRH Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Initialized Initialized Initialized Initialized Initialized Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Hardware Software Module Standby Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MTU (channel 2) INTC Port A Port B Port D Port E Port F Port E Rev.1.00 Sep. 18, 2008 Page 481 of 522 REJ09B0069-0100 Section 19 List of Registers Register PowerManual Abbreviation On Reset Reset PEDRH ICSR1 OCSR ICSR2 PGDR CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADCSR_0 ADCSR_1 ADCSR_2 Initialized Initialized Initialized Initialized Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Hardware Software Module Standby Standby Standby Initialized Initialized Initialized Initialized Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — Held Held Held — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Port E MTU MMT Port G CMT A/D Rev.1.00 Sep. 18, 2008 Page 482 of 522 REJ09B0069-0100 Section 19 List of Registers Register PowerManual Abbreviation On Reset Reset ADCR_0 ADCR_1 ADCR_2 TCSR TCNT RSTCSR SBYCR SYSCR MSTCR1 MSTCR2 BCR1 BCR2 WCR1 ADTSR MMT_TMDR TCNR MMT_TSR MMT_TCNT TPDR TPBR MMT_TDDR TBRU_B TGRUU TGRU TGRUD TDCNT0 TDCNT1 TBRU_F TBRV_B TGRVU TGRV TGRVD TDCNT2 TDCNT3 Initialized Initialized Initialized Initialized Initialized Initialized/ held*2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Initialized Initialized Held Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Hardware Software Module Standby Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized/ held*1 Initialized Initialized Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized — — — — — — — — — — — Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module A/D WDT Power-down modes BSC A/D MMT Rev.1.00 Sep. 18, 2008 Page 483 of 522 REJ09B0069-0100 Section 19 List of Registers Register PowerManual Abbreviation On Reset Reset TBRV_F TBRW_B TGRWU TGRW TGRWD TDCNT4 TDCNT5 TBRW_F Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Hardware Software Module Standby Standby Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Module MMT Notes: 1. Bits 7 to 5 (OVF, WT/IT, and TME) in the TCSR register are initialized. The values of bits 2 to 0 (CKS2, CKS1, and CKS0) are retained. 2. The RSTC SR register value is retained on a power-on reset due to a watchdog timer overflow. Rev.1.00 Sep. 18, 2008 Page 484 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 shows the absolute maximum ratings. Table 20.1 Absolute Maximum Ratings Item Power supply voltage Input voltage EXTAL pin All pins other than analog input and EXTAL pins Analog power supply voltage Analog input voltage Operating temperature Standard product* (except programming or Wide temperature-range erasing flash memory) product* Storage temperature Symbol VCC Vin Vin AVCC VAN Topr Rating –0.3 to +7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to +7.0 –0.3 to AVCC +0.3 –20 to +75 –40 to +85 Tstg –55 to +125 °C Unit V V V V V °C [Operating precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. Note: * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. Rev.1.00 Sep. 18, 2008 Page 485 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.2 DC Characteristics Table 20.2 DC Characteristics (1) Conditions: VCC = 4.0 to 5.5 V, AVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item Input high-level voltage (except Schmitt trigger input pin) Symbol RES, MRES, HSTBY, VIH NMI, FWP, MD3 to MD0 EXTAL A/D port Other input pins Input low-level voltage (except Schmitt trigger input pin) Schmitt trigger input voltage RES, MRES, HSTBY, VIL NMI, FWP, MD3 to MD0, EXTAL Other input pins IRQ3 to IRQ0, POE6 to POE0, TCLKA to TCLKD, TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D VT+ (VH) VT– (VL) VT+–VT– Min. VCC – 0.7 Typ. — Max. VCC + 0.3 Unit V Measurement Conditions VCC – 0.7 2.2 2.2 –0.3 — — — — VCC + 0.3 AVCC + 0.3 VCC + 0.3 0.5 V V V V –0.3 VCC–0.5 –0.3 0.4 — — — — 0.8 VCC + 0.3 1.0 — V V V V Input leakage current RES, MRES, NMI, | Iin | HSTBY, FWP, MD3 to MD0, DBGMD Ports F, G Other input pins — — 1.0 µA Vin = 0.5 to VCC –0.5 V Vin = 0.5 to AVCC –0.5 V Vin = 0.5 to VCC –0.5 V — — — — 1.0 1.0 µA µA Rev.1.00 Sep. 18, 2008 Page 486 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics Measurement Conditions Vin = 0.5 to VCC –0.5 V IOH = –200 µA IOH = –1 mA IOL = 1.6 mA IOL = 15 mA Vin = 0 V φ = 1 MHz Ta = 25°C Item Three-state Ports A, B, D, E leakage current (while off) Output highlevel voltage All output pins Symbol | Itsi | Min. — Typ. — Max. 1.0 Unit µA VOH VCC – 0.5 VCC – 1.0 — — — — — — — — — 0.4 1.5 80 50 20 V V V V pF pF pF Output low-level All output pins voltage PE9, PE11 to PE21 Input capacitance RES NMI All other input pins VOL — — Cin — — — Note: * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. Table 20.2 DC Characteristics (2) Conditions: VCC = 4.0 to 5.5 V, AVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to 1 +75°C (standard product* ), Ta = –40°C to +85°C (wide temperature-range 1 product* ) HD6437108, HD6437106 Item Current consumption*2 Symbol Normal Clock 1:1 ICC operation Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Standby Min. Typ. 110 115 70 70 1 Max. 140 145 90 90 10 50 Analog power supply current During A/D conversion, A/D converter idle state During standby RAM standby voltage VRAM 2.0 — AICC 3.0 5.0 Unit mA mA mA mA µA µA mA Measurement Conditions φ = 40 MHz φ = 50 MHz φ = 40 MHz φ = 50 MHz Ta ≤ 50°C 50°C < Ta — 5.0 — µA V VCC Rev.1.00 Sep. 18, 2008 Page 487 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics HD6437104 Item Current consumption*2 Symbol Clock 1:1 ICC Normal operation Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Standby Min. Typ. 120 125 90 90 1 Max. 150 155 110 110 10 50 Analog power supply current During A/D conversion, A/D converter idle state During standby RAM standby voltage VRAM 2.0 — AICC 3.0 5.0 Unit mA mA mA mA µA µA mA Measurement Conditions φ = 40 MHz φ = 50 MHz φ = 40 MHz φ = 50 MHz Ta ≤ 50°C 50°C < Ta — 5.0 — µA V VCC HD6437101 Item Current consumption*2 Symbol Clock 1:1 ICC Normal operation Clock 1:1/2 Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Clock 1:1/2 Standby Min. Typ. 110 100 120 70 60 70 1 Max. 130 120 140 90 80 90 10 50 Analog power supply current During A/D conversion, A/D converter idle state During standby RAM standby voltage VRAM 2.0 — AICC 3.0 5.0 Unit mA mA mA mA mA mA µA µA mA Measurement Conditions φ = 40 MHz φ = 40 MHz φ = 50 MHz φ = 40 MHz φ = 40 MHz φ = 50 MHz Ta ≤ 50°C 50°C < Ta — 5.0 — µA V VCC Rev.1.00 Sep. 18, 2008 Page 488 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics HD6437109, HD6437107 Item Current consumption*2 Symbol Clock 1:1 ICC Normal operation Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Standby Min. — — — — — — Analog power supply current During A/D conversion, A/D converter idle state During standby RAM standby voltage VRAM AICC — Typ. 110 115 70 70 1 — 2.0 Max. 140 145 90 90 10 50 5.0 Unit mA mA mA mA µA µA mA Measurement Conditions φ = 40 MHz φ = 50 MHz φ = 40 MHz φ = 50 MHz Ta ≤ 50°C 50°C < Ta — — 2.0 — — 5.0 — µA V VCC HD6437105 Item Current consumption*2 Symbol Clock 1:1 ICC Normal operation Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Standby Min. — — — — — — Analog power supply current During A/D conversion, A/D converter idle state During standby RAM standby voltage VRAM AICC — Typ. 120 125 90 90 1 — 2.0 Max. 150 155 110 110 10 50 5.0 Unit mA mA mA mA µA µA mA Measurement Conditions φ = 40 MHz φ = 50 MHz φ = 40 MHz φ = 50 MHz Ta ≤ 50°C 50°C < Ta — — 2.0 — — 5.0 — µA V VCC [Operating precautions] When the A/D converter is not used, do not leave the AVCC and AVSS pins open. Notes: 1. For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. 2. The current consumption is measured when VIHmin. = VCC – 0.5 V, VIL = 0.5 V, with all output pins unloaded. Rev.1.00 Sep. 18, 2008 Page 489 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics Table 20.3 Permitted Output Current Values Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C 1 to +75°C (standard product* ), Ta = –40°C to +85°C (wide temperature-range 1 product* ) Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL Σ IOL –IOH Σ –IOH Min. — — — — Typ. — — — — Max. 2.0* 110 2.0 25 2 Unit mA mA mA mA [Operating precautions] To assure LSI reliability, do not exceed the output values listed in this table. Notes: 1. For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. 2. IOL= 15 mA (max.) about the pins PE9 and PE11 to PE21. However, six pins at most are permitted to have simultaneously IOL > 2.0 mA among these pins. Rev.1.00 Sep. 18, 2008 Page 490 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3 20.3.1 AC Characteristics Test Conditions for AC Characteristics high level: VIH minimum value, low level: VIL maximum value high level: 2.0 V, low level: 0.8 V IOL Input reference levels Output reference levels LSI output pin DUT output CL V VREF IOH CL is a total value that includes the capacitance of measurement equipment, and is set as follows: , , 30 pF: CK, 50 pF: A17 to A0, D7 to D0, , 30 pF: Port output pins and peripheral module output pins other than the above It is assumed that IOL = 1.6 mA, IOH = 200 μA in the test conditions. Figure 20.1 Output Load Circuit Rev.1.00 Sep. 18, 2008 Page 491 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.2 Clock Timing Table 20.4 shows the clock timing. Table 20.4 Clock Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item Operating frequency 50-MHz operation* 40-MHz operation* Clock cycle time 50-MHz operation* 40-MHz operation* Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width 50-MHz operation* 40-MHz operation* 50-MHz operation* 40-MHz operation* 50-MHz operation* 40-MHz operation* tEXH tEXR tEXF tOSC1 tOSC2 tpcyc tEXL tEXcyc tCL tCH tCR tCF fEX tcyc Symbol fop Min. 10 10 20 25 4 4 — — 4 4 80 100 35 45 35 45 — — 10 10 25 5 5 — — 100 ns ns ms ms ns — Figure 20.4 — ns Max. 50 40 100 100 — — 5 5 12.5 10.0 250 250 — ns ns ns ns ns ns MHz Figure 20.3 ns Unit MHz Figures Figure 20.2 EXTAL clock input 50-MHz operation* high-level pulse width 40-MHz operation* EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby return oscillation settling time Clock cycle time for peripheral modules Note: * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. Rev.1.00 Sep. 18, 2008 Page 492 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics tcyc tCH tCL VOH CK 1/2VCC VOH VOL tCF VOL VOH 1/2VCC tCR Figure 20.2 System Clock Timing tEXcyc tEXH tEXL EXTAL VIH 1/2VCC VIH VIL tEXF VIL VIH 1/2VCC tEXR Figure 20.3 EXTAL Clock Input Timing CK VCC VCC min tosc2 tosc1 tosc1 Figure 20.4 Oscillation Settling Time Rev.1.00 Sep. 18, 2008 Page 493 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.3 Control Signal Timing Table 20.5 shows the control signal timing. Table 20.5 Control Signal Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C 1 to +75°C (standard product* ), Ta = –40°C to +85°C (wide temperature-range 1 product* ) Item RES rise time, fall time RES pulse width RES setup time MRES pulse width MRES setup time MD3 to MD0, FWP setup time NMI rise time, fall time NMI setup time IRQ3 to IRQ0 setup time* (edge detection) 2 2 Symbol tRESr, tRESf tRESW tRESS tMRESW tMRESS tMDS tNMIr, tNMIIf tNMIS tIRQES tIRQLS tNMIH tIRQEH tIRQOD tBRQS tBACKD1 tBACKD2 tBZD Min. — 25 25 25 19 20 — 19 19 19 19 19 — 19 — — — Max. 200 — — — — — 200 — — — — — 100 — 30 30 30 Unit ns tcyc ns tcyc ns tcyc ns ns ns ns ns ns ns ns ns ns ns Figures Figure 20.5, Figure 20.6 Figure 20.7 IRQ3 to IRQ0 setup time* (level detection) NMI hold time IRQ3 to IRQ0 hold time IRQOUT output delay time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus three-state delay time Figure 20.8 Figure 20.9 Notes: 1. For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. 2. The RES, MRES, NMI, BREQ, and IRQ3 to IRQ0 signals are asynchronous inputs, but when the setup times shown here are observed, the signals are considered to have been changed at clock rise (RES, MRES, and BREQ) or fall (NMI and IRQ3 to IRQ0). If the setup times are not observed, the recognition of these signals may be delayed until the next clock rise or fall. Rev.1.00 Sep. 18, 2008 Page 494 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics CK tRESS tRESW VIL tMDS tRESS VOH VIH VIH VIL MD3 to MD0, FWP VIH VIL Figure 20.5 Reset Input Timing CK tMRESS tMRESS VIH VIL tMRESW VIL Figure 20.6 Reset Input Timing Rev.1.00 Sep. 18, 2008 Page 495 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics CK VOL VOL tNMIH NMI VIH VIL tIRQEH edge tNMIS VIH VIL tIRQES VIH VIL tIRQLS level VIL Figure 20.7 Interrupt Signal Input Timing VOH tIRQOD tIRQOD CK VOH VOL Figure 20.8 Interrupt Signal Output Timing CK VOH tBRQS (input) tBACKD1 (output) , , VOL tBZD Hi-Z tBZD A17 to A0, D7 to D0 Hi-Z VOH VOL VOH tBRQS VIH tBACKD2 VOH VOL Figure 20.9 Bus Release Timing Rev.1.00 Sep. 18, 2008 Page 496 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.4 Bus Timing Table 20.6 shows the bus timing. Table 20.6 Bus Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C 1 to +75°C (standard product* ), Ta = –40°C to +85°C (wide temperature-range 1 product* ) Item Address delay time CS delay time 1 CS delay time 2 Read strobe delay time 1 Read strobe delay time 2 Read data setup time Read data hold time Write strobe delay time 1 Write strobe delay time 2 Write data delay time Write data hold time WAIT setup time WAIT hold time Read data access time Access time from read strobe Write address setup time Write address hold time Write data hold time Symbol tAD tCSD1 tCSD2 tRSD1 tRSD2 tRDS tRDH tWSD1 tWSD2 tWDD tWDH tWTS tWTH tACC tOE tAS tWR tWRH Min. — — — — — 15 0 — — — 0 15 0 tCYC × 2 (2 + n) − 35* Typ. 22 22 15 20 15 — — 20 15 — — — — — Max. 30 35 35 35 35 — — 30 30 30 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 20.10, Figure 20.11 Figure 20.12 Figures Figure 20.10, Figure 20.11 tCYC × — 2 (1.5 + n) − 33* 0 5 0 — — — Notes: 1. For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. 2. n is the number of wait cycles. Rev.1.00 Sep. 18, 2008 Page 497 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics T1 VOH T2 CK tAD VOL A17 to A0 tCSD1 tCSD2 tRSD1 tOE tRSD2 (read) tACC tRDS tRDH D7 to D0 (read) tWSD1 tWSD2 tWR tWRH tWDD tWDH (write) tAS D7 to D0 (write) Note: tRDH: Specified from the negate timing of A17 to A0, , or , whichever is first. Figure 20.10 Basic Cycle (No Waits) Rev.1.00 Sep. 18, 2008 Page 498 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics T1 TW T2 VOH CK tAD VOL A17 to A0 tCSD1 tCSD2 tRSD1 tOE tRSD2 (read) tACC tRDS tRDH D7 to D0 (read) tWSD1 tAS tWDD tWSD2 tWR (write) tWRH tWDH D7 to D0 (write) Note: tRDH: Specified from the negate timing of A17 to A0, , or , whichever is first. Figure 20.11 Basic Cycle (One Software Wait) Rev.1.00 Sep. 18, 2008 Page 499 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics T1 CK TW TW TWO T2 A17 to A0 (read) D7 to D0 (read) (write) D7 to D0 (write) tWTS tWTH tWTS tWTH Note: tRDH: Specified from the negate timing of A17 to A0, , or , whichever is first. Figure 20.12 Basic Cycle (Two Software Waits + Waits by WAIT Signal) Rev.1.00 Sep. 18, 2008 Page 500 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.5 Multifunction Timer Pulse Unit (MTU) Timing Table 20.7 shows the multifunction timer pulse unit timing. Table 20.7 Multifunction Timer Pulse Unit (MTU) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item Output compare output delay time Input capture input setup time Timer input setup time Timer clock pulse width (single edge specified) Timer clock pulse width (both edges specified) Timer clock pulse width (phase count mode) Note: Symbol tTOCD tTICS tTCKS tTCKWH/L tTCKWH/L tTCKWH/L Min. — 19 35 1.5 2.5 2.5 Max. 100 — — — — — Unit ns ns ns tpcyc tpcyc tpcyc Figure 20.14 Figures Figure 20.13 * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. CK tTOCD Output compare output tTICS Input capture input Figure 20.13 MTU Input/Output Timing Rev.1.00 Sep. 18, 2008 Page 501 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics CK tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 20.14 MTU Clock Input Timing 20.3.6 I/O Port Timing Table 20.8 shows the I/O port timing. Table 20.8 I/O Port Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item Port output data delay time Port input hold time Port input setup time Symbol tPWD tPRH tPRS Min. — 19 19 Max. 100 — — Unit ns ns ns Figure Figure 20.15 [Operating precautions] The port input signals are asynchronous. They are, however, considered to have been changed at CK clock falling edge with two-state intervals shown in figure 20.15. If the setup times shown here are not observed, recognition may be delayed until the clock falling two states after that timing. Note: * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. CK tPRS Port (read) tPWD Port (write) tPRH Figure 20.15 I/O Port Input/Output Timing Rev.1.00 Sep. 18, 2008 Page 502 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.7 Watchdog Timer (WDT) Timing Table 20.9 shows the watchdog timer timing. Table 20.9 Watchdog Timer (WDT) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item WDTOVF delay time Note: Symbol tWOVD Min. — Max. 100 Unit ns Figure Figure 20.16 * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. CK VOH tWOVD VOH tWOVD Figure 20.16 Watchdog Timer Timing Rev.1.00 Sep. 18, 2008 Page 503 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.8 Serial Communication Interface (SCI) Timing Table 20.10 shows the serial communication interface timing. Table 20.10 Serial Communication Interface (SCI) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item Input clock cycle (asynchronous) Input clock cycle (clocked synchronous) Input clock pulse width Input clock rise time Input clock fall time Symbol tscyc tscyc tsckw tsckr tsckf Min. 4 6 0.4 — — — 100 100 — tpcyc + 25 tpcyc + 25 — 0.5 tpcyc + 50 1.5 tpcyc Max. — — 0.6 1.5 1.5 100 — — tspcyc + 70 — — 65 — — Unit tpcyc tpcyc tscyc tpcyc tpcyc ns ns ns ns ns ns ns ns ns Figure 20.18 Figures Figure 20.17 Transmit data Asynchronous tTxD delay time Receive data setup time Receive data hold time Transmit data Clocked delay time synchronous Receive data setup time Receive data hold time Transmit data Clocked delay time synchronous Receive data setup time Receive data hold time (SCK output) (SCK input) tRxS tRxH tTxD tRxS tRxH tTxD tRxS tRxH [Operating precautions] The inputs and outputs are asynchronous in asynchronous mode, but as shown in figure 20.18, the receive data is considered to have been changed at CK clock rise (two-clock intervals). The transmit signals change with a reference of CK clock rise (two-clock intervals). Note: tpcyc (ns) = 1/(Pφ (MHz) supplied to the module) Rev.1.00 Sep. 18, 2008 Page 504 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. tsckw VIH SCK2, SCK3 VIH VIL VIL tsckr VIH VIH tsckf VIL tscyc Figure 20.17 Input Clock Timing SCI input/output timing (clocked synchronous mode) tscyc SCK2, SCK3 (input/output) tTxD TxD2, TxD3 (transmit data) tRxS RxD2, RxD3 (receive data) tRxH SCI input/output timing (asynchronous mode) T1 VOH CK tTxD TxD2, TxD3 (transmit data) tRxS RxD2, RxD3 (receive data) tRxH VOH Tn Figure 20.18 SCI Input/Output Timing Rev.1.00 Sep. 18, 2008 Page 505 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.9 Motor Management Timer (MMT) Timing Table 20.11 Motor Management Timer (MMT) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item MMT output delay time PCI input setup time PCI input pulse time Note: Symbol tMTOD tPCIS tPCIW Min. — 35 1.5 Max. 100 — — Unit ns ns tpcyc Figure Figure 20.19 * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. CK tMTOD MMT output tPCIS PCIO input tPCIW Figure 20.19 MMT Input/Output Timing Rev.1.00 Sep. 18, 2008 Page 506 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.3.10 Output Enable (POE) Timing Table 20.12 Output Enable (POE) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item POE input setup time POE input pulse width Note: Symbol tPOES tPOEW Min. 100 1.5 Max. — — Unit ns tpcyc Figure Figure 20.20 * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. CK tPOES input tPOEW Figure 20.20 POE Input/Output Timing 20.3.11 A/D Converter Timing Table 20.13 shows the A/D converter timing. Table 20.13 A/D Converter Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C to +75°C (standard product*), Ta = –40°C to +85°C (wide temperature-range product*) Item External trigger input start delay time Note: Symbol tTRGS Min. 50 Typ. — Max. — Unit ns Figure Figure 20.22 * For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. Rev.1.00 Sep. 18, 2008 Page 507 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 3 to 5 states CK VOH input tTRGS ADCR (ADST = 1 set) Figure 20.21 External Trigger Input Timing Rev.1.00 Sep. 18, 2008 Page 508 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics 20.4 A/D Converter Characteristics Table 20.14 shows the A/D converter characteristics. Table 20.14 A/D Converter Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20°C 3 to +75°C (standard product* ), Ta = –40°C to +85°C (wide temperature-range 3 product* ) Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Nonlinearlity error (Value provided for reference purposes.) Offset error (Value provided for reference purposes.) Full-scale error (Value provided for reference purposes.) Quantization error Absolute error Min. 10 — — — — — — — — Typ. 10 — — — — — — — — Max. 10 6.7* /5.4* 20 3* /1* 1 2 1 2 Unit bit μs pF kΩ LSB LSB LSB LSB 1 1 ±3.0* / 2 ±5.0* ±3.0* / 2 ±5.0* 1 ±3.0* / 2 ±5.0* 1 ±0.5 ±4.0* / 2 ±6.0* LSB Notes: 1. Value when (CKS1, CKS0) = (11) and tpcyc = 50 ns 2. Value when (CKS1, CKS0) = (11) and tpcyc = 40 ns 3. For details on correspondence of the standard product, wide temperature-range product, and product model name, refer to description of maximum operating frequency and operating temperature range in section 1.1, Features. Rev.1.00 Sep. 18, 2008 Page 509 of 522 REJ09B0069-0100 Section 20 Electrical Characteristics Rev.1.00 Sep. 18, 2008 Page 510 of 522 REJ09B0069-0100 Appendix A Pin States Appendix A Pin States The initial values differ in each MCU operating mode. For details, refer to section 14, Pin Function Controller (PFC). Table A.1 Pin States Pin State Reset State Power-On Extended without ROM O O I I I Z O* Z Z I 3 Pin Function Power-Down Mode Software Standby in Bus Release State O L I I I Z *2 O I L I Type Clock Pin Name CK XTAL EXTAL PLLCAP RES MRES WDTOVF BREQ BACK Extended with ROM SingleChip Z Manual O O I I I I O I O I Hardware Standby Z L Z I I Z O Z Z I Software Standby O L I I I Z*2 O Z Z I Sleep O O I I I I O I O I Bus Release State O O I I I I O I O I System control Operating mode control MD0 to MD3 FWP Interrupts NMI IRQ0 to IRQ3 IRQOUT Address bus Data bus A0 to A17 D0 to D7 CS0 RD WRL MTU TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3C TIOC3B, TIOC3D TIOC4A to TIOC4D I I Z Z O Z Z H H H Z Z Z Z Z Z I I I O O I/O I O O O I I/O I Z Z Z Z Z Z Z Z Z Z Z I I Z*4 K* Z Z Z O O O Z K* 1 1 I I I O O I/O I O O O I I/O I I I O Z I/O I Z Z Z I I/O I I Z *4 K*1 Z Z Z Z Z Z Z K*1 Bus control WAIT Z I/O Z Z*2 I/O I/O Z *2 Rev.1.00 Sep. 18, 2008 Page 511 of 522 REJ09B0069-0100 Appendix A Pin States Pin Function Reset State Power-On Extended without ROM Z Extended with ROM SingleChip Hardware Standby Z Z Software Standby K*1 Z*2 Bus Release State I/O O Pin State Power-Down Mode Software Standby in Bus Release State K*1 Z*2 Type MMT Pin Name PCIO Manual I/O O Sleep I/O O PUOA, PUOB Z PVOA, PVOB PWOA, PWOB Port control POE0 to POE6 Z SCI SCK2, SCK3 RxD2, RxD3 TxD2, TxD3 A/D converter I/O ports AN0 to AN19 ADTRG PA0 to PA15 PB0 to PB5 PD0 to PD8 PE0 to PE8, PE10 PE9, PE11 to PE21 PF0 to PF15 PG0 to PG3 Z Z Z Z Z Z Z Z I I/O I O I I I/O Z Z Z Z Z Z Z Z Z Z O *1 Z Z K*1 I I/O I O I I I/O I I/O I O I I I/O Z Z Z O *1 Z Z K*1 I/O I Z Z Z*2 Z I/O I I/O I Z*2 Z Legend: I: Input O: Output H: High-level output L: Low-level output Z: High impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. When the HIZ bit in SBYCR is set to 1, the output pins enter the high-impedance state. 2. Those pins multiplexed with large-current pins (PE9 and PE11 to PE15) unconditionally enter the high-impedance state. 3. This pin operates as an input pin during a power-on reset. This pin should be pulled up to avoid malfunction. 4. This pin operates as an input pin when the IRQEL bit in SBYCR is cleared to 0. Rev.1.00 Sep. 18, 2008 Page 512 of 522 REJ09B0069-0100 Appendix A Pin States Table A.2 Pin States (1) On-Chip Peripheral Module On-Chip ROM Space H R W H — H — Address Z On-Chip RAM Space H H H H H Address Z 16-Bit Space 8-Bit Space H H H H H Address Z Upper Byte H H H H H Address Z Lower Byte H H H H H Address Z Word/Longword H H H H H Address Z Pin Name CS0 RD WRL R W A17 to A0 D7 to D0 Legend: R: Read W: Write Z: High impedance Table A.2 Pin Name CS0 RD WRL Pin States (2) External Normal Space 8-Bit Space L R W R W L H H L Address Data A17 to A0 D7 to D0 Legend: R: Read W: Write Rev.1.00 Sep. 18, 2008 Page 513 of 522 REJ09B0069-0100 Appendix A Pin States Rev.1.00 Sep. 18, 2008 Page 514 of 522 REJ09B0069-0100 Appendix B Product Code Lineup Appendix B Product Code Lineup Product Type SH7108 Masked ROM version Part No. Standard product HD6437108 HD6437106 HD6437104 HD6437101 SH7109 Masked ROM version Standard product HD6437109 HD6437107 HD6437105 QFP-100 (FP-100M) Package (Package Code) QFP-80 (FP-80Q) Rev.1.00 Sep. 18, 2008 Page 515 of 522 REJ09B0069-0100 Appendix B Product Code Lineup Rev.1.00 Sep. 18, 2008 Page 516 of 522 REJ09B0069-0100 Appendix C Package Dimensions Appendix C Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-QFP80-14x14-0.65 RENESAS Code PRQP0080JD-A Previous Code FP-80Q/FP-80QV MASS[Typ.] 1.2g HD *1 D 60 41 61 40 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section 80 21 Reference Dimension in Millimeters Symbol 1 ZD 20 c F θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 2.70 17.0 17.2 17.4 17.0 17.2 17.4 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0° 8° 0.65 0.12 0.10 0.83 0.83 0.6 0.8 1.0 1.6 Min ZE Figure C.1 FP-80Q Rev.1.00 Sep. 18, 2008 Page 517 of 522 REJ09B0069-0100 A A2 Appendix C Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KB-A Previous Code FP-100M/FP-100MV MASS[Typ.] 1.2g HD *1 D 75 51 76 50 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section ZE 100 26 Reference Dimension in Millimeters Symbol 1 ZD 25 c F θ A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 2.70 15.8 16.0 16.2 15.8 16.0 16.2 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.08 0.10 1.0 1.0 0.4 0.5 0.6 1.0 Min Figure C.2 FP-100M Rev.1.00 Sep. 18, 2008 Page 518 of 522 REJ09B0069-0100 A A2 Index Index A/D converter ......................................... 329 A/D conversion time........................... 342 Continuous scan mode ........................ 339 Single mode ........................................ 338 Single-cycle scan mode ...................... 341 Address map ............................................. 48 Addressing modes..................................... 22 Bus state controller ................................... 93 Clock mode............................................... 46 Clock pulse generator ............................... 55 Crystal resonator ................................... 55 External clock ....................................... 56 Clocked synchronous communication .... 318 Compare match timer.............................. 351 Control registers........................................ 17 Global Base Register (GBR)................. 18 Status register (SR) ............................... 17 Vector base register (VBR)................... 18 Data formats.............................................. 19 Byte data ............................................... 19 Longword data ...................................... 19 Word data.............................................. 19 Delayed branch instructions...................... 21 Exception processing ................................ 59 Address error exception processing ...... 66 General illegal instruction exception processing ............................................. 69 Illegal slot exception processing ........... 68 Interrupt exception processing .............. 67 Manual resets ........................................ 63 Power-on resets..................................... 63 Trap instruction exception processing .. 68 Exception processing vector table ............ 61 Free-running counters .............................159 General registers .......................................17 I/O Ports ..................................................429 Interrupt controller ....................................73 Interrupt response time..........................90 IRQ interrupts .......................................82 NMI interrupt ........................................82 On-chip peripheral module interrupts ...83 Vector numvers .....................................84 Vector table ...........................................84 Masked ROM..........................................445 Motor management timer........................361 High-impedance state..........................386 Multifunction timer pulse unit ................115 Buffer operation ..................................165 Cascaded operation .............................169 Compare match ...................................160 Free-running counter...........................158 High-impedance state..........................261 Input capture .......................................163 Periodic counter ..................................158 Phase counting mode...........................175 PWM mode .........................................169 Reset-synchronized PWM mode.........182 Synchronous operation........................163 Operating modes .......................................45 Pin function controller ............................393 Functions of multiplexed pins .............393 Pin functions in each operating mode .393 Rev.1.00 Sep. 18, 2008 Page 519 of 522 REJ09B0069-0100 Index Power-down modes ................................ 449 Hardware standby mode ..................... 460 Module standby mode......................... 461 Sleep mode ......................................... 456 Software standby mode....................... 457 Processing states ....................................... 42 Bus release state.................................... 43 Exception processing state.................... 42 Power-down state.................................. 43 Program execution state........................ 43 Reset state ............................................. 42 RAM ....................................................... 447 Registers ADCR ......................... 335, 468, 477, 483 ADCSR....................... 334, 468, 477, 482 ADDR......................... 333, 468, 475, 482 ADTSR ....................... 337, 469, 477, 483 BCR1 .................................. 469, 477, 483 BCR2 .......................... 104, 469, 477, 483 BRR ............................ 292, 463, 471, 479 CMCNT ...................... 354, 467, 475, 482 CMCOR...................... 354, 467, 475, 482 CMCSR ...................... 353, 467, 475, 482 CMSTR....................... 352, 467, 475, 482 ICR1 ............................. 76, 466, 474, 481 ICR2 ............................. 77, 466, 474, 481 ICSR1 ......................... 263, 467, 475, 482 ICSR2 ......................... 387, 467, 475, 482 IPR ................................ 80, 465, 473, 481 ISR ................................ 79, 466, 474, 481 MMT_TCNT .............. 368, 469, 477, 483 MMT_TDDR.............. 368, 469, 477, 483 MMT_TMDR ............. 365, 469, 477, 483 MMT_TSR ................. 367, 469, 477, 483 MSTCR....................... 454, 469, 477, 483 OCSR.......................... 266, 467, 475, 482 PACRL ....................... 409, 466, 474, 481 PADRL ....................... 431, 466, 474, 481 PAIORL...................... 409, 466, 474, 481 Rev.1.00 Sep. 18, 2008 Page 520 of 522 REJ09B0069-0100 PBCR .......................... 417, 466, 474, 481 PBDR .......................... 433, 466, 474, 481 PBIOR......................... 416, 466, 474, 481 PDCRL........................ 419, 467, 474, 481 PDDRL ....................... 435, 466, 474, 481 PDIORL ...................... 419, 467, 474, 481 PECR .......................... 421, 467, 475, 481 PEDR .......................... 438, 467, 475, 481 PEIOR ......................... 421, 467, 475, 481 PFDR .......................... 441, 467, 475, 481 PGDR.......................... 442, 467, 475, 482 RDR ............................ 286, 463, 471, 479 RSR..................................................... 286 RSTCSR...................... 275, 469, 477, 483 SBYCR ....................... 453, 469, 477, 483 SCR............................. 288, 463, 471, 479 SDCR .......................... 292, 463, 471, 479 SMR ............................ 287, 463, 471, 479 SSR ............................. 290, 463, 471, 479 SYSCR........................ 454, 469, 477, 483 TBR............................. 368, 470, 477, 483 TCBR .......................... 158, 464, 472, 480 TCDR.......................... 157, 464, 471, 479 TCNR.......................... 366, 469, 477, 483 TCNT ......................... 149, 273, 465, 469, .................................... 472, 477, 480, 483 TCNTS........................ 157, 464, 472, 480 TCR............................. 122, 464, 472, 480 TCSR .......................... 273, 469, 477, 483 TDCNT ....................... 368, 470, 478, 483 TDDR.......................... 157, 464, 472, 479 TDR ............................ 286, 463, 471, 479 TGCR.......................... 155, 464, 471, 479 TGR ........................... 150, 368, 465, 470, .................................... 472, 477, 480, 483 TIER............................ 145, 465, 472, 480 TIOR ........................... 127, 464, 472, 480 TMDR ......................... 126, 464, 472, 480 TOCR.......................... 154, 464, 471, 479 TOER .......................... 153, 464, 471, 479 Index TPBR .......................... 368, 469, 477, 483 TPDR .......................... 369, 469, 477, 483 TSR ..................... 147, 286, 465, 472, 480 TSTR .......................... 150, 464, 472, 480 TSYR .......................... 151, 464, 472, 480 WCR1 ......................... 105, 469, 477, 483 RISC type ................................................. 20 Serial communication interface .............. 283 Multiprocessor communication function ............................................... 312 Overrun error ...................................... 308 System registers ........................................18 Multiply-and-Accumulate Registers (MAC)...................................................18 Procedure Register (PR)........................18 Program counter (PC) ...........................18 Watchdog timer.......................................271 Interval timer mode.............................277 Reading from TCNT, TCSR, and RSTCSR..............................................280 Watchdog timer mode .........................276 Writing to RSTCSR ............................280 Writing to TCNT and TCSR ...............279 Rev.1.00 Sep. 18, 2008 Page 521 of 522 REJ09B0069-0100 Index Rev.1.00 Sep. 18, 2008 Page 522 of 522 REJ09B0069-0100 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7108, SH7109 Group Publication Date: Rev.1.00, September 18, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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