SH7785

REJ09B0261-0100 32 SH7785 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series Rev.1.00 Revision Date: Jan. 10, 2008 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.1.00 Jan. 10, 2008 Page ii of xxx REJ09B0261-0100 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.1.00 Jan. 10, 2008 Page iii of xxx REJ09B0261-0100 Rev.1.00 Jan. 10, 2008 Page iv of xxx REJ09B0261-0100 Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU (SH-4A) and various peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual consists of parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand individual instructions in detail Read the separate manuals SH-4A Extended Functions Software Manual and SH-4A Software Manual. Rules: Bit order: Number notation: Signal notation: The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. An overbar is added to active-low signals: xxxx Rev.1.00 Jan. 10, 2008 Page v of xxx REJ09B0261-0100 Abbreviations ALU ASID BGA CMT CPG CPU DDR DDRIF DMA DMAC FIFO FPU HAC H-UDI INTC JTAG LBSC LRAM LRU LSB MMCIF MMU Arithmetic Logic Unit Address Space Identifier Ball Grid Array Timer/Counter (Compare Match Timer) Clock Pulse Generator Central Processing Unit Double Data Rate DDR-SDRAM Interface Direct Memory Access Direct Memory Access Controller First-In First-Out Floating-point Unit Audio Codec User Debugging Interface Interrupt Controller Joint Test Action Group Local Bus State Controller L Memory Least Recently Used Least Significant Bit Multimedia Card Interface Memory Management Unit Rev.1.00 Jan. 10, 2008 Page vi of xxx REJ09B0261-0100 MSB PC PCI PCIC PFC RISC RTC SCIF SIOF SSI TAP TLB TMU UART UBC WDT Most Significant Bit Program Counter Peripheral Component Interconnect PCI (local bus) Controller Pin Function Controller Reduced Instruction Set Computer Realtime Clock Serial Communication Interface with FIFO Serial Interface with FIFO Serial Sound Interface Test Access Port Translation Lookaside Buffer Timer Unit Universal Asynchronous Receiver/Transmitter User Break Controller Watchdog Timer Rev.1.00 Jan. 10, 2008 Page vii of xxx REJ09B0261-0100 All trademarks and registered trademarks are the property of their respective owners. Rev.1.00 Jan. 10, 2008 Page viii of xxx REJ09B0261-0100 Contents Section 1 Overview .................................................................................................................. 1 1.1 1.2 1.3 1.4 1.5 Features of the SH7785.......................................................................................................... 1 Block Diagram ..................................................................................................................... 13 Pin Arrangement Table ........................................................................................................ 14 Pin Arrangement .................................................................................................................. 22 Physical Memory Address Map ........................................................................................... 24 Section 2 Programming Model ........................................................................................... 25 2.1 2.2 Data Formats........................................................................................................................ 25 Register Descriptions ........................................................................................................... 26 2.2.1 Privileged Mode and Banks .................................................................................. 26 2.2.2 General Registers.................................................................................................. 30 2.2.3 Floating-Point Registers ....................................................................................... 31 2.2.4 Control Registers .................................................................................................. 33 2.2.5 System Registers................................................................................................... 35 Memory-Mapped Registers.................................................................................................. 39 Data Formats in Registers .................................................................................................... 40 Data Formats in Memory ..................................................................................................... 40 Processing States.................................................................................................................. 41 Usage Notes ......................................................................................................................... 43 2.7.1 Notes on Self-Modifying Code............................................................................. 43 2.3 2.4 2.5 2.6 2.7 Section 3 Instruction Set ....................................................................................................... 45 3.1 3.2 3.3 Execution Environment ....................................................................................................... 45 Addressing Modes ............................................................................................................... 47 Instruction Set ...................................................................................................................... 52 Section 4 Pipelining ............................................................................................................... 65 4.1 4.2 4.3 Pipelines............................................................................................................................... 65 Parallel-Executability........................................................................................................... 76 Issue Rates and Execution Cycles........................................................................................ 79 Section 5 Exception Handling ............................................................................................ 89 5.1 5.2 Summary of Exception Handling......................................................................................... 89 Register Descriptions ........................................................................................................... 89 5.2.1 TRAPA Exception Register (TRA) ...................................................................... 90 Rev.1.00 Jan. 10, 2008 Page ix of xxx REJ09B0261-0100 5.3 5.4 5.5 5.6 5.7 5.2.2 Exception Event Register (EXPEVT)................................................................... 91 5.2.3 Interrupt Event Register (INTEVT)...................................................................... 92 5.2.4 Non-Support Detection Exception Register (EXPMASK) ................................... 93 Exception Handling Functions............................................................................................. 95 5.3.1 Exception Handling Flow ..................................................................................... 95 5.3.2 Exception Handling Vector Addresses ................................................................. 95 Exception Types and Priorities ............................................................................................ 96 Exception Flow .................................................................................................................... 98 5.5.1 Exception Flow..................................................................................................... 98 5.5.2 Exception Source Acceptance ............................................................................ 100 5.5.3 Exception Requests and BL Bit .......................................................................... 101 5.5.4 Return from Exception Handling........................................................................ 101 Description of Exceptions.................................................................................................. 102 5.6.1 Resets.................................................................................................................. 102 5.6.2 General Exceptions............................................................................................. 104 5.6.3 Interrupts............................................................................................................. 120 5.6.4 Priority Order with Multiple Exceptions ............................................................ 121 Usage Notes ....................................................................................................................... 123 Section 6 Floating-Point Unit (FPU) .............................................................................. 125 6.1 6.2 Features.............................................................................................................................. 125 Data Formats...................................................................................................................... 126 6.2.1 Floating-Point Format......................................................................................... 126 6.2.2 Non-Numbers (NaN) .......................................................................................... 129 6.2.3 Denormalized Numbers ...................................................................................... 130 Register Descriptions......................................................................................................... 131 6.3.1 Floating-Point Registers ..................................................................................... 131 6.3.2 Floating-Point Status/Control Register (FPSCR) ............................................... 133 6.3.3 Floating-Point Communication Register (FPUL) ............................................... 136 Rounding............................................................................................................................ 137 Floating-Point Exceptions.................................................................................................. 138 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions ................. 138 6.5.2 FPU Exception Sources ...................................................................................... 138 6.5.3 FPU Exception Handling.................................................................................... 139 Graphics Support Functions............................................................................................... 140 6.6.1 Geometric Operation Instructions....................................................................... 140 6.6.2 Pair Single-Precision Data Transfer.................................................................... 141 6.3 6.4 6.5 6.6 Section 7 Memory Management Unit (MMU) ............................................................ 143 7.1 Overview of MMU ............................................................................................................ 144 Rev.1.00 Jan. 10, 2008 Page x of xxx REJ09B0261-0100 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.1.1 Address Spaces ................................................................................................... 146 Register Descriptions ......................................................................................................... 152 7.2.1 Page Table Entry High Register (PTEH)............................................................ 153 7.2.2 Page Table Entry Low Register (PTEL) ............................................................. 154 7.2.3 Translation Table Base Register (TTB) .............................................................. 155 7.2.4 TLB Exception Address Register (TEA) ............................................................ 156 7.2.5 MMU Control Register (MMUCR) .................................................................... 156 7.2.6 Page Table Entry Assistance Register (PTEA)................................................... 159 7.2.7 Physical Address Space Control Register (PASCR)........................................... 160 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) .................................... 162 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 164 7.3.1 Unified TLB (UTLB) Configuration .................................................................. 164 7.3.2 Instruction TLB (ITLB) Configuration............................................................... 167 7.3.3 Address Translation Method............................................................................... 167 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 170 7.4.1 Unified TLB (UTLB) Configuration .................................................................. 170 7.4.2 Instruction TLB (ITLB) Configuration............................................................... 173 7.4.3 Address Translation Method............................................................................... 174 MMU Functions................................................................................................................. 177 7.5.1 MMU Hardware Management............................................................................ 177 7.5.2 MMU Software Management ............................................................................. 177 7.5.3 MMU Instruction (LDTLB)................................................................................ 178 7.5.4 Hardware ITLB Miss Handling .......................................................................... 180 7.5.5 Avoiding Synonym Problems ............................................................................. 181 MMU Exceptions............................................................................................................... 182 7.6.1 Instruction TLB Multiple Hit Exception............................................................. 182 7.6.2 Instruction TLB Miss Exception......................................................................... 183 7.6.3 Instruction TLB Protection Violation Exception ................................................ 184 7.6.4 Data TLB Multiple Hit Exception ...................................................................... 185 7.6.5 Data TLB Miss Exception .................................................................................. 185 7.6.6 Data TLB Protection Violation Exception.......................................................... 187 7.6.7 Initial Page Write Exception............................................................................... 188 Memory-Mapped TLB Configuration................................................................................ 190 7.7.1 ITLB Address Array ........................................................................................... 191 7.7.2 ITLB Data Array (TLB Compatible Mode)........................................................ 192 7.7.3 ITLB Data Array (TLB Extended Mode) ........................................................... 193 7.7.4 UTLB Address Array.......................................................................................... 195 7.7.5 UTLB Data Array (TLB Compatible Mode) ...................................................... 196 7.7.6 UTLB Data Array (TLB Extended Mode).......................................................... 197 32-Bit Address Extended Mode ......................................................................................... 199 Rev.1.00 Jan. 10, 2008 Page xi of xxx REJ09B0261-0100 7.8.1 Overview of 32-Bit Address Extended Mode..................................................... 199 7.8.2 Transition to 32-Bit Address Extended Mode .................................................... 200 7.8.3 Privileged Space Mapping Buffer (PMB) Configuration ................................... 200 7.8.4 PMB Function..................................................................................................... 202 7.8.5 Memory-Mapped PMB Configuration ............................................................... 203 7.8.6 Notes on Using 32-Bit Address Extended Mode ................................................ 204 7.9 32-Bit Boot Function ......................................................................................................... 207 7.9.1 Initial Entries to PMB......................................................................................... 207 7.9.2 Notes on 32-Bit Boot .......................................................................................... 207 7.10 Usage Notes ....................................................................................................................... 209 7.10.1 Note on Using LDTLB Instruction ..................................................................... 209 Section 8 Caches ................................................................................................................... 211 8.1 8.2 Features.............................................................................................................................. 211 Register Descriptions......................................................................................................... 215 8.2.1 Cache Control Register (CCR) ........................................................................... 216 8.2.2 Queue Address Control Register 0 (QACR0)..................................................... 218 8.2.3 Queue Address Control Register 1 (QACR1)..................................................... 219 8.2.4 On-Chip Memory Control Register (RAMCR) .................................................. 220 Operand Cache Operation.................................................................................................. 222 8.3.1 Read Operation ................................................................................................... 222 8.3.2 Prefetch Operation .............................................................................................. 223 8.3.3 Write Operation .................................................................................................. 224 8.3.4 Write-Back Buffer .............................................................................................. 225 8.3.5 Write-Through Buffer......................................................................................... 225 8.3.6 OC Two-Way Mode ........................................................................................... 226 Instruction Cache Operation .............................................................................................. 227 8.4.1 Read Operation ................................................................................................... 227 8.4.2 Prefetch Operation .............................................................................................. 227 8.4.3 IC Two-Way Mode............................................................................................. 228 8.4.4 Instruction Cache Way Prediction Operation ..................................................... 228 Cache Operation Instruction .............................................................................................. 229 8.5.1 Coherency between Cache and External Memory.............................................. 229 8.5.2 Prefetch Operation .............................................................................................. 231 Memory-Mapped Cache Configuration ............................................................................. 232 8.6.1 IC Address Array................................................................................................ 232 8.6.2 IC Data Array ..................................................................................................... 234 8.6.3 OC Address Array .............................................................................................. 234 8.6.4 OC Data Array.................................................................................................... 236 8.6.5 Memory-Mapped Cache Associative Write Operation....................................... 237 8.3 8.4 8.5 8.6 Rev.1.00 Jan. 10, 2008 Page xii of xxx REJ09B0261-0100 8.7 8.8 Store Queues ...................................................................................................................... 238 8.7.1 SQ Configuration................................................................................................ 238 8.7.2 Writing to SQ...................................................................................................... 238 8.7.3 Transfer to External Memory.............................................................................. 239 8.7.4 Determination of SQ Access Exception.............................................................. 240 8.7.5 Reading from SQ ................................................................................................ 240 Notes on Using 32-Bit Address Extended Mode ............................................................... 241 Section 9 On-Chip Memory .............................................................................................. 243 9.1 9.2 Features.............................................................................................................................. 243 Register Descriptions ......................................................................................................... 246 9.2.1 On-Chip Memory Control Register (RAMCR) .................................................. 247 9.2.2 OL memory Transfer Source Address Register 0 (LSA0).................................. 248 9.2.3 OL memory Transfer Source Address Register 1 (LSA1).................................. 250 9.2.4 OL memory Transfer Destination Address Register 0 (LDA0) .......................... 252 9.2.5 OL memory Transfer Destination Address Register 1 (LDA1) .......................... 254 Operation ........................................................................................................................... 256 9.3.1 Instruction Fetch Access from the CPU.............................................................. 256 9.3.2 Operand Access from the CPU and Access from the FPU ................................. 256 9.3.3 Access from the SuperHyway Bus Master Module ............................................ 257 9.3.4 OL Memory Block Transfer ............................................................................... 257 On-Chip Memory Protective Functions ............................................................................. 260 Usage Notes ....................................................................................................................... 261 9.5.1 Page Conflict ...................................................................................................... 261 9.5.2 Access Across Different Pages ........................................................................... 261 9.5.3 On-Chip Memory Coherency ............................................................................. 261 9.5.4 Sleep Mode ......................................................................................................... 262 Note on Using 32-Bit Address Extended Mode................................................................. 262 9.3 9.4 9.5 9.6 Section 10 Interrupt Controller (INTC) ......................................................................... 263 10.1 Features.............................................................................................................................. 263 10.1.1 Interrupt Method................................................................................................. 266 10.1.2 Interrupt Sources................................................................................................. 267 10.2 Input/Output Pins ............................................................................................................... 272 10.3 Register Descriptions ......................................................................................................... 273 10.3.1 External Interrupt Request Registers .................................................................. 277 10.3.2 User Mode Interrupt Disable Function ............................................................... 298 10.3.3 On-chip Module Interrupt Priority Registers ...................................................... 300 10.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7).. 314 10.3.5 GPIO Interrupt Set Register (INT2GPIC) .......................................................... 322 Rev.1.00 Jan. 10, 2008 Page xiii of xxx REJ09B0261-0100 10.4 Interrupt Sources................................................................................................................ 324 10.4.1 NMI Interrupts.................................................................................................... 324 10.4.2 IRQ Interrupts..................................................................................................... 324 10.4.3 IRL Interrupts ..................................................................................................... 325 10.4.4 On-Chip Peripheral Module Interrupts ............................................................... 327 10.4.5 Priority of On-Chip Peripheral Module Interrupts.............................................. 328 10.4.6 Interrupt Exception Handling and Priority ......................................................... 329 10.5 Operation ........................................................................................................................... 337 10.5.1 Interrupt Sequence .............................................................................................. 337 10.5.2 Multiple Interrupts .............................................................................................. 339 10.5.3 Interrupt Masking by MAI Bit............................................................................ 339 10.6 Interrupt Response Time.................................................................................................... 340 10.7 Usage Notes ....................................................................................................................... 343 10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0.LVLMODE = 0 ....................................................... 343 10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function ..................................................... 344 10.7.3 Clearing IRQ and IRL Interrupt Requests .......................................................... 345 Section 11 Local Bus State Controller (LBSC) ........................................................... 347 11.1 Features.............................................................................................................................. 347 11.2 Input/Output Pins............................................................................................................... 350 11.3 Overview of Areas ............................................................................................................. 354 11.3.1 Space Divisions .................................................................................................. 354 11.3.2 Memory Bus Width ............................................................................................ 357 11.3.3 PCMCIA Support ............................................................................................... 358 11.4 Register Descriptions......................................................................................................... 362 11.4.1 Memory Address Map Select Register (MMSELR)........................................... 364 11.4.2 Bus Control Register (BCR) ............................................................................... 367 11.4.3 CSn Bus Control Register (CSnBCR) ................................................................ 371 11.4.4 CSn Wait Control Register (CSnWCR).............................................................. 377 11.4.5 CSn PCMCIA Control Register (CSnPCR)........................................................ 382 11.5 Operation ........................................................................................................................... 387 11.5.1 Endian/Access Size and Data Alignment ........................................................... 387 11.5.2 Areas................................................................................................................... 398 11.5.3 SRAM interface .................................................................................................. 403 11.5.4 Burst ROM Interface .......................................................................................... 412 11.5.5 PCMCIA Interface.............................................................................................. 416 11.5.6 MPX Interface .................................................................................................... 427 11.5.7 Byte Control SRAM Interface ............................................................................ 441 11.5.8 Wait Cycles between Access Cycles .................................................................. 446 Rev.1.00 Jan. 10, 2008 Page xiv of xxx REJ09B0261-0100 11.5.9 11.5.10 11.5.11 11.5.12 11.5.13 11.5.14 Bus Arbitration ................................................................................................... 448 Master Mode....................................................................................................... 450 Slave Mode ......................................................................................................... 451 Cooperation between Master and Slave.............................................................. 451 Power-Down Mode and Bus Arbitration ............................................................ 451 Mode Pin Settings and General Input Output Port Settings about Data Bus Width................................................................................................... 452 11.5.15 Pins Multiplexed with Other Modules Functions ............................................... 452 11.5.16 Register Settings for Divided-Up DACKn Output ............................................. 452 Section 12 DDR2-SDRAM Interface (DBSC2) .......................................................... 457 12.1 12.2 12.3 12.4 Features.............................................................................................................................. 457 Input/Output Pins ............................................................................................................... 460 Data Alignment.................................................................................................................. 465 Register Descriptions ......................................................................................................... 479 12.4.1 DBSC2 Status Register (DBSTATE) ................................................................. 482 12.4.2 SDRAM Operation Enable Register (DBEN)..................................................... 483 12.4.3 SDRAM Command Control Register (DBCMDCNT) ....................................... 484 12.4.4 SDRAM Configuration Setting Register (DBCONF)......................................... 486 12.4.5 SDRAM Timing Register 0 (DBTR0) ................................................................ 488 12.4.6 SDRAM Timing Register 1 (DBTR1) ................................................................ 492 12.4.7 SDRAM Timing Register 2 (DBTR2) ................................................................ 495 12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0) .......................................... 499 12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1) .......................................... 500 12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) .......................................... 502 12.4.11 SDRAM Refresh Status Register (DBRFSTS) ................................................... 504 12.4.12 DDRPAD Frequency Setting Register (DBFREQ) ............................................ 505 12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)..................... 507 12.4.14 SDRAM Mode Setting Register (DBMRCNT) .................................................. 510 12.5 DBSC2 Operation .............................................................................................................. 512 12.5.1 Supported SDRAM Commands.......................................................................... 512 12.5.2 SDRAM Command Issue ................................................................................... 513 12.5.3 Initialization Sequence........................................................................................ 516 12.5.4 Self-Refresh Operation ....................................................................................... 517 12.5.5 Auto-Refresh Operation...................................................................................... 520 12.5.6 Regarding Address Multiplexing........................................................................ 521 12.5.7 Regarding SDRAM Access and Timing Constraints.......................................... 530 12.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products ..... 544 12.5.9 Important Information Regarding ODT Control Signal Output to SDRAM ...... 544 12.5.10 DDR2-SDRAM Power Supply Backup Function............................................... 546 Rev.1.00 Jan. 10, 2008 Page xv of xxx REJ09B0261-0100 12.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation, etc. ................................................................................................ 549 12.5.12 Regarding the Supported Clock Ratio ................................................................ 549 12.5.13 Regarding MCKE Signal Operation ................................................................... 550 Section 13 PCI Controller (PCIC) ................................................................................... 551 13.1 Features.............................................................................................................................. 551 13.2 Input/Output Pins............................................................................................................... 554 13.3 Register Descriptions......................................................................................................... 557 13.3.1 PCIC Enable Control Register (PCIECR) .......................................................... 562 13.3.2 Configuration Registers ...................................................................................... 563 13.3.3 PCI Local Registers ............................................................................................ 590 13.4 Operation ........................................................................................................................... 630 13.4.1 Supported PCI Commands ................................................................................. 630 13.4.2 PCIC Initialization .............................................................................................. 631 13.4.3 Master Access..................................................................................................... 632 13.4.4 Target Access ..................................................................................................... 640 13.4.5 Host Mode .......................................................................................................... 648 13.4.6 Normal Mode...................................................................................................... 651 13.4.7 Power Management ............................................................................................ 651 13.4.8 PCI Local Bus Basic Interface............................................................................ 653 Section 14 Direct Memory Access Controller (DMAC)........................................... 665 14.1 Features.............................................................................................................................. 665 14.2 Input/Output Pins............................................................................................................... 667 14.3 Register Descriptions......................................................................................................... 668 14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11)............................... 675 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9)............................................................ 676 14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) ...................... 677 14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9) ......................................................... 678 14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11)................................ 679 14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9)............................................................ 680 14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) ....................... 681 14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1)................................ 689 14.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)................. 693 14.4 Operation ........................................................................................................................... 701 14.4.1 DMA Transfer Requests ..................................................................................... 701 Rev.1.00 Jan. 10, 2008 Page xvi of xxx REJ09B0261-0100 14.4.2 Channel Priority.................................................................................................. 706 14.4.3 DMA Transfer Types.......................................................................................... 709 14.4.4 DMA Transfer Flow ........................................................................................... 717 14.4.5 Repeat Mode Transfer ........................................................................................ 719 14.4.6 Reload Mode Transfer ........................................................................................ 720 14.4.7 DREQ Pin Sampling Timing .............................................................................. 721 14.5 DMAC Interrupt Sources ................................................................................................... 729 14.6 Usage Notes ....................................................................................................................... 730 14.6.1 Stopping Modules and Changing Frequency ...................................................... 730 14.6.2 Address Error...................................................................................................... 730 14.6.3 NMI Interrupt...................................................................................................... 730 14.6.4 Burst Mode Transfer........................................................................................... 730 14.6.5 Divided-Up DACK Output................................................................................. 730 14.6.6 DACK/DREQ Setting......................................................................................... 731 Section 15 Clock Pulse Generator (CPG) ..................................................................... 733 15.1 15.2 15.3 15.4 Features.............................................................................................................................. 733 Input/Output Pins ............................................................................................................... 736 Clock Operating Modes ..................................................................................................... 737 Register Descriptions ......................................................................................................... 739 15.4.1 Frequency Control Register 0 (FRQCR0) .......................................................... 741 15.4.2 Frequency Control Register 1 (FRQCR1) .......................................................... 742 15.4.3 Frequency Display Register 1 (FRQMR1) ......................................................... 745 15.4.4 PLL Control Register (PLLCR).......................................................................... 747 15.5 Calculating the Frequency ................................................................................................. 748 15.6 How to Change the Frequency........................................................................................... 749 15.6.1 Changing the Frequency of Clocks Other than the Bus Clock ........................... 749 15.6.2 Changing the Bus Clock Frequency ................................................................... 749 15.7 Notes on Designing Board ................................................................................................. 756 Section 16 Watchdog Timer and Reset (WDT) ........................................................... 759 16.1 Features.............................................................................................................................. 759 16.2 Input/Output Pins ............................................................................................................... 761 16.3 Register Descriptions ......................................................................................................... 762 16.3.1 Watchdog Timer Stop Time Register (WDTST) ................................................ 763 16.3.2 Watchdog Timer Control/Status Register (WDTCSR)....................................... 764 16.3.3 Watchdog Timer Base Stop Time Register (WDTBST)..................................... 766 16.3.4 Watchdog Timer Counter (WDTCNT)............................................................... 767 16.3.5 Watchdog Timer Base Counter (WDTBCNT) ................................................... 768 16.4 Operation ........................................................................................................................... 769 Rev.1.00 Jan. 10, 2008 Page xvii of xxx REJ09B0261-0100 16.4.1 Reset Request ..................................................................................................... 769 16.4.2 Using Watchdog Timer Mode ............................................................................ 771 16.4.3 Using Interval Timer Mode ................................................................................ 771 16.4.4 Time until WDT Counters Overflow.................................................................. 772 16.4.5 Clearing WDT Counters ..................................................................................... 773 16.5 Status Pin Change Timing during Reset ............................................................................ 774 16.5.1 Power-On Reset by PRESET Pin ....................................................................... 774 16.5.2 Power-On Reset by Watchdog Timer Overflow................................................. 777 16.5.3 Manual Reset by Watchdog Timer Overflow ..................................................... 779 Section 17 Power-Down Mode ........................................................................................ 781 17.1 Features.............................................................................................................................. 781 17.1.1 Types of Power-Down Modes ............................................................................ 781 17.2 Input/Output Pins............................................................................................................... 783 17.3 Register Descriptions......................................................................................................... 783 17.3.1 Sleep Control Register (SLPCR) ........................................................................ 785 17.3.2 Standby Control Register 0 (MSTPCR0) ........................................................... 786 17.3.3 Standby Control Register 1 (MSTPCR1) ........................................................... 789 17.3.4 Standby Display Register (MSTPMR) ............................................................... 791 17.4 Sleep Mode ........................................................................................................................ 793 17.4.1 Transition to Sleep Mode.................................................................................... 793 17.4.2 Releasing Sleep Mode ........................................................................................ 793 17.5 Deep Sleep Mode............................................................................................................... 794 17.5.1 Transition to Deep Sleep Mode .......................................................................... 794 17.5.2 Releasing Deep Sleep Mode ............................................................................... 795 17.6 Module Standby Functions ................................................................................................ 796 17.6.1 Transition to Module Standby Mode .................................................................. 796 17.6.2 Releasing Module Standby Functions ................................................................ 796 17.7 Timing of the Changes on the STATUS Pins .................................................................... 797 17.7.1 Reset ................................................................................................................... 797 17.7.2 Releasing Sleep Mode ........................................................................................ 797 17.8 DDR-SDRAM Power Supply Backup............................................................................... 797 Section 18 Timer Unit (TMU) .......................................................................................... 799 18.1 Features.............................................................................................................................. 799 18.2 Input/Output Pins............................................................................................................... 801 18.3 Register Descriptions......................................................................................................... 802 18.3.1 Timer Start Registers (TSTRn) (n = 0, 1) ........................................................... 804 18.3.2 Timer Constant Registers (TCORn) (n = 0 to 5) ................................................ 806 18.3.3 Timer Counters (TCNTn) (n = 0 to 5) ................................................................ 806 Rev.1.00 Jan. 10, 2008 Page xviii of xxx REJ09B0261-0100 18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) ..................................................... 807 18.3.5 Input Capture Register 2 (TCPR2) ..................................................................... 809 18.4 Operation ........................................................................................................................... 810 18.4.1 Counter Operation .............................................................................................. 810 18.4.2 Input Capture Function ....................................................................................... 813 18.5 Interrupts............................................................................................................................ 814 18.6 Usage Notes ....................................................................................................................... 815 18.6.1 Register Writes ................................................................................................... 815 18.6.2 Reading from TCNT........................................................................................... 815 18.6.3 External Clock Frequency .................................................................................. 815 Section 19 Display Unit (DU) .......................................................................................... 817 19.1 Features.............................................................................................................................. 817 19.2 Input/Output Pins ............................................................................................................... 820 19.3 Register Descriptions ......................................................................................................... 821 19.3.1 Display Unit System Control Register................................................................ 841 19.3.2 Display Mode Register (DSMR) ........................................................................ 845 19.3.3 Display Status Register (DSSR) ......................................................................... 849 19.3.4 Display Unit Status Register Clear Register (DSRCR) ...................................... 853 19.3.5 Display Unit Interrupt Enable Register (DIER).................................................. 854 19.3.6 Color Palette Control Register (CPCR) .............................................................. 857 19.3.7 Display Plane Priority Register (DPPR) ............................................................. 859 19.3.8 Display Unit Extensional Function Enable Register (DEFR)............................. 862 19.3.9 Horizontal Display Start Register (HDSR)......................................................... 864 19.3.10 Horizontal Display End Register (HDER).......................................................... 865 19.3.11 Vertical Display Start Register (VDSR) ............................................................. 866 19.3.12 Vertical Display End Register (VDER) .............................................................. 867 19.3.13 Horizontal Cycle Register (HCR)....................................................................... 868 19.3.14 Horizontal Sync Width Register (HSWR) .......................................................... 869 19.3.15 Vertical Cycle Register (VCR) ........................................................................... 870 19.3.16 Vertical Sync Point Register (VSPR) ................................................................. 871 19.3.17 Equal Pulse Width Register (EQWR)................................................................. 872 19.3.18 Separation Width Register (SPWR).................................................................... 873 19.3.19 CLAMP Signal Start Register (CLAMPSR) ...................................................... 874 19.3.20 CLAMP Signal Width Register (CLAMPWR)................................................... 875 19.3.21 DE Signal Start Register (DESR) ....................................................................... 876 19.3.22 DE Signal Width Register (DEWR) ................................................................... 877 19.3.23 Color Palette 1 Transparent Color Register (CP1TR)......................................... 878 19.3.24 Color Palette 2 Transparent Color Register (CP2TR)......................................... 881 19.3.25 Color Palette 3 Transparent Color Register (CP3TR)......................................... 884 Rev.1.00 Jan. 10, 2008 Page xix of xxx REJ09B0261-0100 19.3.26 Color Palette 4 Transparent Color Register (CP4TR) ........................................ 887 19.3.27 Display Off Mode Output Register (DOOR)...................................................... 890 19.3.28 Color Detection Register (CDER) ...................................................................... 891 19.3.29 Background Plane Output Register (BPOR)....................................................... 892 19.3.30 Raster Interrupt Offset Register (RINTOFSR) ................................................... 894 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) ....................................................... 895 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6).................................... 898 19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) .............................. 899 19.3.34 Plane n Display Size X Register (PnDSXR) (n = 1 to 6).................................... 901 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6).................................... 902 19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6).............................. 903 19.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6).............................. 904 19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6) ........... 905 19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6) ........... 906 19.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6) ................................... 907 19.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6) ................................... 908 19.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n = 1 to 6) ............ 909 19.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1 to 6) ...... 910 19.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6) ....................................... 911 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6)............................. 912 19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6)............................. 913 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6).................................... 914 19.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R) ........................ 915 19.3.49 Color Palette 2 Register 000 to 255 (CP2_000R to CP2_255R) ........................ 916 19.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R) ........................ 918 19.3.51 Color Palette 4 Register 000 to 255 (CP4_000R to CP4_255R) ........................ 919 19.3.52 External Synchronization Control Register (ESCR)........................................... 921 19.3.53 Output Signal Timing Adjustment Register (OTAR) ......................................... 923 19.4 Operation ........................................................................................................................... 930 19.4.1 Configuration of Output Screen.......................................................................... 930 19.4.2 Display On/Off ................................................................................................... 933 19.4.3 Plane Parameter .................................................................................................. 934 19.4.4 Memory Allocation............................................................................................. 936 19.4.5 Input Display Data Format ................................................................................. 937 19.4.6 Output Data Format ............................................................................................ 940 19.4.7 Endian Conversion.............................................................................................. 940 19.4.8 Color Palettes...................................................................................................... 942 19.4.9 Superpositioning of Planes ................................................................................. 943 19.4.10 Display Contention ............................................................................................. 947 19.4.11 Blinking .............................................................................................................. 949 Rev.1.00 Jan. 10, 2008 Page xx of xxx REJ09B0261-0100 19.4.12 Scroll Display ..................................................................................................... 950 19.4.13 Wraparound Display ........................................................................................... 951 19.4.14 Upper-Left Overflow Display............................................................................. 952 19.4.15 Double Buffer Control ........................................................................................ 953 19.4.16 Sync Mode .......................................................................................................... 954 19.5 Display Control.................................................................................................................. 956 19.5.1 Display Timing Generation ................................................................................ 956 19.5.2 CSYNC............................................................................................................... 959 19.5.3 Scan Method ....................................................................................................... 961 19.5.4 Color Detection................................................................................................... 965 19.5.5 Output Signal Timing Adjustment...................................................................... 966 19.5.6 CLAMP Signal and DE Signal ........................................................................... 967 19.6 Power-Down Sequence ...................................................................................................... 968 19.6.1 Procedures before Executing the Power-Down Sequence .................................. 968 19.6.2 Resetting the Power-Down Sequence ................................................................. 968 Section 20 Graphics Data Translation Accelerator (GDTA) ................................... 969 20.1 Features.............................................................................................................................. 969 20.2 GDTA Address Space........................................................................................................ 973 20.3 Register Descriptions ......................................................................................................... 974 20.3.1 GA Mask Register (GACMR) ............................................................................ 979 20.3.2 GA Enable Register (GACER) ........................................................................... 980 20.3.3 GA Interrupt Source Indicating Register (GACISR) .......................................... 981 20.3.4 GA Interrupt Source Indication Clear Register (GACICR) ................................ 982 20.3.5 GA Interrupt Enable Register (GACIER)........................................................... 983 20.3.6 GA CL Input Data Alignment Register (DRCL_CTL)....................................... 984 20.3.7 GA CL Output Data Alignment Register (DWCL_CTL)................................... 985 20.3.8 GA MC Input Data Alignment Register (DRMC_CTL) .................................... 986 20.3.9 GA MC Output Data Alignment Register (DWMC_CTL)................................. 987 20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL)................................. 988 20.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL) ................................. 989 20.3.12 CL Command FIFO (CLCF) .............................................................................. 990 20.3.13 CL Control Register (CLCR).............................................................................. 991 20.3.14 CL Status Register (CLSR)................................................................................. 993 20.3.15 CL Frame Width Setting Register (CLWR) ....................................................... 994 20.3.16 CL Frame Height Setting Register (CLHR) ....................................................... 995 20.3.17 CL Input Y Padding Size Setting Register (CLIYPR)........................................ 996 20.3.18 CL Input UV Padding Size Setting Register (CLIUVPR) .................................. 997 20.3.19 CL Output Padding Size Setting Register (CLOPR) .......................................... 998 20.3.20 CL Palette Pointer Register (CLPLPR) .............................................................. 999 Rev.1.00 Jan. 10, 2008 Page xxi of xxx REJ09B0261-0100 20.4 20.5 20.6 20.7 20.3.21 MC Command FIFO (MCCF) .......................................................................... 1000 20.3.22 MC Status Register (MCSR) ............................................................................ 1003 20.3.23 MC Frame Width Setting Register (MCWR) ................................................... 1004 20.3.24 MC Frame Height Setting Register (MCHR) ................................................... 1005 20.3.25 MC Y Padding Size Setting Register (MCYPR) .............................................. 1006 20.3.26 MC UV Padding Size Setting Register (MCUVPR) ........................................ 1007 20.3.27 MC Output Frame Y Pointer Register (MCOYPR).......................................... 1008 20.3.28 MC Output Frame U Pointer Register (MCOUPR).......................................... 1008 20.3.29 MC Output Frame V Pointer Register (MCOVPR).......................................... 1009 20.3.30 MC Past Frame Y Pointer Register (MCPYPR)............................................... 1009 20.3.31 MC Past Frame U Pointer Register (MCPUPR)............................................... 1010 20.3.32 MC Past Frame V Pointer Register (MCPVPR)............................................... 1010 20.3.33 MC Future Frame Y Pointer Register (MCFYPR) ........................................... 1011 20.3.34 MC Future Frame U Pointer Register (MCFUPR) ........................................... 1011 20.3.35 MC Future Frame V Pointer Register (MCFVPR) ........................................... 1012 GDTA Operation ............................................................................................................. 1013 20.4.1 Explanation of CL Operation............................................................................ 1013 20.4.2 Explanation of MC Operation........................................................................... 1019 Interrupt Processing ......................................................................................................... 1029 Data Alignment................................................................................................................ 1029 Usage Notes ..................................................................................................................... 1031 20.7.1 Regarding Module Stoppage ............................................................................ 1031 20.7.2 Regarding Deep Sleep Modes........................................................................... 1031 20.7.3 Regarding Frequency Changes ......................................................................... 1032 Section 21 Serial Communication Interface with FIFO (SCIF) ........................... 1033 21.1 Features............................................................................................................................ 1033 21.2 Input/Output Pins............................................................................................................. 1039 21.3 Register Descriptions....................................................................................................... 1040 21.3.1 Receive Shift Register (SCRSR) ...................................................................... 1046 21.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 1046 21.3.3 Transmit Shift Register (SCTSR) ..................................................................... 1047 21.3.4 Transmit FIFO Data Register (SCFTDR)......................................................... 1047 21.3.5 Serial Mode Register (SCSMR) ....................................................................... 1048 21.3.6 Serial Control Register (SCSCR) ..................................................................... 1051 21.3.7 Serial Status Register n (SCFSR) ..................................................................... 1055 21.3.8 Bit Rate Register n (SCBRR) ........................................................................... 1061 21.3.9 FIFO Control Register n (SCFCR) ................................................................... 1062 21.3.10 Transmit FIFO Data Count Register n (SCTFDR) ........................................... 1064 21.3.11 Receive FIFO Data Count Register n (SCRFDR) ............................................ 1065 Rev.1.00 Jan. 10, 2008 Page xxii of xxx REJ09B0261-0100 21.3.12 Serial Port Register n (SCSPTR) ...................................................................... 1066 21.3.13 Line Status Register n (SCLSR) ....................................................................... 1069 21.3.14 Serial Error Register n (SCRER) ...................................................................... 1070 21.4 Operation ......................................................................................................................... 1071 21.4.1 Overview .......................................................................................................... 1071 21.4.2 Operation in Asynchronous Mode .................................................................... 1074 21.4.3 Operation in Clocked Synchronous Mode ........................................................ 1085 21.5 SCIF Interrupt Sources and the DMAC ........................................................................... 1094 21.6 Usage Notes ..................................................................................................................... 1096 Section 22 Serial I/O with FIFO (SIOF) ...................................................................... 1099 22.1 Features............................................................................................................................ 1099 22.2 Input/Output Pins ............................................................................................................. 1101 22.3 Register Descriptions ....................................................................................................... 1102 22.3.1 Mode Register (SIMDR) .................................................................................. 1104 22.3.2 Control Register (SICTR)................................................................................. 1106 22.3.3 Transmit Data Register (SITDR) ...................................................................... 1108 22.3.4 Receive Data Register (SIRDR) ....................................................................... 1109 22.3.5 Transmit Control Data Register (SITCR) ......................................................... 1110 22.3.6 Receive Control Data Register (SIRCR) .......................................................... 1111 22.3.7 Status Register (SISTR).................................................................................... 1112 22.3.8 Interrupt Enable Register (SIIER) .................................................................... 1118 22.3.9 FIFO Control Register (SIFCTR) ..................................................................... 1120 22.3.10 Clock Select Register (SISCR) ......................................................................... 1122 22.3.11 Transmit Data Assign Register (SITDAR) ....................................................... 1123 22.3.12 Receive Data Assign Register (SIRDAR) ........................................................ 1125 22.3.13 Control Data Assign Register (SICDAR) ......................................................... 1126 22.4 Operation ......................................................................................................................... 1128 22.4.1 Serial Clocks..................................................................................................... 1128 22.4.2 Serial Timing .................................................................................................... 1129 22.4.3 Transfer Data Format........................................................................................ 1131 22.4.4 Register Allocation of Transfer Data ................................................................ 1133 22.4.5 Control Data Interface ...................................................................................... 1135 22.4.6 FIFO.................................................................................................................. 1137 22.4.7 Transmit and Receive Procedures..................................................................... 1139 22.4.8 Interrupts........................................................................................................... 1144 22.4.9 Transmit and Receive Timing........................................................................... 1146 Section 23 Serial Peripheral Interface (HSPI)............................................................ 1151 23.1 Features............................................................................................................................ 1151 Rev.1.00 Jan. 10, 2008 Page xxiii of xxx REJ09B0261-0100 23.2 Input/Output Pins............................................................................................................. 1153 23.3 Register Descriptions....................................................................................................... 1153 23.3.1 Control Register (SPCR) .................................................................................. 1155 23.3.2 Status Register (SPSR) ..................................................................................... 1158 23.3.3 System Control Register (SPSCR) ................................................................... 1161 23.3.4 Transmit Buffer Register (SPTBR) .................................................................. 1163 23.3.5 Receive Buffer Register (SPRBR).................................................................... 1164 23.4 Operation ......................................................................................................................... 1165 23.4.1 Operation Overview with FIFO Mode Disabled............................................... 1165 23.4.2 Operation with FIFO Mode Enabled ................................................................ 1166 23.4.3 Timing Diagrams .............................................................................................. 1167 23.4.4 HSPI Software Reset ........................................................................................ 1169 23.4.5 Clock Polarity and Transmit Control................................................................ 1169 23.4.6 Transmit and Receive Routines ........................................................................ 1169 23.4.7 Flags and Interrupt Timing ............................................................................... 1170 23.4.8 Low-Power Consumption and Clock Synchronization..................................... 1170 Section 24 Multimedia Card Interface (MMCIF) ..................................................... 1171 24.1 Features............................................................................................................................ 1171 24.2 Input/Output Pins............................................................................................................. 1172 24.3 Register Descriptions....................................................................................................... 1173 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)............................................ 1177 24.3.2 Command Start Register (CMDSTRT) ............................................................ 1178 24.3.3 Operation Control Register (OPCR)................................................................. 1179 24.3.4 Card Status Register (CSTR)............................................................................ 1181 24.3.5 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2)................................. 1183 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) ............................... 1187 24.3.7 Transfer Clock Control Register (CLKON) ..................................................... 1193 24.3.8 Command Timeout Control Register (CTOCR)............................................... 1194 24.3.9 Transfer Byte Number Count Register (TBCR) ............................................... 1195 24.3.10 Mode Register (MODER)................................................................................. 1196 24.3.11 Command Type Register (CMDTYR).............................................................. 1197 24.3.12 Response Type Register (RSPTYR)................................................................. 1198 24.3.13 Transfer Block Number Counter (TBNCR) ..................................................... 1202 24.3.14 Response Registers 0 to 16, D (RSPR0 to RSPR16, RSPRD).......................... 1203 24.3.15 Data Timeout Register (DTOUTR) .................................................................. 1205 24.3.16 Data Register (DR) ........................................................................................... 1206 24.3.17 FIFO Pointer Clear Register (FIFOCLR) ......................................................... 1207 24.3.18 DMA Control Register (DMACR) ................................................................... 1208 24.4 Operation ......................................................................................................................... 1209 Rev.1.00 Jan. 10, 2008 Page xxiv of xxx REJ09B0261-0100 24.4.1 Operations in MMC Mode................................................................................ 1209 24.5 MMCIF Interrupt Sources................................................................................................ 1239 24.6 Operations when Using DMA.......................................................................................... 1240 24.6.1 Operation in Read Sequence............................................................................. 1240 24.6.2 Operation in Write Sequence ............................................................................ 1250 24.7 Register Accesses with Little Endian Specification......................................................... 1261 Section 25 Audio Codec Interface (HAC) .................................................................. 1263 25.1 Features............................................................................................................................ 1263 25.2 Input/Output Pins ............................................................................................................. 1265 25.3 Register Descriptions ....................................................................................................... 1266 25.3.1 Control and Status Register (HACCR) ............................................................. 1269 25.3.2 Command/Status Address Register (HACCSAR) ............................................ 1271 25.3.3 Command/Status Data Register (HACCSDR).................................................. 1273 25.3.4 PCM Left Channel Register (HACPCML)....................................................... 1275 25.3.5 PCM Right Channel Register (HACPCMR) .................................................... 1277 25.3.6 TX Interrupt Enable Register (HACTIER)....................................................... 1278 25.3.7 TX Status Register (HACTSR)......................................................................... 1279 25.3.8 RX Interrupt Enable Register (HACRIER) ...................................................... 1281 25.3.9 RX Status Register (HACRSR) ........................................................................ 1282 25.3.10 HAC Control Register (HACACR) .................................................................. 1284 25.4 AC 97 Frame Slot Structure............................................................................................. 1286 25.5 Operation ......................................................................................................................... 1288 25.5.1 Receiver ............................................................................................................ 1288 25.5.2 Transmitter........................................................................................................ 1288 25.5.3 DMA................................................................................................................. 1289 25.5.4 Interrupts........................................................................................................... 1289 25.5.5 Initialization Sequence...................................................................................... 1290 25.5.6 Power-Down Mode........................................................................................... 1295 25.5.7 Notes................................................................................................................. 1295 25.5.8 Reference .......................................................................................................... 1295 Section 26 Serial Sound Interface (SSI) Module ...................................................... 1297 26.1 Features............................................................................................................................ 1297 26.2 Input/Output Pins ............................................................................................................. 1299 26.3 Register Descriptions ....................................................................................................... 1300 26.3.1 Control Register (SSICR) ................................................................................. 1301 26.3.2 Status Register (SSISR) .................................................................................... 1308 26.3.3 Transmit Data Register (SSITDR).................................................................... 1313 26.3.4 Receive Data Register (SSIRDR) ..................................................................... 1313 Rev.1.00 Jan. 10, 2008 Page xxv of xxx REJ09B0261-0100 26.4 Operation ......................................................................................................................... 1314 26.4.1 Bus Format ....................................................................................................... 1314 26.4.2 Non-Compressed Modes .................................................................................. 1315 26.4.3 Compressed Modes........................................................................................... 1324 26.4.4 Operation Modes .............................................................................................. 1327 26.4.5 Transmit Operation........................................................................................... 1328 26.4.6 Receive Operation ............................................................................................ 1331 26.4.7 Serial Clock Control ......................................................................................... 1334 26.5 Usage Note....................................................................................................................... 1335 26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation ........ 1335 26.5.2 Pin Function Setting for the SSI Module.......................................................... 1335 26.5.3 Usage Note in Slave Mode ............................................................................... 1335 Section 27 NAND Flash Memory Controller (FLCTL).......................................... 1337 27.1 Features............................................................................................................................ 1337 27.2 Input/Output Pins............................................................................................................. 1340 27.3 Register Descriptions....................................................................................................... 1342 27.3.1 Common Control Register (FLCMNCR) ......................................................... 1344 27.3.2 Command Control Register (FLCMDCR)........................................................ 1346 27.3.3 Command Code Register (FLCMCDR) ........................................................... 1348 27.3.4 Address Register (FLADR) .............................................................................. 1349 27.3.5 Address Register 2 (FLADR2) ......................................................................... 1351 27.3.6 Data Counter Register (FLDTCNTR) .............................................................. 1352 27.3.7 Data Register (FLDATAR) .............................................................................. 1353 27.3.8 Interrupt DMA Control Register (FLINTDMACR) ......................................... 1354 27.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ..................................... 1359 27.3.10 Ready Busy Timeout Counter (FLBSYCNT)................................................... 1360 27.3.11 Data FIFO Register (FLDTFIFO)..................................................................... 1361 27.3.12 Control Code FIFO Register (FLECFIFO)....................................................... 1362 27.3.13 Transfer Control Register (FLTRCR)............................................................... 1363 27.4 Operation ......................................................................................................................... 1364 27.4.1 Operating Modes .............................................................................................. 1364 27.4.2 Command Access Mode ................................................................................... 1364 27.4.3 Sector Access Mode ......................................................................................... 1368 27.4.4 Status Read ....................................................................................................... 1371 27.5 Example of Register Setting ............................................................................................ 1373 27.6 Interrupt Processing ......................................................................................................... 1376 27.7 DMA Transfer Settings.................................................................................................... 1376 Rev.1.00 Jan. 10, 2008 Page xxvi of xxx REJ09B0261-0100 Section 28 General Purpose I/O Ports (GPIO)........................................................... 1377 28.1 Features............................................................................................................................ 1377 28.2 Register Descriptions ....................................................................................................... 1382 28.2.1 Port A Control Register (PACR) ...................................................................... 1386 28.2.2 Port B Control Register (PBCR)....................................................................... 1389 28.2.3 Port C Control Register (PCCR)....................................................................... 1391 28.2.4 Port D Control Register (PDCR) ...................................................................... 1393 28.2.5 Port E Control Register (PECR) ....................................................................... 1395 28.2.6 Port F Control Register (PFCR)........................................................................ 1397 28.2.7 Port G Control Register (PGCR) ...................................................................... 1399 28.2.8 Port H Control Register (PHCR) ...................................................................... 1401 28.2.9 Port J Control Register (PJCR) ......................................................................... 1403 28.2.10 Port K Control Register (PKCR) ...................................................................... 1405 28.2.11 Port L Control Register (PLCR) ....................................................................... 1407 28.2.12 Port M Control Register (PMCR) ..................................................................... 1409 28.2.13 Port N Control Register (PNCR) ...................................................................... 1410 28.2.14 Port P Control Register (PPCR)........................................................................ 1412 28.2.15 Port Q Control Register (PQCR) ...................................................................... 1414 28.2.16 Port R Control Register (PRCR)....................................................................... 1416 28.2.17 Port A Data Register (PADR)........................................................................... 1418 28.2.18 Port B Data Register (PBDR) ........................................................................... 1419 28.2.19 Port C Data Register (PCDR) ........................................................................... 1420 28.2.20 Port D Data Register (PDDR)........................................................................... 1421 28.2.21 Port E Data Register (PEDR)............................................................................ 1422 28.2.22 Port F Data Register (PFDR) ............................................................................ 1423 28.2.23 Port G Data Register (PGDR)........................................................................... 1424 28.2.24 Port H Data Register (PHDR)........................................................................... 1425 28.2.25 Port J Data Register (PJDR) ............................................................................. 1426 28.2.26 Port K Data Register (PKDR)........................................................................... 1427 28.2.27 Port L Data Register (PLDR)............................................................................ 1428 28.2.28 Port M Data Register (PMDR) ......................................................................... 1429 28.2.29 Port N Data Register (PNDR)........................................................................... 1430 28.2.30 Port P Data Register (PPDR) ............................................................................ 1431 28.2.31 Port Q Data Register (PQDR)........................................................................... 1432 28.2.32 Port R Data Register (PRDR) ........................................................................... 1433 28.2.33 Port E Pull-Up Control Register (PEPUPR) ..................................................... 1434 28.2.34 Port H Pull-Up Control Register (PHPUPR) .................................................... 1435 28.2.35 Port J Pull-Up Control Register (PJPUPR)....................................................... 1436 28.2.36 Port K Pull-Up Control Register (PKPUPR) .................................................... 1437 Rev.1.00 Jan. 10, 2008 Page xxvii of xxx REJ09B0261-0100 28.2.37 Port L Pull-Up Control Register (PLPUPR)..................................................... 1438 28.2.38 Port M Pull-Up Control Register (PMPUPR)................................................... 1439 28.2.39 Port N Pull-Up Control Register (PNPUPR) .................................................... 1440 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) ............................................. 1441 28.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2) ............................................. 1441 28.2.42 Peripheral Module Select Register 1 (P1MSELR) ........................................... 1443 28.2.43 Peripheral Module Select Register 2 (P2MSELR) ........................................... 1447 28.3 Usage Example ................................................................................................................ 1449 28.3.1 Port Output Function ........................................................................................ 1449 28.3.2 Port Input function............................................................................................ 1450 28.3.3 Peripheral Module Function ............................................................................. 1451 Section 29 User Break Controller (UBC) .................................................................... 1453 29.1 Features............................................................................................................................ 1453 29.2 Register Descriptions....................................................................................................... 1455 29.2.1 Match Condition Setting Registers 0 and 1 (CBR0 and CBR1) ....................... 1457 29.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1) ....................... 1463 29.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1).......................... 1465 29.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)......... 1466 29.2.5 Match Data Setting Register 1 (CDR1) ............................................................ 1468 29.2.6 Match Data Mask Setting Register 1 (CDMR1)............................................... 1469 29.2.7 Execution Count Break Register 1 (CETR1).................................................... 1470 29.2.8 Channel Match Flag Register (CCMFR) .......................................................... 1471 29.2.9 Break Control Register (CBCR) ....................................................................... 1472 29.3 Operation Description...................................................................................................... 1473 29.3.1 Definition of Words Related to Accesses ......................................................... 1473 29.3.2 User Break Operation Sequence ....................................................................... 1474 29.3.3 Instruction Fetch Cycle Break .......................................................................... 1475 29.3.4 Operand Access Cycle Break ........................................................................... 1476 29.3.5 Sequential Break............................................................................................... 1477 29.3.6 Program Counter Value to be Saved................................................................. 1479 29.4 User Break Debugging Support Function ........................................................................ 1480 29.5 User Break Examples....................................................................................................... 1481 29.6 Usage Notes ..................................................................................................................... 1485 Section 30 User Debugging Interface (H-UDI) ......................................................... 1487 30.1 Features............................................................................................................................ 1487 30.2 Input/Output Pins............................................................................................................. 1489 30.3 Register Description ........................................................................................................ 1491 30.3.1 Instruction Register (SDIR) .............................................................................. 1492 Rev.1.00 Jan. 10, 2008 Page xxviii of xxx REJ09B0261-0100 30.3.2 Interrupt Source Register (SDINT)................................................................... 1492 30.3.3 Bypass Register (SDBPR) ................................................................................ 1493 30.3.4 Boundary Scan Register (SDBSR) ................................................................... 1493 30.4 Operation ......................................................................................................................... 1503 30.4.1 Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) ................................................................................................... 1503 30.4.2 TAP Control...................................................................................................... 1505 30.4.3 H-UDI Reset ..................................................................................................... 1506 30.4.4 H-UDI Interrupt ................................................................................................ 1507 30.5 Usage Notes ..................................................................................................................... 1507 Section 31 Register List .................................................................................................... 1509 31.1 Register Address List....................................................................................................... 1509 31.2 States of the Registers in the Individual Operating Modes .............................................. 1533 Section 32 Electrical Characteristics ............................................................................ 1561 32.1 Absolute Maximum Ratings ............................................................................................ 1561 32.2 DC Characteristics ........................................................................................................... 1562 32.3 AC Characteristics ........................................................................................................... 1567 32.3.1 Clock and Control Signal Timing ..................................................................... 1568 32.3.2 Control Signal Timing ...................................................................................... 1572 32.3.3 Bus Timing ....................................................................................................... 1574 32.3.4 DBSC2 Signal Timing ...................................................................................... 1592 32.3.5 INTC Module Signal Timing............................................................................ 1597 32.3.6 PCIC Module Signal Timing ............................................................................ 1599 32.3.7 DMAC Module Signal Timing ......................................................................... 1601 32.3.8 TMU Module Signal Timing ............................................................................ 1602 32.3.9 SCIF Module Signal Timing............................................................................. 1603 32.3.10 H-UDI Module Signal Timing.......................................................................... 1605 32.3.11 GPIO Signal Timing ......................................................................................... 1607 32.3.12 HSPI Module Signal Timing ............................................................................ 1608 32.3.13 SIOF Module Signal Timing ............................................................................ 1609 32.3.14 MMCIF Module Signal Timing........................................................................ 1613 32.3.15 HAC Interface Module Signal Timing.............................................................. 1614 32.3.16 SSI Interface Module Signal Timing ................................................................ 1616 32.3.17 FLCTL Module Signal Timing......................................................................... 1618 32.3.18 Display Unit Signal Timing.............................................................................. 1622 32.4 AC Characteristic Test Conditions................................................................................... 1625 Rev.1.00 Jan. 10, 2008 Page xxix of xxx REJ09B0261-0100 Appendix A. B. C. D. E. F. ............................................................................................................................ 1627 Package Dimensions ........................................................................................................ 1627 Mode Pin Settings............................................................................................................ 1628 Pin Functions ................................................................................................................... 1631 C.1 Pin States .......................................................................................................... 1631 C.2 Handling of Unused Pins .................................................................................. 1642 Turning On and Off Power Supply .................................................................................. 1653 D.1 Turning On and Off Between Each Power Supply Series ................................ 1653 D.2 Power-On and Power-Off Sequences for Power Supplies with Different Potentials in DDR2-SDRAM Power Supply Backup Mode............................. 1654 D.3 Turning On and Off Between the Same Power Supply Series.......................... 1655 Version Registers (PVR, PRR) ........................................................................................ 1656 Product Lineup................................................................................................................. 1657 Rev.1.00 Jan. 10, 2008 Page xxx of xxx REJ09B0261-0100 1. Overview Section 1 Overview The SH7785 incorporates a DDR2-SDRAM interface, a PCI controller, a DMA controller, timers, serial interfaces, audio interfaces, a graphics data translation accelerator (GDTA) that supports YUV data conversion and motion compensation processing, and a display unit (DU) that supports digital RGB display. The DDR2 interface, PCI interface, and the local bus are independent, providing dedicated external bus interfaces for the transfer of large amounts of data and of streaming data. The SH7785 contains an SH-4A (PVR.VER = H'30: Extended version), which is a 32-bit RISC (reduced instruction set computer) multiprocessor including an FPU as well as a CPU, providing upward compatibility (instruction set level) with the SH-1, SH-2, SH-3, and SH-4 microcomputers. The CPU and FPU run at 600 MHz. The processor also includes an instruction cache, an operand cache for which copy-back or write-through mode is selectable, a four-entry fully associative instruction TLB (translation look-aside buffer), and an MMU (memory management unit) with a 64-entry fully associative unified TLB. 1.1 Features of the SH7785 The features of the SH7785 are listed in table 1.1 Table 1.1 Item LSI SH7785 Features Features • • • • CPU Operating frequency: 600 MHz Voltage: 1.1 V (internal), 1.8 V (DDR2-SDRAM), 3.3 V (I/O) Package: 436-pin BGA (size: 19 × 19 mm, pin pitch: 0.8 mm) External bus (local bus) ⎯ Separate 26-bit address and 64-bit data buses (the PCI bus is not available when the 64-bit data bus is in use) ⎯ External bus frequency: up to 100 MHz • External bus (DDR2-SDRAM bus interface) ⎯ Separate 15-bit address and 32-bit data buses ⎯ External bus frequency: up to 300 MHz (600 Mbps) • External bus (PCI bus): ⎯ 32-bit address/data multiplexed bus ⎯ External bus frequency: 33 MHz or 66 MHz Rev.1.00 Jan. 10, 2008 Page 1 of 1658 REJ09B0261-0100 1. Overview Item CPU Features • • • Renesas Technology original architecture 32-bit internal data bus General-register files: ⎯ Sixteen 32-bit general registers (eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction set (upward compatibility for the SH-1, SH-2, SH-3 and SH-4 processors) ⎯ Instruction length: 16-bit fixed length for improved code efficiency ⎯ Load/store architecture ⎯ Delayed branch instructions ⎯ Conditional instruction execution ⎯ Instruction-set design based on the C language • • • • • • • Super-scalar architecture covering both the FPU and CPU provides for the simultaneous execution of any two instructions Instruction-execution time: Two instructions per cycle (max.) Virtual address space: 4 Gbytes Address-space identifiers (ASID): 8 bits, for 256 virtual address spaces Internal multiplier Eight-stage pipeline PVR.VER = H'30: SH-4A extended version Rev.1.00 Jan. 10, 2008 Page 2 of 1658 REJ09B0261-0100 1. Overview Item FPU Features • • • • • • • • • • • On-chip floating-point coprocessor Supports single (32-bit) and double (64-bit) precisions Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interruptgeneration for IEEE754 compliance Floating-point registers: 32 bits × 16 words × 2 banks (single-precision × 16 words or double-precision × 8 words) × 2 banks 32-bit CPU-FPU floating-point communications register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constants 0 and 1) instructions Instruction-execution times ⎯ Latency (FADD/FSUB): 3 cycles (single-precision), 5 cycles (doubleprecision) ⎯ Latency (FMAC/ FMUL): 5 cycles (single-precision), 7 cycles (doubleprecision) ⎯ Pitch (FADD/FSUB): 1 cycle (single-precision/double-precision) ⎯ Pitch (FMAC/FMUL): 1 cycle (single-precision), 3 cycles (doubleprecision) Note: FMAC only supports single-precision operands. • 3-D graphics instructions (single-precision only) ⎯ 4-dimensional vector-conversion and matrix operations (FTRV): 4 cycles (pitch), 8 cycles (latency) ⎯ 4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 5 cycles (latency) • Ten-stage pipeline Rev.1.00 Jan. 10, 2008 Page 3 of 1658 REJ09B0261-0100 1. Overview Item Memory management unit (MMU) Features • • • • • • • • 4-Gbyte address space, 256 address space identifiers (8-bit ASID) Supports single virtual memory mode and multiple virtual memory mode Multiple page sizes: 1, 4, 8, 64, or 256 Kbytes, or 1, 4, or 64 Mbytes 4-entry fully associative TLB for instructions 64-entry fully associative TLB for instructions and operands Selection of software-driven or random-counter replacement algorithms The TLB is address-mapped, making its contents directly accessible. 29-bit physical address mode/32-bit extended mode Instruction cache (IC) ⎯ 32-Kbyte 4-way set associative ⎯ 256 entries/way, 32-byte block length • Operand cache (OC) ⎯ 32-Kbyte 4-way set associative ⎯ 256 entries/way, 32-byte block length • • • Selectable write method (copy-back or write-through) Store queue (32 bytes × 2 entries) One-stage copy-back buffer and one-stage write-through buffer ILRAM ⎯ 8-Kbyte high-speed memory ⎯ Three independent read/write ports ⎯ 8-/16-/32-/64-bit access from the CPU or FPU ⎯ 8-/16-/32-/64-bit access and 16-/32-byte access in response to external requests ⎯ Support for protection of memory from CPU or FPU access • OLRAM ⎯ 16-Kbyte high-speed memory ⎯ Three independent read/write ports ⎯ 8-/16-/32-/64-bit access by the CPU or the FPU ⎯ 8-/16-/32-/64-bit access and 16-/32-byte access in response to external requests ⎯ Support for protection of memory from CPU or FPU access Cache memory • LRAM • Rev.1.00 Jan. 10, 2008 Page 4 of 1658 REJ09B0261-0100 1. Overview Item URAM Features • • • • 128-Kbyte large-capacity memory Three independent read/write ports 8-/16-/32-bit access by the CPU or the FPU 8-/16-/32-bit access by the DMAC Nine independent external interrupts: NMI and IRQ7 to IRQ0 ⎯ NMI: Falling/rising edge selectable ⎯ IRQ: Falling/rising edge or high level/low level selectable • • 15-level-encoded external interrupts: IRL3 to IRL0, or IRL7 to IRL4 On-chip module interrupts: A priority level can be set for each module. The following modules can issue on-chip module interrupts: TMU, DU, GDTA, SCIF, WDT, H-UDI, DMAC, HAC, PCIC, SIOF, HSPI, MMCIF, SSI, FLCTL, and GPIO. Interrupt controller (INTC) • Rev.1.00 Jan. 10, 2008 Page 5 of 1658 REJ09B0261-0100 1. Overview Item Local bus state controller (LBSC) Features • A dedicated Local-bus interface ⎯ Controls the external memory space divided into seven 64-Mbyte (max.) areas ⎯ The interface type, bus width, and wait-cycle insertion can be set for each area. • SRAM interface ⎯ Wait-cycle insertion can be set by register values. ⎯ Wait-cycle insertion by the RDY pin ⎯ Connectable as area 0, 1, 2, 3, 4, 5, or 6 ⎯ Selectable bus width: 64-/32-/16-/8-bit • Burst ROM interface ⎯ Wait-cycle insertion can be set by register values. ⎯ Number of units in burst transfers can be set by register values. ⎯ Connectable as area 0, 1, 2, 3, 4, 5, or 6 ⎯ Selectable bus width: 64-/32-/16-/8-bit • MPX interface ⎯ Address/data multiplexing ⎯ Connectable as area 1 or 4 ⎯ Selectable bus widths: 64-/32-bit • SRAM interface with byte-control ⎯ Connectable as area 1 or 4 ⎯ Selectable bus width: 64-/32-/16-bit • PCMCIA interface (only for little-endian mode) ⎯ Wait-cycle insertion can be set by register values. ⎯ Bus-sizing function for adaptation to the I/O bus width ⎯ Connectable as area 5 or 6 ⎯ Selectable bus width: 16-/8-bit • Supports transfer to and from E-IDE/ATAPI devices (ATA3) ⎯ Supports PIO mode 4 type and multi-word DMA mode 2 type ⎯ Connectable as area 5 or 6 • Big or little endian is selectable Rev.1.00 Jan. 10, 2008 Page 6 of 1658 REJ09B0261-0100 1. Overview Item Features A dedicated DDR2-SDRAM bus interface ⎯ Multi-bank support: Supports multi-bank (four banks) operation ⎯ Number of banks: Supports four or eight banks (however, no more than four banks can be opened concurrently) ⎯ Selectable bus width: 32-/16-bit ⎯ Supports preceding precharging and activation ⎯ Burst length: Four (fixed) ⎯ Burst type: Sequential (fixed) ⎯ CAS latency: 2, 3, 4, 5, 6 cycles • Auto-refresh mode ⎯ An average interval is selectable by a register setting. Preceding refresh operations are performed when there are no pending requests. • • Self-refresh mode Connectable memory capacity: Up to 1 Gbyte ⎯ With a 32-bit bus width 16 M x 16 bits (256 Mbits) x 2, 32 M x 16 bits (512 Mbits) x 2, 64 M x 16 bits (1 Gbit) x 2, 128 M x 16 bits (2 Gbits) x 2, 32 M x 8 bits (256 Mbits) x 4, 64 M x 8 bits (512 Mbits) x 4, 128 M x 8 bits (1 Gbit) x 4, 256 M x 8 bits (2 Gbits) x 4 ⎯ With a 16-bit bus width 16 M x 16 bits (256 Mbits) x 1, 32 M x 16 bits (512 Mbits) x 1, 64 M x 16 bits (1 Gbit) x 1, 128 M x 16 bits (2 Gbits) x 1, 32 M x 8 bits (256 Mbits) x 2, 64 M x 8 bits (512 Mbits) x 2, 128 M x 8 bits (1 Gbit) x 2, 256 M x 8 bits (2 Gbits) x 2 • Big or little endian is selectable DDR2-SDRAM bus • controller (DBSC) Rev.1.00 Jan. 10, 2008 Page 7 of 1658 REJ09B0261-0100 1. Overview Item PCI bus controller (PCIC) Features • • • • • • • • • • • PCI bus controller (supports a subset of revision 2.2) ⎯ 32-bit bus (33 MHz or 66 MHz) Operation as PCI master/target Operation in PCI host/normal mode ⎯ Built-in bus arbiter (host mode) Operates with up to four external bus-master devices Mode for operation with an external bus arbiter Supports burst transfers Supports parity checking and error reports Supports four individual external interrupt signals (INTA to INTD) in host mode Supports a single external interrupt signal (INTA) in normal mode Up to 512 Mbytes of PCI memory space (32 bit address mode) Up to 64 Mbytes of PCI memory space (29 bit address mode) Number of channels: 12 12-channel physical address DMA controller Four channels support external requests (channels 0 to 3) Address space: 4 Gbytes (Physical address) Units of data transfer: 8, 16, or 32 bits; 16 or 32 bytes Address modes: ⎯ Dual address mode • • • • Transfer requests: External request, on-chip peripheral module request, or auto-request Choice of DACK or DRAK (four external pins) Bus modes: Cycle-stealing or burst mode Priority: Select either fixed mode or round-robin mode CPU frequency: Up to 600 MHz Local bus frequency: Up to 100 MHz DDR2-SDRAM interface frequency: Up to 300 MHz On-chip peripheral bus frequency: Up to 50 MHz Power-down modes ⎯ Sleep mode ⎯ Module-standby mode ⎯ DDR back-up power function (power is supplied only to the DDR) Direct memory access controller (DMAC) • • • • • • Clock pulse generator (CPG) • • • • • Rev.1.00 Jan. 10, 2008 Page 8 of 1658 REJ09B0261-0100 1. Overview Item Watchdog timer (WDT) Features • • • Number of channels: One Single-channel watchdog timer (operation in watchdog-timer or interval-timer mode is selectable) Selectable reset function: Power-on or manual reset Number of channels: Six 6-channel auto-reloading 32-bit down-counter Input-capture function (only on channel 2) Choice of a maximum of six input clock signals to drive counting (external and peripheral clock signals) YUV data translation ⎯ Translation mode: YUYV mode (YUV 4:2:0 → YUV 4:2:2), ARGB mode (YUV 4:2:0 → ARGB8888) Motion Compensation processing ⎯ Generation of estimated images using motion vectors in macroblock units (16 x 16 pixels) ⎯ Modes: Forward, reverse, bidirectional, and intra-macroblock processing • • • Dedicated DMAC for image-data transfer Embedded RAM for color-palette data Embedded RAM for IDCT data Timer unit (TMU) • • • • Graphics data • translation accelerator (GDTA) • Rev.1.00 Jan. 10, 2008 Page 9 of 1658 REJ09B0261-0100 1. Overview Item Display unit (DU) Features • Display plane ⎯ 6 planes (a maximum number at 480 dots x 234 dots) ⎯ 4 planes (a maximum number at 854 dots x 480 dots) ⎯ 3 planes (a maximum number at 800 dots x 600 dots) • • CRT scanning method: Non-interlaced, interlaced, interlaced sync & video Synchronization modes: Master mode (internal synchronization mode), TV synchronization mode (external synchronization mode), synchronization-mode switching mode Incorporates color palettes ⎯ Displays 256 colors from among 260 thousand possible colors ⎯ Four palettes (one can be set for each layer) • Blending ratio setting ⎯ Number of color-palette planes with blending ratios: Four ⎯ α plane: (used in common with the display plane) • • Digital RGB output: 6-bit precision for each of R, G, and B Dot clock: Can be switched between external input and internal clock (division ratio: from 1 to 32) Number of channels: Six (max.) On-chip 64-byte (8 bits x 64) FIFO for each of the six channels Two full-duplex channels Choice of asynchronous mode or synchronous mode Any bit rate that can be generated by the on-chip baud-rate generator is selectable On-chip modem-control function (RTS and CTS) for channel 0 Internal clock signal from the baud-rate generator or external clock signal from the SCK pin is selectable • Serial • communications • interface with FIFO • (SCIF) • • • • Rev.1.00 Jan. 10, 2008 Page 10 of 1658 REJ09B0261-0100 1. Overview Item Features Number of channels: One (max.) Supports full-duplex operation Separate 64-byte (32 bits x 16) FIFOs for transmission and reception Supports the input and output of 8-/16-bit monaural and 16-bit stereophonic audio data Method of synchronization selectable as frame synchronization pulses or left/right channel switching Allows connection of linear, audio, A-law, or μ-Law CODEC chip Select an on-chip peripheral clock or input on an external pin as base for the sampling-rate clock Maximum sampling rate: 48 kHz On-chip prescaler that uses the on-chip peripheral clock Number of channels: One (max.) Supports full-duplex operation Master/slave mode Selectable bit rate generated by the on-chip baud-rate generator Number of channels: One (max.) Supports a subset of version 3.1 of the multimedia card system specification Supports MMC-mode operation Interfaces with MMCCLK output (transfer clock output), MMCCMD I/O (command output/response input), and MMCDAT I/O (data I/O) pins Number of channels: Two (max.) Digital interface for audio codecs Supports transfer via slots 1 to 4 Choice of 16- or 20-bit DMA transfer rates for transmission/reception Supports various sampling rates by adjusting the allocation of data to slots Synchronized serial • I/O with FIFO • (SIOF) • • • • • • • Serial protocol interface (HSPI) • • • • Multimedia card interface (MMCIF) • • • • Audio codec interface (HAC) • • • • • Rev.1.00 Jan. 10, 2008 Page 11 of 1658 REJ09B0261-0100 1. Overview Item Serial sound interface (SSI) Features • • • • • • • Number of channels: Two (max.) Supports transfer of compressed and non-compressed data Selectable frame size Number of channels: One (max.) Exclusively for NAND-type flash memory Operating modes: Command-access mode, sector-access mode Data transfer FIFOs ⎯ On-chip 224-byte FIFO for transfer of data to and from flash memory ⎯ On-chip 32-byte FIFO for transfer of control codes ⎯ Flag bit to indicate overruns and underruns during access from the CPU or DMA NAND flash memory controller (FLCTL) General purpose I/O (GPIO) User break controller (UBC) • • • • • • General purpose I/O port pins: 111 Some GPIO pins are configurable as interrupts Supports user-break interrupts as a facility for debugging Two break channels Addresses, data values, types of access, and widths of data are all specifiable as break conditions Supports a sequential break function JTAG interface (TCK, TMS, TRST, TDI, TDO) Supports the E10A emulator Realtime branch tracing 436-pin flip-chip BGA (body: 19 x 19 mm, ball pitch: 0.8-mm) Internal (VDD), PLL1 (VDD-PLL1, VDDA-PLL1), PLL2 (VDD-PLL2): 1.1 V DDR2 I/O (VDD-DDR): 1.8 V I/O (VDDQ), PLL1 (VDDQ-PLL1), PLL2 (VDDQ-PLL2): 3.3 V User debug interface (H-UDI) • • • • • • • Package Power supply voltage Rev.1.00 Jan. 10, 2008 Page 12 of 1658 REJ09B0261-0100 1. Overview 1.2 Block Diagram A block diagram of the SH7785 is given as figure 1.1. Super Hyway SH-4A Superscalar CPU FPU MMU 32 KB I-cache 32 KB O-cache 8 KB ILRAM 16 KB OLRAM 32 bit/16 bit 300 MHz URAM 128 KB Periperal bus SCIF0/HSPI/FLCTL SCIF2/MMCIF HAC/SSI/SIOF HAC/SSI TMU, WDT DDR bus DDRII-SDRAM Controller (DBSC) DDR2-SDRAM DDR2-400/600 1 GB max Peripheral Bus Controller ROM NOR Flash SRAM 64*/32/16 /8 bit 100 MHz INTC Display Unit Local Bus Controller SRAM, ROM, PCMCIA MPX GDTA CPG DMA Controller Local bus PC Card/ATA3 PCI Controller Debug 32 bit 33/66 MHz PCI bus Note: * The PCI bus and the display unit are not available when the local bus width is 64 bits. The PCI controller and the display unit cannot be used when the local bus width is 64 bits. Figure 1.1 SH7785 Block Diagram Rev.1.00 Jan. 10, 2008 Page 13 of 1658 REJ09B0261-0100 1. Overview 1.3 Table 1.2 Pin Arrangement Table Pin Function I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Function DDR data 0 DDR data 1 DDR data 2 DDR data 3 DDR data 4 DDR data 5 DDR data 6 DDR data 7 DDR data 8 DDR data 9 DDR data 10 DDR data 11 DDR data 12 DDR data 13 DDR data 14 DDR data 15 DDR data 16 No. Pin Name 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MDQ27 MDQ28 MDQ29 MDQ30 MDQ31 MDM0 MDM1 MDM2 MDM3 MDQS0 MDQS1 MDQS2 MDQS3 MDQS0 MDQS1 MDQS2 MDQS3 I/O IO IO IO IO IO O O O O IO IO IO IO IO IO IO IO Function DDR data 27 DDR data 28 DDR data 29 DDR data 30 DDR data 31 DDR data mask 0 DDR data mask 1 DDR data mask 2 DDR data mask 3 DDR data strobe 0 DDR data strobe 1 DDR data strobe 2 DDR data strobe 3 DDR data strobe 0 (antiphase) DDR data strobe 1 (antiphase) DDR data strobe 2 (antiphase) DDR data strobe 3 (antiphase) No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 18 19 20 21 22 23 24 25 26 27 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 IO IO IO IO IO IO IO IO IO IO DDR data 17 DDR data 18 DDR data 19 DDR data 20 DDR data 21 DDR data 22 DDR data 23 DDR data 24 DDR data 25 DDR data 26 45 46 47 48 49 50 51 52 53 54 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 O O O O O O O O O O DDR address 0 DDR address 1 DDR address 2 DDR address 3 DDR address 4 DDR address 5 DDR address 6 DDR address 7 DDR address 8 DDR address 9 Rev.1.00 Jan. 10, 2008 Page 14 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 MA10 MA11 MA12 MA13 MA14 MBA0 MBA1 MBA2 MCK0 MCK0 MCK1 MCK1 MCS MRAS MCAS MWE MODT MCKE MVREF MBKPRST D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 I/O O O O O O O O O O O O O O O O O O O I I IO IO IO IO IO IO IO IO IO IO IO IO Function DDR address 10 DDR address 11 DDR address 12 DDR address 13 DDR address 14 DDR bank address 0 DDR bank address 1 DDR bank address 2 DDR clock 0 DDR clock 0 (antiphase) DDR clock 1 DDR clock 1 (antiphase) DDR chip select DDR row address select DDR column address select DDR write enable DDR on chip terminator DDR clock enable DDR reference voltage DDR backup reset Local bus data 0 Local bus data 1 Local bus data 2 Local bus data 3 Local bus data 4 Local bus data 5 Local bus data 6 Local bus data 7 Local bus data 8 Local bus data 9 Local bus data 10 Local bus data 11 No. Pin Name 87 88 89 90 91 92 93 94 95 96 97 98 99 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 I/O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O O O O O Function Local bus data 12 Local bus data 13 Local bus data 14 Local bus data 15 Local bus data 16 Local bus data 17 Local bus data 18 Local bus data 19 Local bus data 20 Local bus data 21 Local bus data 22 Local bus data 23 Local bus data 24 Local bus data 25 Local bus data 26 Local bus data 27 Local bus data 28 Local bus data 29 Local bus data 30 Local bus data 31 Local bus address 0 Local bus address 1 Local bus address 2 Local bus address 3 Local bus address 4 Local bus address 5 Local bus address 6 Local bus address 7 Local bus address 8 Local bus address 9 Local bus address 10 Local bus address 11 100 D25 101 D26 102 D27 103 D28 104 D29 105 D30 106 D31 107 A0 108 A1 109 A2 110 A3 111 A4 112 A5 113 A6 114 A7 115 A8 116 A9 117 A10 118 A11 Rev.1.00 Jan. 10, 2008 Page 15 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 119 A12 I/O O Function Local bus address 12 No. Pin Name 140 RD/FRAME 141 R/W 142 BS 143 WE0/REG 144 WE1 145 WE2/IORD 146 WE3/IOWR 147 RDY 148 CLKOUT 149 CLKOUTENB 150 D32/AD0/DR0 I/O O/O Function Read strobe/MPX IF FRAME 120 A13 121 A14 122 A15 O O O Local bus address 13 Local bus address 14 Local bus address 15 O O O/O Read/Write Bus start Write enable 0/PCMCIA IF REG 123 A16 124 A17 O O Local bus address 16 Local bus address 17 O O/O Write enable 1 Write enable 2/PCMCIA IF IORD 125 A18 O Local bus address 18 O/O Write enable 3/PCMCIA IF IOWR 126 A19 127 A20 128 A21 129 A22 O O O O Local bus address 19 Local bus address 20 Local bus address 21 Local bus address 22 I O O Bus ready Clock out Clock out enable IO/IO/O Local bus data 32/PCI address data 0/Digital red 0 130 A23 O Local bus address 23 151 D33/AD1/DR1 IO/IO/O Local bus data 33/PCI address data 1/Digital red 1 131 A24 O Local bus address 24 152 D34/AD2/DR2 IO/IO/O Local bus data 34/PCI address data 2/Digital red 2 132 A25 133 CS0 134 CS1 135 CS2 O Local bus address 25 153 D35/AD3/DR3 IO/IO/O Local bus data 35/PCI address data 3/Digital red 3 O Chip select 0 154 D36/AD4/DR4 IO/IO/O Local bus data 36/PCI address data 4/Digital red 4 O Chip select 1 155 D37/AD5/DR5 IO/IO/O Local bus data 37/PCI address data 5/Digital red 5 O Chip select 2 156 D38/AD6/DG0 IO/IO/O Local bus data 38/PCI address data 6/Digital green 0 136 CS3 137 CS4 138 CS5 139 CS6 O Chip select 3 151 D33/AD1/DR1 IO/IO/O Local bus data 33/PCI address data 1/Digital red 1 O Chip select 4 152 D34/AD2/DR2 IO/IO/O Local bus data 34/PCI address data 2/Digital red 2 O Chip select 5 153 D35/AD3/DR3 IO/IO/O Local bus data 35/PCI address data 3/Digital red 3 O Chip select 6 154 D36/AD4/DR4 IO/IO/O Local bus data 36/PCI address data 4/Digital red 4 Rev.1.00 Jan. 10, 2008 Page 16 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 155 D37/AD5/DR5 I/O Function No. Pin Name 168 D50/AD18 I/O IO/IO Function Local bus data 50/PCI address data 18 IO/IO/O Local bus data 37/PCI address data 5/Digital red 5 156 D38/AD6/DG0 IO/IO/O Local bus data 38/PCI address data 6/Digital green 0 169 D51/AD19 IO/IO Local bus data 51/PCI address data 19 157 D39/AD7/DG1 IO/IO/O Local bus data 39/PCI address data 7/Digital green 1 170 D52/AD20 IO/IO Local bus data 52/PCI address data 20 158 D40/AD8/DG2 IO/IO/O Local bus data 40/PCI address data 8/Digital green 2 171 D53/AD21 IO/IO Local bus data 53/PCI address data 21 159 D41/AD9/DG3 IO/IO/O Local bus data 41/PCI address data 9/Digital green 3 172 D54/AD22 IO/IO Local bus data 54/PCI address data 22 160 D42/AD10/DG4 IO/IO/O Local bus data 42/PCI address data 10/Digital green 4 173 D55/AD23 IO/IO Local bus data 55/PCI address data 23 161 D43/AD11/DG5 IO/IO/O Local bus data 43/PCI address data 11/Digital green 5 174 D56/AD24 IO/IO Local bus data 56/PCI address data 24 162 D44/AD12/DB0 IO/IO/O Local bus data 44/PCI address data 12/Digital blue 0 175 D57/AD25 IO/IO Local bus data 57/PCI address data 25 163 D45/AD13/DB1 IO/IO/O Local bus data 45/PCI address data 13/Digital blue 1 176 D58/AD26 IO/IO Local bus data 58/PCI address data 26 164 D46/AD14/DB2 IO/IO/O Local bus data 46/PCI address data 14/Digital blue 2 177 D59/AD27 IO/IO Local bus data 59/PCI address data 27 165 D47/AD15/DB3 IO/IO/O Local bus data 47/PCI address data 15/Digital blue 3 178 D60/AD28 IO/IO Local bus data 60/PCI address data 28 166 D48/AD16/DB4 IO/IO/O Local bus data 48/PCI address data 16/Digital blue 4 179 D61/AD29 IO/IO Local bus data 61/PCI address data 29 167 D49/AD17/DB5 IO/IO/O Local bus data 49/PCI address data 17/Digital blue 5 180 D62/AD30 IO/IO Local bus data 62/PCI address data 30 Rev.1.00 Jan. 10, 2008 Page 17 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 181 D63/AD31 182 WE4/CBE0 183 WE5/CBE1 184 WE6/CBE2 185 WE7/CBE3 186 PCIFRAME/ VSYNC 187 IRDY/HSYNC 188 TRDY/DISP I/O IO/IO Function Local bus data 63/PCI address data 31 No. Pin Name 199 REQ2 200 REQ3 201 GNT1 202 GNT2 I/O I Function Bus request 2 (PCI host) O/IO Write enable 4/PCI command/byte enable 0 I Bus request 3 (PCI host) O/IO Write enable 5/PCI command/byte enable 1 O PCI bus grant 1 O/IO Write enable 6/PCI command/byte enable 2 O PCI bus grant 2 O/IO Write enable 7/PCI command/byte enable 3 203 GNT3/MMCCLK O/O 204 PCIRESET PCI bus grant 3/MMCIF card clock output IO/IO PCI cycle frame/VSYNC output O PCI reset (RST) IO/IO PCI initiator ready/HSYNC output 205 PCICLK/ DCLKIN 206 INTA I/I PCI input clock/DU dot clock input IO/O PCI target ready/display period IO PCI interrupt A 189 IDSEL 190 LOCK/ODDF 191 DEVSEL/ DCLKOUT 192 PAR 193 STOP/CDE 194 SERR 195 PERR I PCI configuration device select 207 EXTAL I External input clock/Crystal resonator IO/IO IO/O PCI lock/even-odd field PCI device select/DU dot clock output 208 XTAL 209 PRESET O I Crystal resonator Power on reset IO IO/O PCI parity PCI transaction stop/color detection 210 NMI 211 IRL0 212 IRL1 213 IRL2 214 IRL3 I I Nonmaskable interrupt IRL interrupt request 0 IO IO PCI system error PCI parity error Bus request 0 (PCI host)/ bus request output I I I IRL interrupt request 1 IRL interrupt request 2 IRL interrupt request 3 196 REQ0/REQOUT I/O 197 GNT0/GNTIN O/I PCI bus grant 0 215 STATUS0/ DRAK0 O/O Status 0/DMA channel 0 transfer request acknowledge 0 198 REQ1 I PCI request 1 (PCI host) 216 STATUS1/ DRAK1 O/O Status 1/DMA channel 1 transfer request acknowledge 1 Rev.1.00 Jan. 10, 2008 Page 18 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 217 BREQ/BSACK I/O I Function Bus request (Master mode)/ Bus acknowledgement (Slave mode) No. Pin Name 233 ASEBRK/ BRKACK I/O I Function H-UDI emulator 218 BACK/BSREQ O Bus acknowledgement (Master mode)/Bus request (Slave mode) 234 AUDCK O H-UDI emulator clock 219 DREQ0 220 DREQ1 221 DREQ2/INTB 222 DREQ3/INTC I I I/I DMA channel 0 request DMA channel 1 request DMA channel 2 request/PCI interrupt B 235 AUDSYNC 236 AUDATA0 237 AUDATA1 O O O H-UDI emulator H-UDI emulator data 0 H-UDI emulator data 1 I/I DMA channel 3 request/PCI interrupt C 238 AUDATA2 O H-UDI emulator data 2 223 DACK0 O DMA channel 0 bus acknowledgment 239 AUDATA3 O H-UDI emulator data 3 224 DACK1 O DMA channel 1 bus acknowledgment 240 SCIF0_TXD/ HSPI_TX/FWE O/O/O SCIF0 transmit data/HSPI transmit data/NAND flash write enable 225 DACK2/ SCIF2_TXD/ MMCCMD/ SIOF_TXD O/O/O/I DMA channel 2 bus O/O acknowledgment/SCIF2 transmit data/MMCIF command response/SIOF transmit data 241 SCIF0_RXD/ HSPI_RX/FRB I/I/I SCIF0 receive data/HSPI receive data/NAND flash ready or busy 226 DACK3/ SCIF2_SCK/ MMCDAT/ SIOF_SCK 227 DRAK2/CE2A O/O/IO/ DMA channel 3 bus IO/IO acknowledgment/SCIF2 serial clock/MMCIF data/SIOF serial clock O/O DMA channel 2 transfer request acknowledge 2/PCMCIA CE2A 242 SCIF0_SCK/ HSPI_CLK/FRE IO/IO/O SCIF0 serial clock/HSPI serial clock/NAND flash read enable 243 SCIF0_RTS/ HSPI_CS/FSE 244 SCIF0_CTS/ INTD/FCE IO/IO/O SCIF0 modem control/HSPI chip selection/NAND flash spare area enable IO/I/O SCIF0 modem control/PCI interrupt D/NAND flash chip enable 228 TCK I H-UDI clock 229 TMS 230 TDI 231 TDO 232 TRST I I O I H-UDI emulator H-UDI data H-UDI data H-UDI emulator 245 SCIF1_TXD 246 SCIF1_RXD 247 SCIF1_SCK 248 SCIF2_RXD/ SIOF_RXD O I IO I/I SCIF1 transmit data SCIF1 receive data SCIF1 serial clock SCIF2 receive data/SIOF receive data Rev.1.00 Jan. 10, 2008 Page 19 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 249 SIOF_SCK/ HAC0_BITCLK/ SSI0_CLK 250 SIOF_MCLK/ HAC_RES I/O IO/I/IO Function SIOF serial clock/HAC0 bit clock/SSI0 serial bit clock No. Pin Name 256 SCIF5_RXD/ HAC1_SDIN/ SSI1_SCK I/O I/I/IO Function SCIF5 receive data/HAC1 serial data/SSI1 serial data I/O SIOF master clock/HAC reset 257 SCIF5_SCK/ HAC1_SDOUT/ SSI1_SDATA IO/O/IO SCIF5 synchrounous/HAC1 serial data/SSI1 serial data 251 SIOF_SYNC/ HAC0_SYNC/ SSI0_WS IO/O/IO SIOF flame synchronous/HAC0 flame synchronous/SSI0 word select 258 MODE0/ IRL4/FD4 I/I/IO Mode control 0/IRL interrupt request 4/NAND flash data 4 252 SIOF_RXD/ HAC0_SDIN/ SSI0_SCK 253 SIOF_TXD/ HAC0_SDOUT/ SSI0_SDATA I/I/IO SIOF receive data/HAC0 serial data incoming to Rx frame/SSI0 serial bit clock 259 MODE1/ IRL5/FD5 I/I/IO Mode control 1/IRL interrupt request 5/NAND flash data 5 O/O/IO SIOF transmit data/HAC0 serial data/SSI0 serial data 260 MODE2/ IRL6/FD6 I/I/IO Mode control 2/IRL interrupt request 6/NAND flash data 6 254 HAC1_BITCLK/ I/IO SSI1_CLK 255 SCIF5_TXD/ HAC1_SYNC/ SSI1_WS 256 SCIF5_RXD/ HAC1_SDIN/ SSI1_SCK 251 SIOF_SYNC/ HAC0_SYNC/ SSI0_WS I/I/IO O/O/IO HAC1 bit clock/SSI1 serial bit clock SCIF5 transmit data/HAC1 synchronous/SSI1 serial bit clock SCIF5 receive data/HAC1 serial data/SSI1 serial data 261 MODE3/ IRL7/FD7 262 MODE4/ SCIF3_TXD/ FCLE 263 MODE5/ SIOF_MCLK I/I/IO Mode control 3/IRL interrupt request 7/NAND flash data 7 I/O/O Mode control 4/SCIF3 transmit data/NAND flash command latch enable I/I Mode control 5/SIOF master clock IO/O/IO SIOF flame synchronous/HAC0 flame synchronous/SSI0 word select 264 MODE6/ SIOF_SYNC I/IO Mode control 6/SIOF frame synchronous 252 SIOF_RXD/ HAC0_SDIN/ SSI0_SCK 253 SIOF_TXD/ HAC0_SDOUT/ SSI0_SDATA I/I/IO SIOF receive data/HAC0 serial data incoming to Rx frame/SSI0 serial bit clock 265 MODE7/ SCIF3_RXD/ FALE 266 MODE8/ SCIF3_SCK/ FD0 I/I/O Mode control 7/SCIF3 receive data/NAND flash ALE O/O/IO SIOF transmit data/HAC0 serial data/SSI0 serial data I/IO/IO Mode control 8/SCIF3 serial clock/NAND flash data 0 254 HAC1_BITCLK/ I/IO SSI1_CLK HAC1 bit clock/SSI1 serial bit clock 267 MODE9/ SCIF4_TXD/ FD1 I/O/IO Mode control 9/SCIF4 transmit data/NAND flash data 1 255 SCIF5_TXD/ HAC1_SYNC/ SSI1_WS O/O/IO SCIF5 transmit data/HAC1 synchronous/SSI1 serial bit clock 268 MODE10/ SCIF4_RXD/ FD2 I/I/IO Mode control 10/SCIF4 receive data/NAND flash data 2 Rev.1.00 Jan. 10, 2008 Page 20 of 1658 REJ09B0261-0100 1. Overview No. Pin Name 269 MODE11/ SCIF4_SCK/ FD3 270 MODE12/ DRAK3/CE2B I/O I/IO/IO Function Mode control 11/SCIF4 serial clock/NAND flash data 3 No. Pin Name 274 MRESETOUT/ IRQOUT I/O O/O Function Manual reset output/Interrupt request output I/O/O Mode control 12/DMA channel 3 transfer request acknowledge 3/PCMCIA CE2B 275 THDAG ⎯ Thermal diode* 271 MODE13/ TCLK/IOIS16 272 MPMD 273 MODE14 I/IO/I TMU clock/PCMCIA IOIS16 276 THDAS ⎯ Thermal diode* I I H-UDI emulator mode Mode control 14 277 THDCD 278 THDCTL I I Thermal diode* Thermal diode* Note: * This pin must be pulled-down to GND. Rev.1.00 Jan. 10, 2008 Page 21 of 1658 REJ09B0261-0100 1. Overview 1.4 Pin Arrangement Package: 436-pin FC-BGA, 19 mm x 19 mm, ball pitch: 0.8 mm 1 A VSS 2 MCK0 VDDDDR MCK1 3 VSS 4 MCKE VDDDDR 5 MBA0 6 MA9 7 8 9 10 11 12 AUDSYNC 13 AUDC K VSS 14 TCK 15 16 17 18 19 20 MODE14 21 VSSQPLL1 22 VSS A MDQ1 MDQ7 MDQ13 MDQ12 MDM1 VDDDDR STATU VSSQ- THDCTL S1/DRA XTAL EXTAL TD K1 VDDQVDDQ TD VSS STATUS0/ DRAK0 B MCK1 MCK0 MA1 VSS MDQ2 MDQ6 VSS MDQ14 AUDAT A2 TDI ASEBRK /BRKACK VDDQ VDDQ VSSAVDDQ B -PLL1 PLL1 VDDAPLL1 VDDPLL1 VSSPLL1 C C VSS MBKPRST MODT MBA2 MA11 MDQ4 MDQ0 MDQS MDQS AUDAT AUDAT MDQ10 A0 A3 0 1 MDQS0 TRST DACK0 DREQ0 MPMD NMI VDDD MVREF DDR MCS MBA1 VSS MA2 VDDDDR MA5 MA13 VSS AUDAT VDDVDDQ THDAG MDQS1 A1 DDR VDDDDR TDO THDAS VSS DREQ1 VDDQ DACK1 DREQ2 /INTB VSS SCIF2_RXD /SIOF_RXD VSS VDDQ VSSQVDDQ D -PLL2 PLL2 DREQ3 /INTC E MA10 MCAS MRAS VDDDDR MA8 MWE MA3 MDQ3 MDM0 MDQ11 MDQ15 VDDDDR VDD TMS DACK3/ DACK2/ SCIF2_TXD/ SCIF2_SCK/ MMCCMD/ MMCDAT/ SIOF_TXD SIOF_SCK MRESETO UT/ IRQOUT VDDPLL2 VSS VSSPLL2 CLKO UT E F MA14 VSS MA6 MA0 VSS MA7 MDQ5 VSS MDQ8 MDQ9 VSS DRAK2 THDCD VDDQ /CE2A VDD CLKOU VDDQ TENB IRL2 MODE12/ DRAK3/ CE2B F G MDQ22 MDQ17 MDQ21 VDDDDR MDQ18 MA4 MA12 VSS VSS VDD VSS VDD VSS VDD VSS IRL3 IRL1 INTA D32/AD G 0/DR0 H MDQ16 VSS MDQ19 VDDDDR VDD VSS VDDQ D35/AD3/ DR3 VSS J MDQ28 MDQ23 MDQS MDQS2 MDM2 MDQ20 2 MDQ25 VDDMDQ27 DDR VSS VSS PKG TOP VIEW VSS VSS VSS VSS VSS VSS VSS VSS D34/AD VDDQ D33/AD H 2/DR2 1/DR1 VDD IRL0 WE4/ D39/AD D38/AD D37/AD D36/AD J CBE0 7/DG1 6/DG0 5/DR5 4/DR4 D41/AD D42/AD VDDQ 9/DG3 10/DG4 VSS D40/AD K 8/DG2 K MDQ26 VSS VDD VSS VSS L MDM3 MDQ31 MDQS MDQS3 MDQ29 MDQ30 3 MODE0 /IRL4 VDDQ /FD4 VDDMDQ24 DDR VSS VSS VDD WE5/ D47/AD D46/AD D45/AD D44/AD D43/AD L CBE1 15/DB3 14/DB2 13/DB1 12/DB0 11/DG5 DEVSEL/ DCLKOUT M VSS VSS VDD VSS VSS VSS VSS VSS STOP LOCK PERR /CDE /ODDF SERR PAR TRDY /DISP M N PRESET VSS MODE1 MODE2 MODE3 /IRL5 /IRL6 /IRL7 /FD6 /FD5 /FD7 VSS VSS VSS VSS VSS VDD PCIFRA IRDY/ VSS ME/VS VDDQ HSYNC YNC D52/A D20 D51/A D19 VSS N P SCIF0_SCK SCIF0_TXD SCIF0_RXD SCIF0_CTS SCIF0_RTS MODE7/ SCIF3_ /HSPI_CLK /HSPI_TX/ /HSPI_RX/ /HSPI_CS /INTD/ FRB FWE RXD/FALE /FRE /FSE FCE VDD VSS D50/A D49/AD D48/AD WE6/ D18 17/DB5 16/DB4 CBE2 VSS D54/A D53/A VDDQ D22 D21 D56/A D24 D60/A D28 D62/A D30 WE7/ CBE3 VSS P R SCIF1_ VDDQ SCK SCIF1_ SCIF1_ RXD TXD SIOF_TXD/ HAC0_SDO UT/SSI0_ SDATA MODE5/ SIOF_MCLK VSS MODE4/ MODE8/ SCIF3_ SCIF3_ SCK/FD0 TXD/FCLE VSS VDD VDDQ D55/A D23 REQ0/ REQOUT R T SIOF_RXD MODE10/ MODE6/SI /HAC0_ SCIF4_RXD OF_SYNC SDIN/SSI0_ /FD2 SCK SIOF_SCK /HAC0_BIT CLK/SSI0_ CLK VDDQ VDD VSS VDD VSS VDD RD/F RAME CS1 VSS VDD VSS MODE13 /TCLK/ IOIS16 VDD VSS D58/A D26 REQ1 D57/A D25 IDSEL T U VSS VDDQ MODE9/ SCIF4_ TXD/FD1 CS6 VSS CS4 VDDQ R/W VSS D12 VSS VDDQ RDY VSS VDDQ D59/A D27 PCICLK /DCLKIN U V SIOF_SYNC HAC1_BI SIOF_MCLK /HAC0_ TCLK/ /HAC_RES SYNC/SSI0_ SSI1_CLK WS SCIF5_SCK /HAC1_SD OUT/SSI1_ SDATA CS5 A14 A11 A6 CS3 CS2 D8 WE0/ REG D7 D11 D16 BS BACK/ BREQ/ REQ2 BSREQ BSACK D22 D27 D63/A D31 VSS D61/A D29 V W VDDQ MODE11 /SCIF4_S CK/FD3 VSS A18 VDDQ A10 VSS A3 VDDQ CS0 VDDQ WE1 VSS VDDQ WE2/ IORD VSS GNT0/ VDDQ GNTIN GNT2 GNT1 REQ3 W PCIRES ET GNT3/ MMCCLK Y SCIF5_TXD SCIF5_RXD /HAC1_ /HAC1_ SDIN/SSI1_ SYNC/ SCK SSI1_WS A23 A20 A17 A13 A9 A5 A2 D1 D4 D10 D15 D18 D21 D26 D29 Y AA A25 VDDQ A22 VDDQ A16 VSS A8 VDDQ A1 VSS D3 D6 VSS D14 VDDQ D20 D25 VDDQ D31 VDDQ WE3/I OWR 21 AA AB VSS 1 A24 2 A21 3 A19 4 A15 5 A12 6 A7 7 A4 8 A0 9 D0 10 D2 11 D5 12 D9 13 D13 14 D17 15 D19 16 D23 17 D24 18 D28 19 D30 20 VSS 22 AB Figure 1.2 SH7785 Pin Arrangement (Top View) Rev.1.00 Jan. 10, 2008 Page 22 of 1658 REJ09B0261-0100 1. Overview 1 AB 2 A24 3 A21 4 A19 5 A15 6 A12 7 A7 8 A4 9 A0 10 D0 11 D2 12 D5 13 D9 14 D13 15 D17 16 D19 17 D23 18 D24 19 D28 20 D30 21 WE3/ IOWR VDDQ 22 VSS AB VSS AA A25 VDDQ A22 VDDQ A16 VSS A8 VDDQ A1 VSS D3 D6 VSS D14 VDDQ D20 VSS WE2/ IORD VDDQ BREQ/ BSACK D25 VDDQ D31 GNT3 /MMC AA CLK PCIRE Y SET REQ3 W Y SCIF5_TXD SCIF5_RXD /HAC1_ /HAC1_ SYNC/SSI1_ SDIN/SSI1_ WS SCK SCIF5_SCK /HAC1_SD OUT/SSI1_ SDATA A23 MODE11/ SCIF4_SCK /FD3 A20 A17 A13 A9 A5 A2 D1 D4 D7 WE0/ REG D8 D10 D15 D18 D21 D26 D29 GNT2 GNT0 /GNTIN GNT1 W VDDQ VSS A18 VDDQ A10 VSS A3 VDDQ CS0 VDDQ WE1 VSS D22 BACK/ BSREQ D27 VSS D63/A D31 VDDQ D61/A D29 V SIOF_SYNC SIOF_MCLK HAC1_BIT MODE9/S /HAC0_ /HAC_RES CLK/SSI1_ CIF4_TXD/ SYNC/ CLK FD1 SSI0_WS SIOF_TXD/ HAC0_SDO UT/SSI0_ SDATA SIOF_SCK /HAC0_BIT CLK/SSI0_ CLK CS5 A14 A11 A6 CS3 CS2 CS1 RD/ FRAME VDD D11 D16 MODE13 /TCLK/ IOIS16 BS REQ2 D62/A D30 PCICLK /DCLKIN V U VSS VDDQ CS6 VSS CS4 VDDQ R/W VSS D12 VSS VDDQ RDY VSS REQ0/ REQOUT REQ1 D58/A D26 D60/A VDDQ D28 D57/A D25 D56/A D24 VSS WE7/ CBE3 D59/A D27 IDSEL U T SCIF1_ SCIF1_ TXD RXD SIOF_RXD MODE10/ MODE6/ /HAC0_SDI SCIF4_RXD SIOF_SYNC N/SSI0_ /FD2 SCK VDDQ VDD VSS VDD VSS VSS VDD VSS VDD VSS T SCIF1_ VDDQ R SCK P MODE5/ SIOF_MCLK VSS MODE8/ MODE4/ SCIF3_SCK/ SCIF3_TXD/ FD0 FCLE VSS VDD SCIF0_SCK SCIF0_TXD SCIF0_RXD SCIF0_CTS SCIF0_RTS MODE7/S /HSPI_CLK /HSPI_TX/ /HSPI_RX/ /HSPI_CS CIF3_RXD/ /INTD/F /FRE FWE /FSE FRB FALE CE VDD PKG BTM VIEW VSS VSS VSS VSS VSS VSS VSS VSS D55/A VDDQ D23 D52/A D20 D51/A D19 VSS D53/A D54/A VDDQ D21 D22 D49/A D48/A D17/D D16/D B5 B4 VSS WE6/ CBE2 TRDY /DISP PAR R VSS D50/A D18 P N PRESET VSS MODE1/ IRL5/FD5 MODE2/ IRL6/FD6 MODE3/ IRL7/FD7 VSS VSS VDD IRDY/ PCIFRA VSS ME/VS VDDQ HSYNC YNC DEVSE STOP LOCK L/DC /CDE /ODDF PERR LKOUT N M VSS VSS MODE0 /IRL4/ FD4 VDDQ VDDMDQ24 DDR VDD VSS SERR M L MDM3 MDQ31 MDQS MDQS3 MDQ29 MDQ30 3 MDQ25 VDDMDQ27 DDR VSS VSS VSS VSS VSS VSS VDD WE5/ D47/AD D46/AD D45/AD D44/AD D43/AD L CBE1 15/DB3 14/DB2 13/DB1 12/DB0 11/DG5 VSS D41/AD D42/AD VDDQ 9/DG3 10/DG4 VSS D40/AD K 8/DG2 K MDQ26 VSS VDD VSS VSS VSS VSS VSS J MDQ28 MDQ23 MDQS MDQS2 MDM2 MDQ20 2 VSS MDQ19 VDDDDR VSS VDD IRL0 WE4/ D39/AD D38/AD D37/AD D36/AD J CBE0 7/DG1 6/DG0 5/DR5 4/DR4 D35/AD 3/DR3 IRL1 MRESET OUT/ IRQOUT H MDQ16 VDDMDQ18 DDR VDD VSS VDDQ VSS D33/AD D34/AD H 2/DR2 VDDQ 1/DR1 MODE12 /DRAK3/ CE2B G MDQ22 MDQ17 MDQ21 MA8 VDDDDR MA4 MA12 VSS VDD VDDDDR VSS VDD VSS VDD VSS VDD VSS VDD IRL3 IRL2 INTA D32/AD G 0/DR0 CLKOU F T VSSPLL2 E F MA14 VSS MA6 MA0 VSS MA7 MDQ5 VSS MDQ8 MDQ9 VDDDDR VSS THDCD VDDQ DRAK2 /CE2A DACK1 VSS DREQ2 /INTB VDDQ CLKO UTENB DREQ3 /INTC VSS E MA10 MVRE F MCS VDDDDR MCK1 VDDDDR MCAS MRAS MWE MA5 VDDDDR MA3 MDQ3 MDM0 MDQ11 MDQ15 TDO THDAS TMS DACK3/S DACK2/S CIF2_TXD/ CIF2_SCK/ MMCCMD/ MMCDAT/ SIOF_TXD SIOF_SCK VDDPLL2 D MBA1 VSS MA2 MA13 VSS MDQS0 VDD- MDQS1 AUDA VDDQ THDAG DDR TA1 AUDA TA3 ASEBRK/ BRKACK VSS DREQ1 VDDQ SCIF2_RXD /SIOF_RXD VSS VDDQ VSSQ- D -PLL2 VDDQ PLL2 VDDAPLL1 VDDPLL1 VSSPLL1 C C VSS MBKPRST MODT MBA2 VDDDDR MA11 MDQ4 MDQ0 VDDDDR MDQS AUDA MDQS MDQ10 TA0 1 0 MDQ6 VSS MDQ14 AUDA TA2 TRST DACK0 VDDQTD DREQ0 MPMD STATUS0 /DRAK0 NMI B MCK1 MCK0 MA1 VSS MDQ2 VSS TDI VDDQ VSS STATUS1 /DRAK1 VDDQ VDDQ VSSA-PLL1 VDDQ PLL1 VSSQPLL1 21 B A VSS 1 MCK0 2 VSS 3 MCKE 4 MBA0 5 MA9 6 MDQ1 MDQ7 MDQ13 MDQ12 MDM1 7 8 9 10 11 AUDSY AUDCK NC 12 13 TCK 14 VSSQTHDCTL TD 15 16 XTAL EXTAL 18 19 MODE14 VSS 22 A 17 20 Figure 1.3 SH7785 Pin Arrangement (Bottom View) Rev.1.00 Jan. 10, 2008 Page 23 of 1658 REJ09B0261-0100 1. Overview 1.5 Physical Memory Address Map The SH7785 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces. For details of mappings from the virtual address space to the physical address spaces, see section 7, Memory Management Unit (MMU). Figure 1.4 shows the relationship between the AREASEL bits and the physical memory address map. The 32-bit physical address space corresponds with the address space of the SuperHyway bus. MMSELR AREASEL[2:0]* H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'2000 0000 H'4000 0000 H'4400 0000 H'4800 0000 H'4C00 0000 H'5000 0000 H'5400 0000 H'5800 0000 H'5C00 0000 H'6000 0000 H'6400 0000 H'6800 0000 H'6C00 0000 H'7000 0000 H'7400 0000 H'7800 0000 H'7C00 0000 H'8000 0000 H'C000 0000 H'E000 0000 H'FFFF FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7(Reserved) (Undefined) DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 DBSC0 DBSC1 DBSC2 DBSC3 DBSC4 DBSC5 DBSC6 DBSC7 DBSC8 DBSC9 DBSC10 DBSC11 DBSC12 DBSC13 DBSC14 DBSC15 B'000 LBSC LBSC LBSC DBSC3 LBSC LBSC LBSC B'001 LBSC LBSC LBSC DBSC3 PCIC LBSC LBSC B'010 LBSC LBSC DBSC2 DBSC3 LBSC LBSC LBSC B'011 LBSC LBSC DBSC2 DBSC3 PCIC LBSC LBSC B'100 LBSC LBSC DBSC2 DBSC3 DBSC4 DBSC5 LBSC B'101 LBSC LBSC LBSC LBSC LBSC LBSC LBSC B'110 LBSC LBSC LBSC LBSC PCIC LBSC LBSC 29-bit physical address space 32-bit physical address space (extended mode) DDR-SDRAM (undefined) PCI (PCIC) (Internal resource) PCIC PCIC PCIC PCIC PCIC PCIC PCIC Note: Memory Address Map Select Register (MMSELR) Area Select Bit (AREASEL) For details, refer to section 11.4.1, Memory Address Map Select Register (MMSELR). Figure 1.4 Relationship between AREASEL Bits and Physical Memory Address Map Rev.1.00 Jan. 10, 2008 Page 24 of 1658 REJ09B0261-0100 2. Programming Model Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. 2.1 Data Formats The data formats supported in this LSI are shown in figure 2.1. 7 Byte (8 bits) 0 15 Word (16 bits) 0 31 Longword (32 bits) 0 Single-precision floating-point (32 bits) 31 30 s e 22 f 0 Double-precision floating-point (64 bits) 63 62 s e 51 f 0 Legend: s :Sign field e :Exponent field f :Fraction field Figure 2.1 Data Formats Rev.1.00 Jan. 10, 2008 Page 25 of 1658 REJ09B0261-0100 2. Programming Model 2.2 2.2.1 (1) Register Descriptions Privileged Mode and Banks Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processing modes. (2) General Registers There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processing mode change. • Privileged mode In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. • User mode In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. (3) Control Registers Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processing modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register Rev.1.00 Jan. 10, 2008 Page 26 of 1658 REJ09B0261-0100 2. Programming Model (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. (4) System Registers System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processing mode. (5) Floating-Point Registers and System Registers Related to FPU There are thirty-two floating-point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0– XF15 can be assigned to either of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1– FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. System registers related to the FPU comprise the floating-point communication register (FPUL) and the floating-point status/control register (FPSCR). These registers are used for communication between the FPU and the CPU, and the exception handling setting. Register values after a reset are shown in table 2.1. Rev.1.00 Jan. 10, 2008 Page 27 of 1658 REJ09B0261-0100 2. Programming Model Table 2.1 Type Initial Register Values Registers Initial Value* Undefined General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Control registers SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = B'1111, reserved bits = 0, others = undefined GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL, PR PC Floating-point registers Note: * FR0 to FR15, XF0 to XF15, FPUL FPSCR H'00000000 Undefined H'A0000000 Undefined H'00040001 Initialized by a power-on reset and manual reset. The CPU register configuration in each processing mode is shown in figure 2.2. User mode and privileged mode are switched by the processing mode bit (MD) in the status register. Rev.1.00 Jan. 10, 2008 Page 28 of 1658 REJ09B0261-0100 2. Programming Model 31 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR 0 31 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR 0 GBR MACH MACL PR PC (a) Register configuration in user mode R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1) R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0) Notes: 1. R0 is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only by LDC/STC instructions when the RB bit is set to 1. Figure 2.2 CPU Register Configuration in Each Processing Mode Rev.1.00 Jan. 10, 2008 Page 29 of 1658 REJ09B0261-0100 2. Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode. This LSI has two processing modes, user mode and privileged mode. • R0_BANK0 to R7_BANK0 Allocated to R0 to R7 in user mode (SR.MD = 0) Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1). • R0_BANK1 to R7_BANK1 Cannot be accessed in user mode. Allocated to R0 to R7 when SR.RB = 1 in privileged mode. SR.MD = 0 or (SR.MD = 1, SR.RB = 0) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15 (SR.MD = 1, SR.RB = 1) R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Figure 2.3 General Registers Rev.1.00 Jan. 10, 2008 Page 30 of 1658 REJ09B0261-0100 2. Programming Model Note on Programming: As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0). 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers, FPR0_BANK0 to FPR15_BANK0, AND FPR0_BANK1 to FPR15_BANK1, comprising two banks. These registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. Reference names of each register are defined depending on the state of the FR bit in FPSCR (see figure 2.4). 1. Floating-point registers, FPRn_BANKj (32 registers) FPR0_BANK0 to FPR15_BANK0 FPR0_BANK1 to FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0; when FPSCR.FR = 1, FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1. 3. Double-precision floating-point registers or single-precision floating-point registers, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} 4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers. FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} 5. Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0 to XF15 are assigned to FPR0_BANK1 to FPR15_BANK1; when FPSCR.FR = 1, XF0 to XF15 are assigned to FPR0_BANK0 to FPR15_BANK0. 6. Double-precision floating-point extended registers, XDi (8 registers): An XD register comprises two XF registers. XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} Rev.1.00 Jan. 10, 2008 Page 31 of 1658 REJ09B0261-0100 2. Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPSCR.FR = 1 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XMTRX FPSCR.FR = 0 FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FV12 DR12 DR14 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 Figure 2.4 Floating-Point Registers Rev.1.00 Jan. 10, 2008 Page 32 of 1658 REJ09B0261-0100 2. Programming Model 2.2.4 (1) Control Registers Status Register (SR) BIt: 31 0 R 15 30 MD 1 R/W 14 0 R 29 RB 1 R/W 13 0 R 28 BL 1 R/W 12 0 R 0 R 11 0 R 0 R 10 0 R 0 R 9 M 0 R/W 0 R 8 Q 0 R/W 0 R 7 1 R/W 0 R 6 0 R 5 0 R 4 1 R/W 0 R 3 0 R 0 R 2 0 R 0 R 1 S 0 R/W 0 R 0 T 0 R/W 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: R/W: BIt: FD Initial value: 0 R/W: R/W IMASK 1 1 R/W R/W Bit 31 Bit Name — Initial Value 0 R/W R Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 30 MD 1 R/W Processing Mode Selects the processing mode. 0: User mode (Some instructions cannot be executed and some resources cannot be accessed.) 1: Privileged mode This bit is set to 1 by an exception or interrupt. 29 RB 1 R/W Privileged Mode General Register Bank Specification Bit 0: R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC/STC instructions 1: R0_BANK1 to R7_BANK1 are accessed as general registers R0 to R7 and R0_BANK0–R7_BANK0 can be accessed using LDC/STC instructions This bit is set to 1 by an exception or interrupt. 28 BL 1 R/W Exception/Interrupt Block Bit This bit is set to 1 by a reset, a general exception, or an interrupt. While this bit is set to 1, an interrupt request is masked. In this case, this processor enters the reset state when a general exception other than a user break occurs. Rev.1.00 Jan. 10, 2008 Page 33 of 1658 REJ09B0261-0100 2. Programming Model Bit Bit Name Initial Value All 0 R/W R Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 27 to 16 — 15 FD 0 R/W FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs. When this bit is set to 1 and an FPU instruction is in a delay slot, a slot FPU disable exception occurs. (FPU instructions: H'F*** instructions and LDS (.L)/STS(.L) instructions using FPUL/FPSCR) 14 to 10 — All 0 R Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 9 8 7 to 4 M Q IMASK 0 0 1111 R/W R/W R/W M Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked. It can be chosen by CPU operation mode register (CPUOPM) whether the level of IMASK is changed to accept an interrupt or not when an interrupt is occurred. For details, see appendix A, CPU Operation Mode Register (CPUOPM). Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. 3, 2 — All 0 R 1 0 S T 0 0 R/W R/W S Bit Used by the MAC instruction. T Bit Indicates true/false condition, carry/borrow, or overflow/underflow. For details, see section 3, Instruction Set. Rev.1.00 Jan. 10, 2008 Page 34 of 1658 REJ09B0261-0100 2. Programming Model (2) Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. (3) Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined) The address of an instruction at which an interrupt or exception occurs is saved to SPC. (4) Global Base Register (GBR) (32 bits, Initial Value = Undefined) GBR is referenced as the base address of addressing @(disp,GBR) and @(R0,GBR). (5) Vector Base Register (VBR) (32 bits, Privileged Mode, Initial Value = H'00000000) VBR is referenced as the branch destination base address in the event of an exception or interrupt. For details, see section 5, Exception Handling. (6) Saved General Register 15 (SGR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of R15 are saved to SGR in the event of an exception or interrupt. (7) Debug Base Register (DBR) (32 bits, Privileged Mode, Initial Value = Undefined) When the user break debugging function is enabled (CBCR.UBDE = 1), DBR is referenced as the branch destination address of the user break handler instead of VBR. 2.2.5 (1) System Registers Multiply-and-Accumulate Registers (MACH and MACL) (32 bits, Initial Value = Undefined) MACH and MACL are used for the added value in a MAC instruction, and to store the operation result of a MAC or MUL instruction. (2) Procedure Register (PR) (32 bits, Initial Value = Undefined) The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine return instruction (RTS). (3) Program Counter (PC) (32 bits, Initial Value = H'A0000000) PC indicates the address of the instruction currently being executed. Rev.1.00 Jan. 10, 2008 Page 35 of 1658 REJ09B0261-0100 2. Programming Model (4) Floating-Point Status/Control Register (FPSCR) BIt: 31 0 R 15 0 R/W 30 0 R 14 0 R/W 29 0 R 13 0 R/W 28 0 R 12 0 R/W 27 0 R 11 0 R/W 26 0 R 10 0 R/W 25 0 R 9 Enable (EN) 24 0 R 8 0 R/W 23 0 R 7 0 R/W 22 0 R 6 0 R/W 21 FR 20 SZ 19 PR 18 DN 17 0 R/W 1 RM 16 0 R/W 0 1 R/W Cause Initial value: R/W: BIt: Initial value: R/W: 0 R/W 5 0 R/W 0 R/W 4 Flag 0 R/W 3 0 R/W 1 R/W 2 0 R/W Cause 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. Floating-Point Register Bank 0: FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1: FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) For relationship between the SZ bit, PR bit, and endian, see figure 2.5. Precision Mode 0: Floating-point instructions are executed as single-precision operations 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined) For relationship between the SZ bit, PR bit, and endian, see figure 2.5 Denormalization Mode 0: Denormalized number is treated as such 1: Denormalized number is treated as zero 31 to 22 — 21 FR 0 R/W 20 SZ 0 R/W 19 PR 0 R/W 18 DN 1 R/W Rev.1.00 Jan. 10, 2008 Page 36 of 1658 REJ09B0261-0100 2. Programming Model Bit Bit Name Initial Value 000000 R/W R/W R/W R/W Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. When an FPU exception occurs, the bits corresponding to FPU exception cause field and flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 2.2. Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved 17 to 12 Cause 11 to 7 6 to 2 Enable (EN) 00000 Flag 00000 1, 0 RM 01 R/W Rev.1.00 Jan. 10, 2008 Page 37 of 1658 REJ09B0261-0100 2. Programming Model 63 Floating-point register 63 FR (2i) FR (2i+1) DR (2i) 0 0 63 Memory area 8n 32 31 8n+3 8n+4 0 8n+7 63 Floating-point register 63 FR (2i) FR (2i+1) DR (2i) 0 63 DR (2i) 0 63 DR (2i) 0 *1, *2 0 63 FR (2i) *2 0 FR (2i+1) 63 FR (2i) FR (2i+1) 0 63 Memory area 4n+3 32 31 4n 4m+3 (1) SZ = 0 0 4m 63 8n+3 32 31 8n 8n+7 (2) SZ = 1, PR = 0 0 8n+4 63 8n+7 32 31 8n+4 8n+3 (3) SZ = 1, PR = 1 0 8n Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used. 2. The bit-location of DR register is used for double precision format when PR = 1. (In the case of (2), it is used when PR is changed from 0 to 1.) Figure 2.5 Relationship between SZ bit and Endian Table 2.2 Field Name Cause Enable Flag FPU exception cause field FPU exception enable field Bit Allocation for FPU Exception Handling FPU Error (E) Bit 17 None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2 FPU exception flag None field (5) Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined) Information is transferred between the FPU and CPU via FPUL. Rev.1.00 Jan. 10, 2008 Page 38 of 1658 REJ09B0261-0100 2. Programming Model 2.3 Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding field of the TLB enables access to a memory-mapped register. The operation of an access to this area without using the address translation function of the MMU is not guaranteed. • H'FC00 0000 to H'FFFF FFFF Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error. Memory-mapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access addresses to which registers are not mapped in either area. The operation of an access to an address with no register mapped is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Rev.1.00 Jan. 10, 2008 Page 39 of 1658 REJ09B0261-0100 2. Programming Model 2.4 Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 76 S 0 31 S 76 S 0 15 14 S 0 31 S 15 14 S 0 Figure 2.6 Formats of Byte Data and Word Data in Register 2.5 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the external pin after a power-on reset. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.7. Rev.1.00 Jan. 10, 2008 Page 40 of 1658 REJ09B0261-0100 2. Programming Model A 31 7 07 A+1 23 07 A+2 15 7 07 A+3 0 0 A + 11 A + 10 A + 9 31 7 23 07 15 07 7 07 A+8 0 0 Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8 15 0 15 Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8 0 15 0 0 15 Word 0 31 Word 1 0 31 Word 1 Word 0 0 Address A + 4 Address A Longword Longword Big endian Little endian Figure 2.7 Data Formats in Memory For the 64-bit data format, see figure 2.5. 2.6 Processing States This LSI has major three processing states: the reset state, instruction execution state, and powerdown state. (1) Reset State In this state the CPU is reset. The reset state is divided into the power-on reset state and the manual reset. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and some registers of on-chip peripheral modules are initialized. For details, see register descriptions for each section. (2) Instruction Execution State In this state, the CPU executes program instructions in sequence. The Instruction execution state has the normal program execution state and the exception handling state. (3) Power-Down State In a power-down state, CPU halts operation and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 17, Power-Down mode. Rev.1.00 Jan. 10, 2008 Page 41 of 1658 REJ09B0261-0100 2. Programming Model From any state when reset/manual reset input Reset state Reset/manual reset clearance Reset/manual reset input Reset/manual reset input Instruction execution state Sleep instruction execution Power-down state Interrupt occurence Figure 2.8 Processing State Transitions Rev.1.00 Jan. 10, 2008 Page 42 of 1658 REJ09B0261-0100 2. Programming Model 2.7 2.7.1 Usage Notes Notes on Self-Modifying Code To accelerate the processing speed, the instruction prefetching capability of this LSI has been significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is rewritten and attempted to be executed immediately, there is increased possibility that the code before being modified, which has already been prefetched, is executed. To ensure execution of the modified code, one of the following sequence of instructions should be executed between the code rewriting instruction and execution of the modified code. (1) When the Codes to be Modified are in Non-Cacheable Area SYNCO ICBI @Rn The target for the ICBI instruction can be any address within the range where no address error exception occurs. (2) When the Codes to be Modified are in Cacheable Area (Write-Through) SYNCO ICBI @Rn All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes. (3) When the Codes to be Modified are in Cacheable Area (Copy-Back) OCBP @Rm or OCBWB @Rm SYNCO ICBI @Rn All operand cache areas corresponding to the modified codes should be written back to the main memory by the OCBP or OCBWB instruction. Then all instruction cache areas corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB, and ICBI instruction should be issued to each cache line. One cache line is 32 bytes. Note: Self-modifying code is the processing which executes instructions while dynamically rewriting the codes in memory. Rev.1.00 Jan. 10, 2008 Page 43 of 1658 REJ09B0261-0100 2. Programming Model Rev.1.00 Jan. 10, 2008 Page 44 of 1658 REJ09B0261-0100 3. Instruction Set Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size. When this LSI moves byte-size or word-size data from memory to a register, the data is sign-extended. 3.1 (1) PC Execution Environment At the start of instruction execution, the PC indicates the address of the instruction itself. (2) Load-Store Architecture This LSI has a load-store architecture in which operations are basically executed using registers. Except for bit-manipulation operations such as logical AND that are executed directly in memory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. (3) Delayed Branches Except for the two branch instructions BF and BT, this LSI's branch instructions and RTE are delayed branches. In a delayed branch, the instruction following the branch is executed before the branch destination instruction. (4) Delay Slot This execution slot following a delayed branch is called a delay slot. For example, the BRA execution sequence is as follows: Rev.1.00 Jan. 10, 2008 Page 45 of 1658 REJ09B0261-0100 3. Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions Instructions BRA ADD : : TARGET (Delayed branch instruction) (Delay slot) Execution Order BRA ↓ ADD ↓ (Branch destination instruction) target-inst TARGET target-inst A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction. (5) T Bit The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below. ADD #1, R0 CMP/EQ R1, R0 BT TARGET ; T bit is not changed by ADD operation ; If R0 = R1, T bit is set to 1 ; Branches to TARGET if T bit = 1 (R0 = R1) In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution. The STC and STC.L SR instructions access all SR bits after modification. (6) Constant Values An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a PC-relative load instruction. MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn There are no PC-relative load instructions for floating-point operations. However, it is possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point register. Rev.1.00 Jan. 10, 2008 Page 46 of 1658 REJ09B0261-0100 3. Instruction Set 3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For details, see section 7, Memory Management Unit (MMU). Table 3.2 Addressing Modes and Effective Addresses Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Addressing Instruction Mode Format Register direct Register indirect Register indirect with postincrement Rn @Rn Calculation Formula — Rn → EA (EA: effective address) Rn → EA After instruction execution Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Quadword: Rn + 8 → Rn @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn + 1/2/4 1/2/4 + Rn Rev.1.00 Jan. 10, 2008 Page 47 of 1658 REJ09B0261-0100 3. Instruction Set Addressing Mode Register indirect with predecrement Instruction Format @–Rn Effective Address Calculation Method Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn – 1/2/4 1/2/4 – Rn – 1/2/4/8 Calculation Formula Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn Quadword: Rn – 8 → Rn Rn → EA (Instruction executed with Rn after calculation) Byte: Rn + disp → EA Word: Rn + disp × 2 → EA Longword: Rn + disp × 4 → EA Register @(disp:4, Rn) Effective address is register Rn contents with indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4 Indexed register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn + R0 Rn + R0 Rn + R0 → EA Rev.1.00 Jan. 10, 2008 Page 48 of 1658 REJ09B0261-0100 3. Instruction Set Addressing Mode Instruction Format Effective Address Calculation Method Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) × 1/2/4 + GBR + disp × 1/2/4 Calculation Formula Byte: GBR + disp → EA Word: GBR + disp × 2 → EA Longword: GBR + disp × 4 → EA GBR indirect @(disp:8, with displace- GBR) ment Indexed GBR @(R0, GBR) indirect Effective address is sum of register GBR and R0 contents. GBR + R0 GBR + R0 GBR + R0 → EA PC-relative @(disp:8, PC) with displacement Effective address is PC + 4 with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC &* H'FFFF FFFC 4 + disp (zero-extended) × 2/4 * With longword operand + PC + 4 + disp ×2 or PC & H'FFFF FFFC + 4 + disp × 4 Word: PC + 4 + disp × 2 → EA Longword: PC & H'FFFF FFFC + 4 + disp × 4 → EA Rev.1.00 Jan. 10, 2008 Page 49 of 1658 REJ09B0261-0100 3. Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method PC-relative disp:8 Effective address is PC + 4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. Calculation Formula PC + 4 + disp × 2 → BranchTarget PC + 4 + disp (sign-extended) × 2 PC-relative disp:12 Effective address is PC + 4 with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC + 4 + disp (sign-extended) × 2 PC + 4 + disp × 2 PC + 4 + disp × 2 PC + 4 + disp × 2 → BranchTarget Rn Effective address is sum of PC + 4 and Rn. PC + 4 Rn + PC + 4 + Rn PC + 4 + Rn → Branch-Target Rev.1.00 Jan. 10, 2008 Page 50 of 1658 REJ09B0261-0100 3. Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. Calculation Formula — — — Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative Rev.1.00 Jan. 10, 2008 Page 51 of 1658 REJ09B0261-0100 3. Instruction Set 3.3 Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Item Instruction mnemonic Notation Used in Instruction List Format OP.Sz SRC, DEST Description OP: Sz: SRC: DEST: Rm: Rn: imm: disp: →, ← (xx) M/Q/T & | Operation code Size Source operand Source and/or destination operand Source register Destination register Immediate data Displacement Operation notation Transfer direction Memory operand SR flag bits Logical AND of individual bits Logical OR of individual bits ∧ Logical exclusive-OR of individual bits ~ Logical NOT of individual bits n n-bit shift MSB ↔ LSB mmmm: nnnn: 0000: 0001: : 1111: mmm: nnn: 000: 001: : 111: mm: nn: 00: 01: 10: 11: iiii: dddd: Register number (Rm, FRm) Register number (Rn, FRn) R0, FR0 R1, FR1 R15, FR15 Register number (DRm, XDm, Rm_BANK) Register number (DRn, XDn, Rn_BANK) DR0, XD0, R0_BANK DR2, XD2, R1_BANK DR14, XD14, R7_BANK Register number (FVm) Register number (FVn) FV0 FV4 FV8 FV12 Immediate data Displacement Instruction code Rev.1.00 Jan. 10, 2008 Page 52 of 1658 REJ09B0261-0100 3. Instruction Set Item Privileged mode T bit New Format Description "Privileged" means the instruction can only be executed in privileged mode. Value of T bit after —: No change instruction execution ⎯ "New" means the instruction which has been newly added in the SH-4A with H’20-valued VER bits in the processor version register (PVR). Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Table 3.4 Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B Fixed-Point Transfer Instructions Operation imm → sign extension → Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd Privileged T Bit New — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — #imm,Rn @(disp*,PC), Rn (disp × 2 + PC + 4) → sign extension → Rn @(disp*,PC), Rn (disp × 4 + PC & H'FFFF FFFC 1101nnnndddddddd + 4) → Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn Rm → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → sign extension → Rn (Rm) → sign extension → Rn (Rm) → Rn Rn-1 → Rn, Rm → (Rn) Rn-2 → Rn, Rm → (Rn) Rn-4 → Rn, Rm → (Rn) (Rm)→ sign extension → Rn, Rm + 1 → Rm (Rm) → sign extension → Rn, Rm + 2 → Rm (Rm) → Rn, Rm + 4 → Rm R0 → (disp + Rn) R0 → (disp × 2 + Rn) Rm → (disp × 4 + Rn) 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd MOV.W @Rm,Rn MOV.L MOV.B @Rm,Rn Rm,@-Rn MOV.W Rm,@-Rn MOV.L MOV.B Rm,@-Rn @Rm+,Rn MOV.W @Rm+,Rn MOV.L MOV.B @Rm+,Rn R0,@(disp*,Rn) MOV.W R0,@(disp*,Rn) MOV.L Rm,@(disp*,Rn) Rev.1.00 Jan. 10, 2008 Page 53 of 1658 REJ09B0261-0100 3. Instruction Set Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA @(disp*,Rm),R0 Operation (disp + Rm) → sign extension → R0 (disp × 2 + Rm) → sign extension → R0 (disp × 4 + Rm) → Rn Rm → (R0 + Rn) Rm → (R0 + Rn) Rm → (R0 + Rn) (R0 + Rm) → sign extension → Rn (R0 + Rm) → sign extension → Rn (R0 + Rm) → Rn R0 → (disp + GBR) R0 → (disp × 2 + GBR) R0 → (disp × 4 + GBR) (disp + GBR) → sign extension → R0 (disp × 2 + GBR) → sign extension → R0 (disp × 4 + GBR) → R0 disp × 4 + PC & H'FFFF FFFC + 4 → R0 LDST → T If (T == 1) R0 → (Rn) 0 → LDST Instruction Code 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd Privileged — — — — — — — — — — — — — — — — T Bit — — — — — — — — — — — — — — — — New — — — — — — — — — — — — — — — — @(disp*,Rm),R0 @(disp*,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn R0,@(disp*,GBR) R0,@(disp*,GBR) R0,@(disp*,GBR) @(disp*,GBR),R0 @(disp*,GBR),R0 @(disp*,GBR),R0 @(disp*,PC),R0 MOVCO.L R0,@Rn 0000nnnn01110011 ⎯ LDST New MOVLI.L @Rm,R0 1 → LDST 0000mmmm01100011 (Rm) → R0 When interrupt/exception occurred 0 → LDST (Rm) → R0 Load non-boundary alignment data (Rm) → R0, Rm + 4 → Rm Load non-boundary alignment data 0100mmmm10101001 ⎯ ⎯ New MOVUA.L @Rm,R0 ⎯ ⎯ New MOVUA.L @Rm+,R0 0100mmmm11101001 ⎯ ⎯ New Rev.1.00 Jan. 10, 2008 Page 54 of 1658 REJ09B0261-0100 3. Instruction Set Instruction MOVT SWAP.B SWAP.W XTRCT Rn Rm,Rn Rm,Rn Rm,Rn Operation T → Rn Rm → swap lower 2 bytes → Rn Rm → swap upper/lower words → Rn Instruction Code Privileged T Bit — — — — New — — — — 0000nnnn00101001 — 0110nnnnmmmm1000 — 0110nnnnmmmm1001 — Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — Note: * The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the displacement (disp). Table 3.5 Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS Arithmetic Operation Instructions Operation Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, carry → T Rn + Rm → Rn, overflow → T When R0 = imm, 1 → T Otherwise, 0 → T When Rn = Rm, 1 → T Otherwise, 0 → T When Rn ≥ Rm (unsigned), 1→T Otherwise, 0 → T When Rn ≥ Rm (signed), 1→T Otherwise, 0 → T When Rn > Rm (unsigned), 1→T Otherwise, 0 → T When Rn > Rm (signed), 1→T Otherwise, 0 → T When Rn ≥ 0, 1 → T Otherwise, 0 → T When Rn > 0, 1 → T Otherwise, 0 → T Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 Privileged T Bit — — — — — — — — — Carry Overflow New — — — — Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result Comparison — result CMP/GE Rm,Rn 0011nnnnmmmm0011 — CMP/HI Rm,Rn 0011nnnnmmmm0110 — CMP/GT Rm,Rn 0011nnnnmmmm0111 — CMP/PZ CMP/PL Rn Rn 0100nnnn00010001 0100nnnn00010101 — — Rev.1.00 Jan. 10, 2008 Page 55 of 1658 REJ09B0261-0100 3. Instruction Set Instruction CMP/STR Rm,Rn Operation Instruction Code Privileged T Bit — New When any bytes are equal, 0010nnnnmmmm1100 1→T Otherwise, 0 → T 1-step division (Rn ÷ Rm) MSB of Rn → Q, MSB of Rm → M, M^Q → T 0 → M/Q/T 0011nnnnmmmm0100 0010nnnnmmmm0111 Comparison — result Calculation result Calculation result 0 — — — DIV1 DIV0S Rm,Rn Rm,Rn — — DIV0U DMULS.L Rm,Rn 0000000000011001 0011nnnnmmmm1101 — — — — Signed, Rn × Rm → MAC, 32 × 32 → 64 bits Unsigned, Rn × Rm → MAC, 32 × 32 → 64 bits Rn – 1 → Rn; when Rn = 0, 1 → T When Rn ≠ 0, 0 → T Rm sign-extended from byte → Rn Rm sign-extended from word → Rn Rm zero-extended from byte → Rn Rm zero-extended from word → Rn DMULU.L Rm,Rn 0011nnnnmmmm0101 — — — DT Rn 0100nnnn00010000 — Comparison — result — — — — — — — — — — EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 — — — — — @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 4 → Rn, Rm + 4 → Rm 32 × 32 + 64 → 64 bits @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → MAC Rn + 2 → Rn, Rm + 2 → Rm 16 × 16 + 64 → 64 bits Rm,Rn Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits Signed, Rn × Rm → MACL 16 × 16 → 32 bits MAC.W 0100nnnnmmmm1111 — — — MUL.L MULS.W 0000nnnnmmmm0111 0010nnnnmmmm1111 — — — — — — Rev.1.00 Jan. 10, 2008 Page 56 of 1658 REJ09B0261-0100 3. Instruction Set Instruction MULU.W Rm,Rn Operation Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn 0 – Rm – T → Rn, borrow → T Rn – Rm → Rn Rn – Rm – T → Rn, borrow → T Rn – Rm → Rn, underflow → T Instruction Code 0010nnnnmmmm1110 Privileged T Bit — — New — NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 — — — — — — Borrow — Borrow Underflow — — — — — Table 3.6 Instruction AND AND Logic Operation Instructions Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) When (Rn) = 0, 1 → T Otherwise, 0 → T In both cases, 1 → MSB of (Rn) Rn & Rm; when result = 0, 1 → T Otherwise, 0 → T R0 & imm; when result = 0, 1 → T Otherwise, 0 → T (R0 + GBR) & imm; when result = 0, 1 → T Otherwise, 0 → T Rn ∧ Rm → Rn Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 Privileged T Bit — — — — — — — — — — — — — — — Test result New — — — — — — — — Rm,Rn #imm,R0 AND.B #imm, @(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm, @(R0,GBR) TAS.B @Rn TST Rm,Rn 0010nnnnmmmm1000 — Test result Test result Test result — — TST #imm,R0 11001000iiiiiiii — — TST.B #imm, @(R0,GBR) 11001100iiiiiiii — — XOR Rm,Rn 0010nnnnmmmm1010 — — Rev.1.00 Jan. 10, 2008 Page 57 of 1658 REJ09B0261-0100 3. Instruction Set Instruction XOR #imm,R0 Operation R0 ∧ imm → R0 (R0 + GBR) ∧ imm → (R0 + GBR) Instruction Code 11001010iiiiiiii 11001110iiiiiiii Privileged T Bit — — — — New — — XOR.B #imm, @(R0,GBR) Table 3.7 Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Shift Instructions Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T When Rm ≥ 0, Rn > Rm → [MSB → Rn] T ← Rn ← 0 MSB → Rn → T When Rm ≥ 0, Rn > Rm → [0 → Rn] T ← Rn ← 0 0 → Rn → T Rn > 2 → Rn Rn > 8 → Rn Rn > 16 → Rn Instruction Code Privileged T Bit MSB LSB MSB LSB — New — — — — — 0100nnnn00000100 — 0100nnnn00000101 — 0100nnnn00100100 — 0100nnnn00100101 — 0100nnnnmmmm1100 — Rm,Rn SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 — 0100nnnn00100001 — 0100nnnnmmmm1101 — MSB LSB — — — — SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn 0100nnnn00000000 — 0100nnnn00000001 — 0100nnnn00001000 — 0100nnnn00001001 — 0100nnnn00011000 — 0100nnnn00011001 — 0100nnnn00101000 — 0100nnnn00101001 — MSB LSB — — — — — — — — — — — — — — Rev.1.00 Jan. 10, 2008 Page 58 of 1658 REJ09B0261-0100 3. Instruction Set Table 3.8 Instruction BF Branch Instructions Operation label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop When T = 1, disp × 2 + PC + 4 → PC When T = 0, nop Delayed branch; when T = 1, disp × 2 + PC + 4 → PC When T = 0, nop Delayed branch, disp × 2 + P C + 4 → PC Instruction Code Privileged T Bit — New — 10001011dddddddd — BF/S label 10001111dddddddd — — — BT label 10001001dddddddd — — — BT/S label 10001101dddddddd — — — BRA BRAF BSR BSRF JMP JSR RTS label Rn label Rn @Rn @Rn 1010dddddddddddd — — — — — — — — — — — — — — — Delayed branch, Rn + PC + 4 → 0000nnnn00100011 — PC Delayed branch, PC + 4 → PR, 1011dddddddddddd — disp × 2 + PC + 4 → PC Delayed branch, PC + 4 → PR, 0000nnnn00000011 — Rn + PC + 4 → PC Delayed branch, Rn → PC 0100nnnn00101011 — Delayed branch, PC + 4 → PR, 0100nnnn00001011 — Rn → PC Delayed branch, PR → PC 0000000000001011 — Table 3.9 Instruction CLRMAC CLRS CLRT ICBI LDC LDC LDC LDC System Control Instructions Operation 0 → MACH, MACL 0→S 0→T @Rn Rm,SR Rm,GBR Rm,VBR Rm,SGR Instruction Code 0000000000101000 0000000001001000 0000000000001000 Privileged T Bit — — — ⎯ — — 0 ⎯ New — — — New — — — — Invalidates instruction cache block 0000nnnn11100011 Rm → SR Rm → GBR Rm → VBR Rm → SGR 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111010 Privileged LSB — — Privileged — Privileged — Rev.1.00 Jan. 10, 2008 Page 59 of 1658 REJ09B0261-0100 3. Instruction Set Instruction LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB MOVCA.L NOP OCBI OCBP OCBWB PREF PREFI RTE @Rn @Rn @Rn @Rn @Rn R0,@Rn Rm,SSR Rm,SPC Rm,DBR Operation Rm → SSR Rm → SPC Rm → DBR Instruction Code 0100mmmm00111110 0100mmmm01001110 0100mmmm11111010 Privileged Privileged Privileged Privileged Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged — — — — — — Privileged — — — — — — ⎯ Privileged T Bit — — — — LSB — — — — — — — — — — — — — — — — — — — — ⎯ — New — — — — — — — — — — — — — — — — — — — — — — — — — New — Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SGR @Rm+,SSR @Rm+,SPC @Rm+,DBR @Rm+,Rn_ BANK Rm,MACH Rm,MACL Rm,PR (Rm) → SR, Rm + 4 → R m 0100mmmm00000111 (Rm) → GBR, Rm + 4 → R m 0100mmmm00010111 (Rm) → VBR, Rm + 4 → R m 0100mmmm00100111 (Rm) → SGR, Rm + 4 → R m 0100mmmm00110110 (Rm) → SSR, Rm + 4 → R m 0100mmmm00110111 (Rm) → SPC, Rm + 4 → R m 0100mmmm01000111 (Rm) → DBR, Rm + 4 → R m 0100mmmm11110110 (Rm) → Rn_BANK, Rm + 4 → R m Rm → MACH Rm → MACL Rm → PR 0100mmmm1nnn0111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm @Rm+,MACL @Rm+,PR (Rm) → MACL, Rm + 4 → Rm (Rm) → PR, Rm + 4 → R m R0 → (Rn) (without fetching cache block) No operation Invalidates operand cache block Writes back and invalidates operand cache block Writes back operand cache block (Rn) → operand cache Reads 32-byte instruction block into instruction cache Delayed branch, SSR/SPC → SR/PC PTEH/PTEL (/PTEA) → TLB 0000000000111000 0000nnnn11000011 0000000000001001 0000nnnn10010011 0000nnnn10100011 0000nnnn10110011 0000nnnn10000011 0000nnnn11010011 0000000000101011 Rev.1.00 Jan. 10, 2008 Page 60 of 1658 REJ09B0261-0100 3. Instruction Set Instruction SETS SETT SLEEP STC STC STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn SGR,Rn DBR,Rn Operation 1→S 1→T Sleep or standby SR → R n GBR → R n VBR → R n SSR → R n SPC → R n SGR → Rn DBR → R n Instruction Code 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn00111010 0000nnnn11111010 0000nnnn1mmm0010 Privileged — — Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged Privileged — Privileged Privileged Privileged Privileged Privileged Privileged T Bit — 1 — — — — — — — — — — — — — — — — — New — — — — — — — — — — — — — — — — — — — Rm_BANK,Rn Rm_BANK → Rn (m = 0 to 7) SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn SGR,@-Rn DBR,@-Rn Rn – 4 → Rn, SR → (Rn) 0100nnnn00000011 Rn – 4 → Rn, GBR → (Rn) Rn – 4 → Rn, VBR → (Rn) Rn – 4 → Rn, SSR → (Rn) Rn – 4 → Rn, SPC → (Rn) Rn – 4 → Rn, SGR → (Rn) Rn – 4 → Rn, DBR → (Rn) 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn00110010 0100nnnn11110010 0100nnnn1mmm0011 Rm_BANK,@- Rn – 4 → Rn, Rn Rm_BANK → (Rn) (m = 0 to 7) MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn MACH → R n MACL → R n PR → R n Rn – 4 → Rn, MACH → (Rn) Rn – 4 → Rn, MACL → (Rn) STS STS STS STS.L STS.L STS.L 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 — — — — — — — — — — — — — — — — — — Rn – 4 → Rn, PR → (Rn) 0100nnnn00100010 Rev.1.00 Jan. 10, 2008 Page 61 of 1658 REJ09B0261-0100 3. Instruction Set Instruction SYNCO Operation Data accesses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed. #imm Instruction Code 0000000010101011 Privileged ⎯ T Bit ⎯ New New TRAPA PC + 2 → SPC, 11000011iiiiiiii SR → SSR, R15 → SGR, 1 → SR.MD/BL/RB, #imm