DATASHEET
X5043, X5045
FN8126
Rev 3.00
September 23, 2015
4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Four industry standard VTRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
Features
• Low VCC Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence.
- Reset signal valid to VCC = 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- 3.3V, IOH = –1.0mA
VCC - 0.8
V
VOH2
Output HIGH Voltage (SO)
2V < VCC 3.3V, IOH = –0.4mA
VCC - 0.4
V
VOH3
Output HIGH Voltage (SO)
VCC 2V, IOH = –0.25mA
VCC - 0.2
V
VOLRS
Output LOW Voltage (RESET,
RESET)
IOL = 1mA
VIL
VIH
Capacitance
CIN(2)
V
TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
COUT(2)
0.4
TEST
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
CONDITIONS
MAX
UNIT
VOUT = 0V
8
pF
VIN = 0V
6
pF
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
3. SCK frequency measured from VCC x 0.1/VCC x 0.9
FN8126 Rev 3.00
September 23, 2015
Page 13 of 21
X5043, X5045
Equivalent A.C. Load Circuit at 5V VCC
5V
A.C. Test Conditions
5V
4.6k
1.64k
Output
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RESET/RESET
1.64k
30pF
30pF
AC Electrical Specifications
(Over recommended operating conditions, unless otherwise specified)
2.7V–5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
3.3
MHz
DATA INPUT TIMING
fSCK
Clock Frequency
tCYC
Cycle Time
300
ns
tLEAD
CS Lead Time
150
ns
tLAG
CS Lag Time
150
ns
tWH
Clock HIGH Time
130
ns
tWL
Clock LOW Time
130
ns
tSU
Data Setup Time
30
ns
tH
Data Hold Time
30
ns
tRI(4)
Input Rise Time
2
µs
tFI(4)
Input Fall Time
2
µs
tCS
CS Deselect Time
tWC(5)
Write Cycle Time
100
ns
10
ms
MIN
MAX
UNIT
0
3.3
MHz
Data Output Timing
2.7–5.5V
SYMBOL
PARAMETER
fSCK
Clock Frequency
tDIS
Output Disable Time
150
ns
Output Valid from Clock Low
120
ns
tV
tHO
Output Hold Time
tRO(4)
Output Rise Time
50
ns
tFO(4)
Output Fall Time
50
ns
0
ns
NOTES:
4. This parameter is periodically sampled and not 100% tested.
5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
FN8126 Rev 3.00
September 23, 2015
Page 14 of 21
X5043, X5045
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
MSB Out
SO
SI
tHO
tWL
tDIS
MSB–1 Out
LSB Out
ADDR
LSB IN
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
MSB In
SI
SO
tRI
tFI
LSB In
High Impedance
Symbol Table
WAVEFORM
FN8126 Rev 3.00
September 23, 2015
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Page 15 of 21
X5043, X5045
Power-Up and Power-Down Timing
VCC
VTRIP
VTRIP
tPURST
0 Volts
tPURST
tF
tR
tRPD
RESET (X5043)
RESET (X5045)
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset Trip Point Voltage, (-4.5A)
Reset Trip Point Voltage, (Blank)
Reset Trip Point Voltage, (-2.7A)
Reset Trip Point Voltage, (-2.7)
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
V
tPURST
Power-up Reset Time Out
100
200
400
ms
tRPD(6)
VCC Detect to Reset/Output
500
ns
tF(6)
VCC Fall Time
10
µs
tR(6)
VCC Rise Time
0.1
ns
VRVALID
Reset Valid VCC
1
V
NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
(5043)
tWDO
tRST
tWDO
tRST
RESET
(5045)
RESET/RESET Output Timing
SYMBOL
MIN
TYP
MAX
UNIT
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
200
600
1.4
300
800
2
ms
ms
sec
tCST
CS Pulse Width to Reset the Watchdog
400
tRST
Reset Time Out
100
tWDO
PARAMETER
FN8126 Rev 3.00
September 23, 2015
ns
200
400
ms
Page 16 of 21
X5043, X5045
VTRIP Programming Timing Diagram
VCC
(VTRIP)
VTRIP
tTSU
tTHD
VP
WP
tVPS
tVPH
tPCS
CS
tVPO
tRP
SCK
SI
06h
02h
01h or
03h
VTRIP Programming Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tVPS
VTRIP Program Enable Voltage Setup time
1
µs
tVPH
VTRIP Program Enable Voltage Hold time
1
µs
tPCS
VTRIP Programming CS inactive time
1
µs
tTSU
VTRIP Setup time
1
µs
tTHD
VTRIP Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tVPO
VTRIP Program Enable Voltage Off time (Between successive adjustments)
0
µs
tRP
VTRIP Program Recovery Period (Between successive adjustments)
10
ms
VP
Programming Voltage
15
18
V
VTRIP Programmed Voltage Range
1.7
4.75
V
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
-25
+25
mV
VTRAN
Vtv
10
ms
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8126 Rev 3.00
September 23, 2015
Page 17 of 21
X5043, X5045
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 23, 2015
FN8126.3
CHANGE
- Updated Ordering Information Table on page 3.
- Added Revision History.
- Added About Intersil Verbiage.
- Attached current POD.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2005-2015 All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8126 Rev 3.00
September 23, 2015
Page 18 of 21
X5043, X5045
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
FN8126 Rev 3.00
September 23, 2015
Page 19 of 21
X5043, X5045
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
6. Dimensioning and tolerancing per ANSI Y14.5M-1994.
7. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
8. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
9. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
10. Terminal numbers are shown for reference only.
11. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
12. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
13. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN8126 Rev 3.00
September 23, 2015
Page 20 of 21
X5043, X5045
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN8126 Rev 3.00
September 23, 2015
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
Page 21 of 21