X9260
®
Dual Supply/Low Power/256-Tap/SPI bus
Data Sheet
August 29, 2006
FN8170.3
DESCRIPTION
Dual Digitally-Controlled (XDCP™)
Potentiometers
The X9260 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 100Ω typical @ V+ = 5V,
V- = -5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position
on Power-up.
• Standby Current VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
400
μA
fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
5
mA
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC1
VCC supply current
(active)
ICC2
VCC supply current
(nonvolatile write)
ISB
VCC current (standby)
5
μA
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
ILI
Input leakage current
10
μA
VIN = VSS to VCC
ILO
Output leakage current
10
μA
VOUT = VSS to VCC
1
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
V
IOL = 3mA
VOH
Output HIGH voltage
VCC - 0.8
0.4
V
IOH = -1mA, VCC ≥ +3V
VOH
Output HIGH voltage
VCC - 0.4
V
IOH = -0.4mA, VCC ≤ +3V
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
COUT
(6)
CIN(6)
Test
Max.
Units
Test Conditions
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC
(6)
tPUR(7)
Parameter
VCC Power-up rate
Power-up to initiation of read operation
Min.
Max.
Units
0.2
50
V/ms
1
ms
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp rate spec is always in effect.
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are not 100% tested.
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EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
1462Ω
SPICE MACROMODEL
1382Ω
RTOTAL
SO pin
SO pin
2714Ω
CW
CL
1217Ω
100pF
RL
RH
100pF
CL
10pF
25pF
10pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Units
2
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle rime
tWH
SSI/SPI clock high rime
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
μs
tFI
SI, SCK, HOLD and CS input fall time
2
μs
tDIS
SO output disable time
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
100
ns
tFO
SO output fall time
100
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
10
ns
tCS
CS deselect time
2
μs
tWPASU
WP, A0 setup time
0
ns
tWPAH
WP, A0 hold time
0
ns
17
500
0
ns
250
ns
200
ns
0
ns
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X9260
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
High-voltage write cycle time (store instructions)
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max. Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
μs
tWRL
Wiper response time after instruction issued (all load instructions)
5
10
μs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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TIMING DIAGRAMS
Input Timing
tCS
CS
SCK
tSU
tH
...
tWH
tWL
...
MSB
SI
tLAG
tCYC
tLEAD
tRI
tFI
LSB
High Impedance
SO
Output Timing
CS
SCK
tV
...
MSB
SO
SI
...
tHO
tDIS
LSB
ADDR
Hold Timing
CS
tHSU
SCK
tHH
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
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XDCP Timing (for All Load Instructions)
CS
SCK
SI
...
tWRL
...
MSB
LSB
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
WP
tWPAH
A0
A1
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APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
THREE- TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Application Circuits
NONINVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERISIS
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
}
10kΩ
}
TL072
10kΩ
VO
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
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Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
R2
R1
VO
–
–
VS
+
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R2
}
VS
R1
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
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Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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