X9271TV14IT1

DATASHEET X9271 Single Supply/Low Power/256-Tap/SPI Bus Single, Digitally Controlled (XDCP™) Potentiometer The X9271 integrates a single, digitally controlled potentiometer (XDCP™) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented by using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile data registers that can be directly written to and read by the user. The contents of the WCR control the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FN8174 Rev 5.00 October 15, 2015 Features • 256 Resistor Taps • SPI Serial Interface for Write, Read, and Transfer Operations of Potentiometer • Wiper Resistance, 100Ω typical at VCC = 5V • 16 Nonvolatile Data Registers • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall; Loads Saved Wiper Position on Power-up • Standby Current VH, VL, and VW. 14. n = 0, 1, 2, …,255; m = 0, 1, 2, …., 254. FN8174 Rev 5.00 October 15, 2015 Page 11 of 19 X9271 D.C. Operating Characteristics Across the recommended operating conditions unless otherwise specified. LIMITS SYMBOL MIN (Note 17) PARAMETER TYP MAX (Note 17) UNITS 400 µA fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS 5 mA fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS TEST CONDITIONS ICC1 VCC Supply Current (Active) ICC2 VCC Supply Current (Nonvolatile Write) ISB VCC Current (Standby) 3 µA SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V ILI Input Leakage Current 10 µA VIN = VSS to VCC ILO Output Leakage Current 10 µA VOUT = VSS to VCC VIH Input HIGH Voltage VCC x 0.7 VCC + 1 V VIL Input LOW Voltage -1 VCC x 0.3 V VOL Output LOW Voltage 0.4 V IOL = 3mA VOH Output HIGH Voltage VCC - 0.8 V IOH = -1mA, VCC  +3V VOH Output HIGH Voltage VCC - 0.4 V IOH = -0.4mA, VCC  +3V 1 Endurance and Data Retention PARAMETER MIN. (Note 17) UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 Years Capacitance SYMBOL TEST MAX. (Note 17) UNITS TEST CONDITIONS 8 pF VOUT = 0V CIN/OUT (Note 15) Input / Output Capacitance (SI) COUT (Note 15) Output Capacitance (SO) 8 pF VOUT = 0V CIN (Note 15) Input Capacitance (A0, CS, WP, HOLD, and SCK) 6 pF VIN = 0V Power-Up Timing SYMBOL tr VCC (Note 15) PARAMETER VCC Power-up Rate MIN. (Note 17) MAX. (Note 17) UNITS 0.2 50 V/ms tPUR (Note 16) Power-up to Initiation of Read Operation 1 ms tPUW (Note 16) Power-up to Initiation of Write Operation 50 ms A.C. Test Conditions INPUT PULSE LEVELS Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 NOTES: 15. This parameter is not 100% tested. 16. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and are not 100% tested. 17. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN8174 Rev 5.00 October 15, 2015 Page 12 of 19 X9271 Equivalent A.C. Load Circuit 5V SPICE MACROMODEL 3V 1462Ω 1382 RTOTAL RH SO pin RL SO pin 2714 Ω 1217 100pF CW CL 100pF CL 10pF 25pF 10pF RW AC Timing SYMBOL PARAMETER MIN MAX UNITS 2.5 MHz fSCK SSI/SPI Clock Frequency tCYC SSI/SPI Clock Cycle Time 500 ns tWH SSI/SPI Clock High Time 200 ns tWL SSI/SPI Clock Low Time 200 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 2 µs tFI SI, SCK, HOLD and CS Input Fall Time 2 µs tDIS SO Output Disable Time 250 ns tV SO Output Valid Time 200 ns tHO SO Output Hold Time tRO SO Output Rise Time 100 ns tFO SO Output Fall Time 100 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 100 ns tHH HOLD Hold Time 100 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 10 ns tCS CS Deselect Time 2 µs tWPASU WP, A0 Setup Time 0 ns tWPAH WP, A0 Hold Time 0 ns 0 0 ns High-voltage Write Cycle Timing SYMBOL tWR PARAMETER High-voltage Write Cycle Time (Store Instructions) FN8174 Rev 5.00 October 15, 2015 TYP MAX UNITS 5 10 ms Page 13 of 19 X9271 XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO Wiper Response Time After Third (Last) Power Supply is Stable 5 10 µs tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 5 10 µs Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Timing Diagrams Input Timing tCS CS SCK tSU tH ... tWH tWL tRI tFI ... MSB SI tLAG tCYC tLEAD LSB High Impedance SO Output Timing CS SCK tV MSB SO SI tHO ... ... tDIS LSB ADDR FN8174 Rev 5.00 October 15, 2015 Page 14 of 19 X9271 Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD XDCP Timing (for All Load Instructions) CS SCK ... ... MSB SI tWRL LSB VWx SO High Impedance Write Protect and Device Address Pins Timing (Any Instruction) CS WP tWPASU tWPAH A0 A1 FN8174 Rev 5.00 October 15, 2015 Page 15 of 19 X9271 Applications information Basic Configurations of Electronic Potentiometers +VR VR RW I 3-terminal Potentiometer; Variable Voltage Divider 2-terminal Variable Resistor; Variable Current Application Circuits VS + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj FIGURE 7. NONINVERTING AMPLIFIER R1 R2 FIGURE 8. VOLTAGE REGULATOR VS VS – VO + 100kΩ – VO } TL072 } + R1 R2 10kΩ 10kΩ +12V 10kΩ -12V FIGURE 9. OFFSET VOLTAGE ADJUSTMENT FN8174 Rev 5.00 October 15, 2015 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) FIGURE 10. COMPARATOR WITH HYSTERESIS Page 16 of 19 X9271 Application Circuits (Continued) C VS R2 R1 R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10k R1 GO = 1 + R2/R1 fc = 1/(2RC) VO = G VS -1/2  G  +1/2 } VS R2 } FIGURE 11. ATTENUATOR R1 VO – – VS + FIGURE 12. FILTER R2 C1 VS + – – VO + R1 ZIN R3 VO = G VS G = - R2/R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FIGURE 13. INVERTING AMPLIFIER FIGURE 14. EQUIVALENT L-R CIRCUIT C R2 – + R1 – } RA + } RB Frequency  R1, R2, C Amplitude  RA, RB FIGURE 15. FUNCTION GENERATOR FN8174 Rev 5.00 October 15, 2015 Page 17 of 19 X9271 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 15, 2015 FN8174.5 CHANGE - Updated Ordering Information Table on page 2. - Added Revision History. - Added About Intersil Verbiage. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8174 Rev 5.00 October 15, 2015 Page 18 of 19 X9271 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN FN8174 Rev 5.00 October 15, 2015 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. Page 19 of 19