DATASHEET
X9313
FN8177
Rev 7.00
October 7, 2015
Digitally Controlled Potentiometer (XDCP™) Linear, 32 Taps, 3 Wire Interface,
Terminal Voltages ± VCC
The Intersil X9313 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
Features
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
• 32 wiper tap points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements
- Temperature compensated
- End-to-end resistance range ±20%
- Terminal voltages, -VCC to +VCC
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
• Control
• Solid-state potentiometer
• 3-wire serial interface
• Low power CMOS
- VCC = 3V or 5V
- Active current, 3mA max.
- Standby current, 500µA max.
• High reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• Parameter adjustments
• Signal processing
• RTOTAL values = 1k, 10k, 50k
• Packages
- 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP
• Pb-free available (RoHS compliant)
Block Diagram
DECODER
U/D
INC
CS
VCC (SUPPLY VOLTAGE)
CONTROL
AND
MEMORY
DEVICE SELECT
(CS)
RH/VH
31
30
29
RH/VH
UP/DOWN
(U/D)
INCREMENT
(INC)
5-BIT
UP/DOWN
COUNTER
5-BIT
NONVOLATILE
MEMORY
RW/VW
RL/VL
28
ONE OF
THIRTY-TWO
OUTPUTS
ACTIVE
AT A
TIME
TRANSFER
GATES
RESISTOR
ARRAY
2
VSS (GROUND)
GENERAL
VCC
VSS
STORE AND
RECALL
CONTROL
CIRCUITRY
1
0
RL/VL
RW/VW
DETAILED
FN8177 Rev 7.00
October 7, 2015
Page 1 of 12
X9313
Ordering Information
PART NUMBER
PART
MARKING
VCC RANGE
(V)
RTOTAL
(k)
TEMPERATURE
RANGE
(°C)
4.5 to 5.5
50
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
PACKAGE
PKG.
DWG. #
X9313UMIZ* (Note)
DDB
X9313USZ* (Note)
X9313U Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313USIZ* (Note)
X9313U ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9313WMZ* (Note)
DDF
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313WMIZ* (Note)
DDE
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313WPIZ
X9313WP ZI
-40 to +85
8 Ld PDIP*** (Pb-free)
MDP0031
X9313WSZ* (Note)
X9313W Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313WSIZ* (Note)
X9313WS ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9313ZMZ* (Note)
DDJ
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313ZMIZ* (Note)
DDH
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313ZSZ* (Note)
X9313 Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
10
1
X9313ZSIZ* (Note)
X9313ZS ZI
8 Ld SOIC (Pb-free)
M8.15
X9313UMZ* (Note)
DDC
3 to 5.5
50
-40 to +85
0 to +70
8 Ld MSOP
M8.118
X9313UMZ-3* (Note)
DDD
3 to 5.5
50
0 to +70
8 Ld MSOP
M8.118
X9313UMIZ-3* (Note)
13UEZ
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313USZ-3* (Note)
X9313U ZD
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313WMZ-3* (Note)
DDG
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9313WMIZ-3* (Note)
13WEZ
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313WSZ-3* (Note)
X9313W ZD
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313ZMZ-3* (Note)
DDK
X9313ZMIZ-3* (Note)
13ZEZ
X9313ZSZ-3* (Note)
X9313ZSIZ-3* (Note)
10
1
0 to +70
8 Ld MSOP (Pb-free)
M8.118
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9313Z ZD
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9313Z ZE
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Descriptions
Up/Down (U/D)
RH/VH and RL/VL
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
The high (RH/VH) and low (RL/VL) terminals of the X9313 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL/VL and RH/VH
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input and not
the voltage potential on the terminal.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the counter
in the direction indicated by the logic level on the U/D input.
RW/VW
RW/VW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 40 at VCC = 5V.
FN8177 Rev 7.00
October 7, 2015
Page 2 of 12
X9313
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
operation is complete, the X9313 will be placed in the low power
standby mode until the device is selected once again.
Pinouts
X9313
(8 LD PDIP, 8 LD SOIC)
TOP VIEW
INC
1
U/D
2
RH/VH
3
VSS
4
X9313
8
VCC
7
CS
6
RL/VL
5
RW/VW
X9313
(8 LD MSOP)
TOP VIEW
RH/VH
VSS
RW/VW
RL/VL
1
2
3
X9313
4
8
U/D
7
INC
6
VCC
5
CS
TABLE 1. PIN NAMES
SYMBOL
DESCRIPTION
RH/VH
High terminal
RW/VW
Wiper terminal
RL/VL
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
INC
Increment control input
CS
Chip Select control input
Principles of Operation
There are three sections of the X9313: the input control,
counter and decode section; the nonvolatile memory; and the
resistor array. The input control section operates just like an
up/down counter. The output of this counter is decoded to turn
on a single electronic switch connecting a point on the resistor
array to the wiper output. Under the proper conditions, the
contents of the counter can be stored in nonvolatile memory
and retained for future use. The resistor array is comprised of
31 individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the potential at that point to the wiper.
FN8177 Rev 7.00
October 7, 2015
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by a
significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled and
the wiper is set to the value last stored.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a seven bit counter.
The output of this counter is decoded to select one of thirty-two
wiper positions along the resistive array.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
The system may select the X9313, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new position
is reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until changed
by the system or until a power-up/down cycle recalled the
previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during system
operation, minor adjustments could be made. The adjustments
might be based on user preference, system parameter
changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
TABLE 2. MODE SELECTION
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position
X
X
Standby current
L
X
No store, return to standby
H
Page 3 of 12
X9313
TABLE 2. MODE SELECTION
CS
INC
U/D
MODE
L
H
Wiper up (not recommended)
L
L
Wiper down (not recommended)
Symbol Table
WAVEFORM
FN8177 Rev 7.00
October 7, 2015
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Page 4 of 12
X9313
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, and
VCC with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage on VH, VL, VW
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +7V
V = |VH - VL|:
X9313Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V
X9313W, X9313U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Temperature:
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC):
X9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V
Max Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4.4mA
Power rating:
RTOTAL 10k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW
RTOTAL 1k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Potentiometer Characteristics
Over recommended operating conditions, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
End-to-end Resistance Tolerance
MAX
UNIT
±20
%
VVH
VH Terminal Voltage
-VCC
+VCC
V
VVL
VL Terminal Voltage
-VCC
+VCC
V
RW
Wiper Resistance
100
IW
Wiper Current
±4.4
mA
Noise (Note 5)
IW = (VH - VL)/RTOTAL, VCC = 5V
Ref: 1kHz
Resolution
CH/CL/CW
(Note 5)
Absolute Linearity (Note 1)
RW(n)(actual) - RW(n)(expected)
Relative Linearity (Note 2)
RW(n+1) - (RW(n)+MI)
40
-120
dBV
3
%
±1
MI
(Note 3)
±0.2
MI
(Note 3)
RTOTAL Temperature Coefficient (Note 5)
±300
ppm/°C
Ratiometric Temperature Coefficient
(Note 5)
±20
ppm/°C
10/10/25
pF
Potentiometer Capacitances
See Circuit #3
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VW(n)(actual) - VW(n)(expected)) = ±1 MI maximum.
2. Relative linearity is a measure of the error in step size between taps = RW(n+1) - (RW(n) + MI) = ±0.2 MI.
3. 1 MI = minimum increment = RTOT/31.
FN8177 Rev 7.00
October 7, 2015
Page 5 of 12
X9313
DC Electrical Specifications
Over recommended operating conditions, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
VCC Active Current
CS = VIL, U/D = VIL or VIH and
INC = 0.42/2.4V @ max tCYC
Standby Supply Current
CS = VCC - 0.3V, U/D and INC = VSS or
VCC - 0.3V
ILI
CS, INC, U/D Input Leakage Current
VIN = VSS to VCC
VIH
CS, INC, U/D Input HIGH Current
VIL
CS, INC, U/D Input LOW Current
CIN
(Note 5)
CS, INC, U/D Input Capacitance
ISB
MIN
TYP
(Note 4)
MAX
UNIT
1
3
mA
200
500
µA
±10
µA
2
V
+0.8
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz
V
10
pF
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit
per register
Data retention
100
Years
VH/RH
VH/RH
RTOTAL
TEST POINT
RH
CW
CH
VS
TEST POINT
VW/RW
VL/RL
FIGURE 1. TEST CIRCUIT #1
FN8177 Rev 7.00
October 7, 2015
VL/RL
VW/RW
VW
FORCE
CURRENT
FIGURE 2. TEST CIRCUIT #2
CL
RL
10pF
25pF
10pF
RW
FIGURE 3. CIRCUIT #3 SPICE MACRO
MODEL
Page 6 of 12
X9313
AC Electrical Specifications
Over recommended operating conditions, unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TYP
(Note 4)
MIN
MAX
UNIT
tCI
CS to INC Setup
100
ns
tID
INC HIGH to U/D Change
100
ns
tDI
U/D to INC Setup
2.9
µs
tIL
INC LOW Period
1
µs
tIH
INC HIGH Period
1
µs
tIC
INC Inactive to CS Inactive
1
µs
tCPH
CS Deselect Time (STORE)
20
ms
tCPH
CS Deselect Time (NO STORE)
100
ns
INC to VW Change
tIW
tCYC
5
INC Cycle Time
tR, tF (Note 5)
tPU (Note 5)
2
µs
INC Input Rise and Fall Time
500
Power-up to Wiper Stable
tR VCC (Note 5)
tWR (Note 5)
µs
10
VCC Power-up Rate
µs
0.2
50
Store Cycle
µs
V/ms
10
ms
NOTES:
4. Typical values are for TA = +25°C and nominal supply voltage.
5. This parameter is not 100% tested.
1ms after VCC reaches its final value. The VCC ramp
specification is always in effect. In order to prevent unwanted
tap position changes, or an inadvertent store, bring the CS and
INC high before or concurrently with the VCC pin on power-up.
Power-Up and Power-Down Requirements
The recommended power-up sequence is to apply VCC/VSS
first, then the potentiometer voltages. During power-up, the
data sheet parameters for the DCP do not fully apply until
CS
tCYC
tCI
tIL
tIH
tCPH
tIC
90%
INC
90%
10%
tID
tDI
tF
tR
U/D
tIW
MI
(SEE NOTE)
VW
NOTE: MI IN THE AC TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN
THE WIPER POSITION.
FIGURE 4. AC TIMING DIAGRAM
FN8177 Rev 7.00
October 7, 2015
Page 7 of 12
X9313
Applications Information
Electronic digitally controlled potentiometers (XDCP) provide
three powerful application advantages:
1. The variability and reliability of a solid-state potentiometer.
2. The flexibility of computer-based digital controls.
3. The retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR
VR
VH
VW/RW
VL
I
THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
BUFFERED REFERENCE VOLTAGE
CASCADING TECHNIQUES
R1
+V
NONINVERTING AMPLIFIER
+5V
+V
VS
+V
+5V
VW
VREF
X
VW/RW
VOUT
–
VO
–
OP-07
+
LM308A
+
-5V
R2
+V
-5V
R1
VW
VOUT = VW/RW
(a)
(b)
VO = (1 + R2/R1)VS
VOLTAGE REGULATOR
R1
VIN
VO (REG)
317
COMPARATOR WITH HYSTERESIS
OFFSET VOLTAGE ADJUSTMENT
R2
VS
VS
LT311A
–
VO
+
10k
+12V
10k
}
10k
R2
}
TL072
Iadj
VO (REG) = 1.25V (1 + R2/R1) + IADJ R2
VO
+
100k
R1
–
R1
R2
VUL = [R1/(R1 + R2)] VO(max)
VLL = [R1/(R1 + R2)] VO(min)
-12V
(FOR ADDITIONAL CIRCUITS SEE AN115)
FN8177 Rev 7.00
October 7, 2015
Page 8 of 12
X9313
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
October 7, 2015
FN8177.7
CHANGE
Added Revision History beginning with Rev 7.
Added About Intersil Verbiage.
Updated Ordering Information on page 2.
DC Electrical Spec Table on page 6 - changed ICC for Parameter VCC Active Current to ISB
Updated POD M8.118 to most current revision with changes as follows:
Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
Updated to new intersil format by adding land pattern and moving dimensions
from table onto drawing.
Updated POD M8.15 to most current revision with changes as follows:
Changed Note 1 "1982" to "1994"
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Updated to new POD format by removing table and moving dimensions onto
drawing and adding land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN8177 Rev 7.00
October 7, 2015
Page 9 of 12
X9313
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN8177 Rev 7.00
October 7, 2015
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
Page 10 of 12
X9313
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN8177 Rev 7.00
October 7, 2015
Page 11 of 12
X9313
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8177 Rev 7.00
October 7, 2015
Page 12 of 12
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