DATASHEET
X9408
FN8191
Rev.4.00
January 15, 2009
Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled (XDCP™)
Potentiometers
Description
Features
The X9408 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
• Four Potentiometers in One Package
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
• 2-wire Serial Interface
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 64 Resistor Taps per Potentiometer
• Wiper Resistance, 40 Typical at 5V
• Four Nonvolatile Data Registers for Each Pot
• Nonvolatile Storage of Wiper Position
• Standby Current < 1µA max (Total Package)
• VCC = 2.7V to 5.5V Operation
V+ = 2.7V to 5.5V
V- = -2.7V to -5.5V
• 10k, 2.5k End to End Resistances
• High reliability
• Endurance–100,000 Data Changes Per Bit Per Register
• Register Data Retention–100 years
• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP Packages
• Pb-Free (RoHS Compliant)
Block Diagram
VCC
V+
VSS
V-
POT 0
R0
R2
WP
R1
R3
VH0/RH0
WIPER
COUNTER
REGISTER
(WCR)
VL0/RL0
A0
A1
A2
R2
R1
R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 2
INTERFACE
AND
CONTROL
CIRCUITRY
A3
VW2/RW2
8
VW1/RW1
DATA
R0
R2
FN8191 Rev.4.00
January 15, 2009
VH2/RH2
VL2/RL2
VW0/RW0
SCL
SDA
R0
R1
R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 1
VH1/RH1
VL1/RL1
VW3/RW3
R0
R2
R1
R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 3
VH3/RH3
VL3/RL3
Page 1 of 20
X9408
Ordering Information
PART NUMBER
POTENTIOMETER
ORGANIZATION
(k)
PART MARKING VCC LIMITS (V)
5 ±10%
2.5
TEMP RANGE
(°C)
PACKAGE
X9408YS24*
X9408YS
0 to +70
24 Ld SOIC (300 mil)
X9408YS24I*
X9408YS I
-40 to +85
24 Ld SOIC (300 mil)
X9408YV24*
X9408YV
0 to +70
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
X9408YV24Z* (Note)
X9408YV Z
0 to +70
X9408YV24I*
X9408YV I
-40 to +85
24 Ld TSSOP (4.4mm)
X9408YV24IZ* (Note)
X9408YV Z I
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-Free)
X9408WS24*
X9408WS
0 to +70
24 Ld SOIC (300 mil)
X9408WS24I*
X9408WS I
10
-40 to +85
24 Ld SOIC (300 mil)
X9408WV24*
X9408WV
0 to +70
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
X9408WV24Z* (Note)
X9408WV Z
0 to +70
X9408WV24I*
X9408WV I
-40 to +85
24 Ld TSSOP (4.4mm)
X9408WV24IZ* (Note)
X9408WV Z I
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-Free)
X9408YS24-2.7*
X9408YS F
0 to +70
24 Ld SOIC (300 mil)
X9408YS24I-2.7*
X9408YS G
-40 to +85
24 Ld SOIC (300 mil)
X9408YV24-2.7*
X9408YV F
0 to +70
X9408YV24Z-2.7* (Note)
X9408YV Z F
X9408YV24I-2.7*
X9408YV G
2.7 to 5.5
2.5
0 to +70
X9408YV24IZ-2.7T1 (Note) X9408YV Z G
X9408WS24-2.7*
X9408WS F
X9408WS24I-2.7*
10
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-Free)
-40 to +85
24 Ld TSSOP (4.4mm)
-40 to +85
24 Ld TSSOP (4.4mm) Tape and Reel
(Pb-Free)
0 to +70
24 Ld SOIC (300 mil)
X9408WS G
-40 to +85
24 Ld SOIC (300 mil)
X9408WS24IZ-2.7* (Note)
X9408WS Z G
-40 to +85
24 Ld SOIC (300 mil) (Pb-Free)
X9408WV24-2.7*
X9408WV F
0 to +70
24 Ld TSSOP (4.4mm)
X9408WV24Z-2.7* (Note)
X9408WV Z F
0 to +70
24 Ld TSSOP (4.4mm) (Pb-Free)
X9408WV24I-2.7*
X9408WV G
-40 to +85
24 Ld TSSOP (4.4mm)
X9408WV24IZ-2.7* (Note)
X9408WV Z G
-40 to +85
24 Ld TSSOP (4.4mm) (Pb-Free)
*Add "T1" suffix for tape and reel. **Add "T1" suffix for tape and reel.Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8191 Rev.4.00
January 15, 2009
Page 2 of 20
X9408
Pin Descriptions
HARDWARE WRITE PROTECT INPUT (WP)
Host Interface Pins
The WP pin when low prevents nonvolatile writes to the Data
Registers.
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the X9408.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A0 - A3)
The address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9408. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3)
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW/RW (VW0/RW0 – VW3/RW3)
ANALOG SUPPLIES V+, VThe Analog Supplies V+, V- are the supply voltages for the
XDCP analog section.
Pin Assignments
SYMBOL
DESCRIPTION
SCL
Serial Clock
SDA
Serial Data
A0-A3
Device Address
VH0/RH0 - VH3/RH3, VL0/RL0 Potentiometer Pins
(terminal equivalent)
- VL3/RL3
VW0/RW0 - VW3/RW3
Potentiometer Pins
(wiper equivalent)
WP
Hardware Write Protection
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Pinouts
X9408
(24 LD TSSOP)
TOP VIEW
X9408
(24 LD DIP/SOIC)
TOP VIEW
VCC 1
24 V+
SDA 1
24 WP
VL0/RL0 2
23 VL3/RL3
A1 2
VH0/RH0 3
22 VH3/RH3
VL1/RL1 3
22 VW0/RW0
21 VW3/R/RH1
VH1/RH1 4
21 VH0/RH0
20 VL0/RL0
VW0/RW0 4
A2 5
20 A0
VW1/RW1 5
WP 6
19 NC
VSS 6
SDA 7
18 A3
A1 8
17 SCL
V-
7
23 A2
19 VCC
18 V+
VW2/RW2 8
17 VL3/RL3
VL1/RL1 9
16 VL2/RL2
VH2/RH2 9
16 VH3/RH3
VH1/RH1 10
15 VH2/RH2
VL2/RL2 10
15 VW3/RW3
VW1/RW1 11
14 VW2/RW2
VSS 12
FN8191 Rev.4.00
January 15, 2009
13 V-
SCL 11
14 A0
A3 12
13 NC
Page 3 of 20
X9408
Principals of Operation
The X9408 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and
the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9408 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9408 will be considered a slave
device in all applications.
time. These switches are controlled by the Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier (refer to Figure 1
below). For the X9408 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (tLOW). SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
0
1
0
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting eight bits. The master generates
a ninth clock cycle and during this period the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
eight bits of data.
The X9408 will respond with an acknowledge after recognition
of a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9408 will respond with a final
acknowledge.
A3
A2
A1
A0
DEVICE ADDRESS
Start Condition
All commands to the X9408 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH (tHIGH). The X9408 continuously monitors the SDA
and SCL lines for the start condition and will not respond to any
command until this condition is met.
1
FIGURE 1. SLAVE ADDRESS
The next four bits of the slave address are the device address.
The physical device address is defined by the state of the A0 A3 inputs. The X9408 compares the serial data stream with the
address input state; a successful compare of all four address
bits is required for the X9408 to respond with an acknowledge.
The A0 - A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
Acknowledge Polling
The disabling of the inputs, during the internal Nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9408
initiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition followed
by the device slave address. If the X9408 is still busy with the
write operation no ACK will be returned. If the X9408 has
completed the write operation an ACK will be returned and the
master can then proceed with the next operation.
Array Description
The X9408 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (RH and
RLinputs).
At both ends of each array and between each resistor segment
is a CMOS switch connected to the wiper (RW) output. Within
each individual array only one switch may be turned on at a
FN8191 Rev.4.00
January 15, 2009
Page 4 of 20
X9408
Flow 1. ACK Polling Sequence
REGISTER
SELECT
NON-VOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
I3
I2
I1
I0
R1
R0
P0
WIPER COUNTER
REGISTER SELECT
INSTRUCTIONS
ISSUE
START
P1
FIGURE 2. INSTRUCTION BYTE FORMAT
ISSUE SLAVE
ADDRESS
The four high order bits define the instruction. The next two bits
(R1 and R0) select one of the four registers that is to be acted
upon when a register oriented instruction is issued. The last
bits (P1, P0) select which one of the four potentiometers is to
be affected by the instruction.
ISSUE STOP
ACK
RETURNED?
NO
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data between
the Wiper Counter Register and one of the Data Registers. A
transfer from a Data Register to a Wiper Counter Register is
essentially a write to a static RAM. The response of the wiper
to this action will be delayed tWRL. A transfer from the Wiper
Counter Register (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers; or it may
occur globally, wherein the transfer occurs between all of the
potentiometers and one of their associated registers.
YES
NO
FURTHER
OPERATION?
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9408; either between the host and one of the data registers or
directly between the host and the Wiper Counter Register.
These instructions are: Read Wiper Counter Register (read the
current wiper position of the selected pot), Write Wiper Counter
Register (change current wiper position of the selected pot),
Read Data Register (read the contents of the selected
nonvolatile register) and Write Data Register (write a new
value to the selected Data Register). The sequence of
operations is shown in Figure 4.
Instruction Structure
The next byte sent to the X9408 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the two pots
and when applicable they point to one of four associated
registers. The format is shown in Figure 2.
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1
P0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
FN8191 Rev.4.00
January 15, 2009
Page 5 of 20
X9408
move one resistor segment towards the RH terminal. Similarly,
for each SCL clock pulse while SDA is LOW, the selected
wiper will move one resistor segment towards the RL terminal.
A detailed illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9408 has
responded with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL
clock pulse (tHIGH) while SDA is HIGH, the selected wiper will
TABLE 1. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3
I2
I1
I0
R1
R0
P1
P0
OPERATION
Read Wiper CounterRegister
1
0
0
1
0
0
P1
P0
Read the contents of the Wiper Counter Register pointed to by
P1 - P0
Write Wiper CounterRegister
1
0
1
0
0
0
P1
P0
Write new value to the Wiper Counter Register pointed to by P1 - P0
Read Data Register
1
0
1
1
R1
R0
P1
P0
Read the contents of the Data Register pointed to by P1 - P0 and
R1 - R0
Write Data Register
1
1
0
0
R1
R0
P1
P0
Write new value to the Data Register pointed to by
P1 - P0 and R1 - R0
XFR Data Register to Wiper
Counter Register
1
1
0
1
R1
R0
P1
P0
Transfer the contents of the Data Register pointed to by P1 - P0
and R1 - R0 to its associated Wiper Counter Register
XFR Wiper Counter Register
to Data Register
1
1
1
0
R1
R0
P1
P0
Transfer the contents of the Wiper Counter Register pointed to by
P1 - P0 to the Data Register pointed to by R1 - R0
Global XFR Data Registers
to Wiper Counter Registers
0
0
0
1
R1
R0
0
0
Transfer the contents of the Data Registers pointed to by R1 - R0
of all four pots to their respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
1
0
0
0
R1
R0
0
0
Transfer the contents of both Wiper Counter Registers to their
respective Data Registers pointed to by
R1 - R0 of all four pots
Increment/Decrement Wiper
Counter Register
0
0
1
0
0
0
P1
P0
A0
A
C
K
Enable Increment/decrement of the Wiper Counter Register
pointed to by P1 - P0
NOTE: (7)1/0 = data is one or zero
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
I3
I2
I1
I0
R1
R0
P1 P0
A
C
K
0
0
D5 D4
D3
D2
D1 D0
A
C
K
S
T
O
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1
P0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
FN8191 Rev.4.00
January 15, 2009
Page 6 of 20
X9408
INC/DEC
CMD
ISSUED
tWRID
SCL
SDA
VOLTAGE OUT
VW/RW
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
FIGURE 7. ACKNOWLEDGE RESPNSE FROM RECEIVER
FN8191 Rev.4.00
January 15, 2009
Page 7 of 20
X9408
SERIAL DATA PATH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
REGISTER 1
8
REGISTER 2
PARALLEL
BUS
INPUT
6
WIPER
COUNTER
REGISTER
(WCR)
REGISTER 3
C
O
U
N
T
E
R
D
E
C
O
D
E
INC/DEC
LOGIC
IF WCR = 00[H] THEN VW/RW = VL/RL
IF WCR = 3F[H] THEN VW/RW = VH/RH
VH/RH
UP/DN
UP/DN
MODIFIED SCL
VL/RL
CLK
VW/RW
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM
Detailed Operation
All XDCP potentiometers share the serial interface and share a
common architecture. Each potentiometer has a Wiper
Counter Register and four Data Registers. A detailed
discussion of the register organization and array operation
follows.
Wiper Counter Register
The X9408 contains four Wiper Counter Registers, one for
each XDCP potentiometer. The Wiper Counter Register can be
envisioned as a 6-bit parallel and serial load counter with its
outputs decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in four
ways: it may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four associated
data registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the Increment/
Decrement instruction. Finally, it is loaded with the contents of
its data register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are lost
when the X9408 is powered-down. Although the register is
automatically loaded with the value in R0 upon power-up, it
should be noted this may be different from the value present at
power-down.
transferred between any of the four Data Registers and the
WCR. It should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple settings
for the potentiometer, these registers can be used as regular
memory locations that could possibly store system parameters
or user preference data.
Register Descriptions
TABLE 2. DATE REGISTERS, (6-BIT), NONVOLATILE
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
(MSB)
(LSB)
Four 6-bit Data Registers for each XDCP. (sixteen 6-bit
registers in total). {D5~D0}: These bits are for general purpose
not volatile data storage or for storage of up to four different
wiper values. The contents of Data Register 0 are
automatically moved to the wiper counter register on power-up.
Data Registers
Each potentiometer has four nonvolatile Data Registers. These
can be read or written directly by the host and data can be
FN8191 Rev.4.00
January 15, 2009
Page 8 of 20
X9408
TABLE 3.
One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit
registers in total.)
WIPER COUNTER REGISTER, (6-BIT), VOLATILE
WP5
WP4
WP3
WP2
WP1
WP0
V
V
V
V
V
V
(MSB)
{D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is loaded on
power-up by the value in Data Register 0. The contents of the
WCR can be loaded from any of the other Data Register or
directly. The contents of the WCR can be saved in a DR.
(LSB)
Instruction Format
NOTES:
1. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
2. “A3 ~ A0”: stands for the device addresses sent by the master.
3. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
4. “I”: stands for the increment operation, SDA held high during active
SCL phase (high).
5. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
0
0
WCR
ADDRESSES
1
0
0
P1
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
A
C
K
P0
0
0
WP WP WP WP WP WP
5
4
3
2
1
0
M
A
C
K
S
T
O
P
S
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
1
DEVICE
ADDRESSES
A3
A2
A1
A0
S
A
C
K
INSTRUCTION
OPCODE
1
0
1
WCR
ADDRESSES
0
0
0
P1
WIPER POSITION
(SENT BY MASTER ON SDA)
S
A
C
K
P0
0
0
W
P5
W
P4
W
P3
W
P2
W
P1
W
P0
Read Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3 A2 A1 A0
S
A
C
K
INSTRUCTION
OPCODE
1
0
1
1
DR AND WCR
ADDRESSES
R1
R0
P1
P0
S
A
C
K
WIPER POSITION/DATA
(SENT BY SLAVE ON SDA)
0
0
W W W W W W
P5 P4 P3 P2 P1 P0
M
A
C
K
S
T
O
P
Write Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
1
DEVICE
ADDRESSES
A3 A2 A1 A0
S
A
C
K
INSTRUCTION
OPCODE
1
1
0
0
DR AND WCR
ADDRESSES
R1 R0 P1 P0
WIPER POSITION/DATA
(SENT BY MASTER ON SDA)
S
A
C
K
0
0
W W W W W W
P5 P4 P3 P2 P1 P0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
FN8191 Rev.4.00
January 15, 2009
0
DEVICE
ADDRESSES
1
A3
A2
A1
A0
S
A
C
K
INSTRUCTION
OPCODE
1
1
0
DR AND WCR
ADDRESSES
1
R1
R0
P1
P0
S
A
C
K
Page 9 of 20
S
T
O
P
X9408
Write Wiper Counter Register (WCR) to Data Register (DR)
DEVICE TYPE
IDENTIFIER
S
T
A
R
T
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
1
1
DR AND WCR
ADDRESSES
0
R1
R0
P1
S
T
O
P
S
A
C
K
P0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
DEVICE TYPE
IDENTIFIER
S
T
A
R
T
0
1
0
1
DEVICE
ADDRESSES
A3
A2
A1
A0
INSTRUCTION
OPCODE
S
A
C
K
0
0
1
WCR
ADDRESSES
0
0
0
P1
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
S
A
C
K
P0
I/D I/D
.
.
.
.
I/D
I/D
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
A0
INSTRUCTION
OPCODE
S
A
C
K
0
0
0
DR
ADDRESSES
1
R1
R0
0
S
T
O
P
S
A
C
K
0
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
DEVICE TYPE
IDENTIFIER
0
1
0
1
DEVICE
ADDRESSES
A3 A2 A1 A0
S
A
C
K
Symbol Table
WAVEFORM
1
0
0
DR
ADDRESSES
0
R1 R0
0
0
S
T
O
P
S
A
C
K
HIGH-VOLTAGE
WRITE CYCLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LO W TO
HIGH
WILL CHANGE
FROM LO
W TO
HIGH
MAY CHANGE
FROM HIGH TO
LOW
WILL CHANGE
FROM HIGH TO
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
FN8191 Rev.4.00
January 15, 2009
INSTRUCTION
OPCODE
120
RMIN =
100
RESISTANCE ()
S
T
A
R
T
80
RMAX =
VCC MAX
IOL MIN
=1.8k
tR
CBUS
MAX.
RESISTANCE
60
40
20
0
Min.
Resistance
0
20
40
60
80
100 120
BUS CAPACITANCE (pF)
Page 10 of 20
S
T
O
P
X9408
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC Limits)
X9408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9408-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Voltage on SDA, SCL any address input
with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage on V+ (Referenced to VSS). . . . . . . . . . . . . . . . . . . . . . .10V
Voltage on V- (Referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . -10V
(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . . . . . . . . . . . . . . V- to V+
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
(Over recommended operating conditions unless otherwise stated.)
Analog Specifications
LIMITS
SYMBOL
RTOTAL
RW
VV+
VV-
VTERM
CH/CL/CW
IAL
PARAMETER
TEST CONDITION
End to end resistance tolerance
MIN
(Note 6)
TYP
(Note 4)
-20
MAX
(Note 6)
UNIT
+20
%
50
mW
Power rating
+25°C, each pot
Wiper resistance
IW = (VH - VL)/RTOTAL
@ V+, V- = ±3V
150
250
IW = (VH - VL)/RTOTAL
@ V+, V- = ±5V
40
100
V
Voltage on V+ pin
Voltage on V- pin
X9408
+4.5
+5.5
X9408-2.7
+2.7
+5.5
X9408
-5.5
-4.5
X9408-2.7
-5.5
-2.7
V-
V+
Voltage on any VH/RH, VL/RL or
VW/RW pin
V
V
Noise
Ref: 1kHz
-120
dBV
Resolution
(Note 4)
1.6
%
Absolute linearity (Note 1)
V(Vwn/Rwn)(actual) V(Vwn/Rwn)(expected) (Note 4)
-1
+1
MI
(Note 3)
Relative linearity (Note 2)
V(Vw(n+1)/Rw(n+1)) [V(Vw(n)/Rw(n)) + MI] (Note 4)
-0.2
+0.2
MI
(Note 3)
Temperature coefficient of RTOTAL
(Note 4)
300
ppm/°C
Ratiometric Temperature Coefficient
(Note 4)
20
ppm/°C
Potentiometer Capacitances
See Macro model
10/10/25
pF
VH/RH, VL/RL, VW/RW Leakage
Current
VIN = V- to V+. Device is in Standby mode.
FN8191 Rev.4.00
January 15, 2009
0.1
10
µA
Page 11 of 20
X9408
DC Electrical Specifications
(Over recommended operating conditions unless otherwise stated.)
LIMITS
SYMBOL
PARAMETER
MIN
(Note 6)
TEST CONDITIONS
TYP
(Note 4)
MAX
(Note 6)
UNIT
ICC1
VCC supply current (nonvolatile write)
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
5
mA
ICC2
VCC supply current (move wiper, write,
read)
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
250
µA
ISB
VCC current (standby)
SCL = SDA = VCC, Addr. = VSS
3
µA
ILI
Input leakage current
10
µA
ILO
Output leakage current
10
µA
VIH
Input HIGH voltage
VCC x 0.7
VCC +0.5
V
VIL
Input LOW voltage
–0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
3. MI = RTOT/63 or [V(VH/RH) - V(VL/RL)]/63, single pot
ENDURANCE AND DATA RETENTION
PARAMETER
MIN
Minimum endurance
100,000
Data retention
100
UNIT
Data changes per bit per register
years
CAPACITANCE
SYMBOL
TEST
TEST CONDITION
TYP
(Note 4)
UNIT
CI/O (Note 4)
Input/output capacitance (SDA)
VI/O = 0V
8
pF
CIN (Note 4)
Input capacitance (A0, A1, A2, A3, and SCL)
VIN = 0V
6
pF
POWER-UP TIMING
SYMBOL
PARAMETER
MIN
(Note 6)
MAX
(Note 6)
UNIT
tPUR (Note 5)
Power-up to initiation of read operation
1
ms
tPUW (Note 5)
Power-up to initiation of write operation
5
ms
tRVCC (Note 6)
VCC Power-up Ramp
50
V/msec
0.2
NOTES:
4. Limits should be considered typical and are not production tested.
5. tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN8191 Rev.4.00
January 15, 2009
Page 12 of 20
X9408
Power-up Requirements
A.C. Test Conditions
(Power-up sequencing can affect correct recall of the wiper
registers).
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
The preferred power-on sequence is as follows: First V-, then
VCC and V+, and then the potentiometer pins, VH/RH, VL/RL,
and VW/RW. Voltage should not be applied to the
potentiometer pins before V+ or V- is applied. The VCC ramp
rate specification should be met, and any glitches or slope
changes in the VCC line should be held to > R2
FUNCTION GENERATOR
C
R2
–
R1
–
+
+
} RA
} RB
FREQUENCY µR1, R2, C
AMPLITUDE µRA, RB
FN8191 Rev.4.00
January 15, 2009
Page 18 of 20
X9408
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
MILLIMETERS
(N/2)+1
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN8191 Rev.4.00
January 15, 2009
Page 19 of 20
X9408
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
B S
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MILLIMETERS
24
0°
24
8°
0°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
7
8°
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
© Copyright Intersil Americas LLC 2005-2009. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8191 Rev.4.00
January 15, 2009
Page 20 of 20
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