X9511WSI

X9511 ® Single Push Button Controlled Potentiometer (XDCP™) Data Sheet February 2, 2007 FN8205.3 DESCRIPTION Linear, 32 Taps, Push Button Controlled, Terminal Voltage ±5V The Intersil X9511 is a push button controlled potentiometer that is ideal for push button controlled resistance trimming. FEATURES • Push button controlled • Low power CMOS —Active current, 3mA max —Standby current, 100µA typical • 31 resistive elements —Temperature compensated —±20% end to end resistance range —-5V to +5V range • 32 wiper tap points —Wiper positioned via two push button inputs —Slow and fast scan modes —AUTOSTORE® option —Manual store option —Wiper position stored in nonvolatile memory and recalled on power-up • 100 year wiper position data retention • X9511W = 10kΩ • Packages —8 Ld PDIP —8 Ld SOIC • Pb-free plus anneal available (RoHS compliant) The X9511 is a resistor array composed of 31 resistive elements. Between each element and at either end are tap points accessible to the wiper element. The position of the wiper element is controlled by the PU and PD inputs. The position of the wiper can be automatically stored in E2 memory and then be recalled upon a subsequent power-on operation. The resolution of the X9511 is equal to the maximum resistance value divided by 31. As an example, for the X9511W (10kΩ) each tap point represents 323Ω. All Intersil nonvolatile products are designed and tested for applications requiring extended endurance and data retention. ORDERING INFORMATION PART NUMBER PART MARKING RTOTAL (kΩ) TEMPERATURE RANGE (°C) 10 0 to +70 8 Ld PDIP 8 Ld PDIP*** (Pb-free) MDP0031 PACKAGE PKG. DWG. # X9511WP X9511WP MDP0031 X9511WPZ (Note) X9511WP Z 0 to +70 X9511WPI X9511WP I -40 to +85 8 Ld PDIP X9511WPIZ (Note) X9511WP Z I -40 to +85 8 Ld PDIP*** (Pb-free) MDP0031 X9511WS** X9511W 0 to +70 8 Ld SOIC MDP0027 X9511WSZ*, **(Note) X9511W Z 0 to +70 8 Ld SOIC (Pb-free) MDP0027 X9511WSI*, ** X9511W I -40 to +85 8 Ld SOIC MDP0027 X9511WSIZ*, ** (Note) X9511W Z I -40 to +85 8 Ld SOIC (Pb-free) MDP0027 MDP0031 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel. ***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9511 BLOCK DIAGRAM PU PD 5-BIT UP/DOWN COUNTER VH 31 30 29 5-BIT EEPROM MEMORY ONE OF 28 THIRTY-TWO DECODER TRANSFER GATES RESISTOR ARRAY 2 ASE STORE AND RECALL CONTROL CIRCUITRY 1 0 VL VW 2 FN8205.3 February 2, 2007 X9511 PIN NAMES PIN DESCRIPTIONS SYMBOL VH/RH and VL/RL The high (VH/RH) and low (VL/RL) terminals of the X9511 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is 5V and the maximum is +5V. It should be noted that the terminology of VL/RL and VH/RH are in reference to the relative position of the terminal in relation to wiper movement direction selected by the PU and PD inputs, and not the voltage potential on the terminal. VH/RH High Terminal VW/RW Wiper Terminal VL/RL The debounced PU input is for incrementing the wiper position. An on-chip pull-up holds the PU input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent higher tap position. PD The debounced PD input is for decrementing the wiper position. An on-chip pull-up holds the PD input HIGH. A switch closure to ground or a LOW logic level will, after a debounce time, move the wiper to the next adjacent lower tap position. ASE The debounced ASE (AUTOSTORE enable) pin can be in one of two states: VIL - AUTOSTORE is enabled. When VCC powers down, an automatic store cycle takes place. VIH - AUTOSTORE is disabled. A LOW to HIGH will initiate a manual store operation. This is for the user who wishes to connect a push button switch to this pin. For every valid push, the X9511 will store the current wiper position to the EEPROM. PIN CONFIGURATION DIP/SOIC PU 1 8 VCC PD 2 7 ASE VH 3 6 VL VSS 4 5 VW X9511 3 Low Terminal VSS Ground VCC Supply Voltage PU Push Up Input PD Push Down Input ASE PU DESCRIPTION AUTOSTORE Enable Input DEVICE OPERATION There are three sections of the X9511: the input control, counter and decode section; the EEPROM memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch, connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in EEPROM memory and retained for future use. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The X9511 is designed to interface directly to two push button switches for effectively moving the wiper up or down. The PU and PD inputs increment or decrement a 5-bit counter respectively. The output of this counter is decoded to select one of the thirty-two wiper positions along the resistive array. The wiper increment input, PU and the wiper decrement input, PD are both connected to an internal pull-up so that they normally remain HIGH. When pulled LOW by an external push button switch or a logic LOW level input, the wiper will be switched to the next adjacent tap position. Internal debounce circuitry prevents inadvertent switching of the wiper position if PU or PD remain LOW for less than 40ms, typical. Each of the buttons can be pushed either once for a single increment/decrement or continuously for a multiple increments/decrements. The number of increments/decrements of the wiper position depend on how long the button is being pushed. When making a continuous push, after the first second, the increment/decrement speed increases. For the first second the device will be in the slow scan mode. Then if the button is held for longer than 1 second the device will go into the fast scan mode. As soon as the button is released the X9511 will return to a standby condition. FN8205.3 February 2, 2007 X9511 The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. Manual (Push Button) Store AUTOSTORE RTOTAL with VCC Removed The value of the counter is stored in EEPROM memory whenever the chip senses a power-down of VCC while ASE is enabled (held LOW). When power is restored, the content of the memory is recalled and the counter reset to the last value stored. The end to end resistance of the array will fluctuate once VCC is removed. When ASE is not enabled (held HIGH) a push button switch may be used to pull ASE LOW and released to perform a manual store of the wiper position. If AUTOSTORE is to be implemented, ASE is typically hard wired to VSS. If ASE is held HIGH during powerup and then taken LOW, the wiper will not respond to the PU or PD inputs until ASE is brought HIGH and held HIGH. VCC VCC 3.3µF 8 1 2kΩ 2 7 VCC VH PU VW PD VL ASE 3 5 6 VSS FIGURE 1. TYPICAL CIRCUIT WITH ASE STORE CONTROLLED BY PUSH BUTTON SWITCH 4 8 1 VCC VSS PU VH 2 PD 7 VW ASE VL 4 3 5 6 FIGURE 2. TYPICAL CIRCUIT WITH ASE STORE PIN USED IN AUTOSTORE MODE FN8205.3 February 2, 2007 X9511 ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature.......................... -65°C to +150°C Voltage on PU, PD, and VCC with respect to VSS ................................. -1V to +7V Voltage on VH and VL referenced to VSS ................................... -8V to +8V ΔV = |VH - VL| X9511W ............................................................. 10V Lead temperature (soldering 10 seconds) ....... +300°C Wiper current ........................................................... ±1mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) .................... 2.5kV Machine Model (Per EIAJ ED-4701 Method C-111)...................... 250V ANALOG CHARACTERISTICS Linearity Absolute linearity(1) ..........................................±1.0 MI(2) Relative linearity(3) ...........................................±0.2 MI(2) COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Coefficient -40°C to +85°C X9511W ......................................+300 ppm/°C Typical Ratiometric temperature coefficient ................±20 ppm Wiper Adjustability Electrical Characteristics End-to-end resistance tolerance ...........................±20% Power rating at +25°C X9511W ......................................................... 10mW Wiper current .................................................±1mA Max. Typical wiper resistance .......................................40Ω Typical noise..............................< -120dB/√Hz Ref: 1V Resolution Resistance ............................................................. 3% Unlimited wiper adjustment ....... (Non-Store operation) Wiper position store operations.......................100,000 data changes Physical Characteristics Marking Includes Manufacturer’s Trademark Resistance Value or Code Date Code Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [VW(n) - (n*MI + VW(0))]/MI = ±1 MI Maximum. (2) 1 Ml = Minimum Increment = RTOT/31 for resistor mode or 1MI = [VW(31) - VW(0)]/31 for voltage divider mode. (3) Relative linearity is a measure of the error in step size between taps = (VW(n+1) - VW(n) ] )/MI - 1= ±0.2 MI SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 5 FN8205.3 February 2, 2007 X9511 RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0×C -40×C Max. Supply Voltage X9511 +70°C +85°C Limits 5V ± 10% D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol Min. Typ.(4) Parameter ICC VCC active current ISB Standby supply current ILI PU, PD, ASE input leakage current VIH PU, PD, ASE input HIGH voltage VlL PU, PD, ASE input LOW voltage RW Wiper resistance VVH VH terminal voltage -5 VVL VL terminal voltage -5 CIN(5) Max. Unit Test Conditions 1 3 mA PU or PD held at VIL the other at VIH 100 500 µA PU = PD = VIH 10 µA VIN = VSS to VCC 2 V 40 ASE, PU, PD input capacitance 0.8 V 100 W +5 V +5 10 Wiper Current VCC/RTOT V pF VCC = 5V, VIN = 0V, TA = +25°C, f = 1MHz A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol tGAP tDB Parameter Time between two separate push button events Min. Typ.(4) Max. 50 Debounce time Unit µs 30 40 ms tS SLOW After debounce to wiper change on a slow mode 100 250 375 ms tS FAST Wiper change on a fast mode 25 50 90 ms 500 µs 50 V/ms tPU Power-up to wiper stable tR VCC tASTO(5) VASTH (5) VASEND(5) VCC power-up rate AUTOSTORE cycle time 0.2 2 ms AUTOSTORE threshold voltage 4 V AUTOSTORE cycle end voltage 3.5 V POWER-UP AND POWER-DOWN REQUIREMENTS The are no restrictions on the sequencing of VCC and the voltage applied to the potentiometer pins during power-up or power-down conditions. During power-up, the data sheet parameters for the DCP do not fully apply until 1ms after VCC reaches its final value. The VCC ramp rate spec is always in effect. 6 FN8205.3 February 2, 2007 X9511 AUTOSTORE Cycle Timing Diagram VCC 5 VASTH VOLTS (V) AUTOS CYCLE IN PROGRESS VASEND tASTO STORE TIME TIME (ms) Notes: VASTH - AUTOSTORE threshold voltage VASEND - AUTOSTORE cycle end voltage tASTO - AUTOSTORE cycle time (4) Typical values are for TA = +25°C and nominal supply voltage. (5) This parameter is periodically sampled and not 100% tested. Slow Mode Timing tDB tGAP PU MI(1) VW Note: (1) MI in the A.C. timing diagram refers to the minimum incremental change in the wiper voltage. Fast Mode Timing tDB PU tS FAST tS SLOW VW MI(1) 1 Second Note: (1) MI in the A.C. timing diagram refers to the minimum incremental change in the wiper voltage. 7 FN8205.3 February 2, 2007 X9511 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 8 FN8205.3 February 2, 2007 X9511 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN8205.3 February 2, 2007