RF2460_06

RF2460 0 RoHS Compliant & Pb-Free Product Typical Applications • CDMA PCS Handsets • GPS Receiver • W-CDMA Handsets Product Description The RF2460 is a receiver front-end designed for the receive section of PCS CDMA and W-CDMA applications. It is designed to amplify and downconvert RF signals while providing 29dB of stepped gain control range and features digital control of LNA gain, mixer gain, and power down mode. A further feature of the chip is adjustable IIP3 of the LNA and mixer using an off-chip current setting resistor. Noise Figure, IP3, and other specs are designed to be compatible with the IS-98B for CDMA PCS communications. The IC is manufactured on an advanced Silicon Germanium Bi-CMOS process and is assembled in a 20-pin, QFN package with an exposed die flag. PCS CDMA LOW NOISE AMPLIFIER/MIXER 1500MHz TO 2200MHz DOWNCONVERTER • General Purpose Downconverter • Commercial and Consumer Systems • Portable Battery-Powered Equipment 0.15 C A -A- 0.05 C 4.00 2 PLCS 1.00 0.90 2 PLCS 0.05 0.15 C B 3.75 4.00 Dimensions in mm. 12° MAX 0.15 C 2 PLCS -B- -C- 3.75 0.15 C 2 PLCS Note orientation of package. 0.10 M C A B 0.20 0.60 0.24 TYP 2 0.65 0.30 4 PLCS NOTES: 1 Shaded lead is Pin 1. Dimension applies to plated terminal: 2 to be measured between 0.02 mm and 0.25 mm from terminal end. 2.10 SQ. 0.75 0.50 0.50 0.23 0.13 4 PLCS Optimum Technology Matching® Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: QFN, 20-Pin, 4x4 Features • Complete Receiver Front-End • Stepped LNA/Mixer Gain Control • Adjustable LNA/Mixer Bias Current • 24dB Gain and 2.2dB Noise Figure at LNA GAIN 17 * 20 19 18 16 MIX GAIN * LNA IN NC NC ENABLE VCC1 VCC2 LO IN NC 1 2 3 4 5 * 15 14 13 12 11 6 NC 7 IF+ 8 NC 9 IF10 NC * LNA OUT ISET1 ISET2 MIX IN LNA2 E Maximum Cascade Gain Ordering Information RF2460 MPCS CDMA Low Noise Amplifier/Mixer 1500MHz to 2200MHz Downconverter RF2460PCBA-41X Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com * Represents "GND". Functional Block Diagram Rev B5 060921 8-81 RF2460 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature Rating -0.5 to +5.0 +6 -40 to +85 -40 to +150 Unit VDC dBm °C °C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Overall RF Frequency Range LO Frequency Range IF Frequency Range Bias Current Specification Min. Typ. Max. 1500 to 2200 1200 to 2600 0.1 to 250 2.5 13.5 +6.0 15.0 1.4 +7.0 Unit Condition T = 25°C, VCC =2.75V, RF=1.96GHz, LO=2170MHz@-7dBm, IF=210MHz 2.8 MHz MHz MHz mA dB dB dBm LNA, mixer and preamp for bias circuitry. US PCS - LNA Gain Noise Figure Input IP3 1.8 IIP3 is adjustable (see plots for setting). ISET1 (pin 14) external resistor sets current consumption and performance. Input VSWR Output VSWR Current at Input IP3 7 -6 +23.0 -5 5 +26.0 2:1 2:1 7.5 mA dB dB dBm US PCS - LNA Bypass Gain Noise Figure Input IP3 Input VSWR Output VSWR Current 5.5 2:1 2:1 0 mA 1kΩ balanced load. 10 +3.0 12 6.5 +4.0 >45 dB dB dBm dB US PCS - Mixer - High Gain Mode Gain Noise Figure Input IP3 RF to IF Isolation 7.5 IIP3 is adjustable (see plots for setting). ISET2 (pin 13) external resistor sets current consumption and performance. Input VSWR Output VSWR Current 12 2:1 2:1 13 mA 1kΩ balanced load. US PCS - Mixer - Low Gain Mode Gain Noise Figure Input IP3 RF to IF Isolation Input VSWR Output VSWR Current 0 +13.0 1.5 15 +14.0 >45 16 dB dB dBm dB IIP3 is adjustable ISET2 (pin 13) external resistor sets current consumption and performance. 7.5 2:1 2:1 8.0 mA 8-82 Rev B5 060921 RF2460 Parameter KPCS - LNA Gain Noise Figure Input IP3 14.5 +5.0 16.0 1.4 +6.0 1.8 dB dB dBm Specification Min. Typ. Max. Unit Condition IIP3 is adjustable (see plots for setting). ISET1 (pin 14) external resistor sets current consumption and performance. Input VSWR Output VSWR Current at Input IP3 7 -6 +23.0 -5 5.0 +26.0 2:1 2:1 7.5 mA dB dB dBm KPCS - LNA Bypass Gain Noise Figure Input IP3 Input VSWR Output VSWR Current 5.5 2:1 2:1 0 mA 1kΩ balanced load. 10 +2.5 12 6.5 +3.5 >45 dB dB dBm dB KPCS - Mixer - High Gain Mode Gain Noise Figure Input IP3 RF to IF Isolation 7.5 IIP3 is adjustable (see plots for setting). ISET2 (pin 13) external resistor sets current consumption and performance. Input VSWR Output VSWR Current 12 2:1 2:1 13 mA 1kΩ balanced load. KPCS - Mixer - Low Gain Mode Gain Noise Figure Input IP3 RF to IF Isolation Input VSWR Output VSWR Current 0 +13.0 1.5 15 +14.0 >45 16 dB dB dBm dB IIP3 is adjustable ISET2 (pin 13) external resistor sets current consumption and performance. 7.5 2:1 2:1 8.0 mA Rev B5 060921 8-83 RF2460 Parameter GPS - LNA Gain Noise Figure Input IP3 16 1.4 +7.0 dB dB dBm Specification Min. Typ. Max. Unit Condition IIP3 is adjustable. ISET1 (pin 14) external resistor sets current consumption and performance. Current at Input IP3 7 17 6 -5.0 mA dB dB dBm GPS - Mixer Gain Noise Figure Input IP3 IIP3 is adjustable. ISET1 (pin 14) external resistor sets current consumption and performance. Current at Input IP3 16 31 1.8 -19.0 mA dB dB dBm GPS - Cascaded Gain Noise Figure Input IP3 IIP3 is adjustable. ISET1 (pin 14) external resistor sets current consumption and performance. Current at Input IP3 23 -10 -7 >40 >60 4.5 0 mA dBm dB dB mA Local Oscillator Input Input Level LO to RF Isolation LO to LNA Isolation LO Current Buffer Any gain state. Any gain state. ICC2 when LO signal is present LNA High Gain/Mixer High Gain Assuming 3dB loss of filter IF 1, 1kΩ balanced load. Single sideband. LNA High Gain/Mixer Low Gain Assuming 3dB loss of filter 13.5 5.3 +1.0 21 dB dB dBm mA IF 1, 1kΩ balanced load. Single sideband. LNA Low Gain/Mixer High Gain Assuming 3dB loss of filter 4 14.5 +12.0 19 dB dB dB mA IF 1, 1kΩ balanced load. Single sideband. LNA Low Gain/Mixer Low Gain Assuming 3dB loss of filter -6.5 23 +20.5 14 dB dB dB mA IF 1, 1kΩ balanced load. Single sideband. 5.0 US PCS - Cascade LNA High/Mixer High Gain Noise Figure Input IP3 Total Current 24 2.2 -8.0 26 dB dB dBm mA US PCS - Cascade LNA High/Mixer Low Gain Noise Figure Input IP3 Total Current US PCS - Cascade LNA Low/Mixer High Gain Noise Figure Input IP3 Total Current US PCS - Cascade LNA Low/Mixer Low Gain Noise Figure Input IP3 Total Current 8-84 Rev B5 060921 RF2460 Parameter KPCS - Cascade LNA High/Mixer High Gain Noise Figure Input IP3 Total Current 25 2.2 -9.5 26 dB dB dBm mA Specification Min. Typ. Max. Unit Condition LNA High Gain/Mixer High Gain Assuming 3dB loss of filter IF 1, 1kΩ balanced load. Single sideband. LNA High Gain/Mixer Low Gain Assuming 3dB loss of filter KPCS - Cascade LNA High/Mixer Low Gain Noise Figure Input IP3 Total Current 14.5 5.3 +1.0 21 dB dB dBm mA IF 1, 1kΩ balanced load. Single sideband. LNA Low Gain/Mixer High Gain Assuming 3dB loss of filter KPCS - Cascade LNA Low/Mixer High Gain Noise Figure Input IP3 Total Current 4 14.5 +12.0 19 dB dB dB mA IF 1, 1kΩ balanced load. Single sideband. LNA Low Gain/Mixer Low Gain Assuming 3dB loss of filter KPCS - Cascade LNA Low/Mixer Low Gain Noise Figure Input IP3 Total Current -6.5 23 +22 14 2.7 3.0 3.3 dB dB dB mA V IF 1, 1kΩ balanced load. Single sideband. Power Supply Voltage Rev B5 060921 8-85 RF2460 Pin 1 2 Function ENABLE VCC1 Description Interface Schematic Power down pin. A logic “low” turns the part off. A logic “high” (>1.6V) turns the part on. Supply Voltage for the LNA, mixer, bias, and logic circuitry. External RF See pin 20. and IF bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Supply Voltage for the LO buffer amplifier. External RF and IF bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Mixer LO Input Pin. No connection. For isolation purposes, this pin is connected to the ground plane. No connection. For isolation purposes, this pin is connected to the ground plane. CDMA IF Output pin. This is a balanced output. The internal circuitry, in conjunction with an external matching/bias inductor to VCC, sets the operating impedance. This inductor is typically incorporated in the matching network between the output and IF filter. The part is designed to drive a 1kΩ load. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. See Application Schematic. No connection. For isolation purposes, this pin is connected to the ground plane. Same as pin 7, except complementary output. No connection. For isolation purposes, this pin is connected to the ground plane. Emitter for LNA2. Increasing the inductance on this pin will reduce the mixer gain, increase IP3 and noise figure. Mixer RF Input Pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. External matching network sets RF and IF impedance for optimum performance. 3 VCC2 4 5 6 7 LO IN NC NC IF+ IF1+ GND2 IF1- 1.2 pF 1.2 pF 8 9 10 11 12 NC IFNC LNA2 E MIX IN See pin 6. MIX IN 13 14 15 16 ISET2 ISET1 LNA OUT MIX GAIN This pin is used to set the bias current and IIP3 of the mixer amplifier using a resistor to ground. See plots for values and current settings. This pin is used to set the bias current and IIP3 of the LNA amplifier using a resistor to ground. See plots for values and current settings. LNA output pin. Open collector. CMOS compatible signal controlling mixer gain mode. Setting this signal high places the mixer in the high gain mode. Setting this signal low places the mixer in low gain mode by bypassing and shutting off the mixer buffer amplifier current. CMOS compatible signal controlling LNA gain mode. Setting this signal high places the LNA in the high gain mode. Setting this signal low bypasses the LNA and shuts off the LNA bias current. No connection. For isolation purposes, this pin is connected to the ground plane. No connection. For isolation purposes, this pin is connected to the ground plane. See pin 20. MIX GAIN 17 LNA GAIN LNA GAIN 18 19 NC NC 8-86 Rev B5 060921 RF2460 Pin 20 Function LNA IN Description RF Input pin. This pin is internally matched for optimum noise figure from a 50 Ω source. LNA IN Interface Schematic VCC1 LNA OUT Pkg Base GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. Rev B5 060921 8-87 RF2460 Output Interface Network of the Mixer L1, C1, C2, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to the following equation: 1 f IF = ----------------------------------------------------------L1 2 π ----- ( C 1 + 2 C 2 + C EQ ) 2 Where CEQ is the equivalent stray capacitance and capacitance looking into pins 7 and 9. An average value to use for CEQ is 2.5pF. R can then be used to set the output impedance according to the following equation: 1 - 1- – 1 R = ⎛ -------------------- – ----- ⎞ ⎝ 4 ⋅ R OUT R P⎠ where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1. C2 should first be set to 0 and C1 should be chosen as high as possible (suggested less than 20pF), while maintaining an RP of L1 that allows for the desired ROUT. If the self-resonant frequencies of the selected C1 produce unsatisfactory linearity performance, their values may be reduced and compensated for by including C2 capacitor with a value chosen to maintain the desired FIF frequency. L2 and C3 serve dual purposes. L2 serves as an output bias choke, and C3 serves as a series DC block. In addition, L2 and C3 may be chosen to form an impedance matching network if the input impedance of the IF filter is not equal to ROUT. Otherwise, L2 is chosen to be large (suggested 120nH) and C3 is chosen to be large (suggested 22nF) if a DC path to ground is present in the IF filter, or omitted if the filter is DC blocked. 8-88 Rev B5 060921 RF2460 Application Schematic - US PCS LNA GAIN VCC 0.1 μF LNA IN 10 nH ENABL E VCC 1 MIX GAIN 10 Ω 19 nH 510 Ω 0.1 μF 1 * 1 2 3 20 19 18 17 16 * 2 nH 15 14 13 12 22 pF LNA OUT VCC 2 18 kΩ 9.1 kΩ LO IN 7.5 nH 82 Ω 4 5 * * Represents "GND". C1 C2 C1 6 7 8 9 10 MIX IN 11 * 0.1 μF 1 nH 47 nH VCC1 VCC2 L1 VCC 1 L2 0.1 μF R C3 C3 0.1 μF C4 0.1 μF C3 and C4 should be placed as closely as possible to pins 2 and 3 IF OUT C1 (pF) US PCS, IF = 210 MHz Korean PCS, IF = 220 MHz GPS, IF = 184 MHz US PCS, IF = 184 MHz 4 3.6 8.2 8 C2 (pF) 3 2 DNI 3 C3 (pF) 6 7 6.2 6 L1 (nH) 82 82 120 82 L2 (nH) 110 120 180 110 R (Ω) 4.7 k 4.7 k 10 k 4.7 k Rev B5 060921 8-89 RF2460 Application Schematic - W-CDMA (See W-CDMA charts for lab measurements at the end of the data sheet) LNA_GAIN MIX_GAIN C2 0.1 μF L1 10 nH * ENABLE VCC1 VCC2 50 Ω μstrip LO IN L2 7.5 nH R1 82 Ω 4 5 * 6 7 8 9 10 12 11 * L5 1.0 nH P2-1 50 Ω μstrip C7 4.3 pF 50 Ω μstrip C8 4.3 pF 50 Ω μstrip 50 Ω μstrip C9 4.3 pF P2-1 P2-3 L6 47 nH P2 1 2 3 CON3 P1 VCC1 VCC2 P1-1 + C1 1 μF 50 Ω μstrip R2 DNI C6 5.6 pF C3 0.1 μF C4 0.1 μF P1-3 1 2 3 VCC1 GND ENABLE LNA_GAIN MIX_GAIN 1 2 3 20 19 18 17 16 * 15 14 13 R3 9.1 kΩ 50 Ω μstrip C10 0.1 μF 50 Ω μstrip R6 18 kΩ R5 10 Ω 50 Ω μstrip L8 19 nH L7 2.0 nH R4 510 Ω C11 22 pF C12 0.1 μF VCC1 50 Ω μstrip LNA IN 50 Ω μstrip LNA OUT 50 Ω μstrip MIX IN L4 82 nH L3 150 nH VCC1 C5 0.1 μF C13 + CON3 1 μF C2 and C3 should be placed as closely as possible to pins 2 and 3 RF2460PCBA-U WCDMA RF @ 2.14 GHz, LO @ 2.33 GHz, IF @ 190 MHz 50 Ω μstrip IF=190 MHz IF OUT 8-90 Rev B5 060921 RF2460 Application Schematic - GPS RF=1575MHz, IF=184MHz, LO=1759MHz LNA GAIN 50 Ω μstrip LNA IN 12 nH 50 Ω μstrip 12 nH ***439 pS electrical delay*** ***0.33 dB line loss*** 50 Ω μstrip 47 nF VCC1 MIX GAIN 5Ω 0.1 uF * 20 19 18 17 16 * 1.2 nH ENABLE VCC1 ***C2 & C3 should be placed as close as possible to pins 2 & 3*** 33 nF 50 Ω μstrip ***359 pS electrical delay*** ***0.23 dB line loss*** 1 2 3 4 15 14 13 12 11 6 7 8 9 10 * 50 Ω μstrip 18 kΩ 13 kΩ 0.1 uF 50 Ω μstrip 50 Ω μstrip 50 Ω μstrip LNA OUT VCC2 ***397 pS electrical delay*** ***0.26 dB line loss*** ***390 pS electrical delay*** ***0.28 dB line loss*** 50 Ω μstrip 68 Ω 5 * MIX IN LO IN 50 Ω μstrip 8.2 pF 50 Ω μstrip 50 Ω μstrip 50 Ω μstrip 8.2 pF * 47 nH Represents "GND". 120 nH VCC1 180 nH 0.1 uF 50 Ω μstrip 10 kΩ 6.2 pF ***323 pS electrical delay*** ***0.03 dB line loss*** 50 Ω μstrip IF OUT Rev B5 060921 8-91 RF2460 Current Measurement To measure only the current of the different circuitry in the evaluation board, use the following procedure. First, replace the bias choke inductor at the output of the mixer (L3 for US-PCS) with a 1 Ω resistor. The voltage across the resistor will represent the mixer current. Terminate all SMA connections at 50 Ω. Second, follow the table below. Current (mA) 25.82 18.77 14.28 10.05 7.72 VCC1 1 1 1 1 1 CONDITION VCC2 EN 1 1 1 1 1 1 0 1 0 1 LNA Gain 1 0 0 0 0 Mix Gain 1 1 0 0 0 ICC Total LNA Off Mixer Preamp Off VCC2 Off Mixer Current Therefore, LNA (Bypass) LNA (High Gain) Mixer (Preamp) Mixer Bias LO Circuitry (VCC2) = (Computer Simulation) = 25.82-18.77 = 18.77-14.28 = (Measured) = 10.05-7.7 = 14.28-10.05 = = = = = = 0mA 7.05mA 4.49mA 7.70mA 2.35mA 4.23mA 25.82mA 8-92 Rev B5 060921 RF2460 Evaluation Board Schematic US-PCS, IF=210MHz (Download Bill of Materials from www.rfmd.com.) LNA GAIN MIX GAIN VCC1 C12 0.1 μF ***439 pS electrical delay*** ***0.33 dB line loss*** J1 LNA IN C2 0.1 μF L1 10 nH L8 19 nH R5 10 Ω R4 510 Ω ENABLE VCC1 ***C3 and C4 should be placed as close as possible to pins 2 and 3*** * 1 C3 0.1 μF 2 3 C4 0.1 μF 4 5 L2 7.5 nH R1 82 Ω * 20 19 18 17 16 * 15 14 13 12 11 L7 2 nH C11 22 pF ***359 pS electrical delay*** ***0.23 dB line loss*** J5 LNA OUT R6 18 kΩ R3 9.1 kΩ C10 0.1 μF ***397 pS electrical delay*** ***0.26 dB line loss*** VCC1 ***390 pS electrical delay*** ***0.28 dB line loss*** J4 MIX IN L6 47 nH J2 LO IN 6 7 8 9 10 * L5 1 nH C7 4 pF C8 3 pF L4 82 nH C9 4 pF * Represents "GND". L3 110 nH VCC1 C5 0.1 μF J3 IF OUT ***323 pS electrical delay*** ***0.03 dB line loss*** C1 0.1 μF P1-1 P1 1 2 VCC1 GND VCC2 P2-1 P2-2 P2-3 P2 1 2 3 CON3 ENABLE LNA GAIN MIX GAIN C6 6 pF R2 4.7 kΩ P1-3 C13 0.1 μF 3 CON3 Rev B5 060921 8-93 RF2460 Evaluation Board Schematic Korean-PCS, IF=220MHz LNA GAIN MIX GAIN VCC1 C13 0.1 μF ***400 pS electrical delay*** ***0.30 dB line loss*** J1 LNA IN C2 1 pF ENABLE VCC1 C3 0.1 μF L1 1.6 nH L2 10 nH * 1 C4 0.1 μF 2 3 C5 0.1 μF 4 5 L3 9 nH R1 68 Ω * 6 7 8 9 10 20 19 18 17 16 * 15 14 13 12 11 * L6 1 nH R6 24 kΩ R3 7.5 kΩ L9 8.2 nH R5 20 Ω R4 510 Ω L8 2.2 nH C12 22 pF ***358 pS electrical delay*** ***0.26 dB line loss*** J5 LNA OUT ***C4 and C5 should be placed as close as possible to pins 2 and 3*** VCC1 ***399 pS electrical delay*** ***0.32 dB line loss*** ***396 pS electrical delay*** ***0.30 dB line loss*** J2 LO IN C11 0.1 μF J4 MIX IN L7 47 nH 2460310, Rev. 5 C8 3.6 pF C9 2 pF L5 82 nH C10 3.6 pF * Represents "GND". L4 120 nH VCC1 C6 0.1 μF J3 IF OUT ***291 pS electrical delay*** ***0.05 dB line loss*** C1 0.1 μF P1-1 P1 1 2 VCC1 GND VCC2 P2-1 P2-2 P2-3 P2 1 2 3 CON3 ENABLE LNA GAIN MIX GAIN C7 7 pF R2 4.7 kΩ P1-3 C14 0.1 μF 3 CON3 8-94 Rev B5 060921 RF2460 Evaluation Board Layout - US PCS Board Size 2.0" x 2.0" Board Thickness 0.034”, Board Material FR-4, Multi-Layer Assembly Top Power Plane 1 Power Plane 2 Rev B5 060921 8-95 RF2460 Back 8-96 Rev B5 060921 RF2460 Assembly Evaluation Board Layout - Korean PCS Top Power Plane 1 Power Plane 2 Back Rev B5 060921 8-97 RF2460 US-PCS LNA Gain, Noise Figure and IIP3 versus ICC - LNA Only (LNA High Gain) 18.0 16.0 10.0 14.0 12.0 10.0 0.0 8.0 Gain (dB) 6.0 4.0 -10.0 2.0 0.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0 -15.0 15.0 NF (dB) IIP3 (dBm) -5.0 5.0 15.0 Resistor (R6) versus ICC (mA) - LNA Only 200.0 180.0 160.0 140.0 (LNA High Gain) Y Axis Label (units) Resistor R6 (k Ω) IIP3 (dBm) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 X Axis Label (units) ICC (mA) 25.0 20.0 15.0 Mixer Gain, Noise Figure and IIP3 versus ICC - Mixer (Mixer High Gain, LO = -7 dBm) 10.0 180.0 160.0 Resistor (R3) versus ICC - Mixer (Mixer High Gain, LO = 2170 @ -7 dBm) 5.0 140.0 120.0 100.0 80.0 60.0 Gain and Noise Figure (dB) 5.0 0.0 -5.0 -5.0 Gain (dB) -10.0 -15.0 -20.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 -15.0 18.0 NF (dB) IIP3 (dBm) -10.0 IIP3 (dBm) 0.0 Resistor R3 (k Ω) 10.0 40.0 20.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 ICC (mA) ICC (mA) Special Instructions (Board loss, taking into consideration description in the schematic) LNA VCC1 =VCC2 =Enable=2.75V; Mix Gain=0.0V To measure ICC LNA only: LNA Gain was switched between 0V and 2.75V, and record the delta current. Mixer VCC1 =VCC2 =Enable=Mix Gain=2.75V; LNA Gain=0.0V To measure ICC Mixer (LNA should be in bypass mode and LO signal should be present): Mixer Current=Total IC Current-LO Circuitry (~4.23mA) (See “Current Measurement” section for more details) VCC2 only affects LO current buffer and R6 doesn’t affect the mixer current. 8-98 Rev B5 060921 RF2460 W-CDMA (See W-CDMA Application Schematic) LNA Gain, Noise Figure, and IIP3 versus ICC - LNA Only (LNA High Gain) 20.00 2.00 1.80 15.00 1.60 80.0 70.0 60.0 90.0 R6 versus ICC for LNA Gain (dB) and IIP3 (dBm) 1.40 R6 (mA) 1.20 5.00 1.00 0.80 0.00 0.60 Gain (dB) -5.00 IIP3 (dBm) NF (dBm) -10.00 1.00 3.00 5.00 7.00 9.00 11.00 13.00 0.20 0.00 15.00 Noise Figure (dB) 10.00 50.0 40.0 30.0 20.0 0.40 10.0 0.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 ICC (mA) ICC (mA) Mixer Gain, Noise Figure and IIP3 versus ICC - Mixer and Bias Circuits (Mixer High Gain, LO=-7dBm) 14.00 12.00 10.00 10.00 12.00 R3 versus ICC for Mixer and Bias Circuits 40.0 35.0 30.0 Gain (dB) and IIP3 (dBm) 8.00 R3 (kΩ) 6.00 4.00 Noise Figure (dB) 8.00 25.0 20.0 6.00 2.00 0.00 -2.00 -4.00 -6.00 -8.00 6.00 6.50 7.00 7.50 8.00 8.50 9.00 9.50 Gain (dB) IIP3 (dBm) NF (dBm) 0.00 10.00 2.00 4.00 15.0 10.0 5.0 0.0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 ICC (mA) ICC (mA) Instructions (Board loss, taking into consideration description in the W-CDMA schematic) LNA ICC LNA current=total current (VCC =LNA Gain=2.75)-total current (VCC =2.75; LNA Gain=0) To measure ICC LNA only: LNA Gain was switched between 0V and 2.75V, and record the delta current. Mixer ICC Mix and Bias Current=Total Current (VCC1 =EN=VCC2 =Mix Gain=2.75; LNA Gain=0)-total current (VCC1 =EN=2.75; Mix Gain=LNA Gain=VCC2 =0) LO signal should be present. VCC2 only affects LO current buffer and R6 doesn’t affect the mixer current. Rev B5 060921 8-99 RF2460 By using a R6=39kΩ and R3=24kΩ, the following results were obtained. RF=2140MHz, LO=2330MHz, IF=190MHz. LNA (High Gain Mode) WCDMA 14.00 13.80 9.00 13.60 13.40 8.00 10.00 LNA (High Gain Mode) W-CDMA 13.00 12.80 12.60 12.40 12.20 12.00 2.75 2.85 2.95 3.05 3.15 3.25 Gain, -30º Gain, 25º Gain, 85º IIP3 (dBm) Gain (dB) 13.20 7.00 6.00 5.00 IIP3, -30º IIP3, 25º IIP3, 85º 4.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 VCC (V) VCC (V) LNA (High Gain Mode) W-CDMA 2.50 4.35 4.30 2.00 4.25 4.20 1.50 LNA Current W-CDMA Noise Figure (dB) ICC (mA) 1.00 0.50 NF, -30º NF, 25º NF, 85º 0.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 4.15 4.10 4.05 4.00 Icc, -30º 3.95 3.90 2.75 2.85 2.95 3.05 3.15 3.25 3.35 Icc, 25º Icc, 85º VCC (V) VCC (V) 8-100 Rev B5 060921 RF2460 Mixer High Gain Mode, LO @ -7 dBm W-CDMA 14.00 11.00 Mixer High Gain Mode, LO @ -7 dBm W-CDMA 13.00 10.50 11.00 Noise Figure (dB) Gain, -30º Gain, 25º Gain, 85º 12.00 10.00 Gain (dB) 9.50 10.00 9.00 9.00 8.50 NF, -30º NF, 25º NF, 85º 8.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 8.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 VCC (V) VCC (V) Mixer High Gain Mode, 13.0 12.5 -0.5 12.0 11.5 -1.0 Mixer IF High Gain Mode, 0.0 VCC @ 2.75 W-CDMA VCC @ 2.75 W-CDMA IIP3, -30º IIP3, 25º IIP3, 85º IIP3 (dBm) Gain, -30º Gain, 25º Gain, 85º -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 Gain (dB) 11.0 10.5 10.0 9.5 9.0 8.5 8.0 -10.0 -1.5 -2.0 -2.5 -3.0 -3.5 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 LO (dBm) LO (dBm) Mixer IF High Gain Mode, 11.0 Mixer IF High Gain Mode, 6.2 VCC @ 2.75 W-CDMA VCC @ 2.75 W-CDMA 10.5 6.1 ICC Mixer and Bias Current (mA) 6.0 Noise Figure (dB) 10.0 Icc, -30º Icc, 25º Icc, 85º 5.9 9.5 5.8 9.0 5.7 8.5 NF, -30º NF, 25º NF, 85º 5.6 8.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 5.5 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 LO (dBm) LO (dBm) Rev B5 060921 8-101 RF2460 Mixer IF High Gain Mode, LO @ -7 dBm W-CDMA 7.50 7.00 ICC Mixer and Bias Circuit (mA) 6.50 6.00 5.50 Icc, -30º Icc, 25º Icc, 85º 5.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 VCC (V) 8-102 Rev B5 060921 RF2460 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is 3 μinch to 8 μinch gold over 180 μinch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern A = 0.69 x 0.28 (mm) Typ. B = 0.28 x 0.69 (mm) Typ. C = 2.40 (mm) Sq. Dimensions in mm. 2.00 Typ. 0.50 Typ. Pin 20 B Pin 1 B B B B Pin 15 0.50 Typ. A A A A A C A A A A A B B B B B Pin 10 1.00 Typ. 2.00 Typ. 0.78 Typ. 0.78 Typ. 1.00 Figure 1. PCB Metal Land Pattern (Top View) Rev B5 060921 8-103 RF2460 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.79 x 0.38 (mm) Typ. B = 0.38 x 0.79 (mm) Typ. C = 2.50 (mm) Sq. Dimensions in mm. 2.00 Typ. 0.50 Typ. Pin 20 B Pin 1 B B B B Pin 15 A A A C A A A B B B B B Pin 10 0.50 Typ. A A A A 1.00 Typ. 2.00 Typ. 0.78 Typ. 0.78 Typ. 1.00 Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 8-104 Rev B5 060921