RT8023GQW

RT8023 1.2MHz 1.5A Synchronous Step-Down Converter with Two LDOs General Description Features The RT8023 combines two low dropout (LDO) linear regulators and a step-down converter with an input voltage range of 2.6V to 5.5V. Each output voltage is adjustable from 0.8V to 5V. With independent Enable and PowerGood pins for each regulator, it is easy to control the power up sequence, which is important in some applications. z Converter Input Voltage Range : 2.6V to 5.5V, LDO Input Voltage Range : 2.4V to 5.5V z Low-Noise LDO for RF Application Ultra-Fast Response in Line/Load Transient LDO Turn-On Time Less Than 40us Only 1μ μ F LDO Output Capacitor Required for Stability Current Limiting Protection 1.5A, High Efficiency Step-Down Converter 1.2MHZ Constant Switching Frequency Low RDS(ON) Internal Switches No Schottky Diode Required 0.8V Reference Allows Low Output Voltage Low Dropout Operation : 100% Duty Cycle Internally Compensated < 2μ μA Shutdown Current Power Good Output Voltage Monitor Internal Soft-Start for PWM Converter Easy Power Sequence Control Over Temperature Protection Short Circuit Protection Thermally Enhanced 24-Lead WQFN Package RoHS Compliant and 100% Lead (Pb)-Free The LDO has an independent input and is capable of delivering up to 700mA(LDO1) and 350mA(LDO2) output currents with ultra-low dropout. The LDO has high PSRR and can work with low-ESR space saving ceramic capacitors. All these make it Ideal for portable RF and wireless applications with demanding performance and space requirements. Other features include high output accuracy, current limiting protection, and 40μs fast turnon time. z z z z z z z z z z z The step-down converter is a 1.2MHz PWM, current mode converter. Its high switching frequency allows the use of tiny, low cost capacitors and inductors 2mm or less in height. Internal power switches with low on-resistance increase efficiency and eliminate the need for external Schottky diodes. The converter can run at 100% duty cycle for low dropout operation that extends battery life in portable systems. Ordering Information RT8023 z z z z z z z Applications z Package Type QW : WQFN-24L 4x4 (W-Type) z Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) z z z z Portable Instruments Microprocessors and DSP Core Supplies Cellular Phones Wireless and DSL Modems PC Cards Digital Cameras Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. DS8023-03 March 2011 Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. www.richtek.com 1 RT8023 Pin Configurations VOUT3 AGND 23 NC FB1 24 VIN3 EN1 (TOP VIEW) 22 21 20 19 PGOOD1 1 18 FB3 VDD1 2 17 PGOOD3 VIN1 3 16 EN3 VIN1 4 15 EN2 VIN1 5 14 PGOOD2 13 FB2 PGND PGND 25 NC 11 12 VIN2 10 VOUT2 9 PHASE1 7 NC 8 PHASE1 6 WQFN-24L 4x4 Typical Application Circuit R1 100 L1 2.2µH R3 100k C5 22uF VIN2 VDD1 21 14 1 PGOOD1 PGOOD2 24 EN1 PGOOD3 17 15 EN2 VOUT2 12 RT8023 16 EN3 FB2 13 8, 9 20 PHASE1 VOUT3 23 FB3 18 FB1 AGND VOUT1 1.2V/1.5A 11 R4 200k 19 PGND PGOOD1 EN1 EN2 EN3 2 VIN1 R2 100k 3, 4, 5 VIN2 C3 1µF C2 0.1µF C1 10µF C4 1µF VIN3 VIN1 6, Exposed Pad (25) VIN3 R5 100k R6 100k PGOOD2 PGOOD3 R7 425k VOUT3 2.5V/0.35A R9 425k R10 200k VOUT2 2.5V/0.7A C7 1µF R8 200k C6 1µF Figure 1. 1.2V Output Step-Down Converter and Dual 2.5V Output Regulators Note : Must to use ceramic X5R/X7R capacitors. www.richtek.com 2 DS8023-03 March 2011 RT8023 Functional Pin Description Pin No. 1 Pin Name PGOOD1 Pin Function Power Good Indicator of step-down converter. Open-drain logic output that is opened when the output voltage exceeds 90% of the regulation point. Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VIN1 is 2 VDD1 3, 4, 5 VIN1 6, PGND 25 (Exposed Pad) 8, 9 PHASE1 equal to VDD1. Keep the voltage difference between VDD1 and VIN1 less than 0.5V. Power Input Supply of step-down converter. Decouple this pin to GND with a capacitor. Power Ground. Must be soldered to PCB ground for electrical contact and optimum thermal performance. The exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. Internal Power MOSFET Switches Output of step-down converter. Connect this pin to the inductor. Power Input Supply of LDO1. Decouple this pin to GND with a 1Uf or greater 11 VIN2 12 VOUT2 Output of LDO1. A 1Uf or greater output low-ESR ceramic capacitor is required for stability.. 13 FB2 Feedback Pin of LDO1. Receives the feedback voltage from a resistive divider connected across the output. 14 PGOOD2 15 EN2 16 EN3 LDO2 Enable. A logic high level at this pin enables LDO2, while a logic low level causes LDO2 to shut down. 17 PGOOD3 Power Good Indicator of LDO2. Open-drain logic output that is opened when the output voltage exceed 90% of regulation point. 18 FB3 Feedback Pin of LDO2. Receives the feedback voltage from a resistive divider connected across the output. 19 AGND 20 VOUT3 21 VIN3 Power Input Supply of LDO2. Decouple this pin to GND with a 1uF or greater capacitor. 7, 10, 22 NC No Internal Connection. 23 FB1 24 EN1 DS8023-03 March 2011 capacitor. Power Good Indicator of LDO1. Open-drain logic output that is opened when the output voltage exceeds 90% of the regulation point. LDO1 Enable. A logical high level at this pin enables LDO1, while a logical low level causes LDO1 to shut down. Analog Grand. All small-signal of the IC should connect to this ground, which connects to PGND at one point for away exposed pad. Output of LDO2. A 1uF or greater output low-ESR ceramic capacitor is required for stability. Feedback Pin of step-down converter. Receives the feedback voltage from a resistive divider connected across the output. Step-down converter Enable. A logic high level at this pin enables step-down converter, while a logic low level causes step-down converter to shut down. www.richtek.com 3 RT8023 Function Block Diagram OT OTP POR POR Slope Compensation OSC VDD1 0.8V FB1 VIN1 ISEN EA OC Limit Output Clamp Driver InternalSoft Start 0.72V Control Logic PHASE1 GND 0.4V PGOOD1 VIN2 VOUT2 EN2 VREF2 PGOOD2 EN1 Current Limit 0.72V 0.8V FB2 EA VOUT3 VIN3 EN3 VREF3 Current Limit PGOOD3 0.72V 0.8V FB3 www.richtek.com 4 EA DS8023-03 March 2011 RT8023 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VIN1, VIN2 ----------------------------------------------------------------------------- −0.3V to 6V Output Pin Voltage ------------------------------------------------------------------------------------------------ −0.3V to (VIN1 + 0.3V) PHASE Pin Voltage ---------------------------------------------------------------------------------------------- −0.3V to (VIN2 + 0.3V) Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to 6V Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 ---------------------------------------------------------------------------------------------------- 1.923W Package Thermal Resistance (Note 2) WQFN-24L 4x4, θJA ----------------------------------------------------------------------------------------------- 52°C/W WQFN-24L 4x4, θJC ---------------------------------------------------------------------------------------------- 7°C/W Junction Temperature --------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z z (Note 4) Supply Input Voltage, Converter ------------------------------------------------------------------------------- 2.6V to 5.5V Supply Input Voltage, LDOs ------------------------------------------------------------------------------------ 2.4V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Step-down converter Input Voltage Range VIN1 2.6 -- 5.5 V Feedback Voltage VFB1 0.784 -- 0.816 V Under Voltage Lockout Threshold VUVLO 2.24 2.36 2.48 V VDD1 Hysteresis -- 150 -- mV Active, VFB = 0.75V, Not Switching -- 300 -- μA DC Bias Current VDD1 Rising Shutdown Current ISHDN EN2 = 0 -- -- 2 μA Switch On Resistance, High RFET_H I PHASE = 0.5A -- 150 270 mΩ Switch On Resistance, Low RFET_L I PHASE = 0.5A -- 90 150 mΩ Peak Current Limit ILIM 1.7 2.3 3.2 A 1 1.2 1.4 MHz -- 0.01 1 %/V Switching Frequency Output Voltage Line Regulation VIN1 = 2.6V to 5.5V To be continued DS8023-03 March 2011 www.richtek.com 5 RT8023 Parameter Symbol Test Conditions Min Typ Max Unit -- 0.01 1 % 0.68 0.72 0.76 V -- -- 100 Ω EN1 Input High 1.4 -- -- V EN1 Input Low -- -- 0.4 V -- 145 -- -- 25 -- Measured by sever loop, EA output from 0.253V to 0.853V Output Voltage Load Regulation FB Threshold for PGOOD Transition PGOOD1 Pull-Down Resistance Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis ΔTSD (Note 5) °C LDO1 (VIN = VOUT + 0.5V, VEN = VIIN, CIN = COUT = 1uF (Ceramic)) Input Voltage Range VIN2 2.4 -- 5.5 V Feed Back Voltage VFB2 0.784 -- 0.816 V Output Noise Voltage eNO VOUT2 = 1.5V, IOUT2 = 1mA -- 30 -- μVRMS Quiescent Current IQ VEN2 = 5V, I OUT2 = 0mA -- 35 60 μA Shutdown Current I SHDN EN2 = 0 -- -- 2 μA EN2 Pin Current I EN2 Measured EN leakage current. EN2 = 5.5V -- 0.1 1 μA Current Limit I LIM RLOAD = 0Ω 0.7 0.9 1.2 A Dropout Voltage VDROP IOUT2 = 500mA, VIN2 > 2.7V -- 250 400 mV Load Regulation ΔVLOAD -- 1 -- % Line Regulation ΔVLINE -- 0.01 0.2 %/V -- 40 -- dB -- 0.72 0.76 V -- -- 120 Ω EN2 Input High 1.4 -- -- V EN2 Input Low -- -- 0.4 V Power Supply Rejection Ratio, f = 100kHz FB Threshold for PGOOD Transition PSRR 1mA < IOUT2 < 500mA, VIN2 > 2.7V VIN2 = (VOUT2 + 0.5) to 5.5V IOUT2 = 1mA IOUT2 = 300mA PGOOD2 Pull-Down Resistance LDO2 (VIN = VOUT + 0.5V, VEN = VIN, CIN = C OUT = 1uF (Ceramic)) Input Voltage Range VIN3 2.4 -- 5.5 V Feed Back Voltage VFB3 0.784 -- 0.816 V Output Noise Voltage eNO VOUT3 = 1.5V, IOUT3 = 1mA -- 30 -- μVRMS Quiescent Current IQ VEN3 = 5V, I OUT3 = 0mA -- 35 60 μA Shutdown Current I SHDN EN1 = 0 -- -- 2 μA EN3 Pin Current I EN3 Measured EN leakage current. EN3 = 5.5V -- 0.1 1 μA To be continued www.richtek.com 6 DS8023-03 March 2011 RT8023 Parameter Symbol Test Conditions Min Typ Max Unit 0.35 0.48 0.6 A -- 250 400 mV -- 1 -- % -- 0.01 0.2 %/V -- 0.1 1 μA 0.35 0.48 0.6 A -- 250 400 mV -- 1 -- % -- 0.01 0.2 %/V -- 40 -- dB -- 0.72 0.76 V -- -- 120 Ω EN3 Input High 1.4 -- -- V EN3 Input Low -- -- 0.4 V Current Limit I LIM RLOAD = 0Ω Dropout Voltage VDROP IOUT3 = 250mA, VIN3 > 2.7V Load Regulation ΔVLOAD Line Regulation ΔVLINE EN3 Pin Current I EN3 1mA < IOUT3 < 250mA, VIN3 > 2.7V VIN3 = (VOUT3 + 0.5) to 5.5V IOUT3 = 1mA Measured EN leakage current. EN3 = 5.5V Current Limit I LIM RLOAD = 0Ω Dropout Voltage VDROP IOUT3 = 250mA, VIN3 > 2.7V Load Regulation ΔVLOAD Line Regulation ΔVLINE Power Supply Rejection Ratio, f = 100kHz FB3 Threshold for PGOOD Transition PSRR 1mA < IOUT3 < 250mA, VIN3 > 2.7V VIN3 = (VOUT3 + 0.5) to 5.5V IOUT3 = 1mA IOUT3 = 150mA PGOOD3 Pull-Down Resistance Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The power source for thermal shutdown circuit must be provided by VIN1. There must be a power input into LDO1 and then the LDO2 can provide the thermal shutdown function. DS8023-03 March 2011 www.richtek.com 7 RT8023 Typical Operating Characteristics Buck Efficiency vs. Output Current Buck Output Voltage vs. Load Current 100 1.203 VIN1 = 5V 90 1.202 VIN1 = 3.3V 70 Output Voltage (V) Efficiency (%) 80 60 50 40 30 1.201 VIN1 = 5.5V 1.200 VIN1 = 3.3V 1.199 1.198 20 1.197 10 VOUT1 = 1.2V 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 VOUT1 = 1.2V 1.196 1.5 0 0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5 Output Current (A) Load Current (A) Buck Current Limit vs. Temperature Buck Output Voltage vs. Temperature 2.6 1.215 VIN1 = 5.5V 1.210 VIN1 = 3.3V 2.5 2.4 Current Limit (A) Output Voltage (V) 1.220 1.205 1.200 1.195 1.190 2.3 2.2 2.1 2.0 VIN1 = 3.3V VIN1 = 5.5V 1.9 1.8 1.185 1.7 VOUT1 = 1.2V 1.180 -50 -25 0 25 50 75 100 VOUT1 = 1.2V 1.6 -50 125 -25 0 Buck Frequency vs. Input Voltage 50 75 100 125 Buck Frequency vs. Input Voltage 1.30 1.30 1.25 1.25 Frequency (MHz) Frequency (MHz) 25 Temperature (°C) Temperature (°C) 1.20 1.15 1.10 1.05 1.20 VIN1 = 5.5V 1.15 1.10 VIN1 = 3.3V 1.05 VOUT1 = 1.2V, IOUT1 = 0.1A 1.00 2.5 3 3.5 4 4.5 Input Voltage (V) www.richtek.com 8 5 5.5 VOUT1 = 1.2V, IOUT1 = 0.1A 1.00 -50 -25 0 25 50 75 100 125 Input Voltage (V) DS8023-03 March 2011 RT8023 Buck Load Transient Response Buck Switching Waveforms VIN1 = 5V, VOUT1 = 1.2V IOUT1 = 0A to 1.5A VIN1 = 3.3V, VOUT1 = 1.2V IOUT1 = 1.5A VOUT1 (5mV/Div) VOUT1 (50mV/Div) I PHASE1 VPHASE1 (5V/Div) IOUT1 (1A/Div) I PHASE1 (500mA/Div) Time (50μs/Div) Time (1μs/Div) Buck Power On from EN Buck PGOOD Response VIN1 = 3.3V, VOUT1 = 1.2V, IOUT1 = 1.5A VIN1 = 3.3V, VOUT1 = 1.2V, IOUT1 = 1.5A VEN1 (2V/Div) VEN1 (2V/Div) VOUT1 (500mV/Div) VOUT1 (500mV/Div) IOUT1 (0.5A/Div) I IN1 (0.5A/Div) VPGOOD1 (2V/Div) Time (100μs/Div) Time (100μs/Div) LDO1 Dropout Voltage vs. Load Current LDO2 Dropout Voltage vs. Load Current 600 600 500 TA = 125°C 400 TA = 25°C 300 200 TA = -40°C 100 VOUT2 = 2.5V 0 0 100 200 300 400 500 Load Current (mA) DS8023-03 March 2011 600 Dropout Voltage (mV) Dropout Voltage (mV) 500 TA = 125°C 400 TA = 25°C 300 200 TA = -40°C 100 VOUT3 = 2.5V 0 700 0 50 100 150 200 250 300 350 Load Current (mA) www.richtek.com 9 RT8023 LDO2 Current Limit vs. Input Voltage 0.60 1.2 0.55 0.50 1.1 Current Limit (A) Current Limit (A) LDO1 Current Limit vs. Input Voltage 1.3 1.0 0.9 0.8 0.7 0.45 0.40 0.35 0.30 0.25 VOUT2 = 2.5V 0.6 VOUT3 = 2.5V 0.20 2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 Input Voltage (V) 4.5 5 5.5 LDO2 Current Limit vs. Temperature 1.3 0.60 1.2 0.55 VIN3 = 5.5V VIN2 = 5.5V 1.1 Current Limit (A) Current Limit (A) LDO1 Current Limit vs. Temperature 1.0 0.9 VIN2 = 3.3V 0.8 0.7 0.50 0.45 VIN3 = 3.3V 0.40 0.35 0.30 0.25 VOUT2 = 2.5V 0.6 -50 -25 0 25 50 75 100 VOUT3 = 2.5V 0.20 -50 125 -25 Temperature (°C) 2.515 2.525 2.510 2.520 Output Voltage (V) 2.530 VIN2 = 5.5V 2.500 25 50 75 100 125 LDO2 Output Voltage vs. Load Current 2.520 2.505 0 Temperature (°C) LDO1 Output Voltage vs. Load Current Output Voltage (V) 4 Input Voltage (V) VIN2 = 3.3V 2.495 2.490 VIN3 = 5.5V 2.515 VIN3 = 3.3V 2.510 2.505 2.500 2.495 2.485 VOUT2 = 2.5V 2.480 0 100 200 300 400 500 Load Current (mA) www.richtek.com 10 600 700 VOUT3 = 2.5V 2.490 0 50 100 150 200 250 300 350 Load Current (mA) DS8023-03 March 2011 RT8023 LDO2 Output Voltage vs. Temperature 2.53 2.52 2.52 Output Voltage (V) Output Voltage (V) LDO1 Output Voltage vs. Temperature 2.53 2.51 2.50 2.49 2.51 2.50 2.49 2.48 2.48 VIN2 = 3.3V, VOUT2 = 2.5V VIN3 = 3.3V, VOUT3 = 2.5V 2.47 2.47 -50 -25 0 25 50 75 100 -50 125 Temperature (°C) 0 25 50 75 100 LDO2 Load Transient Response VIN3 = 5V, VOUT3 = 1.2V IOUT3 = 0A to 0.35A VOUT2 (20mV/Div) VOUT3 (20mV/Div) IOUT2 (0.5A/Div) IOUT3 (0.2A/Div) Time (50μs/Div) Time (50μs/Div) LDO1 Line Transient Response LDO2 Line Transient Response VIN2 = 2.5V to 3.5V, VOUT2 = 1.2V, IOUT2 = 100mA VIN3 = 2.5V to 3.5V, VOUT3 = 1.2V, IOUT3 = 100mA VIN2 (1V/Div) VIN3 (1V/Div) VOUT2 (50mV/Div) VOUT3 (50mV/Div) Time (50μs/Div) DS8023-03 March 2011 125 Temperature (°C) LDO1 Load Transient Response VIN2 = 5V, VOUT2 = 1.2V IOUT2 = 0A to 0.7A -25 Time (50μs/Div) www.richtek.com 11 RT8023 LDO1 Noise LDO2 Noise VIN2 = 4.5V, VOUT2 = 1.5V, IOUT2 = 300mA VIN3 = 4.5V, VOUT3 = 1.5V, IOUT3 = 300mA VOUT2 (50uV/Div) VOUT3 (50uV/Div) Time (10ms/Div) Time (10ms/Div) Crosstalk 0 -10 -10 -20 -20 -30 -30 Crosstalk (dB) PSRR (dB) LDO1 PSRR 0 -40 -50 IOUT = 300mA -60 -70 IOUT = 10mA -80 -90 10 0.01 100 0.1 1000 1 -40 -50 -60 -70 -80 -90 VIN2 = 2.5V to 2.6V, VOUT2 = 1.5V -100 10000 10 100000 100 VIN2 to VOUT3, IOUT3 = 10mA -100 1000000 1000 10 0.01 100 0.1 1000 1 10000 10 100000 100 (kHz) Frequency (Hz) Frequency (kHz) (Hz) LDO1 Power On from EN2 LDO2 Power On from EN3 VIN2 = 5V, VOUT2 = 1.2V, IOUT2 = 0.3A VEN3 (5V/Div) VOUT2 (500mV/Div) VOUT3 (500mV/Div) I IN2 (0.5A/Div) I IN3 (0.5A/Div) Time (10μs/Div) 1000000 1000 VIN3 = 5V, VOUT3 = 1.2V, IOUT3 = 0.3A VEN2 (5V/Div) www.richtek.com 12 LDO1 VIN2 = 2.5V to 2.6V LDO2 VOUT3 = 1.5V Time (10μs/Div) DS8023-03 March 2011 RT8023 LDO1 PGOOD Response LDO2 PGOOD Response VIN2 = 5V, VOUT2 = 1.2V, IOUT2 = 0.3A VIN3 = 5V, VOUT3 = 1.2V, IOUT3 = 0.3A VEN2 (5V/Div) VEN3 (5V/Div) VOUT2 (500mV/Div) VOUT3 (500mV/Div) VPGOOD (2V/Div) IOUT2 (0.5A/Div) VPGOOD (2V/Div) IOUT3 (0.5A/Div) Time (25μs/Div) DS8023-03 March 2011 Time (25μs/Div) www.richtek.com 13 RT8023 Application Information For Buck Converter Part The Typical Application Circuit shows the basic RT8023 application circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. V V ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥ VIN ⎦ ⎣ f ×L ⎦ ⎣ Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔIL = 0.4(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ VOUT ⎤ L =⎢ × ⎢1 − ⎥ ⎥ ⎣ f × ΔIL(MAX) ⎦ ⎣ VIN(MAX) ⎦ Inductor Core Selection The inductor type must be selected once the value for L is known. Generally speaking, high efficiency converters can not afford the core loss found in low cost powdered iron cores. So, the more expensive ferrite or mollypermalloy cores will be a better choice. The selected inductance rather than the core size for a fixed inductor value is the key for actual core loss. As the inductance increases, core losses decrease. Unfortunately, increase of the inductance requires more turns of wire and therefore the copper losses will increase. Ferrite designs are preferred at high switching frequency due to the characteristics of very low core losses. So, design goals can focus on the reduction of copper loss and the saturation prevention. www.richtek.com 14 Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. The previous situation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy. However, they are usually more expensive than the similar powdered iron inductors. The rule for inductor choice mainly depends on the price vs. size requirement and any radiated field/ EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : V IRMS = IOUT(MAX) OUT VIN VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the required effective series resistance (ESR) to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT , is determined by : 1 ⎤ ΔVOUT ≤ ΔIL ⎡⎢ESR + 8fCOUT ⎦⎥ ⎣ DS8023-03 March 2011 RT8023 The output ripple will be highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density than other types. Although Tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Output Voltage Programming The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure2. V OUT R1 FB RT8023 VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟ ⎝ R2 ⎠ Where VREF is the internal reference voltage (0.8V typ.). Efficiency Consideration The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. The efficiency can be expressed as : Efficiency = 100 − (L1 + L2 + L3 + …..) Where L1, L2, etc., are the individual losses as a percentage of input power, although all dissipative elements in the circuit produce losses, VIN quiescent current and I2R losses are two main sources for most of the losses. The VIN quiescent current loss dominates the efficiency loss at a very low load current whereas the I2R loss dominates the efficiency loss at medium to high load current. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VIN quiescent current appears due to two factors including the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from VIN to ground. The value of ΔQ/Δt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) R2 GND Figure 2. Setting the Output Voltage DS8023-03 March 2011 For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : Where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and their effects will be more significant at higher supply voltages. www.richtek.com 15 RT8023 2. I2R losses are calculated from the resistance of the internal switches R SW and external inductor R L. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFETs RDS(ON) and the duty cycle (DC) as follows : RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristic curves. Thus, to obtain I2R loss, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of total losses. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR) also begins to charge or discharge COUT generating a feedback error signal for the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For LDO Part The external capacitors used with the RT8023 must be carefully selected for regulator stability and performance just like any low-dropout regulator. Using a capacitor whose value is >1μF on the RT8023 input and the amount of capacitance can be increased without limit. The input capacitor must be located at a distance of not more than 1cm from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDO www.richtek.com 16 applications. The RT8023 is designed specifically to work with low ESR ceramic output capacitor for space-saving and performance consideration. Enable The RT8023 goes into sleep mode when the EN pin is in the logic low condition. The RT8023 has an EN pin to turn on or turn off the regulator during this condition. When the EN pin is in the logic high condition, the regulator will be turned on. The typical supply current for the EN pin is 0.1μA. The EN pin may be directly tied to VIN to keep the part on. The enable input is CMOS logic and can not be left floating. Current Limit The RT8023 contains an independent current limiter to monitor and control the pass transistor's gate voltage. The part limits the two LDOs' current respectively as follows : LDO1 : 700mA and LDO2 : 350mA (min.). The output can be shorted to ground indefinitely without damaging the part. PGOOD The power good output is an open-drain output. It is designed essentially to work as a power-on reset generator once the regulated voltage was up or a fault condition occurs. The output of the power good drives to low when a fault condition occurs. The power good output will be driven back to up once the output reaches 90% of its nominal value. The output voltage level will be drooped at the fault condition including current limit, thermal shutdown or shutdown and triggers the PGOOD detector to alarm a fault condition. Due to the shutdown mode condition, a fault condition occurs by pulling up the PGOOD output low. And it will sink a current from the open drain and the external power. It is recommended to select a suitable pulling resistance to achieve the goal of ideal power dissipation control. PSRR The power supply rejection ratio (PSRR) is defined as the ability of a regulator to maintain its output voltage as its power supply voltage is varied. The PSRR is found to be: PSRR = 20 x log[ ΔVOUT/ΔVIN] DS8023-03 March 2011 RT8023 How a PCB layout will affect the PSRR is shown as Figure 3. If the FB is placed in parallel with the PGOOD and EN, the output voltage will be interfered to result in a bad PSRR performance that is shown as Figure 5. GND VOUT FB3 PGOOD3 For the layout as shown in Figure 4, the FB is separated from the PGOOD and the EN. In this condition, there will be less interference for the output voltage and it will lead to a better PSRR performance. EN3 EN2 PGOOD2 FB2 As shown in Figure 5, if the FB is separated from the PGOOD and EN and a GND path is added, then it will lead to a better PSRR performance especially for high frequency applications. VOUT GND Figure 3 Thermal Consideration GND GND Path For continuous operation, do not exceed the maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : GND Paht PD(MAX) = (TJ(MAX) − TA )/θJA VOUT FB3 PGOOD3 EN3 EN2 PGOOD2 FB2 VOUT GND For recommended operating conditions specification of RT8023, where T J(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance Figure 4 0 -10 PSRR (dB) -20 Where T J(MAX) is the maximum operating junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. LDO1 PSRR Figure 3 Figure 4 without GND path Figure 4 with GND path θJA is layout dependent. For WQFN-24L 4x4 packages, the thermal resistance θJA is 52°C/W on the standard JEDC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : -30 -40 -50 -60 -70 -80 VOUT = 1.5V, IOUT = 10mA -90 0.01 10 0.1 100 1 1000 10 10000 100 100000 1000 1000000 Frequency (kHz) (Hz) Figure 5. The PSRR for the RT8023 Note : The temperature effect must be taken into P D(MAX) = (125°C − 25°C) / 52°C/W = 1.923 for WQFN-24L 4x4 packages. The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA For RT8023 packages, the Figure 6 of derating curves allows the designer to see the effect of rising ambient temperature of maximum power allowed. consideration for heavy load PSRR measuring. DS8023-03 March 2011 www.richtek.com 17 RT8023 2.0 Follow the PCB layout guidelines for optimal performance of RT 8023 1.8 ` ` ` ` Maximum Power Dissipation (W) Layout Consideration Please refer to the PSRR section for layout improvement. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). LX node is with high frequency voltage swing and should be kept small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up. ` Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT8023. For the LDO layout part, put the output capacitor as close as possible to the device pins. (VIN and GND). ` Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. 1.6 1.4 1.2 1.0 WQFN-24L 4x4 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 6. Derating Curves for RT8023 Packages The resistive dividers R3, R4, R7, R8, R9 and R10 must be located as close to the FB pin as possible. VOUT1 C4 R3 R4 EN1 FB1 NC VIN3 VOUT3 AGND C7 24 23 22 21 20 19 VIN1 R2 2 17 PGOOD3 VIN1 3 16 EN3 VIN1 4 15 EN2 VIN1 5 14 PGOOD2 PGND 6 13 FB2 25 7 8 9 10 11 12 VOUT2 C5 PGND NC Keep output capacitor C5 near the IC. VDD1 VIN2 C1 FB3 PHASE1 Put input capacitor as dose as possible to VIN1 and GND pins. 18 PHASE1 R1 1 NC C2 R10 PGOOD1 L1 The PHASE1 trace must be wide and short, keep sensitive components away from this trace. R9 V OUT3 R6 VIN3 R5 VIN2 R8 R7 C6 C3 Input capacitors C3, C4 and output capacitors C6, C7 must be located at a distance of not more than 1cm from RT8023 to GND. Figure 7 www.richtek.com 18 DS8023-03 March 2011 RT8023 Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b 1 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Symbol 1 2 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8023-03 March 2011 www.richtek.com 19