RT9248APC

RT9248A Preliminary Multi-Phase PWM Controller for CPU Core Power Supply General Description Features The RT9248A is a cost-effective multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9248A controls 2 or 3 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. z RT9248A controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using RDS(ON) as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, VCORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. z The DAC output of RT9248A supports VRM9 & VRD10 by VID125 multi-level input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system. z Ordering Information RT9248A Package Type C : TSSOP-28 Operating Temperature Range C : Commercial Standard P : Pb Free with Commercial Standard Note : z z z z z z z Multi-Phase Power Conversion with Automatic Phase Selection VRM9 & VRD10 DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Multi-Level VID125 Input for VRM9 & VRD10 Selection Power Stage Thermal Balance by RDS(ON) Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number RoHS Compliant and 100% Lead (Pb)-Free Applications z z Intel® Processors Voltage Regulator: VRM9 and VRD10 Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules Pin Configurations (TOP VIEW) VID4 VID3 VID2 VID1 VID0 VID125 SGND FB COMP PGOOD DVD SS RT VOSS 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PWM1 PWM2 PWM3 NC ISP1 ISP2 ISP3 ISN GND ADJ VDIF VSEN IMAX TSSOP-28 RichTek Pb-free products are : −RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. −Suitable for use in SnPb or Pb-free soldering processes. −100% matte tin (Sn) plating. DS9248A-04 November 2005 www.richtek.com 1 www.richtek.com 2 R2 2.4k R4 1k R3 9k +12V C2 R1 15k 33pF R5 12k R6 100k C3 0.1uF PG_VCORE < C1 22nF VID125 > VID0 > VID1 > VID2 > VID3 > VID4 > 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VOSS RT SS DVD PGOOD COMP FB SGND VID125 VID0 VID1 VID2 VID3 VID4 IMAX VSEN VDIF ADJ GND ISN ISP3 ISP2 ISP1 NC PWM3 PWM2 PWM1 VCC RT9248A 3k 3k R9 3k R8 R7 R11 12k 15 16 17 18 19 20 R10 1k 21 22 23 24 25 26 27 28 C4 1uF +5V C15 1uF R16 10 D3 1N4148 +12V C10 1uF R14 10 D2 1N4148 +12V C5 1uF R12 10 D1 1N4148 +12V 2 4 1 2 4 1 2 4 1 C11 1uF 6 PGND DRVL 5 VCC C16 1uF 6 PGND DRVL 5 7 VIN VCC 6 PGND DRVL SW 5 7 RT9603 8 BST DRVH VIN SW RT9603 8 BST DRVH VIN SW IPD06N03LA Q6 IPD09N03LA Q5 +12V IPD06N03LA Q4 IPD09N03LA Q3 +12V IPD06N03LA Q2 7 VCC IPD09N03LA RT9603 8 DRVH BST +12V Q1 C6 1uF C7 4.7uF C17 4.7uF C12 4.7uF C19 0.01uF R17 4.7 L3 1uH C18 2200uF C14 0.01uF R15 4.7 L2 1uH C13 2200uF C9 0.01uF R13 1 L1 1uH C8 2200uF C25 to C28 2200uF x 4 C20 to C24 2200uF x 5 VCORE RT9248A Preliminary Typical Application Circuit DS9248A-04 November 2005 Preliminary RT9248A Functional Pin Description VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), VID0 (Pin 5) & VID125 (Pin 6) DAC voltage identification inputs. Tie VID125 to GND for VRM9 or to VCC for VRD10. These pins are internally pulled to 3.3V if left open. VOSS (Pin 14) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. IMAX (Pin 15) Over-Current protection set. SGND (Pin 7) Connect this pin to the return pin of VCORE . VSEN (Pin 16) FB (Pin 8) Power good and over-voltage monitor input. Connect this to the sense pin of VCORE. Inverting input of the internal error amplifier. VDIF (Pin 17) COMP (Pin 9) This pin is being tied to VSEN pin internally. Output of the error amplifier and input of the PWM comparator. ADJ (Pin 18) PGOOD (Pin 10) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop. Power good open-drain output. GND (Pin 19) DVD (Pin 11) IC ground. Programmable power UVLO detection or converter enable input. ISN (Pin 20) SS (Pin 12) RDS(ON) current sense input from anyone of channel sense components' GND node. Connect this SS pin to GND with a capacitor to set the soft-start time interval. ISP1 (Pin 23), ISP2 (Pin 22), ISP3 (Pin 21) RT (Pin 13) RDS(ON) current sense inputs for individual converter channels. Tie this pin to the component's sense node. Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. NC (Pin 24) No internal connection. Frequency vs. RRT 450 PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) 400 PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 2 channels, connect PWM3 high. 350 f OSC(kHz) 300 250 200 VCC (Pin 28) 150 IC power supply. Connect this pin to a 5V supply. 100 50 0 0 10 20 30 40 50 60 70 RRT (k Ω) DS9248A-04 November 2005 www.richtek.com 3 VOSS VSEN Offset Currrent Source/Sink VDIF DAC + Droop FB ERROR AMP COMP PG Trip Point OVP Trip Point + - SGND SS SS Control GAP AMP - + + - DAC ADJ INH GND Power On Reset OCP Setting - + - + - + + - VID0 VID1 VID2 VID3 VID4 VID125 Oscillator & Sawtooth SUM/M Current Correction + + + + + + PWMCP INH PWMCP INH PWMCP INH ISP3 ISP2 ISP1 PWM3 PWM2 PWM1 ISN PWM Logic & Driver PWM Logic & Driver PWM Logic & Driver - + + - RT - + - PGOOD VCC DVD + - + + - www.richtek.com 4 IMAX RT9248A Preliminary Function Block Diagram DS9248A-04 November 2005 RT9248A Preliminary Table 1. Output Voltage Program Pin Name Nominal Output Voltage DACOUT VID4 VID3 VID2 VID1 VID0 VID125 = H VID125 = L 1 1 1 1 1 No CPU No CPU 0 1 0 0 1 0.850V 1.625V 0 1 0 0 0 0.875V 1.650V 0 0 1 1 1 0.900V 1.675V 0 0 1 1 0 0.925V 1.700V 0 0 1 0 1 0.950V 1.725V 0 0 1 0 0 0.975V 1.750V 0 0 0 1 1 1.000V 1.775V 0 0 0 1 0 1.025V 1.800V 0 0 0 0 1 1.050V 1.825V 0 0 0 0 0 1.075V 1.850V 1 1 1 1 0 1.100V 1.100V 1 1 1 0 1 1.125V 1.125V 1 1 1 0 0 1.150V 1.150V 1 1 0 1 1 1.175V 1.175V 1 1 0 1 0 1.200V 1.200V 1 1 0 0 1 1.225V 1.225V 1 1 0 0 0 1.250V 1.250V 1 0 1 1 1 1.275V 1.275V 1 0 1 1 0 1.300V 1.300V 1 0 1 0 1 1.325V 1.325V 1 0 1 0 0 1.350V 1.350V 1 0 0 1 1 1.375V 1.375V 1 0 0 1 0 1.400V 1.400V 1 0 0 0 1 1.425V 1.425V 1 0 0 0 0 1.450V 1.450V 0 1 1 1 1 1.475V 1.475V 0 1 1 1 0 1.500V 1.500V 0 1 1 0 1 1.525V 1.525V 0 1 1 0 0 1.550V 1.550V 0 1 0 1 1 1.575V 1.575V 0 1 0 1 0 1.600V 1.600V Note: (1) 0: Connected to GND (2) 1: Open (3) For VID125, H: VCC, L: GND DS9248A-04 November 2005 www.richtek.com 5 RT9248A Preliminary Absolute Maximum Ratings z z z z z z z (Note 1) Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Package Thermal Resistance TSSOP-28, θJA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z 7V GND-0.3V to VCC+0.3V 45°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 3) Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V ± 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units -- 12 -- mA 4.0 4.2 4.5 V 0.2 0.5 -- V 0.9 1.0 1.1 V -- 70 -- mV 170 200 230 kHz 50 -- 400 kHz -- 1.9 -- V -- 1.0 -- V 62 66 75 % 0.94 1.0 1.06 V VRD10, VDAC ≥ 1V −1 -- +1 % VRD10, VDAC < 1V −10 -- +10 mV VRM9 −1 -- +1 % VCC Supply Current Nominal Supply Current ICC PWM 1,2,3 Open POR Threshold VCCRTH VCC Rising Hysteresis VCCHYS Power-On Reset VDVD Threshold Trip (Low to High) VDVDTP Hysteresis VDVDHYS Enable Oscillator Free Running Frequency fOSC Frequency Adjustable Range fOSC_ADJ Ramp Amplitude ΔVOSC Ramp Valley VRV RRT = 12kΩ RRT = 12kΩ Maximum On-Time of Each Channel RT Pin Voltage VRT RRT = 12kΩ Reference and DAC DACOUT Voltage Accuracy DACOUT Voltage Accuracy ΔVDAC_10 ΔVDAC_9 To be continued www.richtek.com 6 DS9248A-04 November 2005 RT9248A Preliminary Parameter Symbol Test Conditions Min Typ Max Units DAC (VID0-VID4) Input Low VILDAC -- -- 0.4 V DAC (VID0-VID4) Input High VIHDAC 0.8 -- -- V VID125 Input for VRM9 VVID125_9 -- -- 0.4 V VID125 Input for VRD10 VVID125_10 0.8 -- -- V DAC (VID0-VID125) Bias Current IBIAS_DAC 35 50 65 μA VOSS Pin Voltage VVOSS 0.95 1.0 1.15 V -- 85 -- dB -- 10 -- MHz -- 3 -- V/μs RVOSS = 100kΩ Error Amplifier DC Gain Gain-Bandwidth Product GBW Slew Rate SR COMP = 10pF Current Sense GM Amplifier ISP 1,2,3 Full Scale Source Current IISPFSS 60 -- -- μA ISP 1,2,3 Current for OCP IISPOCP 90 -- -- μA 0.94 1.0 1.06 V -- 13 -- μA -- 140 -- % Protection IMAX Voltage VIMAX RIMAX = 10k SS Current ISS VSS = 1V Over-Voltage Trip (VSEN/DACOUT) ΔOVT Power Good Lower Threshold (VSEN/DACOUT) VPG− VSEN Rising -- 92 -- % Output Low Voltage VPGL IPG = 4mA -- -- 0.2 V Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. DS9248A-04 November 2005 www.richtek.com 7 RT9248A Preliminary Application Information RT9248A is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9248A and its companion MOSFET driver provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT9248A senses the CPU V CORE by an precise instrumental amplifier to minimize the voltage drop on PCB trace at heavy load. VSEN & SGND are the differential inputs. VDIF is the output node of the differential voltage & the input for PGOOD & OVP sense. The internal high accuracy VID DAC allows selection of either VRM9 or VRD10 compliance via VID125 pin setting. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. Like conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal VC of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9248A senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals then produces the balancing signals injected to pulse width modulator. If the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. Fault Detection The chip detects VCORE for over voltage and power good detection. The “hiccup mode” operation of over-current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT9248A interfaces with companion MOSFET drivers (like RT9600, RT9602 or RT9603 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) pins sense the interface voltage at IC POR period (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Please tie the PWM output to VCC and the current sense pins to GND or left floating if the channel is unused. For 2-Channel application, connect PWM3 high. Current Sensing Setting RT9248A senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 1). Be careful to choose GND sense input, ISN, of the GM amplifier for effective channel current balance. IX 1 < < < The sensed power channel current signals regulate the reference of DAC to form a output voltage droop proportional to the load current. The droop or so-called “active voltage positioning” can reduce the output voltage ripple at load transient and the LC filter size. D ro o p T u n e IX 2 IX IX IB P S a m p le & H o ld GM + IS P 1 R SP1 RS IL RS IL RS IL IB N O v e r-C u rre n t D e te c tio n IX 2 < Load Droop C u rre n t B a la n c e < < C u rre n t B a la n c e D ro o p T u n e IX 2 IX IX IB P S a m p le & H o ld GM + IB N O v e r-C u rre n t D e te c tio n IS P 2 R SP2 IS N RSN G N D R e tu rn IX 3 < < < C u rre n t B a la n c e D ro o p T u n e IX 2 IX IX O v e r-C u rre n t D e te c tio n S a m p le & H o ld IB P GM + IS P 3 R SP3 IB N Figure 1. Current Sense Circuit www.richtek.com 8 DS9248A-04 November 2005 RT9248A Preliminary I L × RS by local feedback. RSP RSP = 3 x RSN (at 3 phase operation) to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore, The sensing circuit gets IX = I L (S/H) × R S V O T OFF × , , I L (S/H) = I L (AVG) − 2 R SP L ⎡ V IN − V O ⎤ = ⎢ ⎥ × 5uS for fosc = 200kHz V IN ⎣ ⎦ I X (S/H) = T OFF I X (S/H) ⎡ ⎤ ⎡ V IN − V O ⎤ VO − ⎢ ⎢ ⎥ × 5uS ⎥ RS IN V ⎣ ⎦ ⎥× = ⎢I L(AVG) − 2L ⎢ ⎥ R SP ⎢ ⎥ ⎣ ⎦ Falling Slope = Vo/L IL IL(AVG) IL(S/H) Inductor Current Protection and SS Function For OVP, the RT9248A detects the VCORE by VDIF pin voltage of the differential amplifier output. Eliminate the delay due to compensation network (compared to sensing FB voltage) for fast and accurate detection. The trip point of OVP is 140% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VCC or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 92% lower than the normal level. The PGOOD open drain output pulls low when VCORE is lower than the trip point. For VID jumping issue, only power fail conditions (VCC & DVD are lower than trip point or OVP) reset the output low. Soft-start circuit generates a ramp voltage by charging external capacitor with 13μA current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the inrush current and protect the power devices. PWM Signal & High Side MOSFET Gate Signal Over-current protection trip point is set by the resistor RIMAX connected to IMAX pin. OCP is triggered if one channel ⎛ 0 .6 V ⎞ ⎟ × 1 .4 . Controller forces ⎝ R IMAX ⎠ S/H current signal IX > ⎜ Low Side MOSFET Gate Signal Figure 2. Inductor Current and PWM Signal DAC Offset Voltage & Droop Tuning The DAC offset voltage is set by compensation network ⎛ 1V ⎞ R f 1 & VOSS pin external resistors by ⎜ R VOSS ⎟ × 4 . ⎝ ⎠ The S/H current signals from power channels are injected to ADJ pin to create droop voltage. VADJ = RADJ× 2 IX ∑ The DAC output voltage decreases by VADJ to form the VCORE load droop (see Figure 3). + Current Source ∑ 2IX1 S.S Count ==22 COUNT Count ==33 COUNT Count ==11 COUNT VCORE 0V Overload Applied 2IX2 2IX3 > ILOAD 1 IVOSS 4 > 0A RVOSS - VOSS + IVOSS 1V = RVOSS + EA - - COMP VDAC VADJ PWM output latched at high impedance to turn off both high and low side MOSFETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13μA current after it is less than 90% VCC. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4). FB ADJ RF1 RADJ > VCORE T0,T1 T3,T4 T2 TIME Figure 4. Figure 3. DAC Offset Voltage & Droop Tune Circuit DS9248A-04 November 2005 www.richtek.com 9 RT9248A Preliminary 3-Phase Converter and Components Function Grouping 12V VCC BST DRVH SW RT9603 IN DRVL PGND SGND VSEN VDIF PWM1 12V VID ISP1 PGOOD VCC RT9248A Compensation & Offset BST DRVH VCORE SW COMP FB RT9603 PWM2 IN DRVL PGND ADJ Droop Setting ISP2 ISN 12V Driver Power UVLO DVD 12V VOSS ISP3 SS DAC Offset Voltage Setting VCC PWM3 IMAX SW GND OCP Setting BST DRVH RT9603 IN DRVL PGND Current Sense Components Design Procedure Suggestion Voltage Loop Setting a. Output filter pole and zero (Inductor, output capacitor value & ESR). b. Error amplifier compensation & sawtooth wave amplitude (compensation network). c. Kelvin sense for VCORE. VRM Load Line Setting a. Droop amplitude (ADJ pin resistor). b. No load offset (additional resistor in compensation network). c. DAC offset voltage setting (VOSS pin & compensation network resistor). Current Loop Setting a. GM amplifier S/H current (current sense component RDS(ON), ISPx & ISN pin external resistor value, keep ISPx current < 60μA at full load condition for better load line linearity). b. Over-current protection trip point (IMAX pin resistor, keep ISPx current < 90μA at OCP condition for precision issue). Power Sequence & SS DVD pin external resistor and SS pin capacitor. www.richtek.com 10 PCB Layout a. Kelvin sense for current sense GM amplifier input. b. Refer to layout guide for other item. DS9248A-04 November 2005 RT9248A Preliminary Design Example Asymptotic Bode Plot of PWM Loop Gain 100 Given: 80 Apply for three phase converter 60 VCORE = 1.5V 40 Gain (dB) VIN = 12V ILOAD (max) = 60A VDROOP = 120mV at full load OCP trip point set at 30A for each channel (S/H) RDS(ON) = 6mΩ of low side MOSFET at 27°C Uncompensated EA Gain 20 0 Compensated EA Gain -20 PWM Loop Gain -40 L = 2μH Modulator Gain -60 10 10 COUT = 9,000μF with 2mΩ ESR. 100 100 1K 1000 10K 10000 100K 100000 1M 10M 1000000 10000000 Frequency (Hz) 1. Compensation Setting a. Modulator Gain, Pole and Zero: Figure 6. From the following formula: V IN 12V Modulator Gain = = = 4.2 (12.46dB) V RAMP 1.9V × 3 2. Droop & DAC Offset Setting For each channel the load current is 60A / 3 = 20A and the ripple current, ΔIL, is given as: 2 5us x where VRAMP : ramp amplitude of sawtooth wave 1 LC Filter Pole = 2π x LC = 1.2kHz and ESR Zero = 1 2π x ESR x COUT C1 = 8.8kHz R3 C2 C3 R1 > VDIF COMP FB + R3,C3 are used in type 3 compensation scheme (left NC in type 2) DACOUT Figure 5. From the following formulas: 1 1 FZ = , FP = 2π x R 2 x C 1 ⎛ C1 × C 2 ⎞ 2π x R 2 x ⎜ ⎟ R2 ⎝ C1 + C 2 ⎠ Middle Band Gain = R1 By calculation, the FZ = 1kHz, FP = 200kHz and Middle Band Gain is 10 (i.e 20dB). The asymptotic bode plot of EA compensation and PWM loop gain is shown as Figure 6. DS9248A-04 November 2005 ΔIL = 18.36 A . 2 Using the following formula to select the appropriate IX (MAX) for the S/H of GM amplifier: R DS(ON) × 18.36A I X (MAX) = R SP The suggested IX is in the order of 40 to 50μA, select RSP = 2.4kΩ then IX (MAX) will be 45.9μA. VDROOP = 120mV = 45.9μA × 2 × 3 (phase no.) × RADJ, therefore RADJ will be 435Ω. The RDS(ON) of MOSFET varies with temperature rise. When the low side MOSFET working at 70°C and 5000ppm/°C temperature coefficient of RDS(ON), the RDS(ON) at 70°C is given as: 6mΩ × {1+ (70°C − 27°C) × 5000ppm/°C} = 7.3mΩ. RADJ at 70°C is given as: RADJ_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 358Ω The load current, IL, at S/H is 20 A − b. EA Compensation Network: Select R1 = 2.4kΩ, R2 = 24kΩ, C1 = 6.6nF, C2 = 33pF and use the type 2 compensation scheme shown in Figure 5. R2 1.5V ⎛ 1.5V ⎞ x ⎜1 − ⎟ = 3.28A 2uH ⎝ 12V ⎠ 3. Over-Current Protection Setting OCP trip point set at 30A for each channel, IX = RDS(ON) × 30A 0.6V = 1.4 × , RIMAX = 11.2kΩ RSP RIMAX Take the temperature rise into account, the RIMAX at 70°C will be: RIMAX_27°C × (RDS(ON)_27°C / RDS(ON)_70°C) = 9.2kΩ 4. Soft-Start Capacitor Selection CSS = 0.1μF is the suitable value for most application. www.richtek.com 11 RT9248A Preliminary Layout Guide Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ISN should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate stable current sensing. Keep well Kelvin sense to ensure the stable operation! 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path. SW1 L1 VOUT VIN RIN COUT CIN RL V L2 SW2 Figure 7. Power Stage Ripple Current Path www.richtek.com 12 DS9248A-04 November 2005 RT9248A Preliminary Next to IC +12V CBP +12V or +5V PWM VCC IN BST VOSS DRVH LO1 SW RT9603 CBP IMAX CBOOT +5VIN VCC VCORE CC RT9248A COUT CIN DRVL Kelvin Sense PGND Next to IC COMP RSP Locate next to FB Pin FB ISPx ISN RFB RSN Locate near MOSFETs RC VSEN ADJ GND For Thermal Couple Figure 8. Layout Consideration DS9248A-04 November 2005 www.richtek.com 13 RT9248A Preliminary Outline Dimension D L E1 E e A2 A A1 b Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.850 1.200 0.033 0.047 A1 0.050 0.152 0.002 0.006 A2 0.800 1.050 0.031 0.041 b 0.178 0.305 0.007 0.012 D 9.601 9.804 0.378 0.386 e 0.650 0.026 E 6.300 6.500 0.248 0.256 E1 4.293 4.496 0.169 0.177 L 0.450 0.762 0.018 0.030 28-Lead TSSOP Plastic Package RICHTEK TECHNOLOGY CORP. RICHTEK TECHNOLOGY CORP. Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com www.richtek.com 14 DS9248A-04 November 2005