RT9470WSC

RT9470/D 3A Single Cell Switching Battery Charger General Description Features The RT9470/D device are a highly-integrated 3A switch mode battery charge management and system power path management device for single cell Li-Ion and Li-polymer battery. The low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution.  Applications    Smart Phone/Tablet PC Personal Information Appliances Portable Device and Accessory  Ordering Information RT9470/D Package Type WSC : WL-CSP-30B 2.1x2.5 (BSC)  BC1.2 Detection Default : Not Support D : Support Note : Richtek products are :  RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering High Efficiency, 1.5MHz, Synchronous Switch-Mode Buck Charger  92% Charge Efficiency at 2A from 5V Input and 3.8V Battery  Support 3.9V to 13.5V Input Voltage Range  Average Input Current Regulation (AICR)  Minimum Input Voltage Regulation (MIVR)  Minimum Input Voltage Regulation Track (MIVR Track)  Charge Current Regulation (CCR)  Charge Voltage Regulation (CVR)  Charge Voltage Regulation Track (CVR Track)  Junction Thermal Regulation (JTR) Supports USB On-The-Go (OTG)  92% Boost Efficiency at 1A with 3.8V Battery and 5.15V Output  OTG Current Limit Regulation (OCLR)  OTG Voltage Limit Regulation (OVLR) Protection  Over-Temperature Protection (OTP)  VBUS Over-Voltage Protection (VBUS OVP)  Battery Over-Voltage Protection (VBAT OVP)  System Over-Voltage Protection (VSYS OVP)  System Under-Voltage Protection (VSYS UVP)  System Over-Load Protection (VSYS OLP)  Cycle-by-Cycle Over-Current Protection (OCP)  OTG Low Battery Protection (OTG LBP) processes. Simplified Application Circuit RT9470/D USB CBUS VAC VBUS BTST SW PMID CBTST System L CSYS SYS BAT CBAT QON REGN 2 I C BUS Host Host control Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 TS Battery Pack is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9470/D Marking Information RT9470WSC RT9470DWSC 1N : Product Code YMDNN : Date Code 1N YM DNN 1P : Product Code YMDNN : Date Code 1P YM DNN Pin Configuration (TOP VIEW) A1 GND A2 SW A3 A4 A5 A1 PMID VBUS VAC GND A2 SW A3 A4 A5 PMID VBUS VAC B1 B2 B3 B4 B5 B1 B2 B3 B4 B5 GND SW PMID VBUS NC GND SW PMID VBUS NC C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 BAT SYS BTST REGN PSEL BAT SYS BTST REGN D+ D1 D2 D3 D4 D5 D1 SYS TS QON PG BAT E1 E2 E3 E4 E5 BAT SYS CE SDA STAT BAT D2 D3 D4 D5 SYS TS QON D- E1 E2 E3 E4 E5 BAT SYS CE SDA STAT F1 F2 F3 F4 F5 F1 F2 F3 F4 F5 BAT SYS BATSNS INT SCL BAT SYS BATSNS INT SCL WL-CSP-30B 2.1x2.5 (BSC) (RT9470) WL-CSP-30B 2.1x2.5 (BSC) (RT9470D) Functional Pin Description Pin No. RT9470 RT9470D A1, B1 A1, B1 Pin Name GND I/O Pin Function P Power ground. A2, B2 A2, B2 SW P Switching node connecting to output inductor. Internally SW is connected to the source of the high-side switching MOSFET (Q2) and the drain of the low-side switching MOSFET (Q3). Connect a 47nF bootstrap capacitor from SW to BTST. A3, B3 A3, B3 PMID P Connected to the drain of the reverse blocking MOSFET (Q1) and the drain of high-side switching MOSFET (Q2). Connect 10F capacitor from PMID to GND. VBUS P Charger input voltage. The internal reverse block MOSFET (Q1) is connected between VBUS and PMID with VBUS on source. Connect a 1F capacitor from VBUS to GND and place it as close as possible to IC. A4, B4 A4, B4 A5 A5 VAC AI Input voltage sensing. This pin must be tied to VBUS. B5 B5 NC -- No internal connection. Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Pin No. I/O Pin Function C1, D1, E1, F1 C1, D1, E1, F1 BAT P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10F capacitor closely to the BAT pin. C2, D2, E2, F2 C2, D2, E2, F2 SYS P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect two 10F capacitors closely to the SYS pin. P PWM high-side driver positive supply. Internally, the BTST is connected to the cathode of the boost-strap diode. Connect the 47nF bootstrap capacitor from SW to BTST. P PWM low-side driver and internal supply output. Internally, REGN is connected to the anode of the bootstrap diode. Connect a 4.7F capacitor from REGN to GND. The capacitor should be placed close to the IC. DI Power source selection input. High indicates 0.5A input current limit. Low indicates 2.4A input current limit. Once the device gets into host mode, the host can program different input current limit to AICR register. RT9470 RT9470D C3 C3 C4 C4 C5 -- -- C5 D3 D3 D4 D4 D5 -- Pin Name BTST REGN PSEL D+ Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data AIO contact detection (DCD), primary and secondary detections in BC1.2. TS AI Temperature qualification voltage input to support JEITA profile. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin voltage is out of range. When TS pin is not used, connect a 10k resistor from REGN to TS and a 10k resistor from TS to GND. QON DI BATFET (Q4) enable control input. When BATFET is in ship mode, a logic low duration turns on BATFET (Q4) to exit shipping mode. When no VBUS, a logic low for tQON_RST, the BATFET turns off for tBATFET_RST, and then re-enable BATFET to provide system reset. Pull-High to internal bias circuit via 250k resistor. PG DO Open-drain active low power good indicator. Connect the PG pin to a logic rail via 2.2k to 10k resistor. Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes AIO data contact detection (DCD), primary and secondary detections in BC1.2. -- D5 D- E3 E3 CE E4 E4 E5 E5 DI Charge enable pin. When this pin is driven low, battery charging is enabled. SDA DIO I2C interface clock. Connect SDA to the logic rail through a 10k resistor. STAT DO Open-drain charger status output. Connect the STAT pin to a logic rail via 2.2k to 10k resistor. The STAT pin indicates charger status. Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9470/D Pin No. RT9470 RT9470D F3 F3 Pin Name BATSNS I/O Pin Function AI Battery voltage sensing pin for charge current regulation. The BATNS pin must be connected to the battery pack as close as possible. F4 F4 INT DO Open-drain active low interrupt output. Connect the INT to a logic rail through 10k resistor. The INT pin sends active low pulse to host to report charger device status and fault. F5 F5 SCL DI I2C interface clock. Connect SCL to the logic rail through a 10k resistor. Functional Block Diagram RT9470 Functional Block Diagram Q1 VBUS VAC PSEL PMID PMID BAT Sensing Input Source Detection Q1 Control Power Select REGN LDO REGN BTST Q2 SDA 2 I C Interface Protection SCL Converter Control SW REGN Q3 INT CE GND Digital Control REGN SYS STAT Q4 JEITA Control Power Path Control Q4 Switchingwell Control BAT PG VDDA BATSNS TS Sensing QON TS Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D RT9470D Functional Block Diagram Q1 VBUS PMID PMID BAT Sensing VAC D+ Input Source Detection D- Q1 Control Power Select REGN LDO REGN BTST Q2 SDA 2 I C Interface Protection SCL Converter Control SW REGN Q3 INT CE GND Digital Control REGN SYS STAT Q4 JEITA Control Power Path Control Q4 Switchingwell Control BAT VDDA BATSNS TS Sensing QON TS Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9470/D Absolute Maximum Ratings (Note 1)  Voltage Sense Pin Voltage, VAC --------------------------------------------------------------------------------- 1.4V to 22V  Supply Pin Voltage, VBUS ----------------------------------------------------------------------------------------- 1.4V to 22V  Terminal Pin Voltage, PMID --------------------------------------------------------------------------------------- 0.3V to 22V  Terminal Pin Voltage, SW ------------------------------------------------------------------------------------------ 0.3V to 16V  Terminal Pin Voltage, BTST-SW --------------------------------------------------------------------------------- 0.3V to 6V  Terminal Pin Voltage, SYS ----------------------------------------------------------------------------------------- 0.3V to 6V  Supply Pin Voltage, BAT ------------------------------------------------------------------------------------------- 0.3V to 6V  Voltage Sense Pin Voltage, BATSNS --------------------------------------------------------------------------- 0.3V to 6V  Other Pins Voltage, STAT, SCL, SDA, INT, CE, TS, QON, REGN -------------------------------------- 0.3V to 6V  Other Pins Voltage for RT9470, PSEL, PG ------------------------------------------------------------------ 0.3V to 6V  Other Pins Voltage for RT9470D, D+, D- --------------------------------------------------------------------- 0.3V to 6V  Power Dissipation, PD @ TA = 25C WL-CSP-30B 2.1x2.5 (BSC) --------------------------------------------------------------------------------------- 4.22W  Package Thermal Resistance (Note 2) WL-CSP-30B 2.1x2.5 (BSC), JA---------------------------------------------------------------------------------- 29.6C/W  Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C  Junction Temperature ------------------------------------------------------------------------------------------------ 150C  Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C  ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4)  Voltage Sense Pin Voltage, VAC --------------------------------------------------------------------------------- 3.9V to 13.5V  Supply Input Voltage Range, VBUS ----------------------------------------------------------------------------- 3.9V to 13.5V  Maximum Input Current, IBUS ------------------------------------------------------------------------------------ 3.2A  Maximum Input Current, IBUS (VBUS  12V) ----------------------------------------------------------------- 2A  Maximum Output Current (SW), ISYS -------------------------------------------------------------------------- 3.2A  Maximum Battery Voltage, VBAT -------------------------------------------------------------------------------- 4.7V  Voltage Sense Pin Voltage, BATSNS --------------------------------------------------------------------------- 4.7V  Maximum Charge Current, IBAT --------------------------------------------------------------------------------- 3.15A  Maximum Discharge Current, IBAT ------------------------------------------------------------------------------ 6A  Ambient Temperature Range ------------------------------------------------------------------------------------- 40C to 85C  Junction Temperature Range ------------------------------------------------------------------------------------- 40C to 150C Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Electrical Characteristics (VBUS_MIN_RISE < VAC < VAC_OVP_RISE and VAC > VBAT + VSLEEP_RISE, TA = 25C, unless otherwise specified) Parameter Symbol (Note 5) Test Conditions Min Typ Max Unit Quiescent Current Battery Discharge Current (BAT) in Q4 Disabled IBAT_Q4_DIS VBAT = 4.5V, High-Z mode and I2C disabled, Q4 disabled -- 15 32 A Battery Discharge Current (BAT) in Q4 Enable IBAT_Q4_EN VBAT = 4.5V, High-Z mode and I2C disabled, Q4 enabled -- 55 85 A VBUS = 5V, High-Z mode and no battery -- 50 86 VBUS = 12V, High-Z mode and no battery -- 52 88 Input Supply Current (VBUS) in Buck Mode IBUS_HIZ Input Supply Current (VBUS) in Buck Mode IBUS_BUCK VBUS > VBUS_MIN_RISE, VBUS > VBAT, converter switching, VBAT = 3.8V, ISYS = 0A -- 5 7 mA Battery Discharge Current (BAT) in Boost Mode IBAT_BOOST VBAT = 4.2V, boost mode, IBUS = 0A, converter switching -- 4 5 mA A VAC, VBUS and BAT Power VBUS Operating Range VBUS_OP VBUS rising 3.9 -- 13.5 V REGN Turn Off Level with Only VBUS VBUS_UVLO VBUS falling 3.0 3.3 3.6 V Sleep Mode Falling Threshold VSLEEP_FALL VAC falling, VAC – VBAT 10 60 120 mV Sleep Mode Rising Threshold VSLEEP_RISE VAC rising, VAC – VBAT 160 250 340 mV VAC 5.8V Over-Voltage rising threshold VAC rising 5.5 5.8 6.1 VAC 6.5V Over-Voltage rising threshold VAC rising 6.2 6.5 6.8 VAC rising 10.3 10.9 11.5 VAC 14V Over-Voltage Rising Threshold VAC rising 13.3 14 14.7 VAC 5.8V Over-Voltage Hysteresis VAC falling -- 300 -- VAC falling -- 300 -- VAC 10.9V Over-Voltage Rising Threshold VAC 6.5V Over-Voltage Hysteresis VAC 10.9V Over-Voltage Hysteresis VAC_OVP_RISE VAC_OVP_HYS VAC 14V Over-Voltage Hysteresis BAT for Active I2C, No Adapter V VBAT_UVLO mV VAC falling -- 300 -- VAC falling -- 300 -- VBAT rising 2 2.2 2.4 Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 V is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9470/D Parameter Symbol Test Conditions Min Typ Max Unit Battery Depletion Falling Threshold VBAT_DPL_FALL VBAT falling 2.15 2.38 2.65 V Battery Depletion Rising Threshold VBAT_DPL_RISE VBAT rising 2.4 2.6 2.8 V Battery Depletion Rising Hysteresis VBAT_DPL_HYS VBAT rising -- 220 -- mV Bad Adapter Detection Rising Threshold VBUS_MIN_RISE VBUS rising 3.6 3.8 4 V Bad Adapter Detection Hysteresis VBUS_MIN_HYS VBUS falling -- 200 -- mV Bad Adapter Detection Current Source IBADSRC Sink current from VBUS to GND -- 40 -- mA VSYS_MIN VBAT < VSYS_MIN = 3.5V, Q4 disabled/enable 3.5 3.5 +0.2 -- VSYS ISYS = 0A, VBAT > VSYS_MIN = 3.5V, Q4 disabled -- VBAT +0.05 -- Top Reverse Blocking MOSFET On-Resistance RON(Q1) Between VBUS and PMID 40°C ≤ TA ≤ 125°C -- 29 -- m Top Switching MOSFET On- Resistance Between RON(Q2) PMID and SW VREGN = 5V, 40°C ≤ TA ≤ 125°C -- 46 -- m Bottom Switching MOSFET On-Resistance RON(Q3) Between SW and GND VREGN = 5V, 40°C ≤ TA ≤ 125°C -- 51 -- m SYS-BAT MOSFET On-Resistance RON(BAT-SYS) Measured from BAT to SYS, VBAT = 4.2V, TJ = 25°C -- 14 -- m Charge Voltage Range VBAT_REG_RANGE Default = 4.2V 3.9 -- 4.7 V Charge Voltage Step VBAT_REG_STEP -- 10 -- mV Charge Voltage Setting Accuracy VBAT_REG_ACC –0.5 -- 0.5 % Charge Current Regulation Range ICHG_REG_RANGE 0 -- 3150 mA Charge Current Regulation Step ICHG_REG_STEP -- 50 -- mA VBAT = 3.8V, ICHG_REG < 150mA –20 -- 20 VBAT = 3.8V, 150mA ≤ ICHG_REG < 750mA –10 -- 10 VBAT = 3.8V, ICHG_REG ≥ 750mA –5 -- 5 Power Path System Regulation Voltage V Battery Charger Charge Current Regulation Accuracy ICHG_REG_ACC Default = 2000mA % Pre-Charge Falling Threshold VPRE_CHG_FALL ICHG = 200mA, VPRE_CHG = 3.1V 2.75 2.9 3.05 V Pre-Charge Rising Threshold VPRE_CHG_RISE Pre-charge to fast charge, VPRE_CHG = 3.1V 2.95 3.1 3.25 V Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Parameter Symbol Pre-Charge Current Range IPRE_CHG_RANGE Test Conditions Default = 150mA Pre-Charge Current Step IPRE_CHG_STEP Min Typ Max Unit 50 -- 800 mA -- 50 -- mA Pre-Charge Accuracy IPRE_CHG_ACC VBUS = 5V, IPRE_CHG = 150mA –15 -- 25 % End-Of-Charge Current Range IEOC_CHG_RANGE Default = 200mA 50 -- 800 mA End-Of-Charge Current Step IEOC_CHG_STEP -- 50 -- mA ICHG_REG > 700mA, IEOC_CHG = 200mA, VBAT = 4.2V 20 -- 20 ICHG_REG ≤ 700mA, IEOC_CHG = 200mA, VBAT = 4.2V 10 -- 10 ICHG_REG = 600mA, IEOC_CHG = 50mA, VBAT = 4.2V 25 -- 25 VBAT falling 1.8 2 2.2 V VBAT rising 2.05 2.25 2.45 V VBAT < VTRICKLE_CHG_RISE 80 100 120 mA VBAT falling, VRECHG = 100mV 70 100 130 VBAT falling, VRECHG = 200mV 170 200 230 -- 30 -- mA 3.9 -- 5.4 V -- 100 -- mV 1.5 -- 1.5 % -- 4.3 -- V 3 -- 3 % 0.05 -- 3.2 A -- 50 -- mA VBUS = 5V, IAICR = 500mA 450 470 500 VBUS = 5V, IAICR = 900mA 780 840 900 VBUS = 5V, IAICR = 1500mA 1300 1400 1500 VBUS = 5V, IAICR > 1500mA 15 -- 0 End-Of-Charge Accuracy IEOC_CHG_ACC Trickle-Charge Falling Threshold VTRICKLE_CHG_ Trickle-Charge Rising Threshold VTRICKLE_CHG_ Trickle-Charge Current ITRICKLE_CHG Re-Charge Threshold Below VBAT_REG VRE_CHG System Discharge Load Current ISYS_LOAD FALL RISE VSYS = 4.2V % mV Input Voltage and Current Regulation Minimum Input Voltage Regulation Range VMIVR_RANGE Minimum Input Voltage Regulation Step VMIVR_STEP Minimum Input Voltage Regulation Accuracy VMIVR_ACC VMIVR = 3.9V and 4.4V MIVR Tracking VBAT VMIVR_BAT_TRACK VMIVR = 3.9V, VMIVR_BAT_TRACK = 300mV, VBAT = 4V MIVR Tracking VBAT Accuracy VMIVR_BAT_TRACK _ACC Average Input Current Regulation Range IAICR_RANGE Average Input Current Regulation Step IAICR_STEP Average Input Current Regulation Accuracy Default = 4.5V IAICR_ACC Default = 0.5A mA % BAT Over-Voltage Protection Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9470/D Parameter Symbol Test Conditions Min Typ Max Unit Battery Over-Voltage Rising VBAT_OVP_RISE VBAT rising, as percentage of VBAT_REG 103 104 105 % Battery Over-Voltage Falling VBAT_OVP_FALL VBAT falling, as percentage of VBAT_REG 101 102 103 % 100 -- 120 °C -- 20 -- °C Input Reverse Blocking NFET and Regulation Junction Thermal Regulation Range TJ_THREG_RANGE Junction Thermal Regulation Step TJ_THREG_STEP Thermal Shutdown Rising TOTP Temperature rising -- 160 -- °C Thermal Shutdown Hysteresis TOTP_HYS Temperature falling -- 30 -- °C Default = 120°C NTC Monitor (Charger Mode) Battery Temperature COLD Threshold (0°C) VVTS_COLD VTS rising, the ratio of VREGN 72.5 73.5 74.5 % Battery Temperature COOL Threshold (10°C) VVTS_COOL VTS rising, the ratio of VREGN 67.5 68.5 69.5 % Battery Temperature VVTS_WARM WARM Threshold (45°C) VTS falling, the ratio of VREGN 44 45 46 % Battery Temperature HOT Threshold (60°C) VVTS_HOT VTS falling, the ratio of VREGN 33.5 34.5 35.5 % Battery Temperature Hysteresis VVTS_HYS -- 1.5 -- % NTC Monitor (OTG Mode) Battery Temperature COLD Threshold OTG mode (20°C) VVTS_COLD_OTG VTS rising, the ratio of VREGN 79 80 81 % Battery Temperature HOT Threshold OTG mode (60°C) VVTS_HOT_OTG VTS falling, the ratio of VREGN 33.5 34.5 35.5 % Battery Temperature Hysteresis OTG mode VVTS_HYS_OTG -- 1.5 -- % 5.5 6.5 7.5 A 6 -- -- A VBAT falling, VOTG_LBP = 2.8V 2.65 2.8 2.95 VBAT rising, VOTG_LBP = 2.8V 2.75 2.9 3.05 VBAT falling, VOTG_LBP = 2.5V 2.35 2.5 2.65 VBAT rising, VOTG_LBP = 2.5V 2.45 2.6 2.75 Charger Over-Current Threshold UGFET Cycle-by-Cycle Over-Current Threshold IOCP_UG System Over-Load Threshold IOCP_BATFET USB On-The-Go (OTG) OTG Low Battery Protection VOTG_LBP Copyright © 2019 Richtek Technology Corporation. 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DS9470/D-01 August 2019 RT9470/D Parameter Symbol Test Conditions Min Typ Max Unit 4.85 -- 5.3 V -- 150 -- mV VBAT = 3.8V, IPMID = 0A, VOTG_REG = 5.15V 3 -- 3 % IOTG_LIMIT_REG_SEL = 1.2A 1.2 1.4 1.6 IOTG_LIMIT_REG_SEL = 0.5A 0.5 0.6 0.7 6.2 6.5 6.8 V F OTG Voltage Limit Regulation Range VOTG_CV_RANGE OTG Voltage Limit Regulation Step VOTG_CV_STEP OTG Voltage Limit Regulation Accuracy VOTG_CV_ACC OTG Current Limit Regulation Accuracy IOTG_CC OTG Over-Voltage Threshold VOTG_OVP VAC rising, VAC_OVP = 6.5V OTG Capacitive Load COTG_LOAD VBAT = 3.8V, VOTG_REG = 5.15V, capacitive load plug in -- -- 300 fSW_BUCK Oscillator frequency, buck mode 1350 1500 1650 fSW_BOOST Oscillator frequency, boost mode 1350 1500 1650 -- 97 -- VBUS = 9V, IREGN = 40mA 4.5 4.9 5.3 VBUS = 5V, IREGN = 20mA 4.5 4.9 5 Default = 5.15V A PWM PWM Switching Frequency Maximum PWM Duty Cycle DMAX kHz % REGN REGN LDO Output Voltage VREGN V Control I/O Pin (CE, PSEL, SCL and SDA) Input High Threshold Voltage VIH_CTRL 1.3 -- -- V Input Low Threshold Voltage VIL_CTRL -- -- 0.4 V High Level Leakage Current IBIAS -- -- 1 A -- -- 0.4 V -- 256 -- s 0.25 0.325 0.4 V Pull high to 1.8V Control I/O Pin (PG, STAT and INT) Output Low Threshold Voltage VOL_CTRL INT Pull Low Time tINT_PULL_LOW INT pull low time D+/D- Detection Data Detect Voltage VDAT_REF D- Current Sink ID-_ISNK 50 100 150 A D+D- Leakage Current ID+D-_LKG 1 -- 1 A D- Pull Down for Connection Check RD-_19K 24.8 k D+D- Threshold for Non-Standard Adapter (1.2V) VD+D-_1P2 -- 1.2 -- V D+D- Threshold for Non-Standard Adapter (2V) VD+D-_2P0 -- 2 -- V Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 14.25 19.53 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9470/D Parameter Min Typ Max Unit -- 2.8 -- V VAC OVP Reaction Time tVAC_OVP -- 200 -- ns Bad Adapter Detection Duration -- 30 -- ms D+D- Threshold for Non-Standard Adapter (2.8V) Symbol Test Conditions VD+D-_2P8 Timing Requirements tBAD_AD_ DETECTION Deglitch Time for Charger EOC tEOC_DGL -- 256 -- ms Deglitch Time for Re-Charge tRE_CHG_DGL -- 256 -- ms Charge Safe Timer tCHG_SAFE_TMR Timer = 10hr 9 10 11 hr Back-Ground Charge Timer tBG_CHG_TMR Timer = 30min 29 30 31 min 0.9 1.1 1.3 s 9 10 11 s 430 453 480 ms 11 12 13 s CB ≤ 100pF -- -- 3.4 100pF < CB ≤ 400pF -- -- 1.7 Default = 40s -- 40 -- s -- 500 -- ms QON Timing QON Low Time to Exit Shipping Mode tSHIPMODE_EXIT QON Low Time to Reset System tQON_RST BATFET Reset Time tBATFET_RST Enter Shipping Mode Delay Time tSHIP_MODE_ ENTER I2C Clock and Watchdog Timer SCL Clock fSCL Watchdog Timer tWDT Watchdog Reset Wait Time tWDT_WAIT MHz Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Specification is guaranteed by design and/or correlation with statistical process control. Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Typical Application Circuit RT9470 A5 A4,B4 USB CBUS 1µF D1 A3,B3 CPMID 10µF RT9470 VAC VBUS REGN PMID BTST VREF SW RPULL-UP1 RPULL-UP2 RPULL-UP3 10kΩ 10kΩ 10kΩ D4 E4 F5 F4 Host E3 C5 SYS QON SDA BAT C4 CREGN 4.7µF C3 CBTST 47nF A2,B2 L 1µH C2,D2,E2,F2 C1,D1,E1,F1 CBAT 10µF SCL INT BATSNS CE System CSYS 10µF x 2 F3 PSEL REGN REGN R1 D2 2.2kΩ E5 REGN RTS1 STAT TS D3 R2 D3 5.23kΩ/1% RTS2 2.2kΩ D5 Battery Pack 30.1kΩ/1% PG GND A1,B1 RT9470D A5 A4,B4 USB CBUS 1µF D1 C5 D5 A3,B3 CPMID 10µF VREF RT9470D VAC REGN VBUS BTST D+ RPULL-UP2 RPULL-UP3 10kΩ 10kΩ 10kΩ D4 CREGN 4.7µF C3 CBTST 47nF DSW PMID SYS RPULL-UP1 C4 A2,B2 L 1µH C2,D2,E2,F2 QON BAT C1,D1,E1,F1 CBAT 10µF E4 SDA F5 Host F4 E3 SCL BATSNS F3 INT CE REGN RTS1 REGN D2 System CSYS 10µF x 2 R1 2.2kΩ E5 TS D3 5.23kΩ/1% RTS2 STAT Battery Pack 30.1kΩ/1% GND 17,18 Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9470/D Below are recommended components information Name Description Part Number Package Manufacturer CBUS 1F/25V/X5R GRM155R61E105KA12 0402 muRata CPMID 10F/25V/X5R GRM188R61E106MA73 0603 muRata CBTST 47nF/16V/X5R GRM033R61C473KE84 0201 muRata CSYS 10F/6.3V/X5R GRM185R60J106ME15 0603 muRata CBAT 10F/6.3V/X5R GRM185R60J106ME15 0603 muRata CREGN 4.7F/6.3V/X5R GRM155R60J475ME47 0402 muRata L 1H/20% CIGT252010EH1R0MNE 2.5 x 2.0 x 1.0mm Samsung D1 PTVSHC3N12VU TVS Diode DFN2x2-3L Prisemi Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Typical Operating Characteristics Charger Efficiency vs. Charging Current Charger Efficiency vs. Charging Current 96 VBUS = 5V VBUS = 9V VBUS = 12V 94 Charger Efficiency (%) Charger Efficiency (%) 96 92 90 88 86 VBUS = 5V VBUS = 9V VBUS = 12V 94 92 90 88 86 VBAT = 3.8V, fSW = 1.5MHz, LDCR = 26mΩ VBAT = 4.2V, fSW = 1.5MHz, LDCR = 26mΩ 84 84 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 Charging Current (A) 1.5 2.0 2.5 3.0 3.5 Charging Current (A) MIVR Tracking VBAT Boost Efficiency vs. Output Current 4.9 96 VBAT + 300mV VBAT + 250mV VBAT + 200mV 94 Boost Efficiency (%) 4.8 VBUS (V) 1.0 4.7 4.6 4.5 92 90 VBAT = 4.35V VBAT = 4.2V VBAT = 3.8V VBAT = 3.5V 88 86 84 VBUS = 5.15V, fSW = 1.5MHz, LDCR = 26mΩ 4.4 82 3.8 3.9 4.0 4.1 4.2 4.3 4.4 VBAT Set (V) Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 4.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Output Current (A) is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT9470/D Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT9470/D Register Descriptions I2C Slave Address : 1010011 (53H) R : Read only R/W : Read and write RWSC : Read and write, also automatically set/clear by particular condition Register Address : 0x00, Register Name : OTG_CONFIG Bit Bit Name Default WDT RST REG RST Type Description OTG voltage limit regulation 00 : 4.85V 01 : 5.0V 10 : 5.15V (default) 11 : 5.3V 7:6 OTG_CV 10 N Y R/W 5:2 Reserved 0000 NA NA R 1 OTG_LBP 0 N Y R/W OTG low battery protection 0 : 2.8V (default) 1 : 2.5V 0 OTG_CC 1 Y Y R/W OTG current limit regulation 0 : 0.5A 1 : 1.2A (default) Reserved Register Address : 0x01, Register Name : TOP Bit Bit Name Default WDT RST REG RST Type 7 QON_RST_ EN 1 Y Y R/W 0 : QON = 0 for 10s will NOT do anything 1 : QON = 0 for 10s will turn off BATFET (default) 6 STAT_EN 1 N Y R/W 0 : STAT pin function disable 1 : STAT pin function enable (default) 5:4 Reserved 00 NA NA R 3 DIS_I2C_TO 0 Y Y R/W 0 : Enable I2C time-out function (default) 1 : Disable I2C time-out function 2 WDT_CNT_ RST 0 Y Y RWSC 0 : No action 1 : Reset watchdog counter (Notice : Back to 0 after watchdog reset) 1:0 WDT 01 Y Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 Y R/W Description Reserved 00 : Disable watchdog timer reset function 01 : 40s (default) 10 : 80s 11 : 160s is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x02, Register Name : FUNCTION Bit Bit Name Default 0 WDT RST REG RST N Y Type Description 7 BATFET_DIS RWSC 6 BATFET_DIS_ DLY 1 N Y R/W 5 HZ 0 Y Y RWSC 4 Reserved 0 NA NA R 3 BUCK_PFM_ DIS 0 N Y R/W 2 UUG_FULLON 0 N Y R/W 1 OTG_EN 0 Y Y RWSC 0 CHG_EN 1 Y Y R/W 0 : Allow BATFET turn on (default) 1 : Force BATFET turn off (Notice : Clear by VBUS plug in or QON = 0 for 1s,auto set BATFET_DIS = 1 by system overload from BAT to SYS) 0 : BATFET turn off immediately while BATFET_DIS = 0 1 : BATFET turn off with 12s delay while BATFET_DIS = 1 (default) 0 : Normal mode (default) 1 : HZ mode (Notice : Clear by VBUS plug in) Reserved 0 : Enable PFM (default) 1 : Disable PFM 0 : Q1 turn on by condition (default) 1 : Force Q1 full on 0 : Disable OTG (default) 1 : Enable OTG (Notice : Clear by HZ = 1 or OTP or OTG_LBP or VBUS_OV or QON reset or BATFET_DIS = 1 or auto 7 times hiccup for soft-start fail or overload) 0 : Disable charge 1 : Enable charge (default) Register Address : 0x03, Register Name : IBUS Bit Bit Name Default WDT RST REG RST Type Description 7 AICC_EN 0 Y Y RWSC 0 : Disable AICC function (default) 1 : Enable AICC function (Notice : Auto clear after AICC function done) 6 AUTO_AICR 1 Y Y R/W 0 : No action 1 : Auto set IAICR by BC1.2 done or PSEL change (default) RWSC Average input current regulation 000000 : 50mA 000001 : 50mA 000010 : 100mA … 001010 : 500mA (default) … 111101 : 3050mA 111110 : 3100mA 111111 : 3200mA (Notice : Auto set by BC1.2 done or PSEL change if AUTO_AICR = 1) 5:0 IAICR 001010 N Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Y is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT9470/D Register Address : 0x04, Register Name : VBUS Bit Bit Name 7:6 VAC_OVP 5:4 VMIVR_BAT_ TRACK 3:0 VMIVR Default 01 00 0110 WDT RST REG RST N Y N Y N Y Type Description R/W VAC OVP threshold 00 : 5.8V 01 : 6.5V (default) 10 : 10.9V (6.5V while OTG) 11 : 14V (6.5V while OTG) R/W 00 : VMIVR by 0x04[3:0] (default) 01 : VMIVR = VBAT + 200mV 10 : VMIVR = VBAT + 250mV 11 : VMIVR = VBAT + 300mV R/W Minimum input voltage regulation 0000 : 3900mV 0001 : 4000mV … 0110 : 4500mV (default) ... 1110 : 5300mV 1111 : 5400mV Register Address : 0x05, Register Name : PRECHG Bit Bit Name Default WDT RST REG RST Type 7 Reserved 0 NA NA R 6:4 VPRE_CHG 100 Y Y R/W 3:0 IPRE_CHG 0010 Y Y R/W Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 Description Reserved Pre-charge voltage threshold 000 : 2700mV 001 : 2800mV 010 : 2900mV 011 : 3000mV 100 : 3100mV (default) 101 : 3200mV 110 : 3300mV 111 : 3400mV Pre-charge current 0000 : 50mA 0001 : 100mA 0010 : 150mA (default) ... 1110 : 750mA 1111 : 800mA is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x06, Register Name : REGU Bit Bit Name Default WDT RST REG RST Type 7 Reserved 0 NA NA R 6 THREG 1 Y Y R/W 5:4 Reserved 00 NA NA R 3:0 VSYS_MIN 1001 N Y R/W Description Reserved Junction thermal regulation threshold 0 : 100°C 1 : 120°C (default) Reserved System minimum voltage 0000 : 2600mV 0001 : 2700mV … 1001 : 3500mV (default) ... 1110 : 4000mV 1111 : 4100mV Register Address : 0x07, Register Name : VCHG Bit Bit Name Default WDT RST REG RST Type 7 VRE_CHG 0 Y Y R/W Re-charge voltage threshold 0 : 100mV (default) 1 : 200mV Y R/W Charge voltage 0000000 : 3900mV 0000001 : 3910mV … 0011110 : 4200mV (default) … 1010000 : 4700mV 1010000 to 1111111 : 4700mV 6:0 VBAT_REG 0011110 Y Description Register Address : 0x08, Register Name : ICHG Bit Bit Name Default WDT RST REG RST Type 7:6 Reserved 00 NA NA R 5:0 ICHG_REG 101000 Y Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Y R/W Description Reserved Charge current 000000 : 0mA (disable charge) 000001 : 50mA 000010 : 100mA 000011 : 150mA … 101000 : 2000mA (default) … 111101 : 3100mA 111111 : 3150mA is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT9470/D Register Address : 0x09, Register Name : CHG_TIMER Bit Bit Name Default WDT RST REG RST Type 7 CHG_SAFE_ TMR_EN 1 Y Y R/W 0 : Disable charge safe timer 1 : Enable charge safe timer (default) R/W Double charge safe timer during MIVR, AICR, thermal regulation, and JEITA reduce ICHG 0 : Disable 2x extended charge safe timer 1 : Enable 2x extended charge safe timer (default) Charge safe timer 00 : 5hr 01 : 10hr (default) 10 : 15hr 11 : 20hr 6 CHG_SAFE_ TMR_2XT 1 Y Y 5:4 CHG_SAFE_ TMR 01 Y Y R/W 3:0 Reserved 0000 NA NA R REG RST Type Description Reserved Register Address : 0x0A, Register Name : EOC Bit 7:4 Bit Name IEOC_CHG Default 0011 WDT RST Y Y Description R/W End-of-charge current threshold 0000 : 50mA 0001 : 100mA 0010 : 150mA 0011 : 200mA (default) ... 1110 : 750mA 1111 : 800mA 3:2 BG_CHG_ TMR 00 Y Y R/W EOC back-ground charge timer 00 : 0min (default) 01 : 15min 10 : 30min 11 : 45min 1 TE 1 Y Y R/W 0 : Disable charge current termination 1 : Enable charge current termination (default) 0 EOC_RST 0 Y Y RWSC 0 : No action 1 : Reset EOC (Notice : Back to 0 after reset EOC done) Register Address : 0x0B, Register Name : INFO Bit Bit Name Default WDT RST REG RST Type 7 REG_RST 0 NA NA RWSC 6:3 DEVICE_ID 1001 NA NA R 1001 : RT9470 (PSEL, PGB) 1010 : RT9470D (D+, D-) 2:0 DEVICE_RE NA NA NA R Revision Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 Description 0 : No action 1 : Reset register (Notice : Back to 0 after register reset) is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x0C, Register Name : JEITA Bit Bit Name Default WDT RST REG RST Type 7 JEITA_EN 1 Y Y R/W 0 : JEITA disable 1 : JEITA enable (default) 6 JEITA_COLD 0 Y Y R/W 0 : COLD do NOT charging / OTG (default) 1 : COLD still charging / OTG 5 JEITA_COOL_ ISET 1 Y Y R/W 0 : 50% of ICHG 1 : 25% of ICHG (default) 4 JEITA_COOL_ VSET 1 Y Y R/W 0 : VBAT_REG = 4.1V 1 : VBAT_REG = Register setting (default) 3 JEITA_WARM _ISET 1 Y Y R/W 0 : 50% of ICHG 1 : ICHG = Register setting (default) 2 JEITA_WARM _VSET 0 Y Y R/W 0 : VBAT_REG = 4.1V (default) 1 : VBAT_REG = Register setting 1 JEITA_HOT 0 Y Y R/W 0 : HOT do NOT charging / OTG (default) 1 : HOT still charging / OTG 0 Reserved 0 NA NA R Description Reserved Register Address : 0x0D, Register Name : PUMP_EXP Bit Bit Name Default WDT RST REG RST Type Description 0 : Idle (default) 1 : Trigger MTK Pump Express process (Notice : Auto clear while PE done or no VBUS) 7 PE_EN 0 Y Y RWSC 6 PE_SEL 0 Y Y R/W 0 : PE 1.0 process select (default) 1 : PE 2.0 process select 5 PE10_INC 0 Y Y R/W 0 : PE 1.0 voltage down (default) 1 : PE 1.0 voltage up R/W MTK PE 2.0 voltage request setting 00000 : 5.5V (default) 00001 : 6V … 11101 : 20V 11110 : Adapter healthy self-testing 11111 : Disable cable drop compensation 4:0 PE20_CODE 00000 Y Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Y is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT9470/D Register Address : 0x0E, Register Name : DPDM_DET Bit 7 Bit Name BC12_EN Default 1 WDT RST REG RST Y Y Type Description R/W 0 : Disable BC1.2 detection 1 : Enable BC1.2 detection while VBUS > 3.8V (default) (Notice : For RT9470D only) 6:5 DCDT_SEL 01 Y Y R/W 00 : Disable DCD timeout function 01 : Enable 300ms DCD timeout function (default) 10 : Enable 600ms DCD timeout function 11 : Wait data contact 4 SPEC_TA_EN 1 Y Y R/W 0 : Disable Samsung / Apple TA detection 1 : Enable Samsung / Apple TA detection (default) 3:1 Reserved 000 NA NA R 0 DCP_DP_OPT 0 Y Y R/W Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 Reserved DCP DP behavior option 0 : DP = 0V after BC 1.2 done (default) 1 : DP keep 0.6V while DCP port detected is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x0F, Register Name : IC_STATUS Bit 7:4 3:0 Bit Name Default PORT_STAT 0000 IC_STAT 0000 WDT RST REG RST NA NA Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 NA NA Type Description R 0000 : No information 0001 to 0111 : Reserved 1000 : VBUS = device 1 (2100mA-APPLE-10w) 1001 : VBUS = device 2 (2000mA-SAMSUNG-10w) 1010 : VBUS = device 3 (1000mA-APPLE-5w) 1011 : VBUS = device 4 (2400mA-APPLE-12w) 1100 : VBUS = unknown / NSDP (500mA) 1101 : VBUS = SDP (500mA) / PSEL = High 1110 : VBUS = CDP (1500mA) 1111 : VBUS = DCP (2400mA) / PSEL = Low R 0000 : HZ/SLEEP 0001 : VBUS ready for charge 0010 : Trickle-charge 0011 : Pre-charge 0100 : Fast-charge 0101 : IEOC-charge (EOC and TE = 0) 0110 : Back-Ground charge (EOC and TE = 1 and before turn off power path) 0111 : Charge done (EOC and TE = 1 and power path off) 1000 : Charge fault (VAC_OV / CHG_BUSUV / CHG_TOUT / CHG_SYSOV / CHG_BATOV / JEITA_HOT / JEITA_COLD / OTP) 1001 to 1110 : Reserved 1111 : OTG is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT9470/D Register Address : 0x10, Register Name : STAT0 Bit 7 Bit Name ST_VBUS_GD Default 0 WDT RST REG RST NA NA Type Description R 0 : VBUS is not good 1 : VBUS is good (Notice : After current capability of the input source detection, and HZ = 0, VAC_OV = 0, VBUS > 3.8V) 6 ST_CHG_RDY 0 NA NA R 0 : VBUS is not ready for charging 1 : VBUS is ready for charging (Notice : After port detection, and HZ = 0, VAC_OV = 0, VBUS > 3.8V) 5 ST_IEOC 0 NA NA R 0 : Not in EOC state 1 : While in EOC state (Notice : Charge current < IEOC level) 4 ST_BG_CHG 0 NA NA R 0 : Not in EOC state or TE = 0 or BG_CHG_TMR = 00 1 : While in EOC state and TE = 1 and BG_CHG_TMR ≠ 00 3 ST_CHG_ DONE 0 NA NA R 0 : Not in EOC state or BATFET on 1 : While in EOC state and BATFET off 2:1 Reserved 00 NA NA R Reserved 0 ST_BC12_ DONE 0 NA NA R 0 : BC1.2 process not ready 1 : While BC1.2 process done Register Address : 0x11, Register Name : STAT1 Bit Bit Name Default WDT RST REG RST Type 7 ST_CHG_ MIVR 0 NA NA R 0 : Not in MIVR loop 1 : While in MIVR loop 6 ST_CHG_ AICR 0 NA NA R 0 : Not in AICR loop 1 : While in AICR loop 5 ST_CHG_ THREG 0 NA NA R 0 : Not in THERMAL loop 1 : While in THERMAL loop 4 ST_CHG_ BUSUV 0 NA NA R 0 : Not VBAT < VBUS < 3.8V 1 : While VBAT < VBUS < 3.8V 3 ST_CHG_ TOUT 0 NA NA R 0 : Not in charge safety time-out 1 : While in charge safety time-out 2 ST_CHG_ SYSOV 0 NA NA R 0 : Not in SYS OV 1 : While in SYS OV 1 ST_CHG_ BATOV 0 NA NA R 0 : Not in BAT OV 1 : While in BAT OV 0 Reserved 0 NA NA R Reserved Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 Description is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x12, Register Name : STAT2 Bit Bit Name Default WDT RST REG RST Type 7 ST_JEITA_ HOT 0 NA NA R 0 : Not in BAT is hot 1 : While in BAT is hot 6 ST_JEITA_ WARM 0 NA NA R 0 : Not in BAT is warm 1 : While in BAT is warm 5 ST_JEITA_ COOL 0 NA NA R 0 : Not in BAT is cool 1 : While in BAT is cool 4 ST_JEITA_ COLD 0 NA NA R 0 : Not in BAT is cold 1 : While in BAT is cold 3:2 Reserved 00 NA NA R Reserved 1 ST_SYS_MIN 0 NA NA R 0 : Not in VBAT < VSYS_MIN 1 : While in VBAT < VSYS_MIN 0 Reserved 0 NA NA R Reserved Description Register Address : 0x13, Register Name : STAT3 Bit Bit Name Default WDT RST REG RST Type 7 ST_OTP 0 NA NA R 0 : Not OTP 1 : OTP 6 ST_VAC_OV 0 NA NA R 0 : Not VAC_OV 1 : VAC_OV (charge or OTG mode) 5 ST_WDT 0 NA NA R 0 : WDT is counting 1 : WDT reset will occur after 500ms 4:3 Reserved 00 NA NA R Reserved 2 ST_OTG_CC 0 NA NA R 0 : Not in OTG_CC 1 : While in OTG_CC 1:0 Reserved 00 NA NA R Reserved Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Description is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT9470/D Register Address : 0x20, Register Name : IRQ0 Bit Bit Name Default WDT RST REG RST Type 7 FL_VBUS_GD 0 NA NA R 0 : ST_VBUS_GD not rising 1 : While ST_VBUS_GD rising, read clear 6 FL_CHG_RDY 0 NA NA R 0 : ST_CHG_RDY not rising 1 : While ST_CHG_RDY rising, read clear 5 FL_IEOC 0 NA NA R 0 : ST_IEOC not rising 1 : While ST_IEOC rising, read clear 4 FL_BG_CHG 0 NA NA R 0 : ST_BG_CHG not rising 1 : While ST_BG_CHG rising, read clear 3 FL_CHG_ DONE 0 NA NA R 0 : ST_CHG_DONE not rising 1 : While ST_CHG_DONE rising, read clear 2 FL_RECHG 0 NA NA R 0 : While VBAT > VRECHG after EOC 1 : While VBAT < VRECHG after EOC, read clear Description 1 FL_DETACH 0 NA NA R 0 : ST_VBUS_GD not rising or in ST_VBUS_GD 1 : While ST_VBUS_GD falling then VBUS < VBAT or VBUS < 3.3V, read clear 0 FL_BC12_DO NE 0 NA NA R 0 : BC1.2 process not ready 1 : While BC1.2 process done Register Address : 0x21, Register Name : IRQ1 Bit Bit Name Default WDT RST REG RST Type 7 FL_CHG_ MIVR 0 NA NA R 0 : ST_CHG_MIVR not rising 1 : While ST_CHG_MIVR rising, read clear 6 FL_CHG_ AICR 0 NA NA R 0 : ST_CHG_AICR not rising 1 : While ST_CHG_AICR rising, read clear 5 FL_CHG_ THREG 0 NA NA R 0 : ST_CHG_THREG not rising 1 : While ST_CHG_THREG rising, read clear 4 FL_CHG_ BUSUV 0 NA NA R 0 : ST_CHG_BUSUV not rising 1 : While ST_CHG_BUSUV rising, read clear 3 FL_CHG_ TOUT 0 NA NA R 0 : ST_CHG_TOUT not rising 1 : While ST_CHG_TOUT rising, read clear 2 FL_CHG_ SYSOV 0 NA NA R 0 : ST_CHG_SYSOV not rising 1 : While ST_CHG_SYSOV rising, read clear 1 FL_CHG_ BATOV 0 NA NA R 0 : ST_CHG_BATOV not rising 1 : While ST_CHG_BATOV rising, read clear 0 Reserved 0 NA NA R Reserved Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 Description is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x22, Register Name : IRQ2 Bit Bit Name Default WDT RST REG RST Type 7 FL_JEITA_ HOT 0 NA NA R 0 : ST_JEITA_HOT not rising 1 : While ST_JEITA_HOT rising, read clear 6 FL_JEITA_ WARM 0 NA NA R 0 : ST_JEITA_WARM not rising 1 : While ST_JEITA_WARM rising, read clear 5 FL_JEITA_ COOL 0 NA NA R 0 : ST_JEITA_COOL not rising 1 : While ST_JEITA_COOL rising, read clear 4 FL_JEITA_ COLD 0 NA NA R 0 : ST_JEITA_COLD not rising 1 : While ST_JEITA_COLD rising, read clear 3 FL_PE_DONE 0 NA NA R 0 : FL_PE_DONE not rising 1 : While PE processing done, read clear 2 FL_AICC_ DONE 0 NA NA R 0 : FL_AICC_DONE not rising 1 : While AICC processing done, read clear 1 FL_SYS_ MIN 0 NA NA R 0 : ST_SYS_MIN not rising 1 : While ST_SYS_MIN rising, read clear 0 FL_SYS_ SHORT 0 NA NA R 0 : ST_SYS_SHORT not rising 1 : While ST_SYS_SHORT rising, read clear Description Register Address : 0x23, Register Name : IRQ3 Bit Bit Name Default WDT RST REG RST Type 7 FL_OTP 0 NA NA R 0 : ST_OTP not rising 1 : While ST_OTP rising, read clear 6 FL_VAC_OV 0 NA NA R 0 : ST_VAC_OV not rising 1 : While ST_VAC_OV rising, read clear 5 FL_WDT 0 NA NA R 0 : ST_WDT not rising 1 : While ST_WDT rising, read clear 4:3 Reserved 00 NA NA R Reserved 2 FL_OTG_CC 0 NA NA R 0 : ST_OTG_CC not rising 1 : While ST_OTG_CC rising, read clear 1 FL_OTG_LBP 0 NA NA R 0 : ST_OTG_LBP not rising 1 : While ST_OTG_LBP rising, read clear 0 FL_OTG_ FAULT 0 NA NA R 0 : ST_OTG_FAULT not rising 1 : While ST_OTG_FAULT rising, read clear Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Description is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT9470/D Register Address : 0x30, Register Name : MASK0 Bit Bit Name Default WDT RST REG RST Type 7 MK_VBUS_ GD 1 N Y R/W 0 : Not mask IRQ of FL_VBUS_GD 1 : Mask IRQ of FL_VBUS_GD (default) 6 MK_CHG_ RDY 1 N Y R/W 0 : Not mask IRQ of FL_CHG_RDY 1 : Mask IRQ of FL_CHG_RDY (default) 5 MK_IEOC 1 N Y R/W 0 : Not mask IRQ of FL_IEOC 1 : Mask IRQ of FL_IEOC (default) 4 MK_BG_CHG 1 N Y R/W 0 : Not mask IRQ of MK_BG_CHG 1 : Mask IRQ of MK_BG_CHG (default) 3 MK_CHG_ DONE 1 N Y R/W 0 : Not mask IRQ of FL_CHG_DONE 1 : Mask IRQ of FL_CHG_DONE (default) 2 MK_RECHG 1 N Y R/W 0 : Not mask IRQ of FL_RECHG 1 : Mask IRQ of FL_RECHG (default) 1 MK_DETACH 1 N Y R/W 0 : Not mask IRQ of FL_DETACH 1 : Mask IRQ of FL_DETACH (default) 0 MK_BC12_DO NE 1 N Y R/W 0 : Not mask IRQ of FL_BC12_DONE 1 : Mask IRQ of FL_BC12_DONE (default) Description Register Address : 0x31, Register Name : MASK1 Bit Bit Name Default WDT RST REG RST Type 7 MK_CHG_ MIVR 1 N Y R/W 0 : Not mask IRQ of FL_CHG_MIVR 1 : Mask IRQ of FL_CHG_MIVR (default) 6 MK_CHG_ AICR 1 N Y R/W 0 : Not mask IRQ of FL_CHG_AICR 1 : Mask IRQ of FL_CHG_AICR (default) 5 MK_CHG_ THREG 1 N Y R/W 0 : Not mask IRQ of FL_CHG_THREG 1 : Mask IRQ of FL_CHG_THREG (default) 4 MK_CHG_ BUSUV 1 N Y R/W 0 : Not mask IRQ of FL_CHG_BUSUV 1 : Mask IRQ of FL_CHG_BUSUV (default) 3 MK_CHG_ TOUT 1 N Y R/W 0 : Not mask IRQ of FL_CHG_TOUT 1 : Mask IRQ of FL_CHG_TOUT (default) 2 MK_CHG_ SYSOV 1 N Y R/W 0 : Not mask IRQ of FL_CHG_SYSOV 1 : Mask IRQ of FL_CHG_SYSOV (default) 1 MK_CHG_ BATOV 1 N Y R/W 0 : Not mask IRQ of FL_CHG_BATOV 1 : Mask IRQ of FL_CHG_BATOV (default) 0 Reserved 1 NA NA R Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 Description Reserved is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Register Address : 0x32, Register Name : MASK2 Bit Bit Name Default WDT RST REG RST Type 7 MK_JEITA_ HOT 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_HOT 1 : Mask IRQ of FL_JEITA_HOT (default) 6 MK_JEITA_ WARM 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_WARM 1 : Mask IRQ of FL_JEITA_WARM (default) 5 MK_JEITA_ COOL 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_COOL 1 : Mask IRQ of FL_JEITA_COOL (default) 4 MK_JEITA_ COLD 1 N Y R/W 0 : Not mask IRQ of FL_JEITA_COLD 1 : Mask IRQ of FL_JEITA_COLD (default) 3 MK_PE_ DONE 1 N Y R/W 0 : Not mask IRQ of FL_PE_DONE 1 : Mask IRQ of FL_PE_DONE (default) 2 MK_AICC_ DONE 1 N Y R/W 0 : Not mask IRQ of FL_AICC_DONE 1 : Mask IRQ of FL_AICC_DONE (default) 1 MK_SYS_MIN 1 N Y R/W 0 : Not mask IRQ of FL_SYS_MIN 1 : Mask IRQ of FL_SYS_MIN (default) 0 MK_SYS_ SHORT 1 N Y R/W 0 : Not mask IRQ of FL_SYS_SHORT 1 : Mask IRQ of FL_SYS_SHORT (default) Description Register Address : 0x33, Register Name : IRQ3 Bit Bit Name Default WDT RST REG RST Type 7 MK_OTP 1 N Y R/W 0 : Not mask IRQ of FL_OTP 1 : Mask IRQ of FL_OTP (default) 6 MK_VAC_OV 1 N Y R/W 0 : Not mask IRQ of FL_VAC_OV 1 : Mask IRQ of FL_VAC_OV (default) 5 MK_WDT 1 N Y R/W 0 : Not mask IRQ of FL_WDT 1 : Mask IRQ of FL_WDT (default) 4:3 Reserved 11 NA NA R 2 MK_OTG_CC 1 N Y R/W 0 : Not mask IRQ of FL_OTG_CC 1 : Mask IRQ of FL_OTG_CC (default) 1 MK_OTG_LBP 1 N Y R/W 0 : Not mask IRQ of FL_OTG_LBP 1 : Mask IRQ of FL_OTG_LBP (default) 0 MK_OTG_ FAULT 1 N Y R/W 0 : Not mask IRQ of FL_OTG_FAULT 1 : Mask IRQ of FL_OTG_FAULT (default) Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Description Reserved is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT9470/D Application Information 1. VAC above VBAT + VSLEEP_RISE in buck mode or enable OTG bit in boost mode. Power Up  Power-On-Reset (POR) The device powers internal bias circuits from the higher voltage of VBUS and VBAT. When VBUS rises above 1.8V or VBAT rises above VBAT_UVLO, I2C interface is ready for communication and all the registers are reset to default value.  2. After 220ms delay is completed when VAC above VBAT + VSLEEP_RISE. 3. REGN LDO turns off when device in HZ mode, sleep mode, VBUS over-voltage or OTG disable.  After REGN powers up, the device checks the current capability of the input source. The input source has to meet following requirements to turn on the buck converter. Device Power Up from Battery Only When only Battery is present and VBAT above VBAT_DPL_RISE, the BATFET turns on to connect VBAT to VSYS. The REGN stays off to minimize the quiescent current. The low quiescent current on VBAT and low RDS(ON) of BATFET minimize device power consumption and conduction loss maximum battery run life. The device always monitors the discharge current through BATFET (Battery Supply Mode). When the system is overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and sets BATFET_DIS = 1 to enter Shipping Mode until VBUS plugs in again or uses the methods to exit Shipping Mode to re-enable BATFET.  1. VBUS below VAC_OVP_RISE. 2. VBUS above VBUS_BAD_ADP then pulling IBADSRC (typical = 40mA). When input source passes above conditions, the ST_VBUS_GD and the FL_VBUS_GD turn to high and INT pin is pulsed for interrupting the host. If ST_VBUS_GD doesn’t turn to high, it repeats poor source detection every 2 seconds.  When the VBUS is plugged in, the power up sequence is as listed : Then the following registers are changed: 1. Average Input Current Regulation (AICR) register is changed to the result of VBUS source type detection or PSEL pin status automatically if AUTO_AICR = 1. 1. Power up REGN LDO. 2. Poor Source Detection. 3. PORT_STAT Detection is based on PSEL or input source type to set default Average Input Current Regulation (AICR) register. 5. Buck Converter Power-up.  Power-Up REGN LDO The REGN LDO supplies the High-side and Low-side MOSFET gate drive. The REGN also provides bias to TS external resistor and pull-up rail of STAT. The REGN is enabled when the below conditions are valid : Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 VBUS Source Type Detection After ST_VBUS_GD turns to high, the device runs VBUS source type detection (RT9470D) or PSEL pin status (RT9470). After detection is completed, the ST_CHG_RDY and the FL_CHG_RDY turn to high and INT pin is pulsed for interrupting the host. Device Power Up from VBUS 4. Minimum Input Voltage Regulation (MIVR) setting. Poor Source Detection 2. PORT_STAT bit is updated to indicate VBUS source type.  Average Input Current Regulation (AICR) The charger input current is always limited by AICR register. The range of AICR is from 50mA to 3.2A with 50mA resolution. 1. If the bit AUTO_AICR is set to 0, the device can’t change AICR automatically after VBUS source type detection. is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D 2. The host can over-write AICR register to change input current limit.  After the AICR is set, the converter is enabled and starts switching. BATFET stays on unless charger is disabled (CHG_EN = 0) or enters shipping mode (BATFET_DIS = 1). 3. The AICR register setting from PSEL in the RT9470 refers to Table 1 or from D+/D- detection (include standard USB BC 1.2) in the RT9470D refers to Table 2. The device integrates a synchronous PWM controller with 1.5MHz switching frequency, high-accuracy current and voltage regulation. The device also supports PFM control to improve light-load efficiency. The BUCK_PFM_DIS register bit can be used to prevent PFM operation in buck configuration. 4. PSEL value updates AICR in real time in RT9470. 5. D+/D- detect value updates AICR after BC12_EN disable then enable or re-plug VBUS in the RT9470D. Table 1. AICR Setting from PSEL  Boost Mode Operation (OTG) PSEL pin AICR setting PORT_STAT The device supports OTG (On-The-Go) mode by High 0.5 A 1101 Low 2.4 A 1111 boost converter operation to deliver power from battery to other portable devices. The maximum boost mode output current is up to 1.2A, which includes USB OTG 500mA output requirement. Table 2. AICR Setting from D+/D- Detection  Buck Converter Power-Up Detection AICR setting PORT_STAT Device 1 2.1A 1000 The boost operation can be enabled by following condition : Device 2 2A 1001 1. VBAT above VOTG_LBP Device 3 1A 1010 2. VBUS less than VBAT+VSLEEP_FALL Device 4 2.4A 1011 3. OTG_EN is set to high Unknown/NSDP 0.5A 1100 SDP 0.5A 1101 4. Voltage at TS pin is within acceptable range (VVTS_HOT < VTS < VVTS_COLD) CDP 1.5A 1110 DCP 2.4A 1111 Minimum Input Voltage Regulation (MIVR) The MIVR function prevents input voltage drops due to insufficient current provided from input power source. The VBUS voltage decreases to VMIVR setting level when the over-current condition of input power source occurs. The VMIVR register default setting is 4.5V, it can be set by I2C interface, the range from 3.9V to 5.4V with 0.1V resolution. In addition, the device provides MIVR tracking function by enabling VMIVR_BAT_TRACK register bits. If this tracking function is enabled, the MIVR will be the higher of the VMIVR register and VBAT + VMIVR_ BAT_TRACK offset. Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 5. After 30ms delay from OTG_EN is set to high, boost converter powers up. In boost mode, the IC_STAT register bits is updated to 1111, the VBUS output voltage is 5.15V and output limit current is 1.2A by default, output voltage (OTG_CV) and output current limit (OTG_CC) can be selected through I2C. The boost output maintained when VBAT is above VOTG_LBP. Watchdog Timer (WDT) When the device is controlled by host, most of the registers can be programmed by host. The host has to write WDT_CNT_RST = 1 to reset counter before watchdog timeout and it can also disable WDT function by setting WDT bits to 00. When the watchdog timer expired, ST_WDT and FL_WDT turn to high and INT pin is pulsed for interrupting the host. After delay 512ms, the related registers are reset to default values. (Refer to Register is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT9470/D Descriptions for detail). If the device is watchdog timeout status, host can write any registers or WDT_CNT_RST = 1 to return counting. WDT IDLE WDT disable or change WDT timer or WDT_CNT_RST = 1 Y 2 Y WDT timer reset N I C write any register N N Watchdog Timeout ? WDT reset registers Y Y Y WDT disable or change WDT timer or WDT_CNT_RST = 1 FL_WDT = 1 ST_WDT = 1 N Delay 512ms N Figure 1. WDT Flow Chart Power Path Management The device provides automatic power path selection to supply system (VSYS) from VBUS, VBAT (battery) or both of them.  Enter Shipping Mode (BATFET Disable) To extend battery life when shipping or storage, the device can turn off BATFET to minimize battery leakage current. The host can set BATFET_DIS bit to turn off BATFET immediately or set BATFET_DIS_DLY to delay tSHIP_MODE_ENTER to turn off BATFET.   QON Pin Operations The QON pin has two function to control BATFET. 1. BATFET Enable : QON pin transition from high to low with longer than tSHIPMODE_EXIT deglitch turns on BATFET to exit shipping mode. 2. SYSTEM Reset : QON pin transition from high to low with longer than tQON_RST deglitch and VBUS is not plugged in, it turns off BATFET for tBATFET_RST then it is re-enabled BATFET. This function allows system connect to VSYS to do power-on-reset. This function can be disabled by setting QON_RST_EN bit to 0. Exit Shipping Mode (BATFET Enable) When in shipping mode, one of the following methods can exit shipping mode to restore power for system : 1. VBUS plug in. 2. Set BATFET_DIS bit to 0. QON Press QON Press QON … ... tQON_RST tSHIPMODE_EXIT tBATFET_RST Q4 Q4 off Q4 on Q4 off Figure 2. QON Timing 3. Set REG_RST bit to reset all registers to default. 4. Press QON pin from high to low longer than tSHIPMODE_EXIT. Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 Battery Charging Management The device has charge current up to 3.15A with 18m BATFET to improve charge efficiency and decrease voltage drop during battery discharging. is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D  Charging Cycle 2. Battery charging is enabled (CE pin is low, CHG_EN = 1 and ICHG_REG is not 0mA). When battery charging is enabled (CE pin set to low and CHG_EN = 1), the device autonomously completes a charging cycle without host controls. The device default parameters refers as Table 2. The host can also change charging parameters through I2C. 3. Without any thermal fault on TS. 4. No safety timer fault. 5. BATFET is turned on (BATFET_DIS = 0). The charger is in end of charge status when the charging current is below EOC current threshold, battery voltage is above recharge voltage threshold, and device not in AICR, MIVR or thermal regulation. Table 3. Default Charging Parameters Default Mode RT9470/D Charging Voltage 4.2V Charging Current 2A Pre-Charge Current 150mA End of Charge(EOC) Current 200mA Temperature Profile JEITA Fast Charge Safety Timer 10 Hours When battery voltage is discharged below recharge threshold (threshold setting through VRE_CHG register bits), the device restarts a new charging cycle automatically. After the charge is done, toggle CE pin or CHG_EN can restart a new charging cycle.  Battery Charging Profile The device charges the battery in five status : trickle charge, pre-charge, constant current, constant voltage and back-ground charge (optional). A charging cycle starts with following condition : 1. Buck converter starts. Table 4. Charging Current Setting Current Parameter Default Current Setting IC_STAT ITRICKLE_CHG 100mA 0010 IPRE_CHG 150mA 0011 ICHG_REG 2A 0100 IEOC_CHG 200mA 0111 VBAT_REG[6:0] VRE_CHG Battery Voltage ICHG_REG[5:0] Charge Current VPRE_CHG_RISE[6:4] VTRICKLE_CHG_RISE IPRE_CHG[3:0] IEOC_CHG[7:4] ITRICKLE_CHG Trickle Charge Pre-Charge Fast Charge Constant Current Fast Charge Constant Voltage Back-Ground End of Charge Charge (optional) Figure 3. Charging Profile Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT9470/D  switching to supply power to the system. BATFET will turn on again when battery voltage is under recharge voltage threshold or device is in Battery Supply Mode during EOC. End of Charge (EOC) The charger enters end of charge status when battery voltage is above recharge threshold, and the charge current is below IEOC_CHG. IEOC_CHG setting range is from 50mA to 800mA with 50mA resolution. After EOC, the BATFET turns off with TE = 1 and BG_CHG_TMR = 00, and the buck converter keeps When EOC occurs, there are four conditions as below : Table 5. EOC Status Scenario TE = 1 BG_CHG_TMR (disable) TE = 1 BG_CHG_TMR (counting) TE = 1 BG_CHG_TMR (timeout) TE = 0 BG_CHG_TMR (disable) ST_EOC 1 1 1 1 ST_CHG_DONE 1 0 1 0 ST_BG_CHG 0 1 0 0 STAT Pin High High High Low IC_STAT 0111 0110 0111 0101 BATFET OFF ON OFF ON 1. If the device triggers AICR, MIVR, JEITA or thermal regulation status during charging, the actual charging current will be less than programmed value. In this condition, EOC function will be disabled and the safety timer’s counter clock rate will be half. 2. The back-ground charge can be applied after EOC is detected. The back-ground charge is enabled by setting BG_CHG_TMR and TE = 1 only. When back-ground charge occurs, the IC_STAT is set to 0110, and the BATFET will turn off after back-ground charge timer expires.  Optimized VDS on BATFET The device deploys power path function with BATFET separating system from battery. The minimum system voltage is set by VSYS_MIN bits (default 3.5V). When the battery voltage is under VSYS_MIN setting, the BATFET operates in linear mode (LDO mode) and the system voltage is typically 200mV above the VSYS_MIN setting. When the battery voltage rises above VSYS_MIN, BATFET turns fully on to minimize RDS(ON) for optimizing VDS (voltage different between VSYS and VBAT) on BATFET. 3. The BG_CHG_TMR gets reset at one of the following conditions : 4.5 CHG_EN disable to enable 4.3  EOC status re-trigger 4.1  EOC_RST bit is set  REG_RST bit is set  VSYS (V)  BATFET off 3.9 BATFET on 3.7 BG_CHG_TMR value changes VSYS_MIN 3.5 An INT pulse is asserted to host when entering back-ground charge and back-ground charge timer expires. 3.1 VBAT (V) 2.7 2.9 3.1 3.5 3.7 3.9 4.1 4.3 Figure 4. VSYS vs. VBAT Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D When BATFET turns off and battery voltage is above VSYS_MIN, the system is regulated at typically 50mV above battery voltage. The status register ST_SYS_MIN = 1 when the system is in minimum system voltage regulation.   During charge status, when voltage difference between VBAT and VSYS above 50mV, the BATFET turns on and the BATFET gate is regulated the gate driver of BATFET to minimize VBAT-VSYS voltage stays at 40mV to prevent entering and exiting the battery supply mode frequently. When the voltage of VBAT-VSYS below 0mV, the charger exits the battery supply mode, and starts to charge battery. Power Management System To apply maximum current and avoid over loading from the power source on VBUS, the device’s Power Management System continuously monitors the power source voltage and current. When power source is overloaded, either the current exceeds the AICR or the voltage drops to MIVR, the device will reduce the charge current to priority power energy for system. When the charge current is reduced to zero, but power source still triggers AICR or MIVR, the VSYS starts to drop. Once the VSYS drops under VBAT, the device automatically change to battery supply mode, and the BATFET turns fully on and battery starts to discharge so that the system is supported from both battery and power source. Voltage VBUS 5V MIVR VSYS VBAT Battery Supply Mode  JEITA Protection During Charge Mode The device provides a single thermistor input for temperature monitor. To achieve battery thermal protection, JEITA guidelines were released in 2007. To start a charge cycle, the voltage on TS pin must be in the T1 to T4 range. The device will stop charging if the battery temperature is lower than T1 (Cold) or higher than T4 (Hot) with JEITA_COLD = 0 and JEITA_HOT = 0. In this case, the IC_STAT = 1000 for charge fault and an INT is asserted to the host. In cool temperature range (T1 to T2), the charge current is reduced to 50% or 25% of ICHG_REG (configured by JEITA_COOL_ISET). In warm temperature range (T3 to T4), the voltage setting of VBAT_REG is reduced to 4.1V or the same as VBAT_REG (configured by JEITA_WARM_VSET). The device provides more flexible settings than JEITA requirement. In cool temperature range (T1 to T2), the charger can set voltage of VBAT_REG down to 4.1V (configured by JEITA_COOL_VSET). Current ISYS ICHG_REG IBAT In warm temperature range (T3 to T4), the charge current can be reduced to 50% of ICHG_REG (configured by JEITA_WARM_ISET). AICR IBUS 0A Battery Supply Mode Figure 5. Power Management System Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 37 RT9470/D Current Voltage Default Setting ICHG_REG Default Setting VBAT_REG Cool_VSET = 1 Warm_ISET = 1 Warm_VSET = 1 4.1V Cool_VSET = 0 ICHG_REG/2 Warm_VSET = 0 Cool_ISET = 0 Warm_ISET = 0 ICHG_REG/4 Cool_ISET = 1 Cold Cool T1 Normal T2 Warm T3 Temperature Hot Cold T4 Cool T1 Normal T2 Warm T3 Temperature Hot T4 Figure 6. JEITA Protect for Charging Current and Voltage There are four sections which are implemented for JEITA protection. Base on RHOT and RCOLD, RT1 and RT2 can be calculated with equation (1) and (2). Herein, RHOT is the NTC resistance of battery over-temperature threshold, and RCOLD is the NTC resistance of battery under-temperature threshold. RT1 = VREGN × [(1⁄ VT1 - 1⁄VT4 ) / (1⁄RCOLD - 1⁄RHOT )]………….(1) RT2 = RT1 × [1⁄(VREGN / VT1 -RT1 / RCOLD -1)]………….(2)   Charging Safety Timer The device has safety timer to prevent abnormal charging time due to poor battery condition. The device can be set CHG_SAFE_TMR bits to change timer for fast charge cycle. When the safety timer expires, the device stops charging, the IC_STAT = 1000 for charge fault, ST_CHG_TOUT = 1, and an INT is asserted to the host. The safety timer can be disable by setting CHG_SAFE_TMR_EN = 0. Table 6. Charging Safety Timer Thermal Protect During Boost Mode To start a boost mode to discharge from battery, the voltage on TS pin must be in T0 to T4 range. The device will stop converter if the battery temperature is lower than T0 (COLD_OTG) or higher than T4 (HOT_OTG). In this case, the IC_STAT = 1000 for charge fault and an INT is asserted to the host. Once temperature returns to normal range, the boost mode is recovered. Voltage VBAT Safety Timer < VPRE_CHG 2 Hours > VPRE_CHG 5 Hours, 10 Hours (Default), 15 Hours, 20 Hours When the charger in AICR, MIVR, JEITA cool, JEITA warm or thermal regulation, the safety timer’s counter clock rate will be half. For example, if charger in AICR status, and timer setting is 10 hours, the actual safety timer will expire in 20 hours. The extended charge timer setting can be disabled by setting CHG_SAFE_TMR_2XT = 0. VOTG_CV The safety timer will be reset by : Disable Boost Enable Boost Disable Boost 1. Toggle CE pin 2. CHG_EN disable/enable 3. CHG_SAFE_TMR disable/enable Cold T0 Normal T1 Hot 4. REG_RST is set. T4 Temperature Figure 7. Thermal Protect During Boost Mode Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 38 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D  MediaTek Pump Express+ (MTK, PE+) Status Outputs The device can provide an input current pulse to communicate with an MTK-PE+ high voltage adapter. When PE_EN bit is enabled, the device can increase or decrease adapter output voltage by setting PE10_INC to the desired value. After enabling PE function, the device will generate a VBUS current pattern for the MTK-PE+ adapter to automatically identify whether to increase or decrease output voltage. Once the PE pattern is finished, PE_EN bit will clear to 0, and an INT is asserted to the host to indicate PE_DONE.   (PG Pin and The PG pin goes low to indicate a good power source when : 1. VBUS above VBUS_MIN_RISE, and IBADSRC is applied. 2. VBUS above VBAT (not in sleep mode) 3. VBUS below VAC_OVP threshold setting 4. HZ = 0 (not in HZ mode) 5. The charger thermal is under THREG threshold setting Adaptive Input Current Control (AICC) The AICC function provides an adaptive AICR setting to prevent input voltage drops. When the input power source is over-current and the VBUS drops to the MIVR level, set AICC_EN bit to 1, the device will automatically decrease AICR level step by step until exit MIVR event. Once AICC is finished, AICC_EN bit will clear to 0, and an INT is asserted to the host to indicate AICC_DONE. Power Good Indicator ST_CHG_RDY Bit) 6. Completed VBUS Source Type Detection  Charging Status Indicator (STAT Pin) The device indicates IC_STAT on STAT pin. The STAT pin is an open drain that can be used to drive LED. The STAT pin function can be disable by setting the STAT_EN = 0. VBUS MIVR Target AICR Adaptive AICR by AICC 50mA Power Source Current Limit IBUS AICC_EN Figure 8. AICC Enable Table 7. STAT Pin State IC_STAT STAT Indicator Trickle, Pre, Fast charge, IEOC-charge (EOC and TE = 0) Low Charge done, Back-Ground charge High HZ/SLEEP, VBUS ready for charge, OTG High Charge fault Blinking at 1Hz Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 39 RT9470/D  Interrupt to Host (INT Pin) The device reports IRQ to host by the INT pin, which is an open drain output. The INT pin generates a pulse low with 256s when IRQ event occurs. All IRQ events are masked for default setting. When a fault occurs, the device pulses an INT to the host and keeps IRQ event in register 0x20 to 0x23 until the host reads the IRQ registers. Before the host reads IRQ registers to clean IRQ events, the device would not send any INT pulse again unless any new event occurs. Table 8. STATUS, FLAG and MASK Register Map Name STAT IRQ MASK VBUS_GD Y Y Y CHG_RDY Y Y Y IEOC Y Y Y BK_CHG Y Y Y CHG_DONE Y Y Y RECHG N Y Y DETACH N Y Y BC12_DONE Y Y Y MIVR Y Y Y AICR Y Y Y CHG_THREG Y Y Y CHG_BUSUV Y Y Y CHG_TOUT Y Y Y CHG_SYSOV Y Y Y CHG_BATOV Y Y Y JEITA_HOT Y Y Y JEITA_WARM Y Y Y JEITA_COOL Y Y Y JEITA_COLD Y Y Y SYS_MIN Y Y Y SYS_SHORT N Y Y OTP Y Y Y VAC_OV Y Y Y WDT Y Y Y OTG_CC Y Y Y OTG_LBP N Y Y OTG_FAULT N Y Y Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 40 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Protections       IBUS Overload Protection in Boost Mode In addition, the device has thermal shutdown to turn off the converter when the IC surface temperature exceeds TOTP (160°C) and an INT is asserted to the host indicate OTP fault. The converter is recovered when the surface temperature is below TOTP (160°C) - TOTP_HYS (30°C). VBUS Soft-Start VSYS Over-Voltage Protection SYSOVP threshold is set at 5.2V. Once VSYS is above SYSOVP level, buck stops switching immediately and an INT pulse is asserted to host to indicate CHG_SYSOV fault. The device provides 30mA current sink on VSYS to bring down the VSYS voltage. Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 Thermal Protection in Buck Mode The device monitors the internal junction temperature to avoid overheat. When in buck mode, the thermal regulation threshold is set at 120°C (programmable by register THREG bits). When junction temperature exceeds thermal regulation threshold, the device decreases the charge current. During thermal regulation, EOC function is disabled, the safety timer’s counter clock rate will be half and an INT is asserted to the host indicate CHG_THREG. When the boost function is enabled, the device soft-starts on VBUS to avoid inrush current.  Battery Over-Discharge Protection When battery is discharged below VBAT_DPL_FALL, the BATFET turns off to protect battery over discharged. When VBUS is plugged in, the BAFET turns on to charge battery. The device monitors boost output voltage and current to provide VBUS short circuit protection. The device also builds in constant current regulation to allow OTG to adaptive to various types of load. If short circuit is detected on VBUS, the boost will hiccup 7 times. If boost retries are not successful, OTG_EN bit will set to 0 to disable boost mode and INT pulse is asserted to the host to indicate OTG_FAULT.  Battery Over-Voltage Protection The BAT_OVP threshold is 4% above the VBAT_REG setting. When battery exceeds overvoltage threshold, the device disables charging immediately and an INT is asserted to the host to indicate CHG_BATOV. VBUS Over-Voltage Protection in Boost Mode When boost mode, VAC_OVP setting is locked at 6.5V even if VAC_OVP threshold is set at 10.5V or 14V. When the output voltage (VBUS) exceeds VAC_OVP threshold, the device stops switching immediately, clear OTG_EN bit to 0 and exit boost mode. The fault (OTG_FAULT) is set to high and an INT pulse is asserted to the host to indicate in boost mode. When the output voltage falling VAC_OVP_HYS below VAC_OVP threshold, the OTG_EN bit can be set to 1 by the host.  When the system is shorted or overloaded (IBAT > IOCP_BATFET), the device latches off BATFET (forces enter shipping mode) and an INT pulse is asserted to host to indicate SYS_SHORT fault. Exit shipping mode can reset the latch-off condition and turn on BATFET. VBUS Over-Voltage Protection in Buck Mode If VBUS voltage over VAC_OVP setting (programmable by VAC_OVP bits), the device stops switching immediately and an INT pulse is asserted to the host. When VBUS overvoltage, the status ST_VAC_OV = 1 and the IC_STAT = 1000 for charge fault. The device resume to normal operation when VBUS voltage drops below the VAC_OVP threshold. VSYS Over-Current Protection  Thermal Protection in Boost Mode The device has thermal shutdown during boost mode. In boost mode, when the IC surface temperature exceeds TOTP (160°C), the OTG_EN bit is set to 0 to disable boost mode and an INT is asserted to the host indicate OTP fault. When the surface temperature is below TOTP (160°C) TOTP_HYS (30°C), the host can re-enable boost mode by setting OTG_EN bit to 1. is a registered trademark of Richtek Technology Corporation. www.richtek.com 41 RT9470/D I2C communication, beginning with START (S) condition, and then the host sends slave address. This address is 7-bits long followed by an eighth bits which is a data direction bit (R/W). The second bytes is register address. The third bytes contains data to the selected register. End with STOP (P) condition. Communicate Interface The RT9470 use I2C compatible interface by 2-wire line (SCL and SDA) to communicate with the host. The SCL and SDA pins are open drain which needs to connect to supply voltage by pull-up resistors. The RT9470 operates as an I2C slave device with 7-bits address 53H, supports up to 3.4Mbits conditionally. To start an Read single byte of data from Register Slave Address Register Address S 0 Slave Address A MSB A Sr 1 LSB A A Assume Address = m R/W Data P Data for Address = m Read N bytes of data from Registers Slave Address Register Address S 0 Slave Address A MSB A Sr 1 MSB A Data for Address = m Data 2 LSB MSB Data N LSB A A S 0 Register Address Write N bytes of data to Registers Slave Address 0 LSB A P Data for Address = m Register Address MSB A Data 1 LSB A Assume Address = m R/W Data A Assume Address = m R/W S MSB A P Data for Address = m + N - 1 Data for Address = m + 1 Write single byte of data to Register Slave Address LSB A Assume Address = m R/W Data 1 MSB Data 2 LSB A Data for Address = m MSB A Data for Address = m + 1 Data N LSB A P Data for Address = m + N - 1 Driven by Master, Driven by Slave, P Stop, S Start, Sr Repeat Start Figure 9. Read and Write Function SDA tLOW tF tSU;DAT tR tF tHD;STA tBUF tR tSP SCL tHD;STA S tHD;DAT tHIGH tSU;STA tSU;STO Sr P S Figure 10. I2C Waveform Information  I2C Time-out Reset To avoid I2C hang-ups, a timer runs during I2C activity. If the SDA keep low longer than 1 second, Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 42 the RT9470 will reset I2C to release SDA goes back to High. The I2C hang-ups reset function can be disable by register 0x01[3] bit. is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Thermal Considerations PD(MAX) = (TJ(MAX) - TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. Maximum Power Dissipation (W)1 The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : 4.5 Four-Layer PCB 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 150 Ambient Temperature (°C) Figure 11. Derating Curve of Maximum Power Dissipation For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 150°C. The junction-to-ambient thermal resistance, JA, is highly package dependent. For a WL-CSP-30B 2.1x2.5 (BSC) package, the thermal resistance, JA, is 29.6°C/W on a standard JEDEC 51-7 high effective-thermal-conductivity four-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below : PD(MAX) = (150°C - 25°C) / (29.6°C/W) = 4.22W for a WL-CSP-30B 2.1x2.5 (BSC) package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, JA. The derating curves in Figure 11 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 43 RT9470/D Layout Considerations  The RT9470/D layout guidelines are shown as below, there are several suggestions provided.   placed as close as possible to the RT9470/D.  The capacitor, connected to PMID pin needs to be placed as close as possible to the RT9470/D. The capacitors, connected to IC pins need to be The VBUS needs to router two layers power plane to reduce resistance.  The SYS needs to router two layers power plane The inductor, connected to SW pin needs to not to reduce resistance. Otherwise, the accuracy of only router the trace as short as possible to reduce ICHG will be affected. the EMI but also make sure copper area of the trace is enough for the operating current. TOP Layer Inner Layer1 CPMID Inner Layer2 VBUS GND 0603C Bottom Layer CBUS 0201C CBTST 0402C L GND SW PMID VBUS VAC GND SW PMID VBUS NC BAT SYS BTST REGN PSEL/ D+ BAT SYS TS QON PG/ D- CBAT 0603C 2520L GND BAT SYS CE SDA STAT BAT SYS BAT SNS INT SCL 0603C CREGN GND 0603C VBAT v GND VSYS 0603C VSYS CSYS Figure 12. PCB Layout Guide Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 44 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019 RT9470/D Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.500 0.600 0.020 0.024 A1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 D 2.460 2.540 0.097 0.100 0.079 0.000 0.081 0.084 0.063 0.000 D1 E 2.000 2.060 2.140 E1 1.600 e 0.400 0.016 30B WL-CSP 2.1x2.5 Package (BSC) Copyright © 2019 Richtek Technology Corporation. All rights reserved. DS9470/D-01 August 2019 is a registered trademark of Richtek Technology Corporation. www.richtek.com 45 RT9470/D Footprint Information Package Number of Pin Footprint Dimension (mm) Type Tolerance e NSMD WL-CSP2.1x2.5-30(BSC) 30 A B 0.240 0.340 0.270 0.240 0.400 SMD ±0.025 Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2019 Richtek Technology Corporation. All rights reserved. www.richtek.com 46 is a registered trademark of Richtek Technology Corporation. DS9470/D-01 August 2019