RT9645GQV

Preliminary RT9645 5 Channels ACPI Regulator General Description The RT9645 is a combo regulator which is compliant to ACPI specification for desktop/server power management and system application. The part features one switching regulator for DDR memory VDDQ power; a second PWM controller for GMCH core power, a LDO controller for FSB_ VTT termination, a LDO controller for 5VSB to 3VSB conversion; and a dual power control 5VDL for S0 and S3 system power. The part is generally operated to conform to ACPI specification. In S3 mode, only VDDQ and 3.3VSB regulators remain on while the FSB_ VTT regulator is off. In the transition from S3 to S0, an internal SS capacitor is attached for linear regulators to control its slew rate respectively to avoid inrush current induced. RT9645 supports both Intel VR11 and AMD K8 platform. There is extra control pin VTT_EN to enable FSB_VTT regulator at AMD K8 mode. This part also implements PWM1 (VDDQ) enabled by release COMP1 at AMD K8 application. This part is assemblyed in the tiny VQFN-24L 4x4 package. Features Integrated 5 Channels Power Regulator DC/DC Buck PWM Regulator (Driver Included) DC/DC Buck PWM Controller Linear Regulator Controller for FSB_VTT Power 3.3VSB Linear Regulator Controller with 40mA Output Capability 5VDL Switch Control Conform to ACPI Specification, Supporting Power Management at S0, S3, and S5 State 300kHz Fixed Frequency Oscillator Low-Side RDS(ON) Current Sensing for Precision Over-Current Detection Thermal Shutdown Small 24-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free Applications Desktop System Power Server System Power Pin Configurations Ordering Information RT9645 SB5V_DRV 20 (TOP VIEW) SB3V_SEN VCC_DRV Package Type QV : VQFN-24L 4x4 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. S3 24 23 22 S5 21 SB3V_DRV VDD PWM2 SS2/EN2 COMP2 FB2 GND 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 25 12 VTT_DRV VTT_SEN VTT_EN ISNS2 FB1 COMP1 PGND 15 14 13 BOOT ISNS PHASE PVIN VQFN-24L 4x4 DS9645-00 August 2007 UGATE LGATE www.richtek.com 1 RT9645 Typical Application Circuit Preliminary VCC5 5VSB VCC12 2 VDD VCC5/VCC12 Q3 VGMCH Q4 Richtek MOSFET Driver ROCSET2 3 11 PVIN BOOT ISNS 7 10 ROCSET1 5VDL PWM2 RT9645 15 UGATE ISNS2 COMP2 FB2 GND VTT_DRV COMP1 13 14 VCC5 VCC_DRV 21 5VDL 8 Q1 L1 VDDQ PHASE 9 LGATE 12 19 Q2 5 6 VCC3 FSB_VTT 5VSB Q6 3VSB 1 Q5 18 17 VTT_SEN FB1 SB3V_DRV 24 SB3V_SEN PWM2-EN 4 SS2/EN2 16 VTT_EN 23 S3 SB5V_DRV 20 5VSB VLDT_EN S3 S5 22 S5 Figure 1. RT9645 Typical Application for Intel Mode VCC5 5VSB VCC12 2 VDD VCC5/VCC12 Q3 VGMCH Richtek MOSFET Driver ROCSET2 3 11 PVIN BOOT ISNS 7 10 ROCSET1 5VDL PWM2 RT9645 15 UGATE ISNS2 COMP2 FB2 GND VTT_DRV COMP1 13 14 5VSB Q4 8 Q1 L1 VDDQ PHASE 9 LGATE 12 19 Q2 5 6 VCC3 FSB_VTT 5VSB Q6 3VSB 1 Q5 18 17 VTT_SEN FB1 SB3V_DRV 24 SB3V_SEN VCC_DRV 21 20 VCC5 5VDL PWM2-EN 4 SS2/EN2 SB5V_DRV 16 VTT_EN 23 S3 S5 VDDQ_EN VLDT_EN S3 5VSB 22 S5 Figure 2. RT9645 Typical Application for AMD K8 www.richtek.com 2 DS9645-00 August 2007 Preliminary Timing Diagram ~3Tss 5VSB 3VSB PVIN S5 S3 VCC5/12 5VDL VDDQ FSB_VTT ~Tss ~Tss ~Tss ~Tss 5VSB- VD POR VCC12 - VD RT9645 Figure 3. RT9645 Timing Diagram for Intel CPU ~3Tss 5VSB 3VSB PVIN S5 S3 VCC5/12 5VDL VDDQ_EN VDDQ VTT_EN FSB_VTT ~Tss ~Tss ~Tss ~Tss 5VSB- VD POR VCC12 - VD Figure 4. RT9645 Timing Diagram for AMD CPU VPT_EN2 SS2/EN2 VEN2 PWM2_EN (Internal) PWM2 (Output) PWM2 UV Protection_EN Release fault Figure 5. RT9645 Timing Diagram for PWM2 DS9645-00 August 2007 www.richtek.com 3 RT9645 Functional Pin Description Pin No. 1 Preliminary Pin Name Function Description SB3V_DRV Gate Drive for 3.3VSB Linear Controller. The pin will be high in S0, S3 and S5 state. IC Power Supply. 5VSB is generally applied for bias power for IC logics and gate 2 VDD driver control. 3 PWM2 Second PWM Output Signal Second PWM Soft Start Ramp/Enable Control SS ramp slope is defined by 4 SS2/EN2 V/T = 5μA/CSS. Compensation pin of PWM2. Output of the PWM2 error amplifier. Connect 5 COMP2 compensation network between this pin and FB2. The output feedback of PWM2. The pin is applied for voltage regulation and provide 6 FB2 under-voltage protection. The pin is applied for VDDQ PWM bootstrapped power for the embedded driver 7 BOOT power. High-Side Drive. High-side MOSFET driver output of VDDQ PWM. Connect to gate 8 UGATE of high-side MOSFET. Phase Node of VDDQ PWM. The pin is applied to sense phase node of VDDQ 9 PHASE PWM for gates switch control. Current Sense Input. Monitors the voltage drop across the low-side MOSFET for 10 ISNS Over current protection. ROCSET1 x 40μA = RDS(ON) x IMAX 11 PVIN Apply to Driver Power Source and generate Internal Power Good Signal. Low-Side Drive. The low-side MOSFET driver output. Connect to gate of low-side 12 LGATE MOSFET. Compensation pin of VDDQ. Output of the VDDQ error amplifier. Connect compensation network between this pin and FB1 In AMD Application. This pin can 13 COMP1 be used to control VDDQ sequence. This pin needs to be pulled low ( < VDIS1) to disable the PWM. The output feedback of PWM1. The pin is applied for voltage regulation, 14 FB1 under-voltage and Over Voltage protection. PWM2 Current Sense Input. Monitors the voltage drop across the low-side 15 ISNS2 MOSFET for Over current protection. ROCSET2 x 40μA = RDS(ON) x IMAX 16 VTT_EN In AMD K8 Application, Connect this pin to VLDT_EN to control FSB_VTT Timing. Feedback for the FSB_VTT Linear Controller. The pin is applied for FSB_VTT LDO 17 VTT_SEN output regulation sense. Gate drive for FSB_VTT Linear Controller. The pin will be turned off in S3 and S5 18 VTT_DRV state. 19 GND Signal Ground. 5VSB Control Switch. The pin is applied to drive an external P-Channel MOSFET to 20 SB5V_DRV switch 5VDL power to 5VSB in S3 state. The pin goes high in S0 and S5 States. VCC5 Control Switch. The pin is applied to driver an external N-Channel MOSFET 21 VCC_DRV low in S5 and S3 States. The pin goes high in S0 State. 22 S5 ACPI Control Signal. 23 S3 ACPI Control Signal. Feedback for the 3.3VSB Linear Controller. The pin is applied for 3.3V LDO output 24 SB3V_SEN regulation sense. The exposed pad must be soldered to a large PCB and connected to PGND for Exposed Pad (25) PGND maximum power dissipation. www.richtek.com 4 DS9645-00 August 2007 Preliminary Function Block Diagram SS2/EN2 FB2 FB COMP1 RT9645 EN_Detect EN_Detect SS COMP2 + + VREF PWM2 SB3V_SEN VDD SB3V_DRV + 35k + Digital & Peripheral Control + VDDQ UV or FSB-VTT UV VDDQ OC SB3V Fault (UV &OC) Thermal shut_down Back S5 IOC1 40uA ISNS ISNS2 70k + IOC2 40uA + Oscillator UV + VREF + + PHASE PVIN LGATE BOOT UGATE PVIN VTT_DRV VTT_EN VTT_SEN VDD + + - PVIN VCC_DRV Hiccup VDD SB5V_DRV GND S3 S5 DS9645-00 August 2007 www.richtek.com 5 RT9645 Absolute Maximum Ratings Preliminary (Note 1) 7V 16V −0.5V to 7V −2V to 7V −0.3V to 20V −0.3V to 22V 16V VPHASE − 0.3V to VBOOT + 0.3V GND − 0.3V to VDD + 0.3V GND − 0.3V to 7V 1.85W 54°C/W 150°C 260°C −40°C to 150°C 2kV 200V Supply Voltage, VDD ------------------------------------------------------------------------------------Supply Voltage, PVIN ----------------------------------------------------------------------------------PHASE to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------BOOT to GND DC -----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------BOOT, VBOOT − VPHASE ---------------------------------------------------------------------------------UGATE Voltage ------------------------------------------------------------------------------------------LGATE Voltage -------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C VQFN-24L 4x4 -------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) VQFN-24L 4x4, θJA --------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------- Recommended Operating Conditions (Note 3) 5V ± 5% 12V ± 10% −40°C to 125°C 0°C to 70°C Supply Voltage, VDD ------------------------------------------------------------------------------------Supply Voltage, PVIN ----------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------- Electrical Characteristics (VDD = 5V, PVIN = 12V, TA = 25°C, unless otherwise specification) Parameter S upply Current Nominal Supply Current P ower-On Reset Rising VDD POR Threshold V DD POR Hysteresis Rising PVIN POR Threshold P VIN POR Hysteresis Symbol Test Condition S0; no load for UGATE / LGATE and regulators Min Typ Max Units ICC -- 4 -- mA VPORH_5V VPORHY S_5V VPORH_12V VDD = 5 V 3.9 0.06 9 0.6 4.1 0.1 9.5 1 4.3 -10 -- V V V V VPORHY S_12V VDD = 5 V To be continued www.richtek.com 6 DS9645-00 August 2007 Preliminary Parameter O scillator and Soft-Start PW M Frequency Ramp Amplitude Ramp Offset S oft-Start Interval Reference Voltage Reference Voltage V REF V DDQ PWM1 Controller UGATE Source UGATE Sink LGATE Source LGATE Sink O C Current Source Under Voltage Lockout COMP1 Enable Threshold P WM2 Controller O C current source Under Voltage Lockout S S2/EN2 Source Current E nable Threshold UV Protection Enable Threshold FSB_VTT Regulator E xternal Gate Driver G ate Source Current G ate Sink Current Under Voltage Lockout 3VSB Regulator Regulated Voltage S ource Current O C Current Under Voltage Lockout O thers S 3, S5 High Input Threshold S 3, S5 Low Input Threshold Thermal Shutdown Limit V IL V IH TSHDN -2.2 ---140 V 3VSB ISC4 IOC4 V UV4 3.2 30 40 -3.3 40 80 75 VOH3 ISC3 ISK3 VUV3 V PVIN = 12V V VTT_DRV = 3V V VTT DRV = 0.6V 10.5 -15 --4 22 75 IOC2 V UV2 ISS2 V EN2 V PT_EN2 V DD = 5V V SS2/EN2 = 0V V IS NS2 = 0V 34 ----40 75 5 0.5 3.6 IUGATEsc RUGATEsk V BOOT −V PHASE = 12V; V UGATE − VPHA SE = 6 V V BOOT −V PHASE = 12V; V UGATE − VPHASE = 1V 0.5 -0.5 -34 -0.1 1 4 1 3 40 75 0.2 VREF 0.784 0.8 fOSC ΔVOSC VOSC_OS TSS 265 --4 300 1.2 0.9 8 Symbol Test Condition Min Typ RT9645 Max 345 ---Units kHz V V ms 0.816 V -8 -5 46 --- A Ω A Ω μA % V μA % μA V V ILGATEsc V PVIN = 12V; VLGATE = 6 V RLGATEsk V PVIN = 12V; VLGATE = 1 V IOC1 V UV1 V EN1 V IS NS = 0V 46 ----- ----3.4 ---- V mA mA % V mA mA % 0.75 --- V V °C DS9645-00 August 2007 www.richtek.com 7 RT9645 Preliminary Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is highly recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA i s measured in the natural convection at T A = 25 °C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad for the QFN package. www.richtek.com 8 DS9645-00 August 2007 Preliminary Application Information Overview The RT9645 integrates two synchronous buck PWM controllers, two LDO controllers, and a dual power switching controller. It is primarily designed for computer applications powered from an ATX power supply. A 300kHz Synchronous Buck PWM controller with a precision 0.8V reference provides the proper Core voltage to the system main memory. A second 300kHz PWM Buck controller which requires an external MOSFET driver, provides the GMCH core voltage. One LDO controller regulates for FSB_VTT termination and other one is for the 3VSB power regulation. RT9645 also provides a dual power control 5VDL for S0 and S3 system power. Table 1 State VCC_DRV SB5V_DRV 5VDL S5 L H Off S3 L L On S0 H H On S tate S5 S3 S0 FSB_VTT Off Off On 3VSB On On On VDDQ Off On On RT9645 S0 to S3 Transition When S3 goes LOW but S5 still HIGH ,the RT9645 will disable FSB_VTT regulators. SB5V_DRV and VCC_DRV will go low to continually power on 5VDL rail. The memory power VDDQ is also maintained. S3 to S0 Transition When S3 transits from LOW to HIGH with S5 keeps HIGH and after the PVIN exceeds its POR threshold, in Intel mode the RT9645 will wait a time delay TSS and then softstarts FSB_VTT LDO. In AMD mode, FSB_VTT will softstart after VTT_EN goes high. S0 to S5 Transition When the system transits from active state to shutdown (S0 to S5) state, the RT9645 keeps powering 3VSB and turn off the other power regulators. Fault Protection The RT9645 monitors the VDDQ ,PWM2 and 3VSB regulator for under voltage and over-current protection. The FSB_VTT LDO regulator is monitored for under voltage protection. If RT9645 detects thermal Shutdown, over current (or Under Voltage) of 3VSB, the RT9645 will immediately shutdown all regulators and jump to first system state to redo power sequence. When VDDQ issues Under Voltage or Over Current or FSB_VTT issues Under Voltage, the RT9645 will immediately enters into S5 sleep state.This can only be cleared by toggling the S5 signal. VDDQ and PWM2 Over Current Protection The RT9645 senses the current flowing through low side MOSFET for over current protection (OCP). A 40μA current source flows through the external resistor ROCSET to PHASE pin causes 40μA x ROCSET voltage drop across the resistor. OCP is triggered if the voltage at PHASE pin (drop of lower MOSFET VDS) is lower than Rocset voltage drop when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a function of conducting resistance of lower MOSFET RDS(ON) as : IOCSET = 40μA × ROCSET RDS(ON) ACPI State Transitions ACPI compliance is realized through the S3 and S5 sleep signals. Figure 3 shows how the RT9645 regulators are working during all state transitions. S5 to S0 Transition After AC power is plugged, the RT9645 stays in S5 state until the power button is pushed on. The S3 and S5 signals transit to HIGH and the +12V rail starts to ramp up. The RT9645 POR is executed as soon as PVIN voltage exceeds the threshold. In Intel mode, after an internal time delay TSS the VDDQ PWM will enable soft-start sequence and VCC_DRV will change to high. In AMD mode, VDDQ PWM is enabled after VDDQ_EN goes high. FSB_VTT soft-start will follow VDDQ soft-start with a time delay TSS in Intel mode, but in AMD mode FSB_VTT soft-start is triggered by VTT_EN becoming high. After VDDQ rail and the FSB_VTT softstart completes, all RT9645 regulators work in normal operation. Refer to Figure 3 and Figure 4 for the detailed timing diagrams. DS9645-00 August 2007 www.richtek.com 9 RT9645 Preliminary FP _ LC = 1 2π LCOUT 1 2π × ESR × COUT (1) (2) To prevent OC form tripping in normal operation, ROCSET must be carefully chosen with : 1. Maximum RDS(ON) at highest junction temperature 2. Minimum IOCSET from specification table 3. IL(MAX) > IOUT(MAX) + Δ IL / 2 ΔIL = inductor ripple current If Low side MOSFET with RDS(ON) = 6mΩ is used, the OCP threshold current is about 20A. Once OCP is triggered, the RT9645 enters S5 sleep state. FZ _ ESR = UGATE (20V/Div) The compensation network consists of the error amplifier EA and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest DC gain, the highest 0dB crossing frequency (FC) and adequate phase margin. Typically, FC in range 1/5 to 1/10 of switching frequency is adequate. Higher FC will cause faster dynamic response. A phase margin in the range of 45°C to 60°C is desirable. The equations below relate the compensation network poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. FZ1 = FZ2 1 2π × R2 × C1 1 = 2π × (R1 + R3 ) × C3 1 (3) (4) (5) LGATE (10V/Div) VOUT (1V/Div) FP1 = FP2 Time (250μs/Div) I LOAD (10A/Div) 2π × R2 × C1× C2 C1 + C2 1 = 2π × R3 × C3 V IN OSC Driver L Driver PHASE C OUT ESR Z FB V E/A EA + (6) Figure 6. Over Cuuent Protection Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous buck converter. Figure 8 show s the corresponding Bode plot. The output voltage (VOUT) is regulated to the reference voltage. The error amplifier EA output (COMP) is compared with the oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and COUT). The modulator transfer function is the small-signal transfer function of VOUT/COMP. This function is dominated by a DC gain and the output filter (L and COUT), with a double pole break frequency at FP_LC and a zero at FZ_ESR. The DC gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ΔVOSC. The break frequency FLC and FESR are expressed as Equation (1) and (2) respectively. Δ V OSC PWM Comparator + V OUT Z IN REF C2 C1 COMP EA + Z FB R2 C3 Z IN R3 R1 V OUT FB REF R FB Figure 7 www.richtek.com 10 DS9645-00 August 2007 Preliminary 100 80 60 Gain (dB) 40 20 0 -20 -40 -60 10 100 1K F LC 10K F ESR 100K 1M 10M Modulator Gain 20LOG (R1/R2) 20LOG (V IN /Δ V OSC ) Compensation Gain Closed Loop Gain Open Loop Error AMP Gain F Z1 F Z2 F P1 F P2 RT9645 Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. Output Capacitor Selection The output capacitors determine the output ripple voltage (%VOUT) and the initial voltage drop after a high slew rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as Equation (8). Frequency (Hz) Figure 8 Feedback Loop Design Procedure Use these guidelines for locating the poles and zeros of the compensation network : 1. Pick Gain (R2/R1) for desired 0dB crossing frequency (FC). 2. Place 1st zero FZ1 below modulator double pole FLC (~75% FLC). 3. Place 2nd zero FZ2 at modulator double pole FLC. 4. Place 1st pole FP1 at the ESR zero FZ_ESR 5. Place 2nd pole FP2 at half the switching frequency. 6. Check gain against error amplifier's open-loop gain. 7. Pick RFB for desired output voltage. 8. Estimate phase margin and repeat if necessary. Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (%IL) can be calculated as follows : ΔVOUT = ΔIL × ESR + 1 × 8 I2 VOUT × L × COUT (1 − D) (8) OSC For electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as : IIN(RMS) = IOUT × D × (1 − D) The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. MOSFET Selection of PWM Buck Converter The selection of MOSFETs is based upon the considerations of RDS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as : ΔIL = (VIN − VOUT ) × VOUT VIN × IOSC × L (7) PUPPER = PCOND _ UPPER + PSW _ UPPER 2 = IOUT × RDS(ON) × D + 1 IOUT × VIN × (TRISE + TFALL ) × IOSC 2 DS9645-00 August 2007 www.richtek.com 11 RT9645 Preliminary Place the input capacitor directly to the drain of high-side MOSFET. The MOSFETs of linear regulator should have wide pad to dissipate the heat. In multilayer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guide lines can get better performance of IC : The IC needs a bypassing ceramic capacitor as a R-C filter to isolate the pulse current from power stage and supply to IC, so the ceramic capacitor should be placed adjacent to the IC. Place the high frequency ceramic decoupling close to the power MOSFETs. The feedback part should be placed as close to IC as possible and keep away from the inductor and all noise sources. The components of bootstraps should be closed to each other and close to MOSFETs. The PCB trace from Ug and Lg of controller to MOSFETs should be as short as possible and can carry 1A peak current. Place all of the components as close to IC as possible. where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is expressed as : PLOWER = PCOND _ LOWER + PRR + PDIODE = IOUT × RDS(ON) × (1 − D) + QRR × VIN × fOSC 2 + 1 IOUT × Vf × TDIODE × fOSC 2 where TDIODE is the conducting time of lower body diode. Special control scheme is adopted to minimize body diode conducting time. As a result, the RDS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate RDS(ON) to minimize power loss and satisfy thermal requirements. MOSFET Selection of LDO The main criteria for selection of the LDO pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. The power dissipated in the linear regulator is : PD = IOUT(MAX) x (VIN - VOUT) where IOUT(MAX) is the maximum output current and VOUT is the nominal output voltage of LDO. Layout Consideration Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. www.richtek.com 12 DS9645-00 August 2007 Preliminary Outline Dimension D2 RT9645 D SEE DETAIL A L 1 E E2 1 2 1 2 e A A3 A1 b DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol A A1 A3 b D D2 E E2 e L Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 3.950 2.300 3.950 2.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 4.050 2.750 4.050 2.750 Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.156 0.091 0.156 0.091 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.159 0.108 0.159 0.108 V-Type 24L QFN 4x4 Package Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com DS9645-00 August 2007 www.richtek.com 13