R2045D

R2045S/D 4-wire Serial Interface Real Time Clock Module NO.EA-113-0603 OUTLINE The R2045S/D is a real-time clock module, built in CMOS real-time clock IC and crystal oscillator, connected to the CPU by four signal lines, CE, SCLK, SI, and SO, and configured to perform serial transmission of time and calendar data to the CPU. The oscillation frequency is adjusted to high precision (0±5ppm: 15sec. per month at 25°C) The periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (TYP. 0.48µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. The 32-kHz clock output function (N-channel Open drain output) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment circuit is intended to adjust time by correcting deviations in the oscillation frequency of the crystal oscillator. FEATURES • • • • • • • • • • • • • • • • Built in 32.768kHz crystal unit, The oscillation frequency is adjusted to high precision (0±5ppm: at 25°C) Time keeping voltage 1.15V to 5.5V Super low power consumption 0.48µA TYP (1.2µA MAX) at VDD=3V Four signal lines (CE, SCLK, SI, and SO) required for connection to the CPU. Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days, and weeks) (in BCD format) Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the CPU and provided with an interrupt flag and an interrupt halt 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute alarm settings) 32768Hz clock output pin (N-channel open drain output) With Power-on flag to prove that the power supply starts from 0V With Oscillation halt sensing Flag to judge the validity of internal data Supply voltage monitoring circuit with two supply voltage monitoring threshold settings Automatic identification of leap years up to the year 2099 Selectable 12-hour and 24-hour mode settings Oscillation adjustment circuit for correcting temperature frequency deviation or offset deviation CMOS process Two types of package, SOP14(10.1x7.4x3.1) or SON22(6.1x5.0x1.3) 1 R2045S/D PIN CONFIGURATION R2045S (SOP14) N.C. SCLK 32KOUT N.C. VPP VDD CE 1 2 3 4 5 6 7 14 13 12 11 10 9 8 N.C. SO SI VSS INTR N.C. N.C. R2045D (SON22) CE 1 VDD 2 N.C. 3 VPP 4 32KOUT 5 SCLK 6 SO 7 SI 8 VSS 9 INTR 10 N.C. 11 22 21 20 19 18 17 16 15 14 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. TOP VIEW TOP VIEW BLOCK DIAGRAM 32KOUT 32kHz OUTPUT CONTROL COMPARATOR_W ALARM_W REGISTER (MIN,HOUR, WEEK) ALARM_D REGISTER (MIN,HOUR) VOLTAGE DETECT TEST CIRCUIT VPP VSS VDD COMPARATOR_D OSC DIVIDER CORREC -TION DIV TIME COUNTER (SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR) OSC DETECT ADDRESS DECODER ADDRESS REGISTER SCLK I/O CONTROL SI SO INTR INTERRUPT CONTROL SHIFT REGISTER CE 2 R2045S/D PIN DESCRIPTION Symbol CE Item Chip enable Input Description The CE pin is used for interfacing with the CPU. Should be held high to allow access to the CPU. Incorporates a pull-down resistor. Should be held low or open when the CPU is powered off. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SCLK pin is used to input clock pulses synchronizing the input and output of data to and from the SI and SO pins. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SI pin is used to input data intended for writing in synchronization with the SCLK pin. CMOS input. Allows a maximum input voltage of 5.5v regardless of supply voltage. The SO pin is used to output data intended for reading in synchronization with the SCLK pin. CMOS output. The INTR pin is used to output alarm interrupt (Alarm_W) and alarm interrupt (Alarm_D) and output periodic interrupt signals to the CPU signals. Disabled at power-on from 0V. N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage. The 32KOUT pin is used to output 32.768-kHz clock pulses. And controlled by resister setting. When VDD power-on from 0v, this output is enabled. The pin is N-channel open drain output. Allows a maximum pull-up voltage of 5.5v regardless of supply voltage. The VDD pin is connected to the power supply. SCLK Serial Clock Input Serial Input SI SO INTR Serial Output Interrupt Output 32KOUT 32kHz Clock Output VDD VSS VPP N.C. Positive Power Supply Input Negative Power Supply Input Test input No Connection The VSS pin is grounded. This pin is power pin for testing in the factory. Please don’t connect to any other pins. These pins are not connected to internal IC chip. In R2045D (SON22), N.C. pins from 14 pin to 22 pin are connected together internally. Never connect these pins to any lines, or connect to VDD or VSS. And never connect different voltage level lines each other. 3 R2045S/D ABSOLUTE MAXIMUM RATINGS Symbol VDD VI VO PD Topt Tstg Item Supply Voltage Input Voltage 1 Input Voltage 2 Output Voltage 1 Output Voltage 2 Power Dissipation Operating Temperature Storage Temperature Pin Name and Condition VDD CE, SCLK, SI VPP SO INTR , 32KOUT Topt=25°C (VSS=0V) Description -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +6.5 300 -40 to +85 -55 to +125 Unit V V V mW °C °C RECOMMENDED OPERATING CONDITION Symbol VACCESS VCLK VPUP Item Supply Voltage Time Keeping Voltage Pull-up Voltage Pin Name and Condition VDD power supply voltage for interfacing with CPU INTR (VSS=0V, Topt=-40 to +85°C) Min. Typ. Max Unit . 1.7 5.5 V 1.15 5.5 5.5 V V FREQUENCY CHARACTERISTICS Symbol ∆f/f0 Fv Item Frequency Deviation Frequency Voltage Characteristics Frequency Temperature Characteristics Oscillation Start-up Time Aging Condition Topt=25°C, VDD=3V Topt=25°C, VDD=2.0V to 5.5V Topt=-20°C to +70°C 25°C as standard Topt=25°C, VDD=2V Topt=25°C, VDD=3V, First year -5 (VSS=0V) Min. Typ. -5 0 -1 Max. +5 +1 Unit ppm ppm Top -120 +10 ppm tsta fa +1 +5 sec ppm 4 R2045S/D DC ELECTRICAL CHARACTERISTICS Unless otherwise specified: VSS=0V,VDD=3V,Topt=-40 to +85°C Symbol Item Pin Name Condition VIH “H” Input Voltage CE, VDD=1.7 to 5.5V SCLK, SI VIL “L” Input Voltage IOH IOL1 IOL2 IIL RDNCE IOZ1 IOZ2 IDD1 Output Off-state Leakage Current Time Keeping Current “H” Output Current “L” Output Current SO INTR SO, 32KOUT SCLK, SI CE SO INTR , 32KOUT VDD VO=5.5V or VSS VDD=5.5V VO=5.5V VDD=3V, CE, SCLK, SI, SO, INTR , 32KOUT =VSS 32KOUT disabled VDD=5V, CE, SCLK, SI, SO, INTR , 32KOUT =VSS 32KOUT disabled VDD=3V, CE, SCLK, SI, SO, INTR , 32KOUT =VSS 32KOUT enabled Topt=-30 to +70°C 1.90 VOH=VDD-0.5V 2.0 0.5 -1.0 40 -1.0 -1.0 120 1.0 400 1.0 µA 1.0 Min. 0.8x VDD -0.3 Typ. Max. 5.5 0.2x VDD -0.5 Unit V mA VOL=0.4V VI=5.5V or VSS VDD=5.5V mA µA kΩ Input Leakage Current Pull-down Resistance 0.48 1.20 IDD2 VDD 0.60 1.80 µA IDD3 VDD 0.65 2.00 VDETH Supply Voltage Monitoring Voltage (“H”) Supply Voltage Monitoring Voltage (“L”) VDD 2.10 2.30 V VDETL VDD Topt=-30 to +70°C 1.15 1.30 1.45 V 5 R2045S/D AC ELECTRICAL CHARACTERISTICS Unless otherwise specified: VSS=0V,Topt=-40 TO +85°C Input / Output condition: VIH=0.8xVDD,VIL=0.2xVDD,VOH=0.8xVDD,VOL=0.2xVDD,CL=50pF Symbol Item CondiVDD≥1.7V tions Min. Typ. tCES CE Set-up Time 400 tCEH CE Hold Time 400 tCR CE Recovery Time 62 fSCLK SCLK Clock Frequency tCKH SCLK Clock High Time 400 tCKL SCLK Clock Low Time 400 tCKS SCLK Set-up Time 200 tRD Data Output Delay Time tRZ Data Output Floating Time tCEZ Data Output Delay Time After Falling of CE tDS Input Data Set-up Time 200 tDH Input Data Hold Time 200 Unit Max. ns ns µs MHz ns ns ns ns ns ns ns ns 1.0 300 300 300 tCKH CE tCKS SCLK tCES tCKL tCEH tCR tDS SI SO tDH tCEZ tRD tRD tRZ *) For reading/writing timing, see “P.26 •Considerations in Reading and Writing Time Data under special condition”. 6 R2045S/D PACKAGE DIMENSIONS • R2045S (SOP14) 10.1± #14 0.2 0°-10° #8 0.2 5.0± 7.4± 0.2 #1 #7 0.15 +0.1/-0.05 1.24typ. +0.1/-0.05 +0.0/-0.05 0.1 0.35 +0.1/-0.05 1.27± 0.1 0.1 1.2 • R2045D (SON22) 6.1± #22 0.2 3.1 0.65 #14 A’ #14 #22 0.6± 0.25 0.05 0.2 4.7± 5.0± 0.2 A B B #1 0.2± 0.1 0.5± 0.1 #11 0.43 #11 A A’ #1 1.3± 0.125 0.1 0.1 B +0.1/-0.05 0.2 0.1 0.3 0.2 0.2 0.55typ. 0.3 0.43 0.3± 0.1 7 R2045S/D GENERAL DESCRIPTION • Interface with CPU The R2045S/D is connected to the CPU by four signal lines CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO (Serial Output), through which it reads and writes data from and to the CPU. The CPU can be accessed when the CE pin is held high. Access clock pulses have a maximum frequency of 1 MHz allowing high-speed data transfer to the CPU. • Clock and Calendar Function The R2045S/D reads and writes time data from and to the CPU in units ranging from seconds to the last two digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such. • Alarm Function The R2045S/D incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from INTR pin, and the Alarm_D outputs also from INTR pin. Each alarm function can be checked from the CPU by using a polling function. High-precision Oscillation Adjustment Function To correct deviations in the oscillation frequency of the crystal oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to ±1.5 ppm at 25°C) from the CPU within a maximum range of approximately + 189 ppm in increments of approximately 3 ppm. Such oscillation frequency adjustment in each system has the following advantages: * Corrects seasonal frequency deviations through seasonal oscillation adjustment. * Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through oscillation adjustment in tune with temperature fluctuations. • Oscillation Halt Sensing Flag, Power-on Reset Flag, and Supply Voltage Monitoring Function The R2045S/D incorporates an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt. Power-on reset flag is set to “1” When R2045S/D is powered on from 0V. As such, the oscillation halt sensing flag and Power-on reset flag are useful for judging the validity of time data. The R2045S/D also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold settings can be selected between 2.1 and 1.3 volts through internal register settings. The oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring. 8 R2045S/D • Periodic Interrupt Function The R2045S/D incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside from interrupt signals generated by the periodic interrupt circuit for output from the INTR pin. Periodic interrupt signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60 Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month). Further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour, and month interrupts). The condition of periodic interrupt signals can be monitored by using a polling function. • 32kHz Clock Output The R2045S/D incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32-kHz clock output can be disabled by certain register settings but cannot be disabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the CPU. 9 R2045S/D Address Mapping Address A3A2A1A0 0000 0001 0010 0011 0100 0101 Register Name Second Counter Minute Counter Hour Counter Day-of-week Counter Day-of-month Counter Month Counter and Century Bit Year Counter Oscillation Adjustment Register *3) Alarm_W (Minute Register) Alarm_W (Hour Register) Alarm_W (Day-of-week Register) Alarm_D (Minute Register) Alarm_D (Hour Register) Control Register 1 *3) Control Register 2 *3) D7 *2) 19 /20 Y80 (0) *4) D6 S40 M40 D5 S20 M20 H20 P/ A D20 Data D4 S10 M10 H10 D10 MO10 D3 S8 M8 H8 D8 MO8 D2 S4 M4 H4 W4 D4 MO4 D1 S2 M2 H2 W2 D2 MO2 D0 S1 M1 H1 W1 D1 MO1 0 1 2 3 4 5 6 7 0110 0111 Y40 F6 Y20 F5 Y10 F4 Y8 F3 Y4 F2 Y2 F1 Y1 F0 8 1000 WM40 WM20 WM10 WM8 WM4 WM2 WM1 9 1001 - - WH20 WP/ A WW5 WH10 WH8 WH4 WH2 WH1 A1010 - WW6 WW4 WW3 WW2 WW1 WW0 B1011 - DM40 DM20 DM10 DM8 DM4 DM2 DM1 C1100 - - DH20 DP/ A 12 /24 XST DH10 DH8 DH4 DH2 DH1 D1101 E1110 F1111 WALE VDSL DALE VDET CLEN2 PON *5) TEST CLEN1 CT2 CT1 CT0 DAFG CTFG WAFG Notes: *1) All the data listed above accept both reading and writing. *2) The data marked with "-" is invalid for writing and reset to 0 for reading. *3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control Register 1 and Control Register 2 excluding the XST and PON bits. *4) The (0) bit should be set to 0. *5) XST is oscillation halt sensing bit. *6) PON is power-on reset flag. 10 R2045S/D Register Settings • Control Register 1 (ADDRESS Eh) D7 WALE WALE D6 DALE DALE D5 12 /24 12 /24 D4 CLEN2 CLEN2 D3 TEST TEST D2 CT2 CT2 D1 CT1 CT1 D0 CT0 CT0 (For Writing) (For Reading) 0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. (1) WALE, DALE WALE,DALE 0 1 Alarm_W Enable Bit, Alarm_D Enable Bit Description Disabling the alarm interrupt circuit (under the control of the settings of the Alarm_W registers and the Alarm_D registers). Enabling the alarm interrupt circuit (under the control of the settings of the Alarm_W registers and the Alarm_D registers) (Default) (2) 12 /24 12 /24-hour Mode Selection Bit Description 12 /24 0 Selecting the 12-hour mode with a.m. and p.m. indications. (Default) 1 Selecting the 24-hour mode Setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. 24-hour mode 12-hour mode 24-hour mode 00 12 (AM12) 12 01 01 (AM 1) 13 02 02 (AM 2) 14 03 03 (AM 3) 15 04 04 (AM 4) 16 05 05 (AM 5) 17 06 06 (AM 6) 18 07 07 (AM 7) 19 08 08 (AM 8) 20 09 09 (AM 9) 21 10 10 (AM10) 22 11 11 (AM11) 23 Setting the 12 /24 bit should precede writing time data 12-hour mode 32 (PM12) 21 (PM 1) 22 (PM 2) 23 (PM 3) 24 (PM 4) 25 (PM 5) 26 (PM 6) 27 (PM 7) 28 (PM 8) 29 (PM 9) 30 (PM10) 31 (PM11) (3) CLEN2 32-kHz Clock Output Bit2 Description CLEN2 0 Enabling the 32-kHz clock output (Default) 1 Disabling the 32-kHz clock output Setting the CLEN2 bits or the CLEN1 bit (D3 in the control register 2) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the CLEN1 and the CLEN2 bit to 1 specifies disabling (“H”) such output. 11 R2045S/D (4) TEST TEST Test Bit (Default) Description 0 Normal operation mode. 1 Test mode. The TEST bit is used only for testing in the factory and should normally be set to 0. (5) CT2,CT1, and CT0 CT2 CT1 Periodic Interrupt Selection Bits CT0 Wave form mode Pulse Mode *1) Pulse Mode *1) Level Mode *2) Level Mode *2) Level Mode *2) Level Mode *2) Description Interrupt Cycle and Falling Timing OFF(H) Fixed at “L” 2Hz(Duty50%) 1Hz(Duty50%) Once per 1 second (Synchronized with second counter increment) Once per 1 minute (at 00 seconds of every minute) Once per hour (at 00 minutes and 00 seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) (Default) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. CTFG Bit I N TR Pin Approx. 92µs (Increment of second counter) Rewriting of the second counter In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low. * 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below. 12 R2045S/D CTFG Bit IN T R Pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter) *1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 60sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms. • Control Register 2 (Address Fh) D1 D0 WAF DAFG (For Writing) G PON VDSL VDET CTFG WAF DAFG (For Reading) CLEN1 XST G Indefinite 0 0 1 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. D7 VDSL D6 VDET D5 XST D4 PON D3 CLEN1 D2 CTFG (1) VDSL VDD Supply Voltage Monitoring Threshold Selection Bit (Default) VDSL Description 0 Selecting the VDD supply voltage monitoring threshold setting of 2.1v. 1 Selecting the VDD supply voltage monitoring threshold setting of 1.3v. The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings. (2) VDET VDET 0 Supply Voltage Monitoring Result Indication Bit Description Indicating supply voltage above the supply voltage monitoring (Default) threshold settings. 1 Indicating supply voltage below the supply voltage monitoring threshold settings. Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit. Conversely, setting the VDET bit to 1 causes no event. (3) XST XST Oscillation Halt Sensing Monitor Bit 0 1 Description Sensing a halt of oscillation Sensing a normal condition of oscillation 13 R2045S/D The XST accepts the reading and writing of 0 and 1. The XST bit will be set to 0 when the oscillation halt sensing. The XST bit will hold 0 even after the restart of oscillation. (4) PON Power-on-reset Flag Bit PON Description 0 Normal condition 1 Detecting VDD power-on -reset The PON bit is for sensing power-on reset condition. (Default) * The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even after power-on. * When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control Register 1, and Control Register 2, except XST and PON. As a result, INTR pin stops outputting, and 32KOUT starts outputting. * The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event. (5) CLEN1 CLEN1 0 32-kHz Clock Output Bit 1 Description Enabling the 32-kHz clock output (Default) Disabling the 32-kHz clock output 1 Setting the CLEN1 bit or the CLEN2 bit (D4 in the control register 1) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the CLEN1 and the CLEN2 bit to 1 specifies disabling (“H”) such output. (6) CTFG CTFG Periodic Interrupt Flag Bit Description 0 Periodic interrupt output = “H” (Default) 1 Periodic interrupt output = “L” The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). The CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the INTR pin until it is enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event. (7) WAFG,DAFG Alarm_W Flag Bit and Alarm_D Flag Bit WAFG,DAFG Description 0 Indicating a mismatch between current time and preset alarm time (Default) 1 Indicating a match between current time and preset alarm time The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. INTR pin outputs off (“H”) when this bit is set to 0. And INTR pin outputs “L” again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG (DAFG) bit is synchronized with the output of the INTR pin as shown in the timing chart below. 14 R2045S/D Approx. 61µs W AFG(DAFG) Bit INTR Pin W riting of 0 to WAFG(DAFG) bit (Match between current time and preset alarm time) (Match between current time and preset alarm time) Writing of 0 to WAFG(DAFG) bit (Match between current time and preset alarm time) Approx. 61µs • Time Counter (Address 0-2h) Second Counter (Address 0h) D7 0 0 D6 S40 S40 Indefi nite D5 S20 S20 Indefi nite D4 S10 S10 Indefi nite D3 S8 S8 Indefi nite D2 S4 S4 Indefi nite D1 S2 S2 Indefi nite D0 S1 S1 Indefi nite (For Writing) (For Reading) Default Settings *) Minute Counter (Address 1h) D7 0 0 D6 M40 M40 Indefi nite D5 M20 M20 Indefi nite D4 M10 M10 Indefi nite D3 M8 M8 Indefi nite D2 M4 M4 Indefi nite D1 M2 M2 Indefi nite D0 M1 M1 Indefi nite (For Writing) (For Reading) Default Settings *) Hour Counter (Address 2h) D5 D4 D3 D2 D1 D0 H10 H8 H4 H2 H1 (For Writing) P/ A or H20 H10 H8 H4 H2 H1 (For Reading) 0 0 P/ A or H20 0 0 Indefi Indefi Indefi Indefi Indefi Indefi Default Settings *) nite nite nite nite nite nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. * Time digit display (BCD format) as follows: The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. The hour digits range as shown in "P11 •Control Register 1 (ADDRESS Eh) (2) 12 /24: 12 -24-hour Mode Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from PM11 to AM12 or from 23 to 00. D7 D6 15 R2045S/D * Any writing to the second counter resets divider units of less than 1 second. * Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent time data. • Day-of-week Counter (Address 3h) D2 D1 D0 W4 W2 W1 (For Writing) W4 W2 W1 (For Reading) Indefi Indefi Indefi Default Settings *) nite nite nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. * The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month digits. * Day-of-week display (incremented in septimal notation): (W4, W2, W1) = (0, 0, 0) → (0, 0, 1)→…→(1, 1, 0) → (0, 0, 0) * Correspondences between days of the week and the day-of-week digits are user-definable (e.g. Sunday = 0, 0, 0) * The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused. D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 • Calendar Counter (Address 4-6h) Day-of-month Counter (Address 4h) D7 0 0 D6 0 0 D5 D20 D20 Indefi nite D4 D10 D10 Indefi nite D3 D8 D8 Indefi nite D2 D4 D4 Indefi nite D1 D2 D2 Indefi nite D0 D1 D1 Indefi nite (For Writing) (For Reading) Default Settings *) Month Counter + Century Bit (Address 5h) D7 19 /20 19 /20 Indefi nite D6 0 0 D5 0 0 D4 MO10 MO10 Indefi nite D3 MO8 MO8 Indefi nite D2 MO4 MO4 Indefi nite D1 MO2 MO2 Indefi nite D0 MO1 MO1 Indefi nite (For Writing) (For Reading) Default Settings *) Year Counter (Address 6h) D7 D6 D5 D4 D3 D2 D1 D0 Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For Writing) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Indefi Indefi Default Settings *) nite nite nite nite nite nite nite nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. * The calendar counters are configured to display the calendar digits in BCD format by using the automatic 16 R2045S/D calendar function as follows: The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October, and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap years; from 1 to 28 for February in ordinary years. The day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, …, 92, and 96 in leap years) and are carried to the 19 /20 digits in reversion from 99 to 00. The 19 /20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. * Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar data. • Oscillation Adjustment Register (Address 7h) D7 D6 D5 D4 D3 D2 D1 D0 (0) F6 F5 F4 F3 F2 F1 F0 (For Writing) 0 F6 F5 F4 F3 F2 F1 F0 (For Reading) 0 0 0 0 0 0 0 0 Default Settings *) *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. (0) bit: (0) bit should be set to 0 F6 to F0 bits: * The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the settings of the Oscillation Adjustment Register when the second digits read 00, 20, or 40 seconds. Normally, the Second Counter is incremented once per 32768 32.768-kHz clock pulses generated by the crystal oscillator. Writing to the F6 to F0 bits activates the oscillation adjustment circuit. * The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the Oscillation Adjustment Register. * The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2. The F6 bit setting of 1 causes a decrement of time counts by (( F5,F4,F3,F2,F1,F0 ) + 1) x 2. The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither an increment nor decrement of time counts. Example: When the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 1, 1, 1" in the F6, F5, F4, F3, F2, F1, and F0 bits cause an increment of the current time counts of 32768 by (7 - 1) x 2 to 32780 (a current time count loss). When the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 0, 0, 1" in the F6, F5, F4, F3, F2, F1, and F0 bits cause neither an increment nor a decrement of the current time counts of 32768. When the second digits read 00, 20, or 40, the settings of "1, 1, 1, 1, 1, 1, 0" in the F6, F5, F4, F3, F2, F1, and F0 bits cause a decrement of the current time counts of 32768 by (- 2) x 2 to 32764 (a current time count gain). An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 / 17 R2045S/D (32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. Consequently, deviations in time counts can be corrected with a precision of ±1.5 ppm. Note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-kHz clock pulses. For further details, see "P28 Configuration of Oscillation Circuit and Correction of Time Count Deviations •Oscillation Adjustment Circuit". • Alarm_W Registers (Address 8-Ah) Alarm_W Minute Register (Address 8h) D7 0 0 D6 WM40 WM40 Indefi nite D5 WM20 WM20 Indefi nite D4 WM10 WM10 Indefin ite D3 WM8 WM8 Indefi nite D2 WM4 WM4 Indefi nite D1 WM2 WM2 Indefi nite D0 WM1 WM1 Indefi nite (For Writing) (For Reading) Default Settings *) Alarm_W Hour Register (Address 9h) D7 0 0 D6 0 0 D5 WH20 WP/ A WH20 WP/ A Indefi nite D4 WH10 WH10 Indefi nite D3 WH8 WH8 Indefi nite D2 WH4 WH4 Indefi nite D1 WH2 WH2 Indefi nite D0 WH1 WH1 Indefi nite (For Writing) (For Reading) Default Settings *) Alarm_W Day-of-week Register (Address Ah) D6 D5 D4 D3 D2 D1 D0 WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Writing) WW6 WW5 WW4 WW3 WW2 WW1 WW0 (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Indefi Default Settings *) nite nite nite nite nite nite nite *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. * The D5 bit of the Alarm_W Hour Register represents WP/ A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits). * The Alarm_W Registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively. (See "P11 •Control Register 1 (ADDRESS Eh) (2) 12 /24: 12-/24-hour Mode Selection Bit") * WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). * WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers. D7 0 0 18 R2045S/D Example of Alarm Time Setting Alarm Day-of-week Preset alarm time Sun. Mon. Tue. Wed. Th. Fri. Sat. 12-hour mode 24-hour mode 10 1 10 1 10 1 10 1 hr. hr. min min hr. hr. min min. . . . WW 0 WW 1 WW 2 WW 3 WW 4 WW 5 WW 6 00:00 a.m. on all 1 1 1 1 1 1 1 1 20 0 00 0 days 01:30 a.m. on all 1 1 1 1 1 1 1 0 13 0 01 3 days 11:59 a.m. on all 1 1 1 1 1 1 1 1 15 9 11 5 days 00:00 p.m. on Mon. 0 1 1 1 1 1 0 3 20 0 12 0 to Fri. 01:30 p.m. on Sun. 1 0 0 0 0 0 0 2 13 0 13 3 11:59 p.m. 0 1 0 1 0 1 0 3 15 9 23 5 on Mon. ,Wed., and Fri. Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table is only an example and not mandatory. 0 0 9 0 0 9 • Alarm_D Register (Address B-Ch) Alarm_D Minute Register (Address Bh) D7 0 0 D6 DM40 DM40 Indefinit e D5 DM20 DM20 Indefinit e D4 DM10 DM10 Indefinit e D3 DM8 DM8 Indefinit e D2 DM4 DM4 Indefinit e D1 DM2 DM2 Indefinit e D0 DM1 DM1 Indefinit e (For Writing) (For Reading) Default Settings *) Alarm_D Hour Register (Address Ch) D7 0 0 D6 0 0 D5 DH20 DP/ A DH20 DP/ A Indefini Indefinit Indefinit Indefinit Indefinit Indefinit Default Settings *) te e e e e e *) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from 0 volts. DH10 DH8 DH4 DH2 DH1 (For Reading) D4 DH10 D3 DH8 D2 DH4 D1 DH2 D0 DH1 (For Writing) 19 R2045S/D * The D5 bit represents DP/ A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20 when the 24-hour mode is selected (tens in the hour digits). * The Alarm_D registers should not have any non-existent alarm time settings. (Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers may disable the alarm interrupt circuit.) * When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (See "P11 •Control Register 1 (ADDRESS Eh) (2) 12 /24: 12/24-hour Mode Selection Bit") 20 R2045S/D Interfacing with the CPU • DATA TRANSFER FORMATS (1) Timing Between CE Pin Transition and Data Input / Output The R2045S/D adopts a 4-wire serial interface by which they use the CE (Chip Enable), SCLK (Serial Clock), SI (Serial Input), and SO (Serial Output) pins to receive and send data to and from the CPU. The 4-wire serial interface provides two types of input/output timings with which the SO pin output and the SI pin input are synchronized with the rising or falling edges of the SCLK pin input, respectively, and vice versa. The R2045S/D is configured to select either one of two different input/output timings depending on the level of the SCLK pin in the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of the CE pin, the models will select the timing with which the SO pin output is synchronized with the rising edge of the SCLK pin input, and the SI pin input is synchronized with the falling edge of the SCLK pin input, as illustrated in the timing chart below. CE SCLK tDS SI tDH tRD tCES SO Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the timing with which the SO pin output is synchronized with the falling edge of the SCLK pin input, and the SI pin input is synchronized with the rising edge of the SCLK pin input, as illustrated in the timing chart below. CE SCLK tDS SI tDH tRD tCES SO (2) Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 byte (8 bits). The former 4 bits are used to specify in the Address Pointer a head address with which data transfer is to be commenced from the host. The latter 4 bits are used to select either reading data transfer or writing data transfer, and to set the Transfer Format Register to specify an appropriate data transfer format. All data transfer formats are designed to transfer the most significant bit (MSB) first. 21 R2045S/D CE SCLK SI 1 2 3 4 5 6 7 8 1 2 3 A3 A2 A1 A0 C3 C2 C1 C0 D7 D6 D3 D2 D1 D0 Setting the Address Pointer SO Setting the Transfer Format Register D7 D6 Writing data transfer D3 D2 D1 D0 Reading data transfer Two types of data transfer formats are available for reading data transfer and writing data transfer each. • Writing Data Transfer Formats (1) 1-byte Writing Data Transfer Format The first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. This 1-byte writing data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the address pointer and setting the data transfer format. Example of 1-byte Writing Data Transfer (For Writing Data to Addresses Fh and 7h) CE SI SO Specifying FhSetting 8h in the Transfer in the Address Pointer Format Register Writing data to address Fh Specifying 7h Setting 8h in Writing data to in the Address Pointer the Transfer Format Register address 7h 11111000 Data 01111000 Data Data transfer from the host Data transfer from the RTCs 22 R2045S/D (2) Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 0h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst writing data transfer can be completed by driving the CE pin low. Example of Burst Writing Data Transfer (For Writing Data to Addresses Eh, Fh, and 0h) CE SI SO Specifying EhSetting 0h in Writing data to in the Address Pointer the Transfer Format Register address Eh Writing data to address Fh Writing data to address 0h 11100000 Data Data Data Data transfer from the host Data transfer from the RTCs • Reading Data Transfer Formats (1) 1-byte Reading Data Transfer Format The first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the Address Pointer a head address with which reading data transfer is to be commenced and then the setting of writing Ch to the Transfer Format Register. This 1-byte reading data transfer can be completed by driving the CE pin low or continued by specifying a new head address in the Address Pointer and selecting this type of reading data Transfer Format. Example of 1-byte Reading Data Transfer (For Reading Data from Addresses Eh and 2h) CE SI SO Specifying EhSetting Ch in the Transfer in the Address Pointer Format Register 11101100 Data Reading data from address Eh 00101100 Data Specifying 2h Setting Ch in Reading data from in the Address Pointer the Transfer Format Register address 2h Data transfer from the host Data transfer from the RTCs 23 R2045S/D (2) Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the transfer format register. The address pointer is incremented for each transfer of 1-byte data and cycled from Fh to 0h. This burst reading data transfer can be completed by driving the CE pin low. Example of Burst Reading Data Transfer (For Reading Data from Addresses Fh, 0h, and 1h) CE SI SO 11110100 DATA Specifying FhSetting 4h in Reading data from in the the Transfer address Fh Address Pointer Format Register DATA Reading data from address 0h DATA Reading data from address 1h Data transfer from the host Data transfer from the RTCs (3) Combination of 1-byte Reading and writing Data Transfer Formats The 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format. Example of Reading Modify Writing Data Transfer (For Reading and Writing Data from and to Address Fh) CE SI SO 11111100 DATA Specifying FhSetting Ch in Reading data from the Transfer in the address Fh Address Pointer Format Register Specifying FhSetting 8h in in the Address Pointer the Transfer Format Register Writing data to address Fh 11111000 DATA Data transfer from the host Data transfer from the RTCs 24 R2045S/D The reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below. 1 Byte 8h (1,0,0,0) Ch (1,1,0,0) Burst 0h (0,0,0,0) 4h (0,1,0,0) Writing data transfer Reading data transfer 25 R2045S/D • Considerations in Reading and Writing Time Data under special condition Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of 13:59:59 into 14:00:00 occurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. At this moment, the second digits, the minute digits, and the hour digits read 59 seconds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. A similar error also occurs in writing time data. To prevent such errors in reading and writing time data, the R2045S/D has the function of temporarily locking any carry to the second digits during the high interval of the CE pin and unlocking such a carry in its high to low transition. Note that a carry to the second digits can be locked for only 1 second, during which time the CE pin should be driven low. 13:59:59 14:00:00 14:00:01 Actual time CE Max.62µs Time counts within RTC 13:59:59 14:00:00 14:00:01 The effective use of this function requires the following considerations in reading and writing time data: (1) Hold the CE pin high in each session of reading or writing time data. (2) Ensure that the high interval of the CE pin lasts within 1 second. Should there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the CE pin low or open at the moment that the host actually goes down. (3) Leave a time span of 31µs or more from the low to high transition of the CE pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) Leave a time span of 62µs or more from the high to low transition of the CE pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the CE pin may be adjusted within this time span. The considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits. (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). Good and bad examples of reading and writing time data are illustrated on the next page. 26 R2045S/D Good Example Time span of 31µs or more Any address other than addresses 0h to 6h permits of immediate reading or writing without requiring a time span of 31 µs. CE SI SO Address Pointer = Fh Transfer Format Register = 4h F4h DATA Reading from Address Fh (control2) DATA Reading from Address 0h (sec.) DATA Reading from Address 1h (min.) DATA Reading from Address 2h (hr.) Bad Example (1) (Where the CE pin is once driven low in the process of reading time data) 31µs or more 31µs or more CE SI SO Address Pointer = 0h Transfer Format Register = Ch 0Ch Data Reading from Address 0h (sec.) 14h Data Address Pointer = 1h Transfer Format Register = 4h Reading from Address 1h (min.) Data Reading from Address 2h (hr.) Bad Example (2) (Where a time span of less than 31µs is left until the start of the process of writing time data) Time span of less than 31µs CE SI SO Address Pointer = Fh Transfer Format Register = 0h Writing to Address Fh (contorl2) Writing to Address 0h (sec.) Writing to Address 1h (min.) Writing to Address 2h (hr.) F0h Data Data Data Data Bad Example (3) (Where a time span of less than 61µs is left between the adjacent processes of reading time data) Less than 62µs CE SI SO Address Pointer = 0h Transfer Format Register = Ch 0Ch Data Reading from Address 0h (sec.) 0Ch Data Address Pointer = 0h Transfer Format Register = Ch Reading from Address 0h (sec.) 0Ch Data transfer from the host Data Data transfer from RTCs 27 R2045S/D Correction of Time Count Deviations • The Necessity for Correction of Time Count Deviations The oscillation frequency for R2045S/D is corrected to 0±5ppm at 25°C in fabrication. Oscillation frequency is the fastest at 25°C, (Please see Typical Characteristics Oscillation Frequency Deviation vs. Operating temperature (P.42)). In normal condition, temperature is not kept constant at 25°C. That is, R2045S/D loses without correction of time counts deviation. Generally, a clock is corrected to gain 3 to 6ppm at 25°C. R2045S/D is corrected it by setting clock adjustment register. Ricoh suggests to set 7Fh to clock adjustment register (Address 7h) for time setting to gain 3ppm at 25°C, for the equipment used indoors. And suggests to set 7Eh to clock adjustment register (Address 7h) for time setting to gain 6ppm at 25°C, for the equipment used outdoors. • Measurement of Oscillation Frequency VDD 32KOUT VSS Frequency Counter * 1) When power-on, the R2045S/D is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin. * 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. • Oscillation Adjustment Circuit The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 seconds. The oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below for writing to the oscillation adjustment circuit. (1) When Oscillation Frequency (* 1) Is Higher Than Target Frequency (* 2) (Causing Time Count Gain) Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1) Oscillation frequency × 3.051 × 10-6 ≈ (Oscillation Frequency – Target Frequency) × 10 + 1 28 R2045S/D * 1) Oscillation frequency: Frequency of clock pulse output from the 32KOUT pin at normal temperature in the manner described in " P28 • Measurement of Oscillation Frequency". * 2) Target frequency: Desired frequency to be set. Generally, a 32.768-kHz crystal oscillator has such temperature characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to 32.76810 kHz (+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending on the environment or location where the equipment incorporating the RTC is expected to be operated. * 3) Oscillation adjustment value: Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is represented in 7-bit coded decimal notation. (2) When Oscillation Frequency Is Equal To Target Frequency (Causing Time Count neither Gain nor Loss) Oscillation adjustment value = 0, +1, -64, or –63 (3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss) Oscillation adjustment value = (Oscillation frequency - Target Frequency) Oscillation frequency × 3.051 × 10-6 ≈ (Oscillation Frequency – Target Frequency) × 10 Oscillation adjustment value calculations are exemplified below (A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10-6) ≈ (32768.85 - 32768.05) × 10 + 1 = 9.001 ≈ 9 In this instance, write the settings ((0),F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h. (B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 3.051 × 10-6) ≈ (32762.22 - 32768.05) × 10 = -58.325 ≈ -58 To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from 128 (80h) to obtain 46h. In this instance, write the settings of ((0),F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h. Notes: 1) Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the 32KOUT pin. 2) Oscillation adjustment value range: When the oscillation frequency is higher than the target frequency (causing a time count gain), an appropriate time count gain ranges from -3.05ppm to -189.2ppm with the settings of "0, 0, 0, 0, 0, 1, 0" to "0, 1, 1, 1, 1, 1, 1" written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm. 29 R2045S/D Conversely, when the oscillation frequency is lower than the target frequency (causing a time count loss), an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of "1, 1, 1, 1, 1, 1, 1" to "1, 0, 0, 0, 0, 1, 0" written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register, thus allowing correction of a time count loss of up to -189.2ppm. 3) If following 3 conditions are completed, actual clock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. Using oscillator adjustment function 2. Access to R2045S/D at random, or synchronized with external clock that has no relation to R2045S/D, or synchronized with periodic interrupt in pulse mode. 3. Access to R2045S/D more than 2 times per each second on average. For more details, please contact to Ricoh. • How to evaluate the clock gain or loss The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds. The oscillation adjustment circuit does not effect the frequency of 32768Hz-clock pulse output from the 32OUT pin. Therefore, after writing the oscillation adjustment register, we cannot measure the clock error with probing 32KOUT clock pulses. The way to measure the clock error as follows: (1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh. (2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60 seconds) like next page figure. 1Hz clock pulse T0 T0 19 times T0 T1 1 time Measure the interval of T0 and T1 with frequency counter. A frequency counter with 7 or more digits is recommended for the measurement. (3) Calculate the typical period from T0 and T1 T = (19×T0+1×T1)/20 Calculate the time error from T. 30 R2045S/D Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring • PON, XST , and VDET The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.3v. Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and XST bit is for the oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to “H”. However, XST bit is activated to “L”. The PON and VDET accept only the writing of 0, but XST accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0, and XST is indefinite. The functions of these three monitor bits are shown in the table below. PON Function Monitoring for the power-on reset function D4 in Address Fh High 1 0 only XST Monitoring for the oscillation halt sensing function D5 in Address Fh Low indefinite VDET a drop in supply voltage below a threshold voltage of 2.1 or 1.3v D6 in Address Fh High 0 0 only Address Activated When VDD power up from 0v accept the writing Both 0 and 1 The relationship between the PON, XST , and VDET is shown in the table below. PON 0 XST VDET 0 0 0 0 1 0 1 0 0 1 1 1 * * Conditions of supply voltage and oscillation Halt on oscillation, but no drop in VDD supply voltage below threshold voltage Halt on oscillation and drop in VDD supply voltage below threshold voltage, but no drop to 0V No drop in VDD supply voltage below threshold voltage and no halt in oscillation Drop in VDD supply voltage below threshold voltage and no halt on oscillation Drop in supply voltage to 0v Condition of oscillator, and back-up status Halt on oscillation cause of condensation etc. Halt on oscillation cause of drop in back-up battery voltage Normal condition No halt on oscillation, but drop in back-up battery voltage Power-up from 0v, 31 R2045S/D Threshold voltage (2.1V or 1.3V) VDD 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag ( XST ) VDD supply voltage monitor flag (VDET) VDET←0 XST ←1 PON←0 VDET←0 XST ←1 PON←1 VDET←0 XST ←1 PON←0 Internal initialization period (1 to 2 sec.) Internal initialization period (1 to 2 sec.) When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, 12 /24, CLEN2 , TEST, CT2, CT1, CT0, VDSL, VDET, CLEN1 , CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0 volts. < Considerations in Using Oscillation Halt Sensing Circuit > Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) Instantaneous power-down on the VDD 2) Applying to individual pins voltage exceeding their respective maximum ratings In particular, note that the XST bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. Further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit. VDD 32 R2045S/D • Voltage Monitoring Circuit The VDD supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.3v for the VDSL bit setting of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the Control Register 2. The VDD supply voltage monitor is useful for back-up battery checking. VDD 2.1v or 1.3v PON Internal nitiali-zation period (1 to 2sec.) 7.8ms 1s Sampling timing for VDD supply voltage VDET (D6 in Address Fh) PON←0 VDET←0 VDET←0 33 R2045S/D Alarm and Periodic Interrupt The R2045S/D incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the INTR pin as described below. (1) Alarm Interrupt Circuit The alarm interrupt circuit is configured to generate alarm signals for output from the INTR , which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings). Both The Alarm_W and Alarm_D are output from the INTR . (2) Periodic Interrupt Circuit The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the INTR pin depending on the CT2, CT1, and CT0 bit settings in the control register 1. The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the Control Register 1) as listed in the table below. Flag bits WAFG (D1 at Address Fh) DAFG (D0 at Address Fh) CTFG (D2 at Address Fh) Enable bits WALE (D7 at Address Eh) DALE (D6 at Address Eh) CT2=CT1=CT0=0 (These bit setting of “0” disable the Periodic Interrupt) (D2 to D0 at Address Eh) Alarm_W Alarm_D Peridic Interrupt * At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the INTR pin is driven high (disabled). * When two types of interrupt signals are output simultaneously from the INTR pin, the output from the INTR pin becomes an OR waveform of their negative logic. Example: Combined Output to INTR Pin Under Control of Alarm_D and Periodic Interrupt Alarm_D Periodic Interrupt IN T R In this event, which type of interrupt signal is output from the INTR pin can be confirmed by reading the DAFG, and CTFG bit settings in the Control Register 2. 34 R2045S/D • Alarm Interrupt The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time. The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function. Interval (1min.) during which a match between current time and preset alarm time occurs INTR WALE←1 current time = WALE←0 preset alarm time (DALE) (DALE) WALE←1 (DALE) current time = preset alarm time INTR WALE←1 current time = preset alarm time (DALE) WAFG←0 (DAFG) current time = preset alarm time 35 R2045S/D • Periodic Interrupt Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High (OFF). CT2 CT1 CT0 Wave form mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Pulse Mode *1) Pulse Mode *1) Level Mode *2) Level Mode *2) Level Mode *2) Level Mode *2) Description Interrupt Cycle and Falling Timing OFF(H) Fixed at “L” 2Hz(Duty50%) 1Hz(Duty50%) Once per 1 second (Synchronized with Second counter increment) Once per 1 minute (at 00 seconds of every Minute) Once per hour (at 00 minutes and 00 Seconds of every hour) Once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) (Default) *1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. CTFG Bit INTR Pin Approx. 92µs (Increment of second counter) Rewriting of the second counter In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTR pin low. *2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below. 36 R2045S/D CTFG Bit INTR Pin Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) Setting CTFG bit to 0 (Increment of second counter) *1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows: Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%. Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms. 32-kHz CLOCK OUTPUT For the R2045S/D, 32.768-kHz clock pulses are output from the 32KOUT pin when CLEN1 or CLEN2 bit is set to Low. If CLEN1 and CLEN2 are set to high, the 32KOUT pin is high impedance. CLEN1 bit (D3 at Address Fh) CLEN2 bit (D4 at Address Eh) 32KOUT output pin (N-channel open drain output) OFF(H) 32kHz clock output 1 0(Default) * 1 * 0(Default) The 32KOUT pin output is synchronized with the CLEN1 and CLEN2 bit settings as illustrated in the timing chart below. CLEN1or2 32KOUT PIN Max.62.0µs Max.45.8µs 37 R2045S/D Typical Applications • Typical Power Circuit Configurations Sample circuit configuration 1 System power supply *1) Install bypass capacitors for high frequency and low frequency applications in parallel in close vicinity to the R2045S/D. VDD *1) VSS Sample circuit configuration 2 System power supply *1) When using an OR diode as a power supply for the R2045S/D ensure that voltage exceeding the absolute maximum rating of VDD+0.3v is not applied the SO pin. VDD *1) VSS Primary Battery System power supply VDD *1) VSS Secondary Battery 38 R2045S/D • Connection of INTR Pin The INTR pin follows the N-channel open drain output logic and contains no protective diode on the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 volts regardless of supply voltage. System power supply INTR A *1) B Backup power supply *1) Depending on whether the INTR pin is to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) Position A in the left diagram when it is not to be used during battery backup. (2) Position B in the left diagram when it is to be used during battery backup. VDD VSS • Connection of 32KOUT Pin The 32KOUT pin follows the Nch. open drain output and contains no protective diode on the power supply side. As such, it can be connected to a device with a supply voltage of up to 5.5 volts regardless of supply voltage, provided that such connection involves considerations for the supply current requirements of a pull-up resistor, which can be roughly calculated by the following equation: I = 0.5 × (VDD or VCC) / Rp System power supply 32KOUT A *1) B Backup power supply *1) Depending on whether the 32KOUT pin is to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) Position A in the left diagram when it is not to be used during battery backup. (2) Position B in the left diagram when it is to be used during battery backup. VDD VSS 39 R2045S/D • Connection of CE Pin Connection of the CE pin requires the following considerations: 1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it should be driven low or open at power-on from 0 volts. 2) The CE pin should also be driven low or open immediately upon the host going down (see P.26 "Considerations in Reading and Writing Time Data under special condition"). SCLK I/O CONTROL SI Lower limit operating voltage for the CPU VDD Backup power supply 0.2×VDD SO CE CE Min.0µs Min.0µs Min.0µs • Connection With 3-Wire Serial Interface Bus To connect the R2045S/D with 3-wire serial interface bus, shorten the SI and SO pins and connect them to the data line as shown in the figure below. CE0 Host CE1 SCLK DATA CE SCLK R2045S/D SI SO CE SCLK SIO The other Peripheral IC 40 R2045S/D Typical Characteristics Test Circuit Topt : 25°C Output : Open VDD 32KOUT VSS CL Frequency Counter Timekeeping current vs. Supply Voltage (with no 32-kHz clock output) (Output=Open, Topt=25°C) Timekeeping current IDD(uA) Timekeeping current vs. Supply Voltage (witj 32-kHz clock output) (Output=Open, Topt=25°C) Timekeeping current IDD(uA) 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 Supply Voltage VDD(v) 1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 Supply Voltage VDD(v) CPU Access Current vs. SCL Clock Frequency Temperature (Output=Open, Topt=25°C) (wiithout pull-up resister current) Timekeeping Current IDD(uA) CPU Access Current IDD(uA) Timekeeping current vs. Operating (Output=Open, VDD=3V) 40 30 20 1 32KOUT output 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 Operating Temperature Topt(Celsius) VDD=5v VDD=3v 10 0 0 200 400 600 800 1000 SCL Clock Frequency (kHz) no 32KOUT output 41 R2045S/D Oscillation Frequency Deviation vs. Supply Voltage (Topt=25°C) Oscillation Frequency Deviation vs. Operating Temperature (VDD=3v) 20 Oscillation frequency Deviation (ppm) 0 -20 -40 -60 -80 -100 -120 -60 -40 -20 0 20 40 60 80 100 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 1 2 3 4 5 6 Power Supply VDD (v) Oscillation Frequency Deviation (ppm) Operating Temperature Topt(Celsius) VOL vs. IOL( INTR pin) (Topt=25°C) 35 30 25 IOL (mA) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 VOL (v) IOL (mA) VOL vs. IOL( INTR pin) (VIN=VDD,Topt=25°C) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 VOL (v) VDD=5v VDD=3v Oscillation Start Time vs. Power Supply (Topt=25°C) Oscillation Start Time (ms) 500 400 300 200 100 0 0 1 2 3 4 5 6 Power Supply VDD (v) 42 R2045S/D Typical Software-based Operations • Initialization at Power-on S tart *1) Power-on *2) PON=1? No *3) VDET=0? Yes *4) Yes Set Control Register 1 and 2, etc. No Warning Back-up Battery Run-down *1) After power-on from 0 volt, the start of oscillation and the process of internal initialization require a time span on the order of 1 to 2sec, so that access should be done after the lapse of this time span or more. *2) The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not from 0v. For further details, see "P.31 Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring • PON, XST , and VDET ". *3) This step is not required when the supply voltage monitoring circuit is not used. *4) This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt cycle settings, etc. 43 R2045S/D • Writing of Time and Calendar Data CE ← H *1) W rite to Time Counter and Calendar Counter *2) *1) When writing to clock and calendar counters, do not drive CE to L until all times from second to year have been written to prevent error in writing time. For more detailed in "P.25 Considerations in Reading and Writing Time Data under special condition". *2) Any writing to the second counter will reset divider units lower than the second digits. *3) Please see “P,27 The Necessity for Correction of Time Count Deviations” The R2045S/D may also be initialized not at power-on but in the process of writing time and calendar data. W rite to Clock Adjustment *3) Register CE←L *1) • Reading Time and Calendar Data (1) Ordinary Process of Reading Time and Calendar Data CE ← H *1) *1) When reading clock and calendar counters, do not drive CE to L until all times from second to year have been written to prevent error in writing time. For more detailed in "P.25 Considerations in Reading and Writing Time Data under special condition". Read from Time Counter and Calendar Counter CE ← L *1) 44 R2045S/D (2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function Set Periodic Interrupt Cycle Selection Bits *1) *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 1.0 second. *3) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU. Generate Interrupt in CPU CTFG=1? No *2) Yes Read from Time Counter and Calendar Counter Other Interrupt Processes *3) Control Register 2 ←(X1X1X011) 45 R2045S/D (3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format: Control Register 1← (XXXX0100) Control Register 2← (X1X1X011) *1) Generate interrupt to CPU Other interrupts Processes CTFG=1? No *2) *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step must be completed within 1.0 sec. *3) This step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU. Yes Sec.=00? No *3) Use Previous Min.,Hr., Day,and Day-of-week data Yes Read Min.,Hr.,Day, and Day-of-week Control Register 2 ← (X1X1X011) *4) 46 R2045S/D • Interrupt Process (1) Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits *1) Generate Interrupt to CPU *1) This step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) This step is intended to set the CTFG bit to 0 in the Control Register 2 to cancel an interrupt to the CPU. No CTFG=1? Yes Conduct Periodic Interrupt Other Interrupt Processes *2) Control Register 2 ← (X1X1X011) 47 R2045S/D (2) Alarm Interrupt WALE or DALE←0 *1) Set Alarm Min., Hr., and Day-of-week Registers WALE or DALE←1 *2) *1) This step is intended to once disable the alarm interrupt circuit by setting the WALE or DALE bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) This step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) This step is intended to once cancel the alarm interrupt function by writing the settings of "X,1,X, 1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W Registers and the Alarm_D Registers, respectively. Generate Interrupt to CPU WAFG or DAFG=1? No Other Interrupt Processes Yes Conduct Alarm Interrupt *3) Control Register 2 ← (X1X1X101) 48 R2045S/D Land Pattern (reference) • R2045S 1.4 (SOP14) 14 8 5.4 1 1.4 7 0.7 P 1.27x6=7.62 1.27 unit:mm 8.32 Package top view 14 8 1 7 1. Pad layout and size can modify by customers material, equipment, and method. Please adjust pad layout according to your conditions. 2. In the mount area which descried as , is close to the inside oscillator circuit. To avoid the malfunction by noise, check the other signal lines close to the area, do not intervene with the oscillator circuit. 3. A part of a metal case of the crystal may be seen in the area which described as package. It has no influence on the characteristics and quality of the product. in both sides of the 49 R2045S/D • R2045D (SON22) 0.25 0.75 0.7 22 14 4.0 0.8 1 0.7 11 0.25 P 0.5x10=5.0 0.7 5.25 0.5 0.7 Package top view 22 14 Package bottom view 14 22 1 11 11 0.8 unit : mm 1.4 1 1. Pad layout and size can modify by customers material, equipment, and method. Please adjust pad layout according to your conditions. 2. Any signal line should not pass through the area that described as in the land pattern. If a signal line is located in that area, it may cause a short circuit with a tab suspension leads which is marked with in the figure above or unnecessary remainder of cut lead. 3. In the mount area which descried as , is close to the inside oscillator circuit. To avoid the malfunction by noise, check the other signal lines close to the area, do not intervene with the oscillator circuit. 4. A part of a metal case of the crystal may be seen in the area that described as package. It has no influence on the characteristics and quality of the product. in both sides of the 50