BD8143MUV-E2

Power Supply IC Series for TFT LCD Panels High-precision Gamma Correction IC with built-in DAC BD8143MUV No.09035EBT08 ●Description This gamma correction voltage generation IC feature built-in DACs and provide a 1chip solution with setting control via serial communications, a high-precision 10-bitDAC, and Buffer Amp (12ch). ●Features 1) 1chip design means fewer components 2) Built-in 10bit DAC 3) DAC output Buffer AMP (12ch) 4) Amp input select (CTL) 5) 3-line serial interface control 6) Thermal shut down 7) Power ON Reset Circuit 8) VQFN032V5050 Package ●Applications These ICs can be used with TFT LCD Panels used by Large-Screen and High-Definition LCD TVs. ●Absolute maximum ratings (Ta=25℃) Parameter Symbol Limit Unit Power Supply Voltage 1 DVCC 7 V Power Supply Voltage 2 VCC 20 V REFIN Voltage REF 20 Amplifier Drive Current Junction Temperature Power Dissipation V 1 Io 30 * Tjmax 150 mA ℃ 2 Pd 2440 * Operating Temperature Range Topr -40～+105 mW ℃ Storage Temperature Range Tstg -55～+150 ℃ *1 Pd, should not be exceeded. *2 Reduced by 19.52mW/°C over 25°C, when mounted on a glass epoxy board. (4-layer 74.2×74.2×1.6mm). ●Operating Condition (Ta=-40℃～105℃) Limit Parameter Symbol Power Supply Voltage 1 DVCC Power Supply Voltage 2 VCC 8 18 V REFIN Voltage REF 8 18 V IOA -40 - mA AMP1～10 Drive Current IOB -20 20 mA AMP11 Drive Current IOC - 40 mA AMP0 Drive Current MIN MAX 2.3 5.5 Unit V Serial CLK Frequency fCLK - 5 MHz OSC Frequency FOSC - 200 kHz www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/10 2009.07 - Rev.B Technical Note BD8143MUV ●Electrical Characteristics (Unless otherwise specified, Ta=25℃,DVCC=3.3V,VCC=15V) Limit Parameter Symbol Unit MIN TYP MAX 〔REFIN〕 Sink Current Iref 90 200 µA 〔γCORRECTION AMP〕 Source Drive Current (AMP0) IooA -60 mA Source Drive Current (AMP1～10) IooB -30 mA Source Drive Current (AMP11) IooC -10 mA Sink Drive Current (AMP0) IoiA 10 mA Sink Drive Current (AMP1～10) IoiB 30 mA Sink Drive Current (AMP11) IoiC 60 mA Load regulation (OUT0) ⊿V-A 10 mV Load regulation (OUT1～10) ⊿V-B 10 mV Load regulation (OUT11) ⊿V-C 10 mV Slew Rate SR 3 V/µs OUT Voltage High (OUT0) VOH-A VCC-0.4 VCC-0.15 V OUT Voltage High (OUT1～10) VOH-B VCC-0.75 V OUT Voltage High (OUT11) VOH-C VCC-0.75 V OUT Voltage Low (OUT0) VOL-A 0.75 V OUT Voltage Low (OUT1～10) VOL-B 0.75 V OUT Voltage Low (OUT11) VOL-C 0.1 0.2 V 〔DAC〕 Resolution Coding Res 10 Bit Conditions REF=10V DAC=7V,OUT0=13V DAC=3.5V,OUT1～10=0V DAC=0.5V,OUT11=0V DAC=7V,OUT0=15V DAC=3.5V,OUT1～10=15V DAC=0.5V,OUT11=2V Io=0mA～-35mA, OUTx=6V Io=-15mA～15mA, OUTx=6V Io=0mA～35mA, OUTx=6V Io=-35mA Io=-15mA Io=-15mA Io=15mA Io=15mA Io=35mA Error with ideal straight Range 00A～3F5 Error with ideal amount of Increase in 1LSB Range 00A～3F5 Non-Linear Error (INL) LE -2 - 2 LSB Differential Error (DNL) DLE -2 - 2 LSB fosc - 100 - kHz Internal oscillator mode Ictl VTH DVCC×0.8 µA V VIN=3.3V DVCC×0.2 OUT0 Voltage Vpre0 - - V CTL=”LOW” OUT1 Voltage Vpre1 - - V CTL=”LOW” OUT2 Voltage Vpre2 - - V CTL=”LOW” OUT3 Voltage Vpre3 - - V CTL=”LOW” OUT4 Voltage Vpre4 - - V CTL=”LOW” OUT5 Voltage Vpre5 - - V CTL=”LOW” OUT6 Voltage Vpre6 - - V CTL=”LOW” OUT7 Voltage Vpre7 - - V CTL=”LOW” OUT8 Voltage Vpre8 - - V CTL=”LOW” OUT9 Voltage Vpre9 - - V CTL=”LOW” OUT10 Voltage Vpre10 - - V CTL=”LOW” OUT11 Voltage Vpre11 - - V CTL=”LOW” Vdet ICC 2.6 3.6 V mA CTL=”LOW” 〔OSC〕 OSC Frequency 〔CONTROL SIGNAL〕 Sink Current Threshold Voltage 〔CONTROL〕 〔WHOLE DEVICE〕 VDAC Detection Voltage Circuit Current 16.5 REFIN X 12/13 REFIN X 11/13 REFIN X 10/13 REFIN X 9/13 REFIN X 813 REFIN X 7/13 REFIN X 6/13 REFIN X 5/13 REFIN X 4/13 REFIN X 3/13 REFIN X 2/13 REFIN X 1/13 3.2 5 This product is not designed for protection against radio active rays. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/10 2009.07 - Rev.B Technical Note BD8143MUV OUT7 OUT6 AGND AGND OUT5 OUT4 OUT3 ●Block Diagram OUT8 ●Pin No 24 23 22 21 20 19 18 17 VDD VCC VCC REFIN R VDAC VDAC VCC VCC AMP0 VDAC REGISTER0 x2 REGISTER1 x2 REGISTER2 x2 REGISTER3 x2 REGISTER4 x2 REG OUT9 25 16 OUT2 26 15 OUT1 OUT11 27 14 OUT0 REFIN VDAC DACG ND N.C OUT1 AMP2 OUT10 VCC OUT0 AMP1 R 28 13 29 N.C 11 CTL VREF 10 32 9 UVLO 5 6 7 REGISTER5 CT Power ON Reset AMP6 x2 OUT6 AMP7 REGISTER7 x2 REGISTER8 x2 REGISTER9 x2 N.C REGISTER10 x2 REGISTER11 x2 OUT7 AMP8 Serial I/F OUT8 AMP9 OUT9 CLK AMP10 OUT10 SDOUT OSC AMP11 VDD 8 GND Refresh Control OSC CTL REGISTER12 AGND OUT11 CTL AGND N.C GND OUT5 x2 DAC Control REGISTER6 LATCH DACGND CT DVCC 4 SDOUT 3 CLK SDIN LATCH 2 OUT4 AMP5 OSC 1 OUT3 AMP4 TSD DATA 31 OUT2 AMP3 VCC 12 30 VDD Fig.1 Pin No. & Block Diagram ●Pin NO. & Function Table PIN Pin Function No. Name 1 LATCH LATCH signal input PIN No. 17 Pin Name OUT3 Gamma 3 output Function 2 SDIN DATA signal input 18 OUT4 Gamma 4 output 3 CLK CLK signal input 19 OUT5 Gamma 5 output 4 SDOUT DATA signal output 20 AGND Ground for Buffer AMP 5 DVCC Digital Power Supply 21 AGND Ground for Buffer AMP 6 CT Capacitor connection for Power on Reset 22 OUT6 Gamma 6 output 7 GND Ground 23 OUT7 Gamma 7 output 8 N.C 24 OUT8 Gamma 8 output 9 OSC 10 N.C 11 CTL DAC Synchronized clock inout Output control signal input - 25 OUT9 Gamma 9 output 26 OUT10 Gamma 10 output 27 OUT11 Gamma 11 output 12 N.C 28 VCC 13 VCC Power Supply for Buffer AMP 29 REFIN DAC reference input 14 OUT0 Gamma 0 output 30 VDAC DAC Voltage output 15 OUT1 Gamma 1 output 31 DACGND 16 OUT2 Gamma 2 output 32 N.C www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/10 Power Supply for Buffer AMP Ground for DAC - 2009.07 - Rev.B Technical Note BD8143MUV ●Block Operation ・REG REG amplifiers the voltage applied to REFIN by 0.5x and output it to the VDAC pin. Connect a 1µF phase compensation capacitor to the VDAC pin. ・DAC Control DAC Control convents the 10-bit digital signal read to the register to a voltage. ・Amp Amp amplifiers the voltage output from DAC Control by 2x. Input includes sample & hold function, refreshed by OSC. ・OSC The OSC generates the frequency that determines the Amp's refresh time. External input can be selected using serial input. ・Power On Reset When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, registers. Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the speed with which the power supply starts up. ・VREF This block generates the internal reference voltage. ・TSD(Thermal Shut Down) The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175°C(TYP) in order to prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets. The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC below the thermal shutdown junction temperature of approximately 150°C(TYP). ・CTL CTL signal can select Amp input. If CTL=”L”, each output voltage is fixed at REFIN voltage divided 13th equality. IF CTL=”H”, each Amp input connect DAC output, and each output comply with each register. ・Register A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface is held for each register address. Data is initialized by the reset signal generated during a power-on reset. ・Serial I/F The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages, specify register addresses, and select OSC I/O. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/10 2009.07 - Rev.B Technical Note BD8143MUV ●Serial Communication The serial data control block is composed of Shift-Register, DAC Register and DAC circuit. The DAC register memorizes data from the serial interface (LATCH, CLK and SDIN). The DAC circuit makes control voltage from the register output and it outputs to the each block. The DAC register value turns back the preset value when Power Supply starts up. Then, beginning 1bit of SDIN is always 0, because it is for test. Next 1bit switches OSC mode. If input 0, OSC mode is internal mode (the frequency is 100kHz). If input 1, it is external one that require external clock. SERIAL DATA CONTROL BLOCK CLOCK CONTROL 10bit Register d0 d1 d2 5bit ADDRESS DECORDE OUT0～12 d3 d4 d5 d6 d7 d8 d10 d9 d11 d12 d13 d14 Shift Register d16 CLK SDIN d15 LATCH 1bit OSC MODE 1bit TEST MODE DAC Fig.2 SERIAL BLOCK ①TIMING OF SERIAL COMMUNICATION The 17 bits Serial data from SDIN terminal is loaded to Shift-Register at the rise edge of CLK, and these data is loaded to DAC Register at the rise edge of LATCH. If serial data period is less than 17 bits while LATCH state is LOW, the serial data is not memorized. If serial data period is more than 17 bits while LATCH state is LOW, last 17 bits are effective. TIMING OF SERIAL COMMUNICATION LATCH CLK d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 SDIN Fig.3 TIMING OF SERIAL COMMUNICATION ②SERIAL DATA The composition of SERIAL DATA INPUT(SDIN) First → d0 d1 d2 d3 d4 d5 d6 0 X REGISTER NAME d7 d8 d9 d10 Resister Address d11 d12 d13 d14 → Last d15 d16 DATA ADDRESS PRESET VALUE FUNCTION d2 d3 d4 d5 d6 Register 0 0 0 0 0 0 OUT0 Voltage of control 00 0000 0000 Register 1 0 0 0 0 1 OUT1 Voltage of control 00 0000 0000 Register 2 0 0 0 1 0 OUT2 Voltage of control 00 0000 0000 Register 3 0 0 0 1 1 OUT3 Voltage of control 00 0000 0000 Register 4 0 0 1 0 0 OUT4 Voltage of control 00 0000 0000 Register 5 0 0 1 0 1 OUT5 Voltage of control 00 0000 0000 Register 6 0 0 1 1 0 OUT6 Voltage of control 00 0000 0000 Register 7 0 0 1 1 1 OUT7 Voltage of control 00 0000 0000 Register 8 0 1 0 0 0 OUT8 Voltage of control 00 0000 0000 Register 9 0 1 0 0 1 OUT9 Voltage of control 00 0000 0000 Register 10 0 1 0 1 0 OUT10 Voltage of control 00 0000 0000 OUT11 Voltage of control 00 0000 0000 00 0000 0000 Register 11 0 1 0 1 1 Register 12(*) 0 1 1 0 0 - d7～d16 (*)IF Register 12 is loaded at DATA=1010100000(2A0h), each output comply with each register regardless of CTL signal. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/10 2009.07 - Rev.B Technical Note BD8143MUV ●Serial Communication Timing Chart LATCH tWL tCL tWH tLA tLC CLK tSC SDIN Fig.4 ●Timing Standard Value Parameter LATCH Set up time LIMIT Symbol tLC Unit Min. Typ. Max. 0.1 － － us SDIN Set up time tSC 0.1 － － us CLK “H” time tWH 0.1 － － us CLK “L” time tWL 0.1 － － us LATCH hold time tCL 0.1 － － us LATCH “H” time tLA 0.6 － － us ●Setting γ-Correction Formula (1) shows the relationship between γ output voltage (OUT0～OUT11) and DAC digital value. Output Voltage(OUT0～OUT11)=({(DAC digital value +1)/1024}×(REFIN/2)‐10mV)×2.0025 ・・・(1) ●Power Supply Sequence Digital power supply DVCC must be supplied earlier than VCC for the prevent of wrong behavior. The serial data must be input after cancellation of “Power on Reset”. When turn off power supply, VCC must be done earlier than DVCC. ・・・ VCC ・・・ tVcc tVD ・・・ REFIN ・・・ tVR ・・・ DVCC ・・・ ・・・ LATCH tRV ・・・ tSV tDS CLK ・・・ ・・・ SDIN ・・・ ・・・ Fig.5 Power Supply Sequence ●Power Supply Sequence Standard Value Parameter Timing of serial data input Symbol tDS LIMIT Min. Typ. Max. 100 - - Unit μs Timing of VCC ON tSV - 10 - μs Timing of REFIN ON tVR 0 10 - μs Timing of REFIN OFF tRV 0 10 - μs tVD 0 10 - μs tVCC 1 - - ms Timing of VCC OFF VCC rise time www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/10 Condition Cct=1000pF 2009.07 - Rev.B Technical Note BD8143MUV ●Data writing time for register Data writing time for register depend on frequency of CLK. Below formula shows data writing time for all registers. (Because data writing time for a register is needed at 17bit data + LATCH “H” time.) 1 18 CLK × ×12ch [µs] fCLK [MHz] ●Refresh time of Amp input Each Amp input have sample & hold function refreshed by OSC frequency (fosc). Below formula shows refresh cycle. 1 ×12ch [µs] fOSC [kHz] When internal OSC mode, fOSC=100kHz (Typ). ●Function of selecting Amp input This IC can select Amp input by CTL signal. If CTL=”L”, Amp input is connected to resistance division of REFIN voltage. IF CTL=”H”, connected to DAC output. When VCC(REFIN) supplies with CTL=”L”, it is possible to start up without opposite Voltage of each output. Then, if the CTL signal changes “H” after 1ms and over since VCC(REFIN) supplied and data send finished, start up sequence should be below Fig. (*Amp input is connected to DAC output not only by CTL=”H”, but also DATA=1010100000(2A0h) sended to Register 12. Also in this case, please send DATA=1010100000(2A0h) to Register 12 after 1ms and over since VCC(REFIN) supplied And output data send finished, at this time CTL=”L”.) REFIN VCC Preset value CTL OUT0 VDAC OUT1 VCC OUT2 x2 OUT DAC Control OUT10 DAC value OUT11 CTL Preset value Fig.6 Selecting Amp input block diagram www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. DAC value Fig.7 Start up sequence 7/10 2009.07 - Rev.B Technical Note BD8143MUV ●Input Output Circuit (BD8143MUV) 1.LATCH 2.SDIN 3.CLK 4.SDOUT 6.CT DVCC DVCC DVCC GND GND 9.OSC 11. CTL DVCC GND 14.OUT0 17.OUT3 22.OUT6 25.OUT9 15.OUT1 18.OUT4 23.OUT7 26.OUT10 16.OUT2 19.OUT5 24.OUT8 27.OUT11 VCC DVCC GND GND 29.REFIN AGND 30.VDAC VCC VCC AGND AGND Fig.8 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/10 2009.07 - Rev.B Technical Note BD8143MUV ●Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in below Fig.9, a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage to input and output pins. Resistor Transistor (NPN) B ～ ～ (Pin B) E B C ～ ～ C (Pin B) ～ ～ (Pin A) E GND GND N P+ N N P P P+ N N Parasitic elements P+ N N (Pin A) ～ ～ P P+ P substrate Parasitic elements GND Parasitic elements Parasitic elements GND Fig.9 Example of a Simple Monolithic IC Architecture 9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) Thermal shutdown circuit (TSD) This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. The circuit automatically resets once the junction temperature Tj drops.Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. 12) Push Current This IC may rush current momentary by power supply order or delay, use caution about power supply coupling capacitor, width or routing of VCC ,GND patterns GND www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/10 2009.07 - Rev.B Technical Note BD8143MUV ●Ordering part number B D 8 Part No. 1 4 3 Part No. M U V - Package MUV: VQFN032V5050 E 2 Packaging and forming specification E2: Embossed tape and reel VQFN032V5050 5.0 ± 0.1 5.0±0.1 1.0MAX 3.4±0.1 0.4 ± 0.1 1 8 9 32 16 25 24 0.75 0.5 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold ) (0.22) ( reel on the left hand and you pull out the tape on the right hand 3.4 ± 0.1 +0.03 0.02 -0.02 S C0.2 Embossed carrier tape Quantity Direction of feed 1PIN MARK 0.08 S Tape 17 +0.05 0.25 -0.04 1pin (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 10/10 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.07 - Rev.B Datasheet Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment, OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you (Note 1) , transport intend to use our Products in devices requiring extremely high reliability (such as medical equipment equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance. 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