Power Supply IC Series for TFT-LCD Panels
4-channel System Power Supply
+ Gamma Buffer Amp IC
BD8150KVT
No.09035EBT03
●Description
The BD8150KVT is a system power supply IC that offers a 4-channel power supply with 10 gamma correction output channels
and VCOM. The DC/DC block can be switched between step-up and step-down and supports both 5V and 12V input.
●Features
1) Multi-channel power supply with two DC/DC converter controller channels and two charge pump channels
2) 10channel gamma correction Buffer Amp output and 1channel VCOM
3) High reference voltage accuracy: ±1 %
4) Oscillating frequency: 1MHz
5) Built-in UVLO (Under Voltage Lockout) and output short-circuit protection circuits
6) Standby current of 0μA (Typ.)
7) Controllable start up sequence
8) TQFP64V package
●Applications
Power supply for LCD monitors and LCD TVs
●Absolute Maximum Ratings (Ta=25°C)
Parameter
Power supply voltage
Regulator power supply voltage
Driver power supply voltage
Junction temperature
Power dissipation
Operating temperature range
Storage temperature range
Symbol
VCC
REGVCC
PVCC
Tjmax
Pd
Topr
Tstg
Rating
15
15
15
125
1000*1
−30 to 85
−55 to 150
Unit
V
V
V
°C
mW
°C
°C
*1 Derated at 10mW/°C at Ta>25°C when mounted on a 70.0 mm 70.0 mm 1.6 mm glass epoxy board
●Operating Conditions (Ta=-30°C ~+85°C)
Parameter
Power supply voltage
Regulator power supply voltage
Driver power supply voltage
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Symbol
VCC
REGVCC
PVCC
Limits
Min.
2.7
4.5
2.7
1/18
Max.
13
14
13
Unit
V
V
V
2009.07 - Rev.B
Technical Note
BD8150KVT
●Electrical Characteristics (Unless otherwise specified, VCC = 5 V, REGVCC = 12V, Ta = 25°C)
Limit
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
[ (1) DC/DC converter controller ERR AMP1, 2 ]
Input bias current
Ib12
−3
−0.1
3
μA INV = 0.5 V
Input offset voltage
Vos12
−10
0
10
mV
Output source current
Iesc12
−2
−0.7
−0.2
mA VFB = 1.25 V, INV = 0.5 V, NON = 2.5 V
Output sink current
Iesk12
0.1
0.3
1
mA VFB = 1.25 V, INV = 1.5 V, NON = 0 V
Input voltage range
VNON12
−0.1
−
VCC−1
V
Max. output voltage
Voh12
1.8
2.1
2.4
V IFB = −0.1 mA
Min. output voltage
Vol12
0.6
0.8
1.0
V IFB = 0.1 mA
Feedback voltage
FB1
1.225
1.25
1.275
V ERRAMP1 only
[ (1) PWM and DRV ]
Output sink current
Ipsk12
70
130
200
mA GD1, 2 = 5 V
Output source current
Ipsc12
−245
−160
−85
mA GD1, 2 = 0 V
[ (1) UD Selector ]
High-side threshold voltage
Vudh
VCC 0.7
VCC
−
V Step-down operation
Low-side threshold voltage
Vudl
−
0
VCC 0.3
V Step-up operation
[ (1) Detector 1, 2 ]
High-side threshold voltage 1
Vdeh12
0.9
1.0
1.1
V DET1, 2 L H sweep up VINV
Low-side threshold voltage 1
Vdel12
0.6
0.7
0.8
V DET1, 2 H L sweep down VINV
High-side threshold voltage 2
Vdeh22
0.1
0.2
0.3
V DET2 LH,Inverting sweep down VNON
Low-side threshold voltage 2
Vdel22
0.4
0.5
0.6
V DET2 HL,Inverting sweep up VNON
DET1 max. output voltage
Vdh1
4.8
5.0
−
V
DET1 min. output voltage
Vdl1
−
0
0.2
V
DET2 max. output voltage
Vdh2
4.8
5.0
−
V
DET2 min. output voltage
Vdl2
−
0
0.2
V
[ (1) Oscillator ]
Switching frequency
Fsw12
0.8
1.0
1.2
MHz
Frequency variation
Fc12
−
10
−
% VCC = 3 V to 13 V
[ (1) Soft start ]
Source current
Iscss
6
10
14
μA
Sink current
Iskss
0.5
1
2
mA CTL1, 2 = 0 V
[ (1) Timer latch ]
Source current
Isctl
6
10
14
μA SCP = 1.0 V
SCP threshold voltage
Vthscp
−
1.25
−
V
[ (1) DTC1 ]
Input bias current
Vdtc1
−3
−0.1
3
μA
High-side threshold voltage
VdtcH1
−
1.5
−
V On Duty = 0%
Low-side threshold voltage
VdtcL1
−
1.0
−
V On Duty = 100%
[ (1) DTC2 ]
Input bias current
Idtc2
−3
−0.1
3
μA
High-side threshold voltage
IdtcH2
−
1.5
−
V On Duty = 100%
Low-side threshold voltage
IdtcL2
−
1.0
−
V On Duty = 0%
[ (2) Charge pump driver ERR AMP3, 4 ]
FB3
1.212
1.25
1.288
V
Feedback voltage
FB4
−
0
−
V
Input bias current
Ib34
−3
−0.1
3
μA Buffer
I/O voltage difference
∆Vd34
−
0.2
0.5
V Io = −10 mA
Output current capacity
Io34
−
−130
−50
mA VFB = 0 V
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2/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Electrical Characteristics (Unless otherwise specified, VCC = 5 V, REGVCC = 12 V, Ta = 25°C)
Limit
Unit
Conditions
Parameter
Symbol
Min.
Typ.
Max.
[ (2) Driver ]
Switching frequency
Fsw34
200
250
300
kHz
Frequency variation
Fc34
−
10
−
% VCC = 3V to 13V
[ (2) Detector ]
Vdeh3
0.9
1.0
1.1
V DET3 L H, sweep up INV3
High-side threshold voltage
Vdeh4
0.1
0.2
0.3
V DET4 L H, sweep down NON4
Vdel3
0.6
0.7
0.8
V DET3 H L, sweep down NON3
Low-side threshold voltage
Vdel4
0.4
0.5
0.6
V DET4 H L, sweep up NON4
Vdh3
4.8
5.0
−
V
DET3 min. output voltage
Vdl3
−
0
0.2
V
Vdh4
4.8
5.0
−
V
DET4 max. output voltage
Vdl4
−
0
0.2
V
[ (3) Low-dropout regulator]
Feedback voltage
FBR
1.237
1.25
1.263
V Buffer, Io = −10mA
Input bias current
Ibr
−3
−0.1
3
μA Buffer
I/O voltage difference
∆Vdr
−
0.2
0.5
V Io = −10mA
Output current capacity
Io
−
−130
−50
mA VREG = 0V
Input stability
RegI
−
1
10
mV REGVCC = 4.5V to 14V
Load stability
RegL
−
1
10
mV Io = 1mA 10mA
Ripple rejection ratio
RR
35
50
−
dB f = 120Hz
[ (4) Buffer Amp ]
Input offset voltage
Voso
−10
0
10
mV
Input bias current
Ibo
−3
−0.1
3
μA IN+ = 6V
Driver current
Ioo
20
50
−
mA
Load stability
∆Vo
−
1
10
mV Io = +1mA to −1mA
Slew rate
SRo
−
2
−
V/μs
REGVCC REGVCC
−
V Io = −1mA, IN+ = REGVCC
Max. output current
Voho
−1.0
−0.8
Min. output current
Vohl
[ (5) Overall BG ]
BG output voltage
Vref
Input stability
∆Vi
Load stability
∆Vl
Output current capacity
Iovr
[ VREF17 ]
VREF17 output voltage
Vref17
Input stability
∆Vi17
Load stability
∆Vl17
Output current capacity
Iovr17
[ (5)CTL1 to CTL4 ]
High-side threshold voltage
Vcth
Low-side threshold voltage
Vctl
[ (5) Under-voltage lockout protection ]
Threshold voltage
Vuvlo
Hysteresis
Hys
[ (5)Total supply current ]
Standby current
Istb
Average consumption current
Icc
[ (5)All ENABLE ]
Sink current
Ies
[ (5)PG ]
Source current
Igso
Sink current
Igsi
−
0.1
0.16
V
Io = 1mA, IN+ = 0V
1.225
−
−
0.2
1.250
5
1
1
1.275
20
10
−
V
mV
mV
mA
Io = −0.1mA
VCC = 3V to 13V
Io = 0mA 0.1mA
BG = 0V
1.666
−
−
0.2
1.700
5
1
1
1.734
20
10
−
V
mV
mV
mA
Io = −0.1mA
VCC = 3V to 13V
Io = 0mA 0.1mA
VREF17 = 0V
VCC0.7
−
VCC
0
−
VCC0.3
V
V
2.327
−
2.45
0.1
2.573
−
V
V
−
1.1
0
2
10
2.9
μA
mA
2
4
8
mA
ENABLE = 5V
1.2
2
2.5
5
5
8
mA
μA
CTL1 = CTL2 = 0V, PG = 2.5V
CTL1 = 5V, PG = 2.5V
Circuit active
Circuit off
* This product is not designed for protection against radio active rays.
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3/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Electrical Characteristics Curves (Unless otherwise specified, Ta = 25°C)
10
1
7.5
20
0.8
-40℃
15
ICC [uA]
2.5
0.4
0
0
4
8
12
16
10
5
0.2
0
0
0
4
8
12
16
0
4
8
12
16
Vcc[V]
VCC
[V]
Vcc[V]
VCC
[V]
VENBLE [V]
Fig. 1 Total Supply Current
Fig. 2 Standby Current
Fig. 3 ENB Pin Current
1.27
IPG [uA]
1.26
VREG [V]
0.6
1.25
10
5
8
4
6
3
IPG[mA]
ICC [mA]
125℃
5
IENBLE [mA]]
25℃
4
2
2
1
1.24
1.23
-40
0
0
0
40
80
120
0
1
2
Ta [℃]
3
4
0
5
1
2
Fig. 4 VREG Voltage vs Temperature
Fig. 5 PG Pin Sinking
Current
6
3
4
5
VPG [V]
VPG [V]
Fig. 6 PG Pin Source Current
6
16
4.5
12
4
0
-2
125℃
25
25℃
Vo[V]
FB[V]
VOS [mV]
2
3
8
-40℃
1.5
4
-4
-6
0.75
0
0.85
0.95
1.05
1.15
1.25
VIN [V]
Fig. 7 Error Amp Offset Voltage
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0
1
2
3
4
0
0
Fig. 8 Error Amp Slew Rate Waveform
4/18
40
80
120
160
Io[mA]
VCC
[V]
TIME [μS]
Fig. 9
Regulator Output Current Capacity
2009.07 - Rev.B
Technical Note
BD8150KVT
●Electrical Characteristics Curves (Unless otherwise specified, Ta = 25°C)
150
120
150
300
120
240
-40℃
60
30
90
125
25℃
-40℃
60
4
8
12
16
120
125℃
0
4
RegVcc [V]
8
12
2
16
Fig. 11 Charge Pump
NMOS On Resistance
7.5
2
2.5
VOS[mV]
7.5
VDET4[V]
4
5
0
3
4
5
-4
0
0.25
0.5
0.75
0
1
2.8
5.6
8.4
11.2
VIN [V]
Vcc [V]
Fig. 13 Detectors 1 to 3
Threshold Voltage
16
-2
0
Vcc [V]
12.5
0
2.5
2
9
Fig. 12 Charge Pump
Switching Frequency
10
5
-40℃
RegVcc [V]
10
1
5.5
RegVcc [V]
Fig. 10 Charge Pump
PMOS On Resistance
Fig. 15 Buffer Amp
Offset Voltage
Fig. 14 Detector 4
Threshold Voltage
180
180
100
12
144
144
PHASE
72
72
GAIN [dB]
VO[V]
9
6
1V
3
1μs
0
-60
108
108
60
-38
-16
6
28
50
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0 0
GAIN
-20
-36
-36
-60
-108
-108
-72
-72
-144
-144
-180
-100
-180
1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0
2
3
4
5
6
7
8
f [Hz]
|
IO [mA]
Fig. 16 Buffer Amp
Output current capacity
3636
20
Fig. 17 Buffer Amp
Slew Rate Waveform
5/18
Fig.18 Buffer Amp
Open Loop
2009.07 - Rev.B
PHA [deg]
0
25℃
0
0
0
180
60
30
0
VDET1[V]
CD freq[kHz]
25℃
90
VOL[mV]
VOH[V]
125℃
Technical Note
BD8150KVT
●Pinout Diagram
●Block Diagram
Vcc
VCC
NON2
51
BG
VREF17
43
CT
42
VREF
41
UDSEL1
32
VREF17
+
-
1
50
U/D SELECTER
PWM1
DTC1 59
DTC2 60
49
+
-
DET1
52
FB1
53
INV1
48
GD2
+
-
54
1V
SS1 55
SOFTSTART
PWM2
+
+
1
SS2 56
U/D SELECTER
CT
INV5
VREG
REGVCC
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
COM
AMPGND
SOFTSTART
47
PGND
45
FB2
44
INV2
ERR2
CTL1 61
CTL2 62
+
-
DET2
+
-
CTL3 63
CTL4 64
1V
33 SCP
TIMERLATCH
REG 29
Vcc
VCC
REG
VREG
INV5
+
-
30
1
DET1
2
DET2
3
DET3
4
DET4
31
GND
46
2BitCOUNTER
CD4
37
LV SHIFT
FB4
36
34
ENABLE
38
CD3
39
FB3
40
INV3
DET1
DET2
DET3
DET4
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN+
IN-
GD1
PVCC
VCC
FB1
IVN1
PG
SS1
SS2
UDSEL1
UDSEL2
DTC1
DTC2
CTL4
CTL3
CTL2
CTL1
PVCC
PVcc
GD1
ERR1
Vcc
VCC
GD2
PGND
GND
FB2
INV2
NON2
VREF17
BG
INV3
FB3
CD3
CD4
FB4
NON4
ENABLE
SCP
58
OSC
UVLO
PG
UDSEL2
59
+
ERR4
16
IN+
15
COM
18
+
-
DET3
DET4
+
NON4 35
IN-
LV SHIFT
+
-
0.2V
ERR3
1V
17
AMPVcc
AMPVCC
5
+
-
+
-
OUT2
27
6
OUT1
7
IN1
26
IN2
8
OUT0
+
-
+
-
OUT4
25
OUT3
9
IN3
24
IN4
10
+
-
+
-
OUT6
23
OUT5
11
IN5
22
IN6
12
+
-
+
-
OUT8
21
OUT7
OUT9
IN9
13
IN7
20
IN8
14
+
-
+
-
+
-
19
28
AMPGND
IN0
Fig. 19 BD8150KVT Pin Assignment Diagram and Block Diagram
●Pin Description
Pin No.
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DET1
DET2
DET3
DET4
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN+
INAMPGND
COM
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
29
REGVCC
30
31
32
VREG
INV5
CT
Function
Pin No.
Pin Name
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SCP
ENABLE
NON4
FB4
CD4
CD3
FB3
INV3
BG
VREF17
NON2
INV2
FB2
GND
PGND
GD2
GD1
PVCC
VCC
FB1
INV1
PG
SS1
SS2
UDSEL1
UDSEL2
DTC1
DTC2
DC/DC detector output 1
DC/DC detector output 2
Charge pump detector output 3
Charge pump detector output 4
Buffer amp 0 input
Buffer amp 1 input
Buffer amp 2 input
Buffer amp 3 input
Buffer amp 4 input
Buffer amp 5 input
Buffer amp 6 input
Buffer amp 7 input
Buffer amp 8 input
Buffer amp 9 input
Op-amp non inverting input
Op-amp inverting input
Buffer amp and op-amp ground
Op-amp output
Buffer amp 9 output
Buffer amp 8 output
Buffer amp 7 output
Buffer amp 6 output
Buffer amp 5 output
Buffer amp 4 output
Buffer amp 3 output
Buffer amp 2 output
Buffer amp 1 output
Buffer amp 0 output
Charge pump, Regulator, op-amp and buffer amp
power supply
Regulator output
Regulator negative feed back input
Ramp wave monitor
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6/18
Function
Connect timer latch capacitor
All channel output enable
Charge pump feed back input 4
Charge pump E/A output 4
Charge pump driver output 4
Charge pump driver output 3
Charge pump E/A output 3
Charge pump feed back input 3
Reference voltage monitor
1.7V Reference Voltage
DC/DC E/A non inverting input 2
DC/DC E/A inverting input 2
DC/DC E/A output 2
Ground
Power ground
DC/DC driver output 2
DC/DC driver output 1
Power VCC supply
VCC supply
DC/DC E/A output 1
DC/DC E/A inverting input 1
Pch FET switch driver output
Connect soft start capacitor 1
Connect soft start capacitor 2
Step up/down select switch 1
Step up/down select switch 2
Dead time control voltage input1
Dead time control voltage input2
61
CTL4
Charge pump control switch 4
62
63
64
CTL3
CTL2
CTL1
Charge pump control switch 3
DC/DC control switch 2
DC/DC control switch 1
2009.07 - Rev.B
Technical Note
BD8150KVT
●Block Description
VREF
This block outputs a highly accurate reference voltage of 2.5V and has a current capacity of over 1mA. ON/OFF control is
possible using the CTL pin.
ERRAMP
This is an error amp that amplifies and outputs the NON and INV voltage differential. The output pulse duty is determined by the
output FB voltage. When FB is 1.95V or more it is switched OFF, and when 1.45V or less the output NPN Tr is switched ON.
OSC
This block determines the RT and CT switching frequency. The triangular waveform is determined by RT and CT.
Timer latch
This is a protection circuit that detects output short-circuits (when the error amp output is 1V or less). Once activated, the
timer begins charging the SCP terminal capacitance at 7μA. When the SCP voltage is 1.8V or more, the latch is applied
and shutdown begins. Recovery can be accomplished by turning on Vcc and CTL.
PWM/driver
This is a PWM comparator that determines the duty by comparing the error amp output and the oscillator triangular
waveform in order to determine the maximum duty ratio for the DTC. It is turned to OFF when the DTC voltage is 1.95V
and turned ON at 1.45V. Use the VREF resistance division to set the DTC voltage.
UVLO
This is a protective circuit that shuts down the system when the input voltage becomes 2.5V in order to prevent IC
malfunction. A 0.1V hysteresis exists and reset is implemented once the voltage is at least 2.6V.
Soft start
Soft start is activated during startup in order to prevent DC/DC converter inrush current. The delay time depends on the pin
capacitance. The circuit is set to LOW when a protective circuit is triggered. When reset, soft start will once again operate
at startup.
DET
This is a comparator that detects whether each output voltage is output as set. When output as set, High is output to pins
DET1 to DET4. When all of the DET pins are High, the ENABLE pin is set to High.
U/D selector
This selector switches between the step-up DC/DC and step-down DC/DC. Step-down operation is performed for high
input, and step-up operation is performed for low input.
VREF17
A 1.7V reference voltage is output. This is used for the DTC setting. Perform resistance division from this voltage and set
the DTC voltage.
REG
This is the regulator output for the gamma correction setting. Providing gamma correction resistance division under this
regulator makes it possible to obtain a stable gamma correction voltage.
2-bit counter
A charge pump switching frequency is generated from the DC/DC converter frequency. This becomes 1/4 of the DC/DC
converter frequency.
DRV block (DC/DC converter)
This is a driver block that outputs the pulse between Vcc and GND. This directly drives the P-channel FET or N-channel
FET. For step-up, connect the N-channel FET, for step-down, connect the P-channel FET.
DRV (charge pump)
This driver block outputs the pulse between FB and GND. Feedback control is applied to the FB voltage to stabilize the
charge pump. The FB voltage only increases to the Reg Vcc voltage, so the Reg Vcc voltage is the maximum switching
amplitude.
Buffer Amp
This IC has a built-in 10channel buffer amp for gamma correction voltage generation. Using this amp allows generation of
a gamma correction voltage that is input to the source driver.
VCOM
A 1-channel differential input operation amp is built-in for VCOM. Using an external bipolar Tr buffer makes it possible to
generate a VCOM voltage.
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7/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Timing Chart
Basic Operation
5V
Vcc
23 V
10 V
Each output
voltage
3.3 V
SS2
SS1
-6 V
ENABLE
Fig. 20 Basic Operation
●When short protection is triggered
5V
Vcc
23 V
Each
output
voltage
10 V
3.3 V
-6 V
1.25 V
SCP
Fig. 21 During Short Protection Operation
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8/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Selecting Application Components
1 DC/DC converter block design
1-1 Operating mode determination
The step-down, step-up, and inverting switching regulators are comprised of UDSEL (Pins 58, 59), error amp input
NON (Pin 43), and INV pins (Pins 44, 53). NON1 is internally connected to BG.
Operating mode
UDSEL
NON
INV
10000
VCC
BG
FEEDBACK
Step-up
GND
BG
FEEDBACK
Inverting
VCC
FEEDBACK
GND
1000
FREQ [kHz]
Step-down
1-2 Setting the oscillating frequency
Applying capacitance to the CT pin (Pin 32) allows the oscillating frequency
to be set. Refer to Fig.22 when setting the capacitance. When nothing is
applied, the frequency is set to 1 MHz (Typ.).
100
10
1
10
100
1000
CCT [pF]
Fig. 22 CT Capacitance vs
Oscillating Frequency
1-3 L and C selection
Select the output L and C so that the output ripple voltage is within specifications. Select L so that the sum of the
ripple current and load current (input current for step-up and inversion) does not exceed the rated current of the coil.
And select C so that the output ripple voltage including the switching noise does not exceed breakdown voltage.
Coil current
∆IL = (VCC − VO) VO / (L f VCC) [A] (step-down)
∆IL = VCC (VO − VCC) / (L f VO) [A] (Step-up)
∆IL = VCC VO / (L f (VO − VCC)) [A] (Inversion)
Output ripple voltage
∆VPP = ∆IL RESR + (∆IL VO) / (2 C f VCC) [V] (step-down)
∆VPP = (∆IL + IO) RESR + (ΔIL VO) / (2 C f VCC) [V] (Step-up, Inversion)
Where, RESR = Internal resistance component in output C.
1-4 Switching MOSFET selection
There is no problem if the absolute maximum rating exceeds the rated current of L and the breakdown voltage +
rectification diode VF for C, but select a low gate capacitance (inrush charge amount) to achieve high-speed switching.
1-5 Rectification diode selection
Select a Schottky barrier diode having a current capacity above the rated current of L and an inverse breakdown
voltage above the breakdown voltage of C and that, in particular, has a low forward direction voltage VF.
1-6 Feedback resistance value setting
Use the following equation to set the feedback resistance value to achieve stability at the specified output voltage.
Output voltage
VO = (R1 + R2) BG / R2 [V] (step-down)
VO = (R1 + R2) BG / R2 [V] (Step-up)
VO = −(R1 BG) / R2 [V] (Inversion)
VO
VO
R1
INV
R2
R1
VO
INV
R1
NON
R2
R2
BG
(a) Step-down
(b) Step -up
(c) Inverting
Fig. 23 Feedback Resistance Setting
The INV and NON pins are easily affected by noise, so use as short a pattern layout as possible and make sure that
there is no overlap of the switching lines.
DELAY [sec] RISETIME [sec]
1.00E-01
1.00E-02
TIME [sec]
1-7 Setting soft start time
Applying capacitance to the SS pins (pins 55, 56) allows the soft
start time to be set. Refer to Fig. 24 in order to select the
appropriate capacitance. The soft start time will vary depending on
the application, such as frequency, coil, and capacitance, so
always verify operation under actual conditions.
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
CSS [F]
Fig. 24 Soft Start Time for
SS Capacitance
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© 2009 ROHM Co., Ltd. All rights reserved.
9/18
2009.07 - Rev.B
Technical Note
BD8150KVT
1-8 Load switch MOSFET selection and corresponding soft start (step-up channels only)
Switching does not exist in the circuits from VCC to VO for normal step-up applications, so the coil or rectification diode
could be damaged by an output short. To prevent this, insert a PMOSFET load switch between the VCC and coil.
Select a PMOSFET with breakdown voltage between the gate sources and between the drain sources higher than VCC.
Furthermore, if soft start is to be applied to the load switch, insert a capacitor between the gate sources. Refer to Fig.
26 when selecting the soft start time. Please note that the soft start time depends on the PMOSFET gate capacitance.
L←
PG PIN CAPACITOR vs. SOFT START TIME
Vo
DELAY [sec]
SBDi
RISETIME [sec]
1.00E-01
C
1.00E-02
TIME [sec]
VCC
Load switch FET
1.00E-03
1.00E-04
Switching FET
1.00E-05
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
CPG [F]
Fig. 25 Load Switch Circuit Diagram
Fig. 26 Soft Start Time for PG Capacitance
1-9 RC filter setting for phase compensation
Phase compensation is required for stabilization in DC/DC converter applications. A built-in phase compensation
circuit makes this possible.
1) When using internal phase compensation, observe the following requirements in designs.
(1) Internally set the switching frequency (1MHz Typ.).
(2) 1 / (2π√LC) = 10 - 30 kHz
(3) 1 / (2πR1C1) = 10 - 100 kHz
VCC
BG
L
VCC
C
C1
NON
R1
+
FB
ERR
INV
100 kΩ
150 kΩ
R2
5 pF
100 pF
Fig. 27 Internal Phase Compensation
2) Using external phase compensation
When changing the oscillating frequency and L or C values, insert an RC filter circuit between INV and FB.
(1) (1/2π√LC) 0.5 < 1 / (2πR1C1) < (1/2π√LC) 2
(2) (1/2π√LC) 0.5 < 1 / (2πR4C2) < (1/2π√LC) 2
(3) R3 > R4
(4) (1/2πR4C2) 5 < 1 / (2πR3C3) < fsw / 2
VCC
BG
L
C
NON
+
C1
R1
R3
+
INV
ERR
R2
R4
C2
150 kΩ
C3
100 kΩ
100 pF
FB
5 pF
Fig. 28 External Phase Compensation
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© 2009 ROHM Co., Ltd. All rights reserved.
10/18
2009.07 - Rev.B
Technical Note
BD8150KVT
1-10 When only one channel is used for the DC/DC converter
This IC has built-in detector circuits for detection of output voltage startup. The ENABLE signal changes to High when
all detectors are on, meaning the ENABLE signal (Pin 34) will not switch to High if channels not used by the DC/DC
converter are set to OFF. If there exist channels that are not used, set them as follows so that the ENABLE signal will
be switched to High.
(1) Make the CTL (Pins 63, 64) HIGH (VCC).
(2) Detection is performed on the feedback side, so the INV and NON of unused channels should be shorted.
(3) Connect the SS pin to GND.
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11/18
SCP PIN CAPACITOR vs. SCP TIME
1.00E-01
1.00E-02
TIME [sec]
1-11 Output short protection circuit
This IC has a built-in timer latch type output short protection function
to prevent damage from overcurrent from the output MOSFET.
Adding capacitance to the SCP pin (Pin 33) allows the delay time
to be set until protection can be provided.
In the event of an output short, a rated current (7μA, Typ.) flows
to the SCP capacitor. When the threshold voltage (1.25V, Typ.) is
attained, a latch is applied and the IC is shut down. The
shutdown is canceled by CTL or turning the power on again. Refer
to Fig. 29 in order to determine the capacitance that will set the
delay time.
The output power transistor damage time varies depending on
the application, so perform evaluations using the actual product
under operating conditions. Furthermore, if not using short
protection, short the SCP pin to GND.
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
CSCP [F]
Fig. 29 SCP Capacitance vs
Short Protection Delay Time
2009.07 - Rev.B
Technical Note
BD8150KVT
2 Charge pump design
2-1 Basic circuit operation
The charge pump circuit stores a charge in a flying capacitor and then supplies the charge to a post-circuit. There are
double charge pumps, triple charge pumps, etc. In this example, the charge pump error amp output voltage FB (Pins
36, 39) is added to the step-up side voltage, so a circuit equation that stabilizes the set voltage is used.
For the high-side (VO3) charge pump, the output voltage VO3 is set by feedback resistors R5 and R6.
VO3 = BG (R5 + R6) / R6 [V]
Further, the maximum output voltage (no load) of VO3 is found using the following equation.
VO3MAX = 2 VO1 + FB3 - 3VF [V]
Where, VF is the diode's forward voltage. For VO3MAX, set the numerical V amount higher than VO3. (See Fig. 30.)
LX1 Step-up switching
BG
-
VO1
REGVCC
FB3
+
VO3
R5
CD3
R6
INV3
Fig. 30 High-side Charge Pump Circuit Diagram
For the low-side (VO4) charge pump, the output voltage (VO4) setting and maximum output voltage (VO4MAX) is
found using the following equation.
VO4 = -(R7 / R8) BG [V]
VO4MAX = -FB4 + 2 VF [V]
Where, VF is the diode's forward voltage
For VO4MAX, set the numerical V amount higher than VO4.
REGVCC
FB4
+
VO4
R7
CD4
R8
BG
NON4
Fig. 31 Low-side Charge Pump Circuit Diagram
2-2 Flying capacitor setting
For the flying capacitor, select a breakdown voltage that is sufficiently high compared to the switching voltage.
2-3 Output capacitance setting
Use an output capacitance with a breakdown voltage that is sufficiently high compared to the output voltage. In addition,
for the output capacitance CO, refer to the following equation and set it within the output ripple voltage ∆VPP range.
∆VPP = IO / (2 CO fSW) [V]
Where, the fSW is the charge pump switching frequency and has a period 4 times that of the DC/DC.
2-4 Diode selection
The charge pump switching voltage is applied in reverse to the diode. For this reason, select a sufficiently high
reverse breakdown voltage. For the current capacity, use one with a rating of at least 5 times the load.
2-5 Error amp output voltage FB capacitance selection
CHARGE PUMP LOAD vs. VO4
0
32.5
-2
VO4 [V]
VO3 [V]
CHARGE PUMP LOAD vs. VO3
35
30
27.5
-4
-6
-8
-10
25
0
7.5
15
22.5
-12
30
-25
LOAD [mA]
-20
-15
-10
-5
0
LOAD [mA]
Fig. 32 High-side Charge Pump Load vs Maximum Voltage
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© 2009 ROHM Co., Ltd. All rights reserved.
12/18
Fig. 33 Low-side Charge Pump Load vs Maximum
2009.07 - Rev.B
Technical Note
BD8150KVT
3 Regulator Block Design
3-1 Basic operation
The voltage at the very top of the gamma correction voltage range is set using an internal low-saturation regulator.
The output voltage VREG (pin 30) is set using the resistance division R9 and R10.
VREG = BG (R9 + R10) / R10 [V]
Vo1
REGVCC
BG
-
Source driver
Gamma correction
voltage input
VREG
+
INV5
R9
R10
Fig. 34 Gamma Correction Voltage Regulator Circuit Diagram
Note that a 0.5V potential difference is required between REGVCC and VREG for the regulator power supply.
The reference voltage BG accuracy is ±1%.
3-2 VREG output capacitance selection
A capacitor for preventing oscillation is required at the VREG (Pin 30) output. Select one 1F or larger with a
sufficiently high breakdown voltage.
4 Gamma correction voltage block design
4-1 Gamma correction voltage setting resistance value selection
A 10channel Buffer Amp is incorporated. The input voltage set by resistance division allows output of a gamma
correction voltage with greater current capacity. The configuration in the figure below can output gamma correction
voltage with high accuracy.
VREG
IC
IN0
IN1
1
OUT0
1
OUT1
IN9
OUT9
1
Fig. 35 Gamma Correction Voltage Generation Block Circuit Diagram
4-2 Back plate bias common voltage setting
This IC incorporates a 1channel operation Buffer in addition to the 10channel Buffer Amp. This Op Amp, along with
discrete Transistor, can be used to set the back plate bias common voltage.
VREG
VREG
IN+
IN-
IC
+
-
COM
VCOM
Fig. 36 Common Voltage Setting Circuit Diagram
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© 2009 ROHM Co., Ltd. All rights reserved.
13/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Application Circuit Diagram
INITIAL
CTL
VO1
13 V / 100 mA
VCC
5V
VO2
3.3 V / 500 mA
R- RADER
ALL
ENABLE
FROM
VO1
FROM
VO1
VO3
24 V / 10 mA
FROM
SOURCE
DRIVER
VO1
VO4
-6 V / 10 mA
VO5
10.5 V / 100 mA
Fig. 37 BD8150KVT Application Circuit Diagram
●Startup sequence
The startup sequence of each output terminal can be set using the detection (DET1 to DET4) and control pins (CTL1 to
CTL4). The detection pins switch from L to H when the feedback side INV voltage of each block reaches 80% of the
reference side. For this reason, the startup sequence can be set by connecting a detection pin to the control pin to be started
up next.
The detection pins have a hysteresis width with a standard value of 0.3 V. However, if a ripple exceeding this is applied to the
INV pin, chattering will occur. After all outputs have begun, if even one turns off, all outputs will stop.
[Example]
IC
CTL1
Initial
Input
Timing Chart (VCC = 5 V)
CTL2
CTL3
5V
CTL4
DET
DET
DET
DET
Initial
FROM 12 V
OUTPUT (CTL1)
FROM 3.3 V
OUTPUT (CTL2)
FROM 32 V
OUTPUT (CTL3)
FROM –6 V
OUTPUT (CTL4)
32 V
3.3 V
(All output enabled)
12 V
3.3 V
–6 V
Fig. 38 Timing Chart
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© 2009 ROHM Co., Ltd. All rights reserved.
14/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●I/O Equivalent Circuit Diagrams
1. DET1
2. DET2
3. DET3
4. DET4
5. IN0
9. IN4
13. IN8
15 .IN+
Vcc
Vcc
6. IN1
10. IN5
14. IN9
16. IN-
7. IN2
11. IN6
8. IN3
12. IN7
18. COM
22. OUT6
26. OUT2
19. OUT9
23. OUT5
27. OUT1
21. OUT7
25. OUT3
30.VREG
REGVcc
REGVcc
REGVcc
REGV cc
REGVcc
REGV cc
20. OUT8
24. OUT4
28. OUT0
11 kĦk
11kk
Ħ
20
20 Ħ
1 1k
kĦ
55k Ħk
31. INV5
32. CT
33. SCP
Vcc
Vcc
REGVcc
REGVcc
34. ENABLE
Vcc
Vcc
Vcc
Vcc
500
500 Ħ
11 k
kĦ
Ħ
51
5 1kk
35. NON4
36. FB4
39. FB3
37. CD4
REGVcc
REGVcc
REGVcc
38. CD3
40. INV3
REGVcc
REGVcc
REGVcc
100
k
1 00 kĦ
Ħ
1010
11kk
Ħ
5 k
Ħ
5k
5 kĦ
5 k
41. BG
42. VREF17
Vcc
Vcc
43. NON
Vcc
Vcc
20
20Ħ
20
20Ħ
Ħ
k
0
5
44. INV2
Vcc
Vcc
53. INV1
Vcc
Vcc
Ħ
11k k
Ħ
11 kk
88kĦ
k
200 k
61 k
50 k
Ħ
k
1
6
Ħ
k
0
0
2
88 k
Ħ
k
8
8
45. FB2
52. FB1
48. GD2
49. GD1
Vcc
Vcc
PVcc
PVcc
54. PG
55. SS2
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
20
20Ħ
5 kĦ
5 k
11KĦ
k
10
10Ħ
Ħ
11Kk
56. SS2
PVcc
PVcc
11 kk
Ħ
500Ħ
500
KĦ
2020k
57. UDSEL
62. CTL3
58. UDSEL
63. CTL2
61. CTL4
64. CTL1
59. DTC1
60. DTC2
Vcc
Vcc
Vcc
Vcc
Vcc
11kĦ
k
11kk
Ħ
175 k
11 kk
Ħ
Fig. 39
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© 2009 ROHM Co., Ltd. All rights reserved.
I/O Equivalent Circuit Diagram
15/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Notes for use
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals
to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
9. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
P+
N
P+
P
N
Parasitic
element
N
GND
P+
P
P substrate
Parasitic element
B
N
N
C
E
Parasitic
element
P substrate
Parasitic element
GND
GND
GND
Other adjacent elements
Fig.40 Example of IC structure
10. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.
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© 2009 ROHM Co., Ltd. All rights reserved.
16/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Thermal Dissipation Curve
1000
800
700
PD 600
(1) IC without heat sink
(2) When mounted on a glass epoxy board
(70 mm 70 mm 1.6 mm)
（2）
（1）
400
200
0
25
50
75
100
125
Ta (℃)
Fig.41
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© 2009 ROHM Co., Ltd. All rights reserved.
17/18
2009.07 - Rev.B
Technical Note
BD8150KVT
●Ordering part number
B
D
8
1
5
0
Part No.
Part No.
K
V
T
-
Package
KVT: TQFP64V
E
2
Packaging and forming specification
E2: Embossed tape and reel
TQFP64V
12.0±0.3
10.0±0.2
48
33
32
17
1
1000pcs
E2
direction is the 1pin of product is at the upper left when you hold
( The
)
reel on the left hand and you pull out the tape on the right hand
0.5
64
Embossed carrier tape (with dry pack)
Quantity
Direction
of feed
10.0±0.2
12.0±0.3
49
Tape
16
0.1±0.1
1.0±0.1
0.125±0.1
0.5
0.2 ± 0.1
1pin
0.1
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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